sound/soc/codecs/wm8994.c

   1 /*
   2  * wm8994.c  --  WM8994 ALSA SoC Audio driver
   3  *
   4  * Copyright 2009 Wolfson Microelectronics plc
   5  *
   6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   7  *
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/i2c.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/regulator/consumer.h>
  23 #include <linux/slab.h>
  24 #include <sound/core.h>
  25 #include <sound/jack.h>
  26 #include <sound/pcm.h>
  27 #include <sound/pcm_params.h>
  28 #include <sound/soc.h>
  29 #include <sound/initval.h>
  30 #include <sound/tlv.h>
  31 #include <trace/events/asoc.h>
  32
  33 #include <linux/mfd/wm8994/core.h>
  34 #include <linux/mfd/wm8994/registers.h>
  35 #include <linux/mfd/wm8994/pdata.h>
  36 #include <linux/mfd/wm8994/gpio.h>
  37
  38 #include "wm8994.h"
  39 #include "wm_hubs.h"
  40
  41 struct fll_config {
  42         int src;
  43         int in;
  44         int out;
  45 };
  46
  47 #define WM8994_NUM_DRC 3
  48 #define WM8994_NUM_EQ  3
  49
  50 static int wm8994_drc_base[] = {
  51         WM8994_AIF1_DRC1_1,
  52         WM8994_AIF1_DRC2_1,
  53         WM8994_AIF2_DRC_1,
  54 };
  55
  56 static int wm8994_retune_mobile_base[] = {
  57         WM8994_AIF1_DAC1_EQ_GAINS_1,
  58         WM8994_AIF1_DAC2_EQ_GAINS_1,
  59         WM8994_AIF2_EQ_GAINS_1,
  60 };
  61
  62 struct wm8994_micdet {
  63         struct snd_soc_jack *jack;
  64         int det;
  65         int shrt;
  66 };
  67
  68 /* codec private data */
  69 struct wm8994_priv {
  70         struct wm_hubs_data hubs;
  71         enum snd_soc_control_type control_type;
  72         void *control_data;
  73         struct snd_soc_codec *codec;
  74         int sysclk[2];
  75         int sysclk_rate[2];
  76         int mclk[2];
  77         int aifclk[2];
  78         struct fll_config fll[2], fll_suspend[2];
  79
  80         int dac_rates[2];
  81         int lrclk_shared[2];
  82
  83         int mbc_ena[3];
  84
  85         /* Platform dependant DRC configuration */
  86         const char **drc_texts;
  87         int drc_cfg[WM8994_NUM_DRC];
  88         struct soc_enum drc_enum;
  89
  90         /* Platform dependant ReTune mobile configuration */
  91         int num_retune_mobile_texts;
  92         const char **retune_mobile_texts;
  93         int retune_mobile_cfg[WM8994_NUM_EQ];
  94         struct soc_enum retune_mobile_enum;
  95
  96         /* Platform dependant MBC configuration */
  97         int mbc_cfg;
  98         const char **mbc_texts;
  99         struct soc_enum mbc_enum;
 100
 101         struct wm8994_micdet micdet[2];
 102
 103         wm8958_micdet_cb jack_cb;
 104         void *jack_cb_data;
 105         bool jack_is_mic;
 106         bool jack_is_video;
 107
 108         int revision;
 109         struct wm8994_pdata *pdata;
 110
 111         unsigned int aif1clk_enable:1;
 112         unsigned int aif2clk_enable:1;
 113 };
 114
 115 static int wm8994_readable(unsigned int reg)
 116 {
 117         switch (reg) {
 118         case WM8994_GPIO_1:
 119         case WM8994_GPIO_2:
 120         case WM8994_GPIO_3:
 121         case WM8994_GPIO_4:
 122         case WM8994_GPIO_5:
 123         case WM8994_GPIO_6:
 124         case WM8994_GPIO_7:
 125         case WM8994_GPIO_8:
 126         case WM8994_GPIO_9:
 127         case WM8994_GPIO_10:
 128         case WM8994_GPIO_11:
 129         case WM8994_INTERRUPT_STATUS_1:
 130         case WM8994_INTERRUPT_STATUS_2:
 131         case WM8994_INTERRUPT_RAW_STATUS_2:
 132                 return 1;
 133         default:
 134                 break;
 135         }
 136
 137         if (reg >= WM8994_CACHE_SIZE)
 138                 return 0;
 139         return wm8994_access_masks[reg].readable != 0;
 140 }
 141
 142 static int wm8994_volatile(unsigned int reg)
 143 {
 144         if (reg >= WM8994_CACHE_SIZE)
 145                 return 1;
 146
 147         switch (reg) {
 148         case WM8994_SOFTWARE_RESET:
 149         case WM8994_CHIP_REVISION:
 150         case WM8994_DC_SERVO_1:
 151         case WM8994_DC_SERVO_READBACK:
 152         case WM8994_RATE_STATUS:
 153         case WM8994_LDO_1:
 154         case WM8994_LDO_2:
 155         case WM8958_DSP2_EXECCONTROL:
 156         case WM8958_MIC_DETECT_3:
 157                 return 1;
 158         default:
 159                 return 0;
 160         }
 161 }
 162
 163 static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg,
 164         unsigned int value)
 165 {
 166         int ret;
 167
 168         BUG_ON(reg > WM8994_MAX_REGISTER);
 169
 170         if (!wm8994_volatile(reg)) {
 171                 ret = snd_soc_cache_write(codec, reg, value);
 172                 if (ret != 0)
 173                         dev_err(codec->dev, "Cache write to %x failed: %d\n",
 174                                 reg, ret);
 175         }
 176
 177         return wm8994_reg_write(codec->control_data, reg, value);
 178 }
 179
 180 static unsigned int wm8994_read(struct snd_soc_codec *codec,
 181                                 unsigned int reg)
 182 {
 183         unsigned int val;
 184         int ret;
 185
 186         BUG_ON(reg > WM8994_MAX_REGISTER);
 187
 188         if (!wm8994_volatile(reg) && wm8994_readable(reg) &&
 189             reg < codec->driver->reg_cache_size) {
 190                 ret = snd_soc_cache_read(codec, reg, &val);
 191                 if (ret >= 0)
 192                         return val;
 193                 else
 194                         dev_err(codec->dev, "Cache read from %x failed: %d\n",
 195                                 reg, ret);
 196         }
 197
 198         return wm8994_reg_read(codec->control_data, reg);
 199 }
 200
 201 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
 202 {
 203         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 204         int rate;
 205         int reg1 = 0;
 206         int offset;
 207
 208         if (aif)
 209                 offset = 4;
 210         else
 211                 offset = 0;
 212
 213         switch (wm8994->sysclk[aif]) {
 214         case WM8994_SYSCLK_MCLK1:
 215                 rate = wm8994->mclk[0];
 216                 break;
 217
 218         case WM8994_SYSCLK_MCLK2:
 219                 reg1 |= 0x8;
 220                 rate = wm8994->mclk[1];
 221                 break;
 222
 223         case WM8994_SYSCLK_FLL1:
 224                 reg1 |= 0x10;
 225                 rate = wm8994->fll[0].out;
 226                 break;
 227
 228         case WM8994_SYSCLK_FLL2:
 229                 reg1 |= 0x18;
 230                 rate = wm8994->fll[1].out;
 231                 break;
 232
 233         default:
 234                 return -EINVAL;
 235         }
 236
 237         if (rate >= 13500000) {
 238                 rate /= 2;
 239                 reg1 |= WM8994_AIF1CLK_DIV;
 240
 241                 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
 242                         aif + 1, rate);
 243         }
 244
 245         if (rate && rate < 3000000)
 246                 dev_warn(codec->dev, "AIF%dCLK is %dHz, should be >=3MHz for optimal performance\n",
 247                          aif + 1, rate);
 248
 249         wm8994->aifclk[aif] = rate;
 250
 251         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
 252                             WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
 253                             reg1);
 254
 255         return 0;
 256 }
 257
 258 static int configure_clock(struct snd_soc_codec *codec)
 259 {
 260         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 261         int old, new;
 262
 263         /* Bring up the AIF clocks first */
 264         configure_aif_clock(codec, 0);
 265         configure_aif_clock(codec, 1);
 266
 267         /* Then switch CLK_SYS over to the higher of them; a change
 268          * can only happen as a result of a clocking change which can
 269          * only be made outside of DAPM so we can safely redo the
 270          * clocking.
 271          */
 272
 273         /* If they're equal it doesn't matter which is used */
 274         if (wm8994->aifclk[0] == wm8994->aifclk[1])
 275                 return 0;
 276
 277         if (wm8994->aifclk[0] < wm8994->aifclk[1])
 278                 new = WM8994_SYSCLK_SRC;
 279         else
 280                 new = 0;
 281
 282         old = snd_soc_read(codec, WM8994_CLOCKING_1) & WM8994_SYSCLK_SRC;
 283
 284         /* If there's no change then we're done. */
 285         if (old == new)
 286                 return 0;
 287
 288         snd_soc_update_bits(codec, WM8994_CLOCKING_1, WM8994_SYSCLK_SRC, new);
 289
 290         snd_soc_dapm_sync(&codec->dapm);
 291
 292         return 0;
 293 }
 294
 295 static int check_clk_sys(struct snd_soc_dapm_widget *source,
 296                          struct snd_soc_dapm_widget *sink)
 297 {
 298         int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
 299         const char *clk;
 300
 301         /* Check what we're currently using for CLK_SYS */
 302         if (reg & WM8994_SYSCLK_SRC)
 303                 clk = "AIF2CLK";
 304         else
 305                 clk = "AIF1CLK";
 306
 307         return strcmp(source->name, clk) == 0;
 308 }
 309
 310 static const char *sidetone_hpf_text[] = {
 311         "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
 312 };
 313
 314 static const struct soc_enum sidetone_hpf =
 315         SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
 316
 317 static const char *adc_hpf_text[] = {
 318         "HiFi", "Voice 1", "Voice 2", "Voice 3"
 319 };
 320
 321 static const struct soc_enum aif1adc1_hpf =
 322         SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
 323
 324 static const struct soc_enum aif1adc2_hpf =
 325         SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
 326
 327 static const struct soc_enum aif2adc_hpf =
 328         SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
 329
 330 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
 331 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
 332 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
 333 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
 334 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
 335
 336 #define WM8994_DRC_SWITCH(xname, reg, shift) \
 337 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 338         .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
 339         .put = wm8994_put_drc_sw, \
 340         .private_value =  SOC_SINGLE_VALUE(reg, shift, 1, 0) }
 341
 342 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
 343                              struct snd_ctl_elem_value *ucontrol)
 344 {
 345         struct soc_mixer_control *mc =
 346                 (struct soc_mixer_control *)kcontrol->private_value;
 347         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 348         int mask, ret;
 349
 350         /* Can't enable both ADC and DAC paths simultaneously */
 351         if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
 352                 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
 353                         WM8994_AIF1ADC1R_DRC_ENA_MASK;
 354         else
 355                 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
 356
 357         ret = snd_soc_read(codec, mc->reg);
 358         if (ret < 0)
 359                 return ret;
 360         if (ret & mask)
 361                 return -EINVAL;
 362
 363         return snd_soc_put_volsw(kcontrol, ucontrol);
 364 }
 365
 366 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
 367 {
 368         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 369         struct wm8994_pdata *pdata = wm8994->pdata;
 370         int base = wm8994_drc_base[drc];
 371         int cfg = wm8994->drc_cfg[drc];
 372         int save, i;
 373
 374         /* Save any enables; the configuration should clear them. */
 375         save = snd_soc_read(codec, base);
 376         save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
 377                 WM8994_AIF1ADC1R_DRC_ENA;
 378
 379         for (i = 0; i < WM8994_DRC_REGS; i++)
 380                 snd_soc_update_bits(codec, base + i, 0xffff,
 381                                     pdata->drc_cfgs[cfg].regs[i]);
 382
 383         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
 384                              WM8994_AIF1ADC1L_DRC_ENA |
 385                              WM8994_AIF1ADC1R_DRC_ENA, save);
 386 }
 387
 388 /* Icky as hell but saves code duplication */
 389 static int wm8994_get_drc(const char *name)
 390 {
 391         if (strcmp(name, "AIF1DRC1 Mode") == 0)
 392                 return 0;
 393         if (strcmp(name, "AIF1DRC2 Mode") == 0)
 394                 return 1;
 395         if (strcmp(name, "AIF2DRC Mode") == 0)
 396                 return 2;
 397         return -EINVAL;
 398 }
 399
 400 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
 401                                struct snd_ctl_elem_value *ucontrol)
 402 {
 403         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 404         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 405         struct wm8994_pdata *pdata = wm8994->pdata;
 406         int drc = wm8994_get_drc(kcontrol->id.name);
 407         int value = ucontrol->value.integer.value[0];
 408
 409         if (drc < 0)
 410                 return drc;
 411
 412         if (value >= pdata->num_drc_cfgs)
 413                 return -EINVAL;
 414
 415         wm8994->drc_cfg[drc] = value;
 416
 417         wm8994_set_drc(codec, drc);
 418
 419         return 0;
 420 }
 421
 422 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
 423                                struct snd_ctl_elem_value *ucontrol)
 424 {
 425         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 426         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 427         int drc = wm8994_get_drc(kcontrol->id.name);
 428
 429         ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
 430
 431         return 0;
 432 }
 433
 434 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
 435 {
 436         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 437         struct wm8994_pdata *pdata = wm8994->pdata;
 438         int base = wm8994_retune_mobile_base[block];
 439         int iface, best, best_val, save, i, cfg;
 440
 441         if (!pdata || !wm8994->num_retune_mobile_texts)
 442                 return;
 443
 444         switch (block) {
 445         case 0:
 446         case 1:
 447                 iface = 0;
 448                 break;
 449         case 2:
 450                 iface = 1;
 451                 break;
 452         default:
 453                 return;
 454         }
 455
 456         /* Find the version of the currently selected configuration
 457          * with the nearest sample rate. */
 458         cfg = wm8994->retune_mobile_cfg[block];
 459         best = 0;
 460         best_val = INT_MAX;
 461         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
 462                 if (strcmp(pdata->retune_mobile_cfgs[i].name,
 463                            wm8994->retune_mobile_texts[cfg]) == 0 &&
 464                     abs(pdata->retune_mobile_cfgs[i].rate
 465                         - wm8994->dac_rates[iface]) < best_val) {
 466                         best = i;
 467                         best_val = abs(pdata->retune_mobile_cfgs[i].rate
 468                                        - wm8994->dac_rates[iface]);
 469                 }
 470         }
 471
 472         dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
 473                 block,
 474                 pdata->retune_mobile_cfgs[best].name,
 475                 pdata->retune_mobile_cfgs[best].rate,
 476                 wm8994->dac_rates[iface]);
 477
 478         /* The EQ will be disabled while reconfiguring it, remember the
 479          * current configuration.
 480          */
 481         save = snd_soc_read(codec, base);
 482         save &= WM8994_AIF1DAC1_EQ_ENA;
 483
 484         for (i = 0; i < WM8994_EQ_REGS; i++)
 485                 snd_soc_update_bits(codec, base + i, 0xffff,
 486                                 pdata->retune_mobile_cfgs[best].regs[i]);
 487
 488         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
 489 }
 490
 491 /* Icky as hell but saves code duplication */
 492 static int wm8994_get_retune_mobile_block(const char *name)
 493 {
 494         if (strcmp(name, "AIF1.1 EQ Mode") == 0)
 495                 return 0;
 496         if (strcmp(name, "AIF1.2 EQ Mode") == 0)
 497                 return 1;
 498         if (strcmp(name, "AIF2 EQ Mode") == 0)
 499                 return 2;
 500         return -EINVAL;
 501 }
 502
 503 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 504                                          struct snd_ctl_elem_value *ucontrol)
 505 {
 506         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 507         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 508         struct wm8994_pdata *pdata = wm8994->pdata;
 509         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
 510         int value = ucontrol->value.integer.value[0];
 511
 512         if (block < 0)
 513                 return block;
 514
 515         if (value >= pdata->num_retune_mobile_cfgs)
 516                 return -EINVAL;
 517
 518         wm8994->retune_mobile_cfg[block] = value;
 519
 520         wm8994_set_retune_mobile(codec, block);
 521
 522         return 0;
 523 }
 524
 525 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 526                                          struct snd_ctl_elem_value *ucontrol)
 527 {
 528         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 529         struct wm8994_priv *wm8994 =snd_soc_codec_get_drvdata(codec);
 530         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
 531
 532         ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
 533
 534         return 0;
 535 }
 536
 537 static const char *aif_chan_src_text[] = {
 538         "Left", "Right"
 539 };
 540
 541 static const struct soc_enum aif1adcl_src =
 542         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
 543
 544 static const struct soc_enum aif1adcr_src =
 545         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
 546
 547 static const struct soc_enum aif2adcl_src =
 548         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
 549
 550 static const struct soc_enum aif2adcr_src =
 551         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
 552
 553 static const struct soc_enum aif1dacl_src =
 554         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
 555
 556 static const struct soc_enum aif1dacr_src =
 557         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
 558
 559 static const struct soc_enum aif2dacl_src =
 560         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
 561
 562 static const struct soc_enum aif2dacr_src =
 563         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
 564
 565 static const char *osr_text[] = {
 566         "Low Power", "High Performance",
 567 };
 568
 569 static const struct soc_enum dac_osr =
 570         SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
 571
 572 static const struct soc_enum adc_osr =
 573         SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
 574
 575 static void wm8958_mbc_apply(struct snd_soc_codec *codec, int mbc, int start)
 576 {
 577         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 578         struct wm8994_pdata *pdata = wm8994->pdata;
 579         int pwr_reg = snd_soc_read(codec, WM8994_POWER_MANAGEMENT_5);
 580         int ena, reg, aif, i;
 581
 582         switch (mbc) {
 583         case 0:
 584                 pwr_reg &= (WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA);
 585                 aif = 0;
 586                 break;
 587         case 1:
 588                 pwr_reg &= (WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
 589                 aif = 0;
 590                 break;
 591         case 2:
 592                 pwr_reg &= (WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA);
 593                 aif = 1;
 594                 break;
 595         default:
 596                 BUG();
 597                 return;
 598         }
 599
 600         /* We can only enable the MBC if the AIF is enabled and we
 601          * want it to be enabled. */
 602         ena = pwr_reg && wm8994->mbc_ena[mbc];
 603
 604         reg = snd_soc_read(codec, WM8958_DSP2_PROGRAM);
 605
 606         dev_dbg(codec->dev, "MBC %d startup: %d, power: %x, DSP: %x\n",
 607                 mbc, start, pwr_reg, reg);
 608
 609         if (start && ena) {
 610                 /* If the DSP is already running then noop */
 611                 if (reg & WM8958_DSP2_ENA)
 612                         return;
 613
 614                 /* Switch the clock over to the appropriate AIF */
 615                 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
 616                                     WM8958_DSP2CLK_SRC | WM8958_DSP2CLK_ENA,
 617                                     aif << WM8958_DSP2CLK_SRC_SHIFT |
 618                                     WM8958_DSP2CLK_ENA);
 619
 620                 snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
 621                                     WM8958_DSP2_ENA, WM8958_DSP2_ENA);
 622
 623                 /* If we've got user supplied MBC settings use them */
 624                 if (pdata && pdata->num_mbc_cfgs) {
 625                         struct wm8958_mbc_cfg *cfg
 626                                 = &pdata->mbc_cfgs[wm8994->mbc_cfg];
 627
 628                         for (i = 0; i < ARRAY_SIZE(cfg->coeff_regs); i++)
 629                                 snd_soc_write(codec, i + WM8958_MBC_BAND_1_K_1,
 630                                               cfg->coeff_regs[i]);
 631
 632                         for (i = 0; i < ARRAY_SIZE(cfg->cutoff_regs); i++)
 633                                 snd_soc_write(codec,
 634                                               i + WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_1,
 635                                               cfg->cutoff_regs[i]);
 636                 }
 637
 638                 /* Run the DSP */
 639                 snd_soc_write(codec, WM8958_DSP2_EXECCONTROL,
 640                               WM8958_DSP2_RUNR);
 641
 642                 /* And we're off! */
 643                 snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
 644                                     WM8958_MBC_ENA | WM8958_MBC_SEL_MASK,
 645                                     mbc << WM8958_MBC_SEL_SHIFT |
 646                                     WM8958_MBC_ENA);
 647         } else {
 648                 /* If the DSP is already stopped then noop */
 649                 if (!(reg & WM8958_DSP2_ENA))
 650                         return;
 651
 652                 snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
 653                                     WM8958_MBC_ENA, 0);
 654                 snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
 655                                     WM8958_DSP2_ENA, 0);
 656                 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
 657                                     WM8958_DSP2CLK_ENA, 0);
 658         }
 659 }
 660
 661 static int wm8958_aif_ev(struct snd_soc_dapm_widget *w,
 662                     struct snd_kcontrol *kcontrol, int event)
 663 {
 664         struct snd_soc_codec *codec = w->codec;
 665         int mbc;
 666
 667         switch (w->shift) {
 668         case 13:
 669         case 12:
 670                 mbc = 2;
 671                 break;
 672         case 11:
 673         case 10:
 674                 mbc = 1;
 675                 break;
 676         case 9:
 677         case 8:
 678                 mbc = 0;
 679                 break;
 680         default:
 681                 BUG();
 682                 return -EINVAL;
 683         }
 684
 685         switch (event) {
 686         case SND_SOC_DAPM_POST_PMU:
 687                 wm8958_mbc_apply(codec, mbc, 1);
 688                 break;
 689         case SND_SOC_DAPM_POST_PMD:
 690                 wm8958_mbc_apply(codec, mbc, 0);
 691                 break;
 692         }
 693
 694         return 0;
 695 }
 696
 697 static int wm8958_put_mbc_enum(struct snd_kcontrol *kcontrol,
 698                                struct snd_ctl_elem_value *ucontrol)
 699 {
 700         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 701         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 702         struct wm8994_pdata *pdata = wm8994->pdata;
 703         int value = ucontrol->value.integer.value[0];
 704         int reg;
 705
 706         /* Don't allow on the fly reconfiguration */
 707         reg = snd_soc_read(codec, WM8994_CLOCKING_1);
 708         if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
 709                 return -EBUSY;
 710
 711         if (value >= pdata->num_mbc_cfgs)
 712                 return -EINVAL;
 713
 714         wm8994->mbc_cfg = value;
 715
 716         return 0;
 717 }
 718
 719 static int wm8958_get_mbc_enum(struct snd_kcontrol *kcontrol,
 720                                struct snd_ctl_elem_value *ucontrol)
 721 {
 722         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 723         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 724
 725         ucontrol->value.enumerated.item[0] = wm8994->mbc_cfg;
 726
 727         return 0;
 728 }
 729
 730 static int wm8958_mbc_info(struct snd_kcontrol *kcontrol,
 731                            struct snd_ctl_elem_info *uinfo)
 732 {
 733         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
 734         uinfo->count = 1;
 735         uinfo->value.integer.min = 0;
 736         uinfo->value.integer.max = 1;
 737         return 0;
 738 }
 739
 740 static int wm8958_mbc_get(struct snd_kcontrol *kcontrol,
 741                           struct snd_ctl_elem_value *ucontrol)
 742 {
 743         int mbc = kcontrol->private_value;
 744         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 745         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 746
 747         ucontrol->value.integer.value[0] = wm8994->mbc_ena[mbc];
 748
 749         return 0;
 750 }
 751
 752 static int wm8958_mbc_put(struct snd_kcontrol *kcontrol,
 753                           struct snd_ctl_elem_value *ucontrol)
 754 {
 755         int mbc = kcontrol->private_value;
 756         int i;
 757         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 758         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 759
 760         if (ucontrol->value.integer.value[0] > 1)
 761                 return -EINVAL;
 762
 763         for (i = 0; i < ARRAY_SIZE(wm8994->mbc_ena); i++) {
 764                 if (mbc != i && wm8994->mbc_ena[i]) {
 765                         dev_dbg(codec->dev, "MBC %d active already\n", mbc);
 766                         return -EBUSY;
 767                 }
 768         }
 769
 770         wm8994->mbc_ena[mbc] = ucontrol->value.integer.value[0];
 771
 772         wm8958_mbc_apply(codec, mbc, wm8994->mbc_ena[mbc]);
 773
 774         return 0;
 775 }
 776
 777 #define WM8958_MBC_SWITCH(xname, xval) {\
 778         .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
 779         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
 780         .info = wm8958_mbc_info, \
 781         .get = wm8958_mbc_get, .put = wm8958_mbc_put, \
 782         .private_value = xval }
 783
 784 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
 785 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
 786                  WM8994_AIF1_ADC1_RIGHT_VOLUME,
 787                  1, 119, 0, digital_tlv),
 788 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
 789                  WM8994_AIF1_ADC2_RIGHT_VOLUME,
 790                  1, 119, 0, digital_tlv),
 791 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
 792                  WM8994_AIF2_ADC_RIGHT_VOLUME,
 793                  1, 119, 0, digital_tlv),
 794
 795 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
 796 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
 797 SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
 798 SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
 799
 800 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
 801 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
 802 SOC_ENUM("AIF2DACL Source", aif2dacl_src),
 803 SOC_ENUM("AIF2DACR Source", aif2dacr_src),
 804
 805 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
 806                  WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 807 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
 808                  WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 809 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
 810                  WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 811
 812 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
 813 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
 814
 815 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
 816 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
 817 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
 818
 819 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
 820 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
 821 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
 822
 823 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
 824 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
 825 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
 826
 827 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
 828 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
 829 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
 830
 831 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
 832                5, 12, 0, st_tlv),
 833 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
 834                0, 12, 0, st_tlv),
 835 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
 836                5, 12, 0, st_tlv),
 837 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
 838                0, 12, 0, st_tlv),
 839 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
 840 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
 841
 842 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
 843 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
 844
 845 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
 846 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
 847
 848 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
 849 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
 850
 851 SOC_ENUM("ADC OSR", adc_osr),
 852 SOC_ENUM("DAC OSR", dac_osr),
 853
 854 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
 855                  WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 856 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
 857              WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
 858
 859 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
 860                  WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 861 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
 862              WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
 863
 864 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
 865                6, 1, 1, wm_hubs_spkmix_tlv),
 866 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
 867                2, 1, 1, wm_hubs_spkmix_tlv),
 868
 869 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
 870                6, 1, 1, wm_hubs_spkmix_tlv),
 871 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
 872                2, 1, 1, wm_hubs_spkmix_tlv),
 873
 874 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
 875                10, 15, 0, wm8994_3d_tlv),
 876 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
 877            8, 1, 0),
 878 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
 879                10, 15, 0, wm8994_3d_tlv),
 880 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
 881            8, 1, 0),
 882 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
 883                10, 15, 0, wm8994_3d_tlv),
 884 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
 885            8, 1, 0),
 886 };
 887
 888 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
 889 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
 890                eq_tlv),
 891 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
 892                eq_tlv),
 893 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
 894                eq_tlv),
 895 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
 896                eq_tlv),
 897 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
 898                eq_tlv),
 899
 900 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
 901                eq_tlv),
 902 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
 903                eq_tlv),
 904 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
 905                eq_tlv),
 906 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
 907                eq_tlv),
 908 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
 909                eq_tlv),
 910
 911 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
 912                eq_tlv),
 913 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
 914                eq_tlv),
 915 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
 916                eq_tlv),
 917 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
 918                eq_tlv),
 919 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
 920                eq_tlv),
 921 };
 922
 923 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
 924 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
 925 WM8958_MBC_SWITCH("AIF1DAC1 MBC Switch", 0),
 926 WM8958_MBC_SWITCH("AIF1DAC2 MBC Switch", 1),
 927 WM8958_MBC_SWITCH("AIF2DAC MBC Switch", 2),
 928 };
 929
 930 static int clk_sys_event(struct snd_soc_dapm_widget *w,
 931                          struct snd_kcontrol *kcontrol, int event)
 932 {
 933         struct snd_soc_codec *codec = w->codec;
 934
 935         switch (event) {
 936         case SND_SOC_DAPM_PRE_PMU:
 937                 return configure_clock(codec);
 938
 939         case SND_SOC_DAPM_POST_PMD:
 940                 configure_clock(codec);
 941                 break;
 942         }
 943
 944         return 0;
 945 }
 946
 947 static void wm8994_update_class_w(struct snd_soc_codec *codec)
 948 {
 949         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 950         int enable = 1;
 951         int source = 0;  /* GCC flow analysis can't track enable */
 952         int reg, reg_r;
 953
 954         /* Only support direct DAC->headphone paths */
 955         reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
 956         if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
 957                 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
 958                 enable = 0;
 959         }
 960
 961         reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
 962         if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
 963                 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
 964                 enable = 0;
 965         }
 966
 967         /* We also need the same setting for L/R and only one path */
 968         reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
 969         switch (reg) {
 970         case WM8994_AIF2DACL_TO_DAC1L:
 971                 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
 972                 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 973                 break;
 974         case WM8994_AIF1DAC2L_TO_DAC1L:
 975                 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
 976                 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 977                 break;
 978         case WM8994_AIF1DAC1L_TO_DAC1L:
 979                 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
 980                 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 981                 break;
 982         default:
 983                 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
 984                 enable = 0;
 985                 break;
 986         }
 987
 988         reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
 989         if (reg_r != reg) {
 990                 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
 991                 enable = 0;
 992         }
 993
 994         if (enable) {
 995                 dev_dbg(codec->dev, "Class W enabled\n");
 996                 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
 997                                     WM8994_CP_DYN_PWR |
 998                                     WM8994_CP_DYN_SRC_SEL_MASK,
 999                                     source | WM8994_CP_DYN_PWR);
1000                 wm8994->hubs.class_w = true;
1001
1002         } else {
1003                 dev_dbg(codec->dev, "Class W disabled\n");
1004                 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
1005                                     WM8994_CP_DYN_PWR, 0);
1006                 wm8994->hubs.class_w = false;
1007         }
1008 }
1009
1010 static int late_enable_ev(struct snd_soc_dapm_widget *w,
1011                           struct snd_kcontrol *kcontrol, int event)
1012 {
1013         struct snd_soc_codec *codec = w->codec;
1014         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1015
1016         switch (event) {
1017         case SND_SOC_DAPM_PRE_PMU:
1018                 if (wm8994->aif1clk_enable)
1019                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1020                                             WM8994_AIF1CLK_ENA_MASK,
1021                                             WM8994_AIF1CLK_ENA);
1022                 if (wm8994->aif2clk_enable)
1023                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1024                                             WM8994_AIF2CLK_ENA_MASK,
1025                                             WM8994_AIF2CLK_ENA);
1026                 break;
1027         }
1028
1029         return 0;
1030 }
1031
1032 static int late_disable_ev(struct snd_soc_dapm_widget *w,
1033                            struct snd_kcontrol *kcontrol, int event)
1034 {
1035         struct snd_soc_codec *codec = w->codec;
1036         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1037
1038         switch (event) {
1039         case SND_SOC_DAPM_POST_PMD:
1040                 if (wm8994->aif1clk_enable) {
1041                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1042                                             WM8994_AIF1CLK_ENA_MASK, 0);
1043                         wm8994->aif1clk_enable = 0;
1044                 }
1045                 if (wm8994->aif2clk_enable) {
1046                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1047                                             WM8994_AIF2CLK_ENA_MASK, 0);
1048                         wm8994->aif2clk_enable = 0;
1049                 }
1050                 break;
1051         }
1052
1053         return 0;
1054 }
1055
1056 static int aif1clk_ev(struct snd_soc_dapm_widget *w,
1057                       struct snd_kcontrol *kcontrol, int event)
1058 {
1059         struct snd_soc_codec *codec = w->codec;
1060         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1061
1062         switch (event) {
1063         case SND_SOC_DAPM_PRE_PMU:
1064                 wm8994->aif1clk_enable = 1;
1065                 break;
1066         }
1067
1068         return 0;
1069 }
1070
1071 static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1072                       struct snd_kcontrol *kcontrol, int event)
1073 {
1074         struct snd_soc_codec *codec = w->codec;
1075         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1076
1077         switch (event) {
1078         case SND_SOC_DAPM_PRE_PMU:
1079                 wm8994->aif2clk_enable = 1;
1080                 break;
1081         }
1082
1083         return 0;
1084 }
1085
1086 static const char *hp_mux_text[] = {
1087         "Mixer",
1088         "DAC",
1089 };
1090
1091 #define WM8994_HP_ENUM(xname, xenum) \
1092 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1093         .info = snd_soc_info_enum_double, \
1094         .get = snd_soc_dapm_get_enum_double, \
1095         .put = wm8994_put_hp_enum, \
1096         .private_value = (unsigned long)&xenum }
1097
1098 static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
1099                               struct snd_ctl_elem_value *ucontrol)
1100 {
1101         struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol);
1102         struct snd_soc_codec *codec = w->codec;
1103         int ret;
1104
1105         ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
1106
1107         wm8994_update_class_w(codec);
1108
1109         return ret;
1110 }
1111
1112 static const struct soc_enum hpl_enum =
1113         SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
1114
1115 static const struct snd_kcontrol_new hpl_mux =
1116         WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
1117
1118 static const struct soc_enum hpr_enum =
1119         SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
1120
1121 static const struct snd_kcontrol_new hpr_mux =
1122         WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
1123
1124 static const char *adc_mux_text[] = {
1125         "ADC",
1126         "DMIC",
1127 };
1128
1129 static const struct soc_enum adc_enum =
1130         SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1131
1132 static const struct snd_kcontrol_new adcl_mux =
1133         SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1134
1135 static const struct snd_kcontrol_new adcr_mux =
1136         SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1137
1138 static const struct snd_kcontrol_new left_speaker_mixer[] = {
1139 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1140 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1141 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1142 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1143 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1144 };
1145
1146 static const struct snd_kcontrol_new right_speaker_mixer[] = {
1147 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1148 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1149 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1150 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1151 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1152 };
1153
1154 /* Debugging; dump chip status after DAPM transitions */
1155 static int post_ev(struct snd_soc_dapm_widget *w,
1156             struct snd_kcontrol *kcontrol, int event)
1157 {
1158         struct snd_soc_codec *codec = w->codec;
1159         dev_dbg(codec->dev, "SRC status: %x\n",
1160                 snd_soc_read(codec,
1161                              WM8994_RATE_STATUS));
1162         return 0;
1163 }
1164
1165 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1166 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1167                 1, 1, 0),
1168 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1169                 0, 1, 0),
1170 };
1171
1172 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1173 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1174                 1, 1, 0),
1175 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1176                 0, 1, 0),
1177 };
1178
1179 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1180 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1181                 1, 1, 0),
1182 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1183                 0, 1, 0),
1184 };
1185
1186 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1187 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1188                 1, 1, 0),
1189 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1190                 0, 1, 0),
1191 };
1192
1193 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1194 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1195                 5, 1, 0),
1196 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1197                 4, 1, 0),
1198 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1199                 2, 1, 0),
1200 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1201                 1, 1, 0),
1202 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1203                 0, 1, 0),
1204 };
1205
1206 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1207 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1208                 5, 1, 0),
1209 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1210                 4, 1, 0),
1211 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1212                 2, 1, 0),
1213 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1214                 1, 1, 0),
1215 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1216                 0, 1, 0),
1217 };
1218
1219 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1220 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1221         .info = snd_soc_info_volsw, \
1222         .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1223         .private_value =  SOC_SINGLE_VALUE(reg, shift, max, invert) }
1224
1225 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1226                               struct snd_ctl_elem_value *ucontrol)
1227 {
1228         struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol);
1229         struct snd_soc_codec *codec = w->codec;
1230         int ret;
1231
1232         ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1233
1234         wm8994_update_class_w(codec);
1235
1236         return ret;
1237 }
1238
1239 static const struct snd_kcontrol_new dac1l_mix[] = {
1240 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1241                       5, 1, 0),
1242 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1243                       4, 1, 0),
1244 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1245                       2, 1, 0),
1246 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1247                       1, 1, 0),
1248 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1249                       0, 1, 0),
1250 };
1251
1252 static const struct snd_kcontrol_new dac1r_mix[] = {
1253 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1254                       5, 1, 0),
1255 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1256                       4, 1, 0),
1257 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1258                       2, 1, 0),
1259 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1260                       1, 1, 0),
1261 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1262                       0, 1, 0),
1263 };
1264
1265 static const char *sidetone_text[] = {
1266         "ADC/DMIC1", "DMIC2",
1267 };
1268
1269 static const struct soc_enum sidetone1_enum =
1270         SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1271
1272 static const struct snd_kcontrol_new sidetone1_mux =
1273         SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1274
1275 static const struct soc_enum sidetone2_enum =
1276         SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1277
1278 static const struct snd_kcontrol_new sidetone2_mux =
1279         SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1280
1281 static const char *aif1dac_text[] = {
1282         "AIF1DACDAT", "AIF3DACDAT",
1283 };
1284
1285 static const struct soc_enum aif1dac_enum =
1286         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1287
1288 static const struct snd_kcontrol_new aif1dac_mux =
1289         SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1290
1291 static const char *aif2dac_text[] = {
1292         "AIF2DACDAT", "AIF3DACDAT",
1293 };
1294
1295 static const struct soc_enum aif2dac_enum =
1296         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1297
1298 static const struct snd_kcontrol_new aif2dac_mux =
1299         SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1300
1301 static const char *aif2adc_text[] = {
1302         "AIF2ADCDAT", "AIF3DACDAT",
1303 };
1304
1305 static const struct soc_enum aif2adc_enum =
1306         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1307
1308 static const struct snd_kcontrol_new aif2adc_mux =
1309         SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1310
1311 static const char *aif3adc_text[] = {
1312         "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1313 };
1314
1315 static const struct soc_enum wm8994_aif3adc_enum =
1316         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1317
1318 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1319         SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1320
1321 static const struct soc_enum wm8958_aif3adc_enum =
1322         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1323
1324 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1325         SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1326
1327 static const char *mono_pcm_out_text[] = {
1328         "None", "AIF2ADCL", "AIF2ADCR",
1329 };
1330
1331 static const struct soc_enum mono_pcm_out_enum =
1332         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1333
1334 static const struct snd_kcontrol_new mono_pcm_out_mux =
1335         SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1336
1337 static const char *aif2dac_src_text[] = {
1338         "AIF2", "AIF3",
1339 };
1340
1341 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1342 static const struct soc_enum aif2dacl_src_enum =
1343         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1344
1345 static const struct snd_kcontrol_new aif2dacl_src_mux =
1346         SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1347
1348 static const struct soc_enum aif2dacr_src_enum =
1349         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1350
1351 static const struct snd_kcontrol_new aif2dacr_src_mux =
1352         SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1353
1354 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1355 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_ev,
1356         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1357 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_ev,
1358         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1359
1360 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1361         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1362 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1363         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1364 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1365         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1366 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1367         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1368
1369 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1370 };
1371
1372 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1373 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
1374 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0)
1375 };
1376
1377 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1378 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1379 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1380 SND_SOC_DAPM_INPUT("Clock"),
1381
1382 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1383                     SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1384
1385 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
1386 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
1387 SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
1388
1389 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1390                      0, WM8994_POWER_MANAGEMENT_4, 9, 0),
1391 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1392                      0, WM8994_POWER_MANAGEMENT_4, 8, 0),
1393 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1394                       WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
1395                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1396 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1397                       WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
1398                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1399
1400 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1401                      0, WM8994_POWER_MANAGEMENT_4, 11, 0),
1402 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1403                      0, WM8994_POWER_MANAGEMENT_4, 10, 0),
1404 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1405                       WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
1406                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1407 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1408                       WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
1409                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1410
1411 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1412                    aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1413 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1414                    aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1415
1416 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1417                    aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1418 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1419                    aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1420
1421 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1422                    aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1423 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1424                    aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1425
1426 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1427 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1428
1429 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1430                    dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1431 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1432                    dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1433
1434 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1435                      WM8994_POWER_MANAGEMENT_4, 13, 0),
1436 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1437                      WM8994_POWER_MANAGEMENT_4, 12, 0),
1438 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1439                       WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
1440                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1441 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1442                       WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
1443                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1444
1445 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1446 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1447 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1448 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1449
1450 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1451 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1452 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1453
1454 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
1455 SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
1456
1457 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1458
1459 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1460 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1461 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1462 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1463
1464 /* Power is done with the muxes since the ADC power also controls the
1465  * downsampling chain, the chip will automatically manage the analogue
1466  * specific portions.
1467  */
1468 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1469 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1470
1471 SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1472 SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1473
1474 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1475 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1476 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1477 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1478
1479 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1480 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1481
1482 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1483                    left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1484 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1485                    right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1486
1487 SND_SOC_DAPM_POST("Debug log", post_ev),
1488 };
1489
1490 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1491 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1492 };
1493
1494 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1495 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1496 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1497 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1498 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1499 };
1500
1501 static const struct snd_soc_dapm_route intercon[] = {
1502         { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1503         { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1504
1505         { "DSP1CLK", NULL, "CLK_SYS" },
1506         { "DSP2CLK", NULL, "CLK_SYS" },
1507         { "DSPINTCLK", NULL, "CLK_SYS" },
1508
1509         { "AIF1ADC1L", NULL, "AIF1CLK" },
1510         { "AIF1ADC1L", NULL, "DSP1CLK" },
1511         { "AIF1ADC1R", NULL, "AIF1CLK" },
1512         { "AIF1ADC1R", NULL, "DSP1CLK" },
1513         { "AIF1ADC1R", NULL, "DSPINTCLK" },
1514
1515         { "AIF1DAC1L", NULL, "AIF1CLK" },
1516         { "AIF1DAC1L", NULL, "DSP1CLK" },
1517         { "AIF1DAC1R", NULL, "AIF1CLK" },
1518         { "AIF1DAC1R", NULL, "DSP1CLK" },
1519         { "AIF1DAC1R", NULL, "DSPINTCLK" },
1520
1521         { "AIF1ADC2L", NULL, "AIF1CLK" },
1522         { "AIF1ADC2L", NULL, "DSP1CLK" },
1523         { "AIF1ADC2R", NULL, "AIF1CLK" },
1524         { "AIF1ADC2R", NULL, "DSP1CLK" },
1525         { "AIF1ADC2R", NULL, "DSPINTCLK" },
1526
1527         { "AIF1DAC2L", NULL, "AIF1CLK" },
1528         { "AIF1DAC2L", NULL, "DSP1CLK" },
1529         { "AIF1DAC2R", NULL, "AIF1CLK" },
1530         { "AIF1DAC2R", NULL, "DSP1CLK" },
1531         { "AIF1DAC2R", NULL, "DSPINTCLK" },
1532
1533         { "AIF2ADCL", NULL, "AIF2CLK" },
1534         { "AIF2ADCL", NULL, "DSP2CLK" },
1535         { "AIF2ADCR", NULL, "AIF2CLK" },
1536         { "AIF2ADCR", NULL, "DSP2CLK" },
1537         { "AIF2ADCR", NULL, "DSPINTCLK" },
1538
1539         { "AIF2DACL", NULL, "AIF2CLK" },
1540         { "AIF2DACL", NULL, "DSP2CLK" },
1541         { "AIF2DACR", NULL, "AIF2CLK" },
1542         { "AIF2DACR", NULL, "DSP2CLK" },
1543         { "AIF2DACR", NULL, "DSPINTCLK" },
1544
1545         { "DMIC1L", NULL, "DMIC1DAT" },
1546         { "DMIC1L", NULL, "CLK_SYS" },
1547         { "DMIC1R", NULL, "DMIC1DAT" },
1548         { "DMIC1R", NULL, "CLK_SYS" },
1549         { "DMIC2L", NULL, "DMIC2DAT" },
1550         { "DMIC2L", NULL, "CLK_SYS" },
1551         { "DMIC2R", NULL, "DMIC2DAT" },
1552         { "DMIC2R", NULL, "CLK_SYS" },
1553
1554         { "ADCL", NULL, "AIF1CLK" },
1555         { "ADCL", NULL, "DSP1CLK" },
1556         { "ADCL", NULL, "DSPINTCLK" },
1557
1558         { "ADCR", NULL, "AIF1CLK" },
1559         { "ADCR", NULL, "DSP1CLK" },
1560         { "ADCR", NULL, "DSPINTCLK" },
1561
1562         { "ADCL Mux", "ADC", "ADCL" },
1563         { "ADCL Mux", "DMIC", "DMIC1L" },
1564         { "ADCR Mux", "ADC", "ADCR" },
1565         { "ADCR Mux", "DMIC", "DMIC1R" },
1566
1567         { "DAC1L", NULL, "AIF1CLK" },
1568         { "DAC1L", NULL, "DSP1CLK" },
1569         { "DAC1L", NULL, "DSPINTCLK" },
1570
1571         { "DAC1R", NULL, "AIF1CLK" },
1572         { "DAC1R", NULL, "DSP1CLK" },
1573         { "DAC1R", NULL, "DSPINTCLK" },
1574
1575         { "DAC2L", NULL, "AIF2CLK" },
1576         { "DAC2L", NULL, "DSP2CLK" },
1577         { "DAC2L", NULL, "DSPINTCLK" },
1578
1579         { "DAC2R", NULL, "AIF2DACR" },
1580         { "DAC2R", NULL, "AIF2CLK" },
1581         { "DAC2R", NULL, "DSP2CLK" },
1582         { "DAC2R", NULL, "DSPINTCLK" },
1583
1584         { "TOCLK", NULL, "CLK_SYS" },
1585
1586         /* AIF1 outputs */
1587         { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1588         { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1589         { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1590
1591         { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1592         { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1593         { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1594
1595         { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1596         { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1597         { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1598
1599         { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1600         { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1601         { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1602
1603         /* Pin level routing for AIF3 */
1604         { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1605         { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1606         { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1607         { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1608
1609         { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1610         { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1611         { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1612         { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1613         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1614         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1615         { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1616
1617         /* DAC1 inputs */
1618         { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1619         { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1620         { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1621         { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1622         { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1623
1624         { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1625         { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1626         { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1627         { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1628         { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1629
1630         /* DAC2/AIF2 outputs  */
1631         { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1632         { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1633         { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1634         { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1635         { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1636         { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1637
1638         { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1639         { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1640         { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1641         { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1642         { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1643         { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1644
1645         { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1646         { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1647         { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1648         { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1649
1650         { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1651
1652         /* AIF3 output */
1653         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1654         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1655         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1656         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1657         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1658         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1659         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1660         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1661
1662         /* Sidetone */
1663         { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1664         { "Left Sidetone", "DMIC2", "DMIC2L" },
1665         { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1666         { "Right Sidetone", "DMIC2", "DMIC2R" },
1667
1668         /* Output stages */
1669         { "Left Output Mixer", "DAC Switch", "DAC1L" },
1670         { "Right Output Mixer", "DAC Switch", "DAC1R" },
1671
1672         { "SPKL", "DAC1 Switch", "DAC1L" },
1673         { "SPKL", "DAC2 Switch", "DAC2L" },
1674
1675         { "SPKR", "DAC1 Switch", "DAC1R" },
1676         { "SPKR", "DAC2 Switch", "DAC2R" },
1677
1678         { "Left Headphone Mux", "DAC", "DAC1L" },
1679         { "Right Headphone Mux", "DAC", "DAC1R" },
1680 };
1681
1682 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1683         { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1684         { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1685         { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1686         { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1687         { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1688         { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1689         { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1690         { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1691 };
1692
1693 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1694         { "DAC1L", NULL, "DAC1L Mixer" },
1695         { "DAC1R", NULL, "DAC1R Mixer" },
1696         { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1697         { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1698 };
1699
1700 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1701         { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1702         { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1703         { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1704         { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
1705 };
1706
1707 static const struct snd_soc_dapm_route wm8994_intercon[] = {
1708         { "AIF2DACL", NULL, "AIF2DAC Mux" },
1709         { "AIF2DACR", NULL, "AIF2DAC Mux" },
1710 };
1711
1712 static const struct snd_soc_dapm_route wm8958_intercon[] = {
1713         { "AIF2DACL", NULL, "AIF2DACL Mux" },
1714         { "AIF2DACR", NULL, "AIF2DACR Mux" },
1715
1716         { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1717         { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1718         { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1719         { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1720
1721         { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1722         { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1723
1724         { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1725 };
1726
1727 /* The size in bits of the FLL divide multiplied by 10
1728  * to allow rounding later */
1729 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1730
1731 struct fll_div {
1732         u16 outdiv;
1733         u16 n;
1734         u16 k;
1735         u16 clk_ref_div;
1736         u16 fll_fratio;
1737 };
1738
1739 static int wm8994_get_fll_config(struct fll_div *fll,
1740                                  int freq_in, int freq_out)
1741 {
1742         u64 Kpart;
1743         unsigned int K, Ndiv, Nmod;
1744
1745         pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1746
1747         /* Scale the input frequency down to <= 13.5MHz */
1748         fll->clk_ref_div = 0;
1749         while (freq_in > 13500000) {
1750                 fll->clk_ref_div++;
1751                 freq_in /= 2;
1752
1753                 if (fll->clk_ref_div > 3)
1754                         return -EINVAL;
1755         }
1756         pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1757
1758         /* Scale the output to give 90MHz<=Fvco<=100MHz */
1759         fll->outdiv = 3;
1760         while (freq_out * (fll->outdiv + 1) < 90000000) {
1761                 fll->outdiv++;
1762                 if (fll->outdiv > 63)
1763                         return -EINVAL;
1764         }
1765         freq_out *= fll->outdiv + 1;
1766         pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1767
1768         if (freq_in > 1000000) {
1769                 fll->fll_fratio = 0;
1770         } else if (freq_in > 256000) {
1771                 fll->fll_fratio = 1;
1772                 freq_in *= 2;
1773         } else if (freq_in > 128000) {
1774                 fll->fll_fratio = 2;
1775                 freq_in *= 4;
1776         } else if (freq_in > 64000) {
1777                 fll->fll_fratio = 3;
1778                 freq_in *= 8;
1779         } else {
1780                 fll->fll_fratio = 4;
1781                 freq_in *= 16;
1782         }
1783         pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1784
1785         /* Now, calculate N.K */
1786         Ndiv = freq_out / freq_in;
1787
1788         fll->n = Ndiv;
1789         Nmod = freq_out % freq_in;
1790         pr_debug("Nmod=%d\n", Nmod);
1791
1792         /* Calculate fractional part - scale up so we can round. */
1793         Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1794
1795         do_div(Kpart, freq_in);
1796
1797         K = Kpart & 0xFFFFFFFF;
1798
1799         if ((K % 10) >= 5)
1800                 K += 5;
1801
1802         /* Move down to proper range now rounding is done */
1803         fll->k = K / 10;
1804
1805         pr_debug("N=%x K=%x\n", fll->n, fll->k);
1806
1807         return 0;
1808 }
1809
1810 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
1811                           unsigned int freq_in, unsigned int freq_out)
1812 {
1813         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1814         int reg_offset, ret;
1815         struct fll_div fll;
1816         u16 reg, aif1, aif2;
1817
1818         aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
1819                 & WM8994_AIF1CLK_ENA;
1820
1821         aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
1822                 & WM8994_AIF2CLK_ENA;
1823
1824         switch (id) {
1825         case WM8994_FLL1:
1826                 reg_offset = 0;
1827                 id = 0;
1828                 break;
1829         case WM8994_FLL2:
1830                 reg_offset = 0x20;
1831                 id = 1;
1832                 break;
1833         default:
1834                 return -EINVAL;
1835         }
1836
1837         switch (src) {
1838         case 0:
1839                 /* Allow no source specification when stopping */
1840                 if (freq_out)
1841                         return -EINVAL;
1842                 src = wm8994->fll[id].src;
1843                 break;
1844         case WM8994_FLL_SRC_MCLK1:
1845         case WM8994_FLL_SRC_MCLK2:
1846         case WM8994_FLL_SRC_LRCLK:
1847         case WM8994_FLL_SRC_BCLK:
1848                 break;
1849         default:
1850                 return -EINVAL;
1851         }
1852
1853         /* Are we changing anything? */
1854         if (wm8994->fll[id].src == src &&
1855             wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
1856                 return 0;
1857
1858         /* If we're stopping the FLL redo the old config - no
1859          * registers will actually be written but we avoid GCC flow
1860          * analysis bugs spewing warnings.
1861          */
1862         if (freq_out)
1863                 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
1864         else
1865                 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
1866                                             wm8994->fll[id].out);
1867         if (ret < 0)
1868                 return ret;
1869
1870         /* Gate the AIF clocks while we reclock */
1871         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1872                             WM8994_AIF1CLK_ENA, 0);
1873         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1874                             WM8994_AIF2CLK_ENA, 0);
1875
1876         /* We always need to disable the FLL while reconfiguring */
1877         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1878                             WM8994_FLL1_ENA, 0);
1879
1880         reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
1881                 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
1882         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
1883                             WM8994_FLL1_OUTDIV_MASK |
1884                             WM8994_FLL1_FRATIO_MASK, reg);
1885
1886         snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k);
1887
1888         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
1889                             WM8994_FLL1_N_MASK,
1890                                     fll.n << WM8994_FLL1_N_SHIFT);
1891
1892         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
1893                             WM8994_FLL1_REFCLK_DIV_MASK |
1894                             WM8994_FLL1_REFCLK_SRC_MASK,
1895                             (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
1896                             (src - 1));
1897
1898         /* Enable (with fractional mode if required) */
1899         if (freq_out) {
1900                 if (fll.k)
1901                         reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
1902                 else
1903                         reg = WM8994_FLL1_ENA;
1904                 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1905                                     WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
1906                                     reg);
1907         }
1908
1909         wm8994->fll[id].in = freq_in;
1910         wm8994->fll[id].out = freq_out;
1911         wm8994->fll[id].src = src;
1912
1913         /* Enable any gated AIF clocks */
1914         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1915                             WM8994_AIF1CLK_ENA, aif1);
1916         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1917                             WM8994_AIF2CLK_ENA, aif2);
1918
1919         configure_clock(codec);
1920
1921         return 0;
1922 }
1923
1924
1925 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
1926
1927 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
1928                           unsigned int freq_in, unsigned int freq_out)
1929 {
1930         return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
1931 }
1932
1933 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
1934                 int clk_id, unsigned int freq, int dir)
1935 {
1936         struct snd_soc_codec *codec = dai->codec;
1937         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1938         int i;
1939
1940         switch (dai->id) {
1941         case 1:
1942         case 2:
1943                 break;
1944
1945         default:
1946                 /* AIF3 shares clocking with AIF1/2 */
1947                 return -EINVAL;
1948         }
1949
1950         switch (clk_id) {
1951         case WM8994_SYSCLK_MCLK1:
1952                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
1953                 wm8994->mclk[0] = freq;
1954                 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
1955                         dai->id, freq);
1956                 break;
1957
1958         case WM8994_SYSCLK_MCLK2:
1959                 /* TODO: Set GPIO AF */
1960                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
1961                 wm8994->mclk[1] = freq;
1962                 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
1963                         dai->id, freq);
1964                 break;
1965
1966         case WM8994_SYSCLK_FLL1:
1967                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
1968                 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
1969                 break;
1970
1971         case WM8994_SYSCLK_FLL2:
1972                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
1973                 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
1974                 break;
1975
1976         case WM8994_SYSCLK_OPCLK:
1977                 /* Special case - a division (times 10) is given and
1978                  * no effect on main clocking.
1979                  */
1980                 if (freq) {
1981                         for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
1982                                 if (opclk_divs[i] == freq)
1983                                         break;
1984                         if (i == ARRAY_SIZE(opclk_divs))
1985                                 return -EINVAL;
1986                         snd_soc_update_bits(codec, WM8994_CLOCKING_2,
1987                                             WM8994_OPCLK_DIV_MASK, i);
1988                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
1989                                             WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
1990                 } else {
1991                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
1992                                             WM8994_OPCLK_ENA, 0);
1993                 }
1994
1995         default:
1996                 return -EINVAL;
1997         }
1998
1999         configure_clock(codec);
2000
2001         return 0;
2002 }
2003
2004 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2005                                  enum snd_soc_bias_level level)
2006 {
2007         struct wm8994 *control = codec->control_data;
2008         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2009
2010         switch (level) {
2011         case SND_SOC_BIAS_ON:
2012                 break;
2013
2014         case SND_SOC_BIAS_PREPARE:
2015                 /* VMID=2x40k */
2016                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
2017                                     WM8994_VMID_SEL_MASK, 0x2);
2018                 break;
2019
2020         case SND_SOC_BIAS_STANDBY:
2021                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
2022                         pm_runtime_get_sync(codec->dev);
2023
2024                         switch (control->type) {
2025                         case WM8994:
2026                                 if (wm8994->revision < 4) {
2027                                         /* Tweak DC servo and DSP
2028                                          * configuration for improved
2029                                          * performance. */
2030                                         snd_soc_write(codec, 0x102, 0x3);
2031                                         snd_soc_write(codec, 0x56, 0x3);
2032                                         snd_soc_write(codec, 0x817, 0);
2033                                         snd_soc_write(codec, 0x102, 0);
2034                                 }
2035                                 break;
2036
2037                         case WM8958:
2038                                 if (wm8994->revision == 0) {
2039                                         /* Optimise performance for rev A */
2040                                         snd_soc_write(codec, 0x102, 0x3);
2041                                         snd_soc_write(codec, 0xcb, 0x81);
2042                                         snd_soc_write(codec, 0x817, 0);
2043                                         snd_soc_write(codec, 0x102, 0);
2044
2045                                         snd_soc_update_bits(codec,
2046                                                             WM8958_CHARGE_PUMP_2,
2047                                                             WM8958_CP_DISCH,
2048                                                             WM8958_CP_DISCH);
2049                                 }
2050                                 break;
2051                         }
2052
2053                         /* Discharge LINEOUT1 & 2 */
2054                         snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2055                                             WM8994_LINEOUT1_DISCH |
2056                                             WM8994_LINEOUT2_DISCH,
2057                                             WM8994_LINEOUT1_DISCH |
2058                                             WM8994_LINEOUT2_DISCH);
2059
2060                         /* Startup bias, VMID ramp & buffer */
2061                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2062                                             WM8994_STARTUP_BIAS_ENA |
2063                                             WM8994_VMID_BUF_ENA |
2064                                             WM8994_VMID_RAMP_MASK,
2065                                             WM8994_STARTUP_BIAS_ENA |
2066                                             WM8994_VMID_BUF_ENA |
2067                                             (0x11 << WM8994_VMID_RAMP_SHIFT));
2068
2069                         /* Main bias enable, VMID=2x40k */
2070                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
2071                                             WM8994_BIAS_ENA |
2072                                             WM8994_VMID_SEL_MASK,
2073                                             WM8994_BIAS_ENA | 0x2);
2074
2075                         msleep(20);
2076                 }
2077
2078                 /* VMID=2x500k */
2079                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
2080                                     WM8994_VMID_SEL_MASK, 0x4);
2081
2082                 break;
2083
2084         case SND_SOC_BIAS_OFF:
2085                 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
2086                         /* Switch over to startup biases */
2087                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2088                                             WM8994_BIAS_SRC |
2089                                             WM8994_STARTUP_BIAS_ENA |
2090                                             WM8994_VMID_BUF_ENA |
2091                                             WM8994_VMID_RAMP_MASK,
2092                                             WM8994_BIAS_SRC |
2093                                             WM8994_STARTUP_BIAS_ENA |
2094                                             WM8994_VMID_BUF_ENA |
2095                                             (1 << WM8994_VMID_RAMP_SHIFT));
2096
2097                         /* Disable main biases */
2098                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
2099                                             WM8994_BIAS_ENA |
2100                                             WM8994_VMID_SEL_MASK, 0);
2101
2102                         /* Discharge line */
2103                         snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2104                                             WM8994_LINEOUT1_DISCH |
2105                                             WM8994_LINEOUT2_DISCH,
2106                                             WM8994_LINEOUT1_DISCH |
2107                                             WM8994_LINEOUT2_DISCH);
2108
2109                         msleep(5);
2110
2111                         /* Switch off startup biases */
2112                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2113                                             WM8994_BIAS_SRC |
2114                                             WM8994_STARTUP_BIAS_ENA |
2115                                             WM8994_VMID_BUF_ENA |
2116                                             WM8994_VMID_RAMP_MASK, 0);
2117
2118                         pm_runtime_put(codec->dev);
2119                 }
2120                 break;
2121         }
2122         codec->dapm.bias_level = level;
2123         return 0;
2124 }
2125
2126 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2127 {
2128         struct snd_soc_codec *codec = dai->codec;
2129         struct wm8994 *control = codec->control_data;
2130         int ms_reg;
2131         int aif1_reg;
2132         int ms = 0;
2133         int aif1 = 0;
2134
2135         switch (dai->id) {
2136         case 1:
2137                 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2138                 aif1_reg = WM8994_AIF1_CONTROL_1;
2139                 break;
2140         case 2:
2141                 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2142                 aif1_reg = WM8994_AIF2_CONTROL_1;
2143                 break;
2144         default:
2145                 return -EINVAL;
2146         }
2147
2148         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2149         case SND_SOC_DAIFMT_CBS_CFS:
2150                 break;
2151         case SND_SOC_DAIFMT_CBM_CFM:
2152                 ms = WM8994_AIF1_MSTR;
2153                 break;
2154         default:
2155                 return -EINVAL;
2156         }
2157
2158         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2159         case SND_SOC_DAIFMT_DSP_B:
2160                 aif1 |= WM8994_AIF1_LRCLK_INV;
2161         case SND_SOC_DAIFMT_DSP_A:
2162                 aif1 |= 0x18;
2163                 break;
2164         case SND_SOC_DAIFMT_I2S:
2165                 aif1 |= 0x10;
2166                 break;
2167         case SND_SOC_DAIFMT_RIGHT_J:
2168                 break;
2169         case SND_SOC_DAIFMT_LEFT_J:
2170                 aif1 |= 0x8;
2171                 break;
2172         default:
2173                 return -EINVAL;
2174         }
2175
2176         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2177         case SND_SOC_DAIFMT_DSP_A:
2178         case SND_SOC_DAIFMT_DSP_B:
2179                 /* frame inversion not valid for DSP modes */
2180                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2181                 case SND_SOC_DAIFMT_NB_NF:
2182                         break;
2183                 case SND_SOC_DAIFMT_IB_NF:
2184                         aif1 |= WM8994_AIF1_BCLK_INV;
2185                         break;
2186                 default:
2187                         return -EINVAL;
2188                 }
2189                 break;
2190
2191         case SND_SOC_DAIFMT_I2S:
2192         case SND_SOC_DAIFMT_RIGHT_J:
2193         case SND_SOC_DAIFMT_LEFT_J:
2194                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2195                 case SND_SOC_DAIFMT_NB_NF:
2196                         break;
2197                 case SND_SOC_DAIFMT_IB_IF:
2198                         aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2199                         break;
2200                 case SND_SOC_DAIFMT_IB_NF:
2201                         aif1 |= WM8994_AIF1_BCLK_INV;
2202                         break;
2203                 case SND_SOC_DAIFMT_NB_IF:
2204                         aif1 |= WM8994_AIF1_LRCLK_INV;
2205                         break;
2206                 default:
2207                         return -EINVAL;
2208                 }
2209                 break;
2210         default:
2211                 return -EINVAL;
2212         }
2213
2214         /* The AIF2 format configuration needs to be mirrored to AIF3
2215          * on WM8958 if it's in use so just do it all the time. */
2216         if (control->type == WM8958 && dai->id == 2)
2217                 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2218                                     WM8994_AIF1_LRCLK_INV |
2219                                     WM8958_AIF3_FMT_MASK, aif1);
2220
2221         snd_soc_update_bits(codec, aif1_reg,
2222                             WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2223                             WM8994_AIF1_FMT_MASK,
2224                             aif1);
2225         snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2226                             ms);
2227
2228         return 0;
2229 }
2230
2231 static struct {
2232         int val, rate;
2233 } srs[] = {
2234         { 0,   8000 },
2235         { 1,  11025 },
2236         { 2,  12000 },
2237         { 3,  16000 },
2238         { 4,  22050 },
2239         { 5,  24000 },
2240         { 6,  32000 },
2241         { 7,  44100 },
2242         { 8,  48000 },
2243         { 9,  88200 },
2244         { 10, 96000 },
2245 };
2246
2247 static int fs_ratios[] = {
2248         64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2249 };
2250
2251 static int bclk_divs[] = {
2252         10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2253         640, 880, 960, 1280, 1760, 1920
2254 };
2255
2256 static int wm8994_hw_params(struct snd_pcm_substream *substream,
2257                             struct snd_pcm_hw_params *params,
2258                             struct snd_soc_dai *dai)
2259 {
2260         struct snd_soc_codec *codec = dai->codec;
2261         struct wm8994 *control = codec->control_data;
2262         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2263         int aif1_reg;
2264         int aif2_reg;
2265         int bclk_reg;
2266         int lrclk_reg;
2267         int rate_reg;
2268         int aif1 = 0;
2269         int aif2 = 0;
2270         int bclk = 0;
2271         int lrclk = 0;
2272         int rate_val = 0;
2273         int id = dai->id - 1;
2274
2275         int i, cur_val, best_val, bclk_rate, best;
2276
2277         switch (dai->id) {
2278         case 1:
2279                 aif1_reg = WM8994_AIF1_CONTROL_1;
2280                 aif2_reg = WM8994_AIF1_CONTROL_2;
2281                 bclk_reg = WM8994_AIF1_BCLK;
2282                 rate_reg = WM8994_AIF1_RATE;
2283                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2284                     wm8994->lrclk_shared[0]) {
2285                         lrclk_reg = WM8994_AIF1DAC_LRCLK;
2286                 } else {
2287                         lrclk_reg = WM8994_AIF1ADC_LRCLK;
2288                         dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2289                 }
2290                 break;
2291         case 2:
2292                 aif1_reg = WM8994_AIF2_CONTROL_1;
2293                 aif2_reg = WM8994_AIF2_CONTROL_2;
2294                 bclk_reg = WM8994_AIF2_BCLK;
2295                 rate_reg = WM8994_AIF2_RATE;
2296                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2297                     wm8994->lrclk_shared[1]) {
2298                         lrclk_reg = WM8994_AIF2DAC_LRCLK;
2299                 } else {
2300                         lrclk_reg = WM8994_AIF2ADC_LRCLK;
2301                         dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2302                 }
2303                 break;
2304         case 3:
2305                 switch (control->type) {
2306                 case WM8958:
2307                         aif1_reg = WM8958_AIF3_CONTROL_1;
2308                         break;
2309                 default:
2310                         return 0;
2311                 }
2312         default:
2313                 return -EINVAL;
2314         }
2315
2316         bclk_rate = params_rate(params) * 2;
2317         switch (params_format(params)) {
2318         case SNDRV_PCM_FORMAT_S16_LE:
2319                 bclk_rate *= 16;
2320                 break;
2321         case SNDRV_PCM_FORMAT_S20_3LE:
2322                 bclk_rate *= 20;
2323                 aif1 |= 0x20;
2324                 break;
2325         case SNDRV_PCM_FORMAT_S24_LE:
2326                 bclk_rate *= 24;
2327                 aif1 |= 0x40;
2328                 break;
2329         case SNDRV_PCM_FORMAT_S32_LE:
2330                 bclk_rate *= 32;
2331                 aif1 |= 0x60;
2332                 break;
2333         default:
2334                 return -EINVAL;
2335         }
2336
2337         /* Try to find an appropriate sample rate; look for an exact match. */
2338         for (i = 0; i < ARRAY_SIZE(srs); i++)
2339                 if (srs[i].rate == params_rate(params))
2340                         break;
2341         if (i == ARRAY_SIZE(srs))
2342                 return -EINVAL;
2343         rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2344
2345         dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2346         dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2347                 dai->id, wm8994->aifclk[id], bclk_rate);
2348
2349         if (params_channels(params) == 1 &&
2350             (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2351                 aif2 |= WM8994_AIF1_MONO;
2352
2353         if (wm8994->aifclk[id] == 0) {
2354                 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2355                 return -EINVAL;
2356         }
2357
2358         /* AIFCLK/fs ratio; look for a close match in either direction */
2359         best = 0;
2360         best_val = abs((fs_ratios[0] * params_rate(params))
2361                        - wm8994->aifclk[id]);
2362         for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2363                 cur_val = abs((fs_ratios[i] * params_rate(params))
2364                               - wm8994->aifclk[id]);
2365                 if (cur_val >= best_val)
2366                         continue;
2367                 best = i;
2368                 best_val = cur_val;
2369         }
2370         dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2371                 dai->id, fs_ratios[best]);
2372         rate_val |= best;
2373
2374         /* We may not get quite the right frequency if using
2375          * approximate clocks so look for the closest match that is
2376          * higher than the target (we need to ensure that there enough
2377          * BCLKs to clock out the samples).
2378          */
2379         best = 0;
2380         for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2381                 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2382                 if (cur_val < 0) /* BCLK table is sorted */
2383                         break;
2384                 best = i;
2385         }
2386         bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2387         dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2388                 bclk_divs[best], bclk_rate);
2389         bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2390
2391         lrclk = bclk_rate / params_rate(params);
2392         dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2393                 lrclk, bclk_rate / lrclk);
2394
2395         snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2396         snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
2397         snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2398         snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2399                             lrclk);
2400         snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2401                             WM8994_AIF1CLK_RATE_MASK, rate_val);
2402
2403         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2404                 switch (dai->id) {
2405                 case 1:
2406                         wm8994->dac_rates[0] = params_rate(params);
2407                         wm8994_set_retune_mobile(codec, 0);
2408                         wm8994_set_retune_mobile(codec, 1);
2409                         break;
2410                 case 2:
2411                         wm8994->dac_rates[1] = params_rate(params);
2412                         wm8994_set_retune_mobile(codec, 2);
2413                         break;
2414                 }
2415         }
2416
2417         return 0;
2418 }
2419
2420 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2421                                  struct snd_pcm_hw_params *params,
2422                                  struct snd_soc_dai *dai)
2423 {
2424         struct snd_soc_codec *codec = dai->codec;
2425         struct wm8994 *control = codec->control_data;
2426         int aif1_reg;
2427         int aif1 = 0;
2428
2429         switch (dai->id) {
2430         case 3:
2431                 switch (control->type) {
2432                 case WM8958:
2433                         aif1_reg = WM8958_AIF3_CONTROL_1;
2434                         break;
2435                 default:
2436                         return 0;
2437                 }
2438         default:
2439                 return 0;
2440         }
2441
2442         switch (params_format(params)) {
2443         case SNDRV_PCM_FORMAT_S16_LE:
2444                 break;
2445         case SNDRV_PCM_FORMAT_S20_3LE:
2446                 aif1 |= 0x20;
2447                 break;
2448         case SNDRV_PCM_FORMAT_S24_LE:
2449                 aif1 |= 0x40;
2450                 break;
2451         case SNDRV_PCM_FORMAT_S32_LE:
2452                 aif1 |= 0x60;
2453                 break;
2454         default:
2455                 return -EINVAL;
2456         }
2457
2458         return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2459 }
2460
2461 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2462 {
2463         struct snd_soc_codec *codec = codec_dai->codec;
2464         int mute_reg;
2465         int reg;
2466
2467         switch (codec_dai->id) {
2468         case 1:
2469                 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2470                 break;
2471         case 2:
2472                 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2473                 break;
2474         default:
2475                 return -EINVAL;
2476         }
2477
2478         if (mute)
2479                 reg = WM8994_AIF1DAC1_MUTE;
2480         else
2481                 reg = 0;
2482
2483         snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2484
2485         return 0;
2486 }
2487
2488 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2489 {
2490         struct snd_soc_codec *codec = codec_dai->codec;
2491         int reg, val, mask;
2492
2493         switch (codec_dai->id) {
2494         case 1:
2495                 reg = WM8994_AIF1_MASTER_SLAVE;
2496                 mask = WM8994_AIF1_TRI;
2497                 break;
2498         case 2:
2499                 reg = WM8994_AIF2_MASTER_SLAVE;
2500                 mask = WM8994_AIF2_TRI;
2501                 break;
2502         case 3:
2503                 reg = WM8994_POWER_MANAGEMENT_6;
2504                 mask = WM8994_AIF3_TRI;
2505                 break;
2506         default:
2507                 return -EINVAL;
2508         }
2509
2510         if (tristate)
2511                 val = mask;
2512         else
2513                 val = 0;
2514
2515         return snd_soc_update_bits(codec, reg, mask, val);
2516 }
2517
2518 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2519
2520 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2521                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2522
2523 static struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2524         .set_sysclk     = wm8994_set_dai_sysclk,
2525         .set_fmt        = wm8994_set_dai_fmt,
2526         .hw_params      = wm8994_hw_params,
2527         .digital_mute   = wm8994_aif_mute,
2528         .set_pll        = wm8994_set_fll,
2529         .set_tristate   = wm8994_set_tristate,
2530 };
2531
2532 static struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2533         .set_sysclk     = wm8994_set_dai_sysclk,
2534         .set_fmt        = wm8994_set_dai_fmt,
2535         .hw_params      = wm8994_hw_params,
2536         .digital_mute   = wm8994_aif_mute,
2537         .set_pll        = wm8994_set_fll,
2538         .set_tristate   = wm8994_set_tristate,
2539 };
2540
2541 static struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
2542         .hw_params      = wm8994_aif3_hw_params,
2543         .set_tristate   = wm8994_set_tristate,
2544 };
2545
2546 static struct snd_soc_dai_driver wm8994_dai[] = {
2547         {
2548                 .name = "wm8994-aif1",
2549                 .id = 1,
2550                 .playback = {
2551                         .stream_name = "AIF1 Playback",
2552                         .channels_min = 1,
2553                         .channels_max = 2,
2554                         .rates = WM8994_RATES,
2555                         .formats = WM8994_FORMATS,
2556                 },
2557                 .capture = {
2558                         .stream_name = "AIF1 Capture",
2559                         .channels_min = 1,
2560                         .channels_max = 2,
2561                         .rates = WM8994_RATES,
2562                         .formats = WM8994_FORMATS,
2563                  },
2564                 .ops = &wm8994_aif1_dai_ops,
2565         },
2566         {
2567                 .name = "wm8994-aif2",
2568                 .id = 2,
2569                 .playback = {
2570                         .stream_name = "AIF2 Playback",
2571                         .channels_min = 1,
2572                         .channels_max = 2,
2573                         .rates = WM8994_RATES,
2574                         .formats = WM8994_FORMATS,
2575                 },
2576                 .capture = {
2577                         .stream_name = "AIF2 Capture",
2578                         .channels_min = 1,
2579                         .channels_max = 2,
2580                         .rates = WM8994_RATES,
2581                         .formats = WM8994_FORMATS,
2582                 },
2583                 .ops = &wm8994_aif2_dai_ops,
2584         },
2585         {
2586                 .name = "wm8994-aif3",
2587                 .id = 3,
2588                 .playback = {
2589                         .stream_name = "AIF3 Playback",
2590                         .channels_min = 1,
2591                         .channels_max = 2,
2592                         .rates = WM8994_RATES,
2593                         .formats = WM8994_FORMATS,
2594                 },
2595                 .capture = {
2596                         .stream_name = "AIF3 Capture",
2597                         .channels_min = 1,
2598                         .channels_max = 2,
2599                         .rates = WM8994_RATES,
2600                         .formats = WM8994_FORMATS,
2601                 },
2602                 .ops = &wm8994_aif3_dai_ops,
2603         }
2604 };
2605
2606 #ifdef CONFIG_PM
2607 static int wm8994_suspend(struct snd_soc_codec *codec, pm_message_t state)
2608 {
2609         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2610         int i, ret;
2611
2612         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2613                 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
2614                        sizeof(struct fll_config));
2615                 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
2616                 if (ret < 0)
2617                         dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2618                                  i + 1, ret);
2619         }
2620
2621         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2622
2623         return 0;
2624 }
2625
2626 static int wm8994_resume(struct snd_soc_codec *codec)
2627 {
2628         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2629         int i, ret;
2630
2631         /* Restore the registers */
2632         ret = snd_soc_cache_sync(codec);
2633         if (ret != 0)
2634                 dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
2635
2636         wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2637
2638         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2639                 if (!wm8994->fll_suspend[i].out)
2640                         continue;
2641
2642                 ret = _wm8994_set_fll(codec, i + 1,
2643                                      wm8994->fll_suspend[i].src,
2644                                      wm8994->fll_suspend[i].in,
2645                                      wm8994->fll_suspend[i].out);
2646                 if (ret < 0)
2647                         dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2648                                  i + 1, ret);
2649         }
2650
2651         return 0;
2652 }
2653 #else
2654 #define wm8994_suspend NULL
2655 #define wm8994_resume NULL
2656 #endif
2657
2658 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2659 {
2660         struct snd_soc_codec *codec = wm8994->codec;
2661         struct wm8994_pdata *pdata = wm8994->pdata;
2662         struct snd_kcontrol_new controls[] = {
2663                 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2664                              wm8994->retune_mobile_enum,
2665                              wm8994_get_retune_mobile_enum,
2666                              wm8994_put_retune_mobile_enum),
2667                 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2668                              wm8994->retune_mobile_enum,
2669                              wm8994_get_retune_mobile_enum,
2670                              wm8994_put_retune_mobile_enum),
2671                 SOC_ENUM_EXT("AIF2 EQ Mode",
2672                              wm8994->retune_mobile_enum,
2673                              wm8994_get_retune_mobile_enum,
2674                              wm8994_put_retune_mobile_enum),
2675         };
2676         int ret, i, j;
2677         const char **t;
2678
2679         /* We need an array of texts for the enum API but the number
2680          * of texts is likely to be less than the number of
2681          * configurations due to the sample rate dependency of the
2682          * configurations. */
2683         wm8994->num_retune_mobile_texts = 0;
2684         wm8994->retune_mobile_texts = NULL;
2685         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2686                 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2687                         if (strcmp(pdata->retune_mobile_cfgs[i].name,
2688                                    wm8994->retune_mobile_texts[j]) == 0)
2689                                 break;
2690                 }
2691
2692                 if (j != wm8994->num_retune_mobile_texts)
2693                         continue;
2694
2695                 /* Expand the array... */
2696                 t = krealloc(wm8994->retune_mobile_texts,
2697                              sizeof(char *) *
2698                              (wm8994->num_retune_mobile_texts + 1),
2699                              GFP_KERNEL);
2700                 if (t == NULL)
2701                         continue;
2702
2703                 /* ...store the new entry... */
2704                 t[wm8994->num_retune_mobile_texts] =
2705                         pdata->retune_mobile_cfgs[i].name;
2706
2707                 /* ...and remember the new version. */
2708                 wm8994->num_retune_mobile_texts++;
2709                 wm8994->retune_mobile_texts = t;
2710         }
2711
2712         dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2713                 wm8994->num_retune_mobile_texts);
2714
2715         wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
2716         wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
2717
2718         ret = snd_soc_add_controls(wm8994->codec, controls,
2719                                    ARRAY_SIZE(controls));
2720         if (ret != 0)
2721                 dev_err(wm8994->codec->dev,
2722                         "Failed to add ReTune Mobile controls: %d\n", ret);
2723 }
2724
2725 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
2726 {
2727         struct snd_soc_codec *codec = wm8994->codec;
2728         struct wm8994_pdata *pdata = wm8994->pdata;
2729         int ret, i;
2730
2731         if (!pdata)
2732                 return;
2733
2734         wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
2735                                       pdata->lineout2_diff,
2736                                       pdata->lineout1fb,
2737                                       pdata->lineout2fb,
2738                                       pdata->jd_scthr,
2739                                       pdata->jd_thr,
2740                                       pdata->micbias1_lvl,
2741                                       pdata->micbias2_lvl);
2742
2743         dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2744
2745         if (pdata->num_drc_cfgs) {
2746                 struct snd_kcontrol_new controls[] = {
2747                         SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
2748                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
2749                         SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
2750                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
2751                         SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
2752                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
2753                 };
2754
2755                 /* We need an array of texts for the enum API */
2756                 wm8994->drc_texts = kmalloc(sizeof(char *)
2757                                             * pdata->num_drc_cfgs, GFP_KERNEL);
2758                 if (!wm8994->drc_texts) {
2759                         dev_err(wm8994->codec->dev,
2760                                 "Failed to allocate %d DRC config texts\n",
2761                                 pdata->num_drc_cfgs);
2762                         return;
2763                 }
2764
2765                 for (i = 0; i < pdata->num_drc_cfgs; i++)
2766                         wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
2767
2768                 wm8994->drc_enum.max = pdata->num_drc_cfgs;
2769                 wm8994->drc_enum.texts = wm8994->drc_texts;
2770
2771                 ret = snd_soc_add_controls(wm8994->codec, controls,
2772                                            ARRAY_SIZE(controls));
2773                 if (ret != 0)
2774                         dev_err(wm8994->codec->dev,
2775                                 "Failed to add DRC mode controls: %d\n", ret);
2776
2777                 for (i = 0; i < WM8994_NUM_DRC; i++)
2778                         wm8994_set_drc(codec, i);
2779         }
2780
2781         dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
2782                 pdata->num_retune_mobile_cfgs);
2783
2784         if (pdata->num_mbc_cfgs) {
2785                 struct snd_kcontrol_new control[] = {
2786                         SOC_ENUM_EXT("MBC Mode", wm8994->mbc_enum,
2787                                      wm8958_get_mbc_enum, wm8958_put_mbc_enum),
2788                 };
2789
2790                 /* We need an array of texts for the enum API */
2791                 wm8994->mbc_texts = kmalloc(sizeof(char *)
2792                                             * pdata->num_mbc_cfgs, GFP_KERNEL);
2793                 if (!wm8994->mbc_texts) {
2794                         dev_err(wm8994->codec->dev,
2795                                 "Failed to allocate %d MBC config texts\n",
2796                                 pdata->num_mbc_cfgs);
2797                         return;
2798                 }
2799
2800                 for (i = 0; i < pdata->num_mbc_cfgs; i++)
2801                         wm8994->mbc_texts[i] = pdata->mbc_cfgs[i].name;
2802
2803                 wm8994->mbc_enum.max = pdata->num_mbc_cfgs;
2804                 wm8994->mbc_enum.texts = wm8994->mbc_texts;
2805
2806                 ret = snd_soc_add_controls(wm8994->codec, control, 1);
2807                 if (ret != 0)
2808                         dev_err(wm8994->codec->dev,
2809                                 "Failed to add MBC mode controls: %d\n", ret);
2810         }
2811
2812         if (pdata->num_retune_mobile_cfgs)
2813                 wm8994_handle_retune_mobile_pdata(wm8994);
2814         else
2815                 snd_soc_add_controls(wm8994->codec, wm8994_eq_controls,
2816                                      ARRAY_SIZE(wm8994_eq_controls));
2817 }
2818
2819 /**
2820  * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
2821  *
2822  * @codec:   WM8994 codec
2823  * @jack:    jack to report detection events on
2824  * @micbias: microphone bias to detect on
2825  * @det:     value to report for presence detection
2826  * @shrt:    value to report for short detection
2827  *
2828  * Enable microphone detection via IRQ on the WM8994.  If GPIOs are
2829  * being used to bring out signals to the processor then only platform
2830  * data configuration is needed for WM8994 and processor GPIOs should
2831  * be configured using snd_soc_jack_add_gpios() instead.
2832  *
2833  * Configuration of detection levels is available via the micbias1_lvl
2834  * and micbias2_lvl platform data members.
2835  */
2836 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2837                       int micbias, int det, int shrt)
2838 {
2839         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2840         struct wm8994_micdet *micdet;
2841         struct wm8994 *control = codec->control_data;
2842         int reg;
2843
2844         if (control->type != WM8994)
2845                 return -EINVAL;
2846
2847         switch (micbias) {
2848         case 1:
2849                 micdet = &wm8994->micdet[0];
2850                 break;
2851         case 2:
2852                 micdet = &wm8994->micdet[1];
2853                 break;
2854         default:
2855                 return -EINVAL;
2856         }
2857
2858         dev_dbg(codec->dev, "Configuring microphone detection on %d: %x %x\n",
2859                 micbias, det, shrt);
2860
2861         /* Store the configuration */
2862         micdet->jack = jack;
2863         micdet->det = det;
2864         micdet->shrt = shrt;
2865
2866         /* If either of the jacks is set up then enable detection */
2867         if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2868                 reg = WM8994_MICD_ENA;
2869         else
2870                 reg = 0;
2871
2872         snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
2873
2874         return 0;
2875 }
2876 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
2877
2878 static irqreturn_t wm8994_mic_irq(int irq, void *data)
2879 {
2880         struct wm8994_priv *priv = data;
2881         struct snd_soc_codec *codec = priv->codec;
2882         int reg;
2883         int report;
2884
2885 #ifndef CONFIG_SND_SOC_WM8994_MODULE
2886         trace_snd_soc_jack_irq(dev_name(codec->dev));
2887 #endif
2888
2889         reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
2890         if (reg < 0) {
2891                 dev_err(codec->dev, "Failed to read microphone status: %d\n",
2892                         reg);
2893                 return IRQ_HANDLED;
2894         }
2895
2896         dev_dbg(codec->dev, "Microphone status: %x\n", reg);
2897
2898         report = 0;
2899         if (reg & WM8994_MIC1_DET_STS)
2900                 report |= priv->micdet[0].det;
2901         if (reg & WM8994_MIC1_SHRT_STS)
2902                 report |= priv->micdet[0].shrt;
2903         snd_soc_jack_report(priv->micdet[0].jack, report,
2904                             priv->micdet[0].det | priv->micdet[0].shrt);
2905
2906         report = 0;
2907         if (reg & WM8994_MIC2_DET_STS)
2908                 report |= priv->micdet[1].det;
2909         if (reg & WM8994_MIC2_SHRT_STS)
2910                 report |= priv->micdet[1].shrt;
2911         snd_soc_jack_report(priv->micdet[1].jack, report,
2912                             priv->micdet[1].det | priv->micdet[1].shrt);
2913
2914         return IRQ_HANDLED;
2915 }
2916
2917 /* Default microphone detection handler for WM8958 - the user can
2918  * override this if they wish.
2919  */
2920 static void wm8958_default_micdet(u16 status, void *data)
2921 {
2922         struct snd_soc_codec *codec = data;
2923         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2924         int report = 0;
2925
2926         /* If nothing present then clear our statuses */
2927         if (!(status & WM8958_MICD_STS)) {
2928                 wm8994->jack_is_video = false;
2929                 wm8994->jack_is_mic = false;
2930                 goto done;
2931         }
2932
2933         /* Assume anything over 475 ohms is a microphone and remember
2934          * that we've seen one (since buttons override it) */
2935         if (status & 0x600)
2936                 wm8994->jack_is_mic = true;
2937         if (wm8994->jack_is_mic)
2938                 report |= SND_JACK_MICROPHONE;
2939
2940         /* Video has an impedence of approximately 75 ohms; assume
2941          * this isn't used as a button and remember it since buttons
2942          * override it. */
2943         if (status & 0x40)
2944                 wm8994->jack_is_video = true;
2945         if (wm8994->jack_is_video)
2946                 report |= SND_JACK_VIDEOOUT;
2947
2948         /* Everything else is buttons; just assign slots */
2949         if (status & 0x4)
2950                 report |= SND_JACK_BTN_0;
2951         if (status & 0x8)
2952                 report |= SND_JACK_BTN_1;
2953         if (status & 0x10)
2954                 report |= SND_JACK_BTN_2;
2955         if (status & 0x20)
2956                 report |= SND_JACK_BTN_3;
2957         if (status & 0x80)
2958                 report |= SND_JACK_BTN_4;
2959         if (status & 0x100)
2960                 report |= SND_JACK_BTN_5;
2961
2962 done:
2963         snd_soc_jack_report(wm8994->micdet[0].jack,
2964                             SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2 |
2965                             SND_JACK_BTN_3 | SND_JACK_BTN_4 | SND_JACK_BTN_5 |
2966                             SND_JACK_MICROPHONE | SND_JACK_VIDEOOUT,
2967                             report);
2968 }
2969
2970 /**
2971  * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
2972  *
2973  * @codec:   WM8958 codec
2974  * @jack:    jack to report detection events on
2975  *
2976  * Enable microphone detection functionality for the WM8958.  By
2977  * default simple detection which supports the detection of up to 6
2978  * buttons plus video and microphone functionality is supported.
2979  *
2980  * The WM8958 has an advanced jack detection facility which is able to
2981  * support complex accessory detection, especially when used in
2982  * conjunction with external circuitry.  In order to provide maximum
2983  * flexiblity a callback is provided which allows a completely custom
2984  * detection algorithm.
2985  */
2986 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2987                       wm8958_micdet_cb cb, void *cb_data)
2988 {
2989         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2990         struct wm8994 *control = codec->control_data;
2991
2992         if (control->type != WM8958)
2993                 return -EINVAL;
2994
2995         if (jack) {
2996                 if (!cb) {
2997                         dev_dbg(codec->dev, "Using default micdet callback\n");
2998                         cb = wm8958_default_micdet;
2999                         cb_data = codec;
3000                 }
3001
3002                 wm8994->micdet[0].jack = jack;
3003                 wm8994->jack_cb = cb;
3004                 wm8994->jack_cb_data = cb_data;
3005
3006                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3007                                     WM8958_MICD_ENA, WM8958_MICD_ENA);
3008         } else {
3009                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3010                                     WM8958_MICD_ENA, 0);
3011         }
3012
3013         return 0;
3014 }
3015 EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3016
3017 static irqreturn_t wm8958_mic_irq(int irq, void *data)
3018 {
3019         struct wm8994_priv *wm8994 = data;
3020         struct snd_soc_codec *codec = wm8994->codec;
3021         int reg;
3022
3023         reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3024         if (reg < 0) {
3025                 dev_err(codec->dev, "Failed to read mic detect status: %d\n",
3026                         reg);
3027                 return IRQ_NONE;
3028         }
3029
3030         if (!(reg & WM8958_MICD_VALID)) {
3031                 dev_dbg(codec->dev, "Mic detect data not valid\n");
3032                 goto out;
3033         }
3034
3035 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3036         trace_snd_soc_jack_irq(dev_name(codec->dev));
3037 #endif
3038
3039         if (wm8994->jack_cb)
3040                 wm8994->jack_cb(reg, wm8994->jack_cb_data);
3041         else
3042                 dev_warn(codec->dev, "Accessory detection with no callback\n");
3043
3044 out:
3045         return IRQ_HANDLED;
3046 }
3047
3048 static int wm8994_codec_probe(struct snd_soc_codec *codec)
3049 {
3050         struct wm8994 *control;
3051         struct wm8994_priv *wm8994;
3052         struct snd_soc_dapm_context *dapm = &codec->dapm;
3053         int ret, i;
3054
3055         codec->control_data = dev_get_drvdata(codec->dev->parent);
3056         control = codec->control_data;
3057
3058         wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
3059         if (wm8994 == NULL)
3060                 return -ENOMEM;
3061         snd_soc_codec_set_drvdata(codec, wm8994);
3062
3063         wm8994->pdata = dev_get_platdata(codec->dev->parent);
3064         wm8994->codec = codec;
3065
3066         pm_runtime_enable(codec->dev);
3067         pm_runtime_resume(codec->dev);
3068
3069         /* Read our current status back from the chip - we don't want to
3070          * reset as this may interfere with the GPIO or LDO operation. */
3071         for (i = 0; i < WM8994_CACHE_SIZE; i++) {
3072                 if (!wm8994_readable(i) || wm8994_volatile(i))
3073                         continue;
3074
3075                 ret = wm8994_reg_read(codec->control_data, i);
3076                 if (ret <= 0)
3077                         continue;
3078
3079                 ret = snd_soc_cache_write(codec, i, ret);
3080                 if (ret != 0) {
3081                         dev_err(codec->dev,
3082                                 "Failed to initialise cache for 0x%x: %d\n",
3083                                 i, ret);
3084                         goto err;
3085                 }
3086         }
3087
3088         /* Set revision-specific configuration */
3089         wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3090         switch (control->type) {
3091         case WM8994:
3092                 switch (wm8994->revision) {
3093                 case 2:
3094                 case 3:
3095                         wm8994->hubs.dcs_codes = -5;
3096                         wm8994->hubs.hp_startup_mode = 1;
3097                         wm8994->hubs.dcs_readback_mode = 1;
3098                         break;
3099                 default:
3100                         wm8994->hubs.dcs_readback_mode = 1;
3101                         break;
3102                 }
3103
3104         case WM8958:
3105                 wm8994->hubs.dcs_readback_mode = 1;
3106                 break;
3107
3108         default:
3109                 break;
3110         }
3111
3112         switch (control->type) {
3113         case WM8994:
3114                 ret = wm8994_request_irq(codec->control_data,
3115                                          WM8994_IRQ_MIC1_DET,
3116                                          wm8994_mic_irq, "Mic 1 detect",
3117                                          wm8994);
3118                 if (ret != 0)
3119                         dev_warn(codec->dev,
3120                                  "Failed to request Mic1 detect IRQ: %d\n",
3121                                  ret);
3122
3123                 ret = wm8994_request_irq(codec->control_data,
3124                                          WM8994_IRQ_MIC1_SHRT,
3125                                          wm8994_mic_irq, "Mic 1 short",
3126                                          wm8994);
3127                 if (ret != 0)
3128                         dev_warn(codec->dev,
3129                                  "Failed to request Mic1 short IRQ: %d\n",
3130                                  ret);
3131
3132                 ret = wm8994_request_irq(codec->control_data,
3133                                          WM8994_IRQ_MIC2_DET,
3134                                          wm8994_mic_irq, "Mic 2 detect",
3135                                          wm8994);
3136                 if (ret != 0)
3137                         dev_warn(codec->dev,
3138                                  "Failed to request Mic2 detect IRQ: %d\n",
3139                                  ret);
3140
3141                 ret = wm8994_request_irq(codec->control_data,
3142                                          WM8994_IRQ_MIC2_SHRT,
3143                                          wm8994_mic_irq, "Mic 2 short",
3144                                          wm8994);
3145                 if (ret != 0)
3146                         dev_warn(codec->dev,
3147                                  "Failed to request Mic2 short IRQ: %d\n",
3148                                  ret);
3149                 break;
3150
3151         case WM8958:
3152                 ret = wm8994_request_irq(codec->control_data,
3153                                          WM8994_IRQ_MIC1_DET,
3154                                          wm8958_mic_irq, "Mic detect",
3155                                          wm8994);
3156                 if (ret != 0)
3157                         dev_warn(codec->dev,
3158                                  "Failed to request Mic detect IRQ: %d\n",
3159                                  ret);
3160                 break;
3161         }
3162
3163         /* Remember if AIFnLRCLK is configured as a GPIO.  This should be
3164          * configured on init - if a system wants to do this dynamically
3165          * at runtime we can deal with that then.
3166          */
3167         ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_1);
3168         if (ret < 0) {
3169                 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
3170                 goto err_irq;
3171         }
3172         if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3173                 wm8994->lrclk_shared[0] = 1;
3174                 wm8994_dai[0].symmetric_rates = 1;
3175         } else {
3176                 wm8994->lrclk_shared[0] = 0;
3177         }
3178
3179         ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_6);
3180         if (ret < 0) {
3181                 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
3182                 goto err_irq;
3183         }
3184         if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3185                 wm8994->lrclk_shared[1] = 1;
3186                 wm8994_dai[1].symmetric_rates = 1;
3187         } else {
3188                 wm8994->lrclk_shared[1] = 0;
3189         }
3190
3191         wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
3192
3193         /* Latch volume updates (right only; we always do left then right). */
3194         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
3195                             WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3196         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
3197                             WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3198         snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
3199                             WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3200         snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
3201                             WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3202         snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
3203                             WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3204         snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
3205                             WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3206         snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
3207                             WM8994_DAC1_VU, WM8994_DAC1_VU);
3208         snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
3209                             WM8994_DAC2_VU, WM8994_DAC2_VU);
3210
3211         /* Set the low bit of the 3D stereo depth so TLV matches */
3212         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
3213                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
3214                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
3215         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
3216                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
3217                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
3218         snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
3219                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
3220                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
3221
3222         /* Unconditionally enable AIF1 ADC TDM mode; it only affects
3223          * behaviour on idle TDM clock cycles. */
3224         snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
3225                             WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
3226
3227         wm8994_update_class_w(codec);
3228
3229         wm8994_handle_pdata(wm8994);
3230
3231         wm_hubs_add_analogue_controls(codec);
3232         snd_soc_add_controls(codec, wm8994_snd_controls,
3233                              ARRAY_SIZE(wm8994_snd_controls));
3234         snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
3235                                   ARRAY_SIZE(wm8994_dapm_widgets));
3236
3237         switch (control->type) {
3238         case WM8994:
3239                 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3240                                           ARRAY_SIZE(wm8994_specific_dapm_widgets));
3241                 if (wm8994->revision < 4)
3242                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3243                                                   ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3244                 else
3245                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3246                                                   ARRAY_SIZE(wm8994_lateclk_widgets));
3247                 break;
3248         case WM8958:
3249                 snd_soc_add_controls(codec, wm8958_snd_controls,
3250                                      ARRAY_SIZE(wm8958_snd_controls));
3251                 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3252                                           ARRAY_SIZE(wm8958_dapm_widgets));
3253                 break;
3254         }
3255
3256
3257         wm_hubs_add_analogue_routes(codec, 0, 0);
3258         snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
3259
3260         switch (control->type) {
3261         case WM8994:
3262                 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
3263                                         ARRAY_SIZE(wm8994_intercon));
3264
3265                 if (wm8994->revision < 4) {
3266                         snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3267                                                 ARRAY_SIZE(wm8994_revd_intercon));
3268                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3269                                                 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3270                 } else {
3271                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3272                                                 ARRAY_SIZE(wm8994_lateclk_intercon));
3273                 }
3274                 break;
3275         case WM8958:
3276                 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3277                                         ARRAY_SIZE(wm8958_intercon));
3278                 break;
3279         }
3280
3281         return 0;
3282
3283 err_irq:
3284         wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994);
3285         wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994);
3286         wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994);
3287         wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET, wm8994);
3288 err:
3289         kfree(wm8994);
3290         return ret;
3291 }
3292
3293 static int  wm8994_codec_remove(struct snd_soc_codec *codec)
3294 {
3295         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3296         struct wm8994 *control = codec->control_data;
3297
3298         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3299
3300         pm_runtime_disable(codec->dev);
3301
3302         switch (control->type) {
3303         case WM8994:
3304                 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT,
3305                                 wm8994);
3306                 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET,
3307                                 wm8994);
3308                 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT,
3309                                 wm8994);
3310                 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET,
3311                                 wm8994);
3312                 break;
3313
3314         case WM8958:
3315                 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET,
3316                                 wm8994);
3317                 break;
3318         }
3319         kfree(wm8994->retune_mobile_texts);
3320         kfree(wm8994->drc_texts);
3321         kfree(wm8994);
3322
3323         return 0;
3324 }
3325
3326 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
3327         .probe =        wm8994_codec_probe,
3328         .remove =       wm8994_codec_remove,
3329         .suspend =      wm8994_suspend,
3330         .resume =       wm8994_resume,
3331         .read =         wm8994_read,
3332         .write =        wm8994_write,
3333         .readable_register = wm8994_readable,
3334         .volatile_register = wm8994_volatile,
3335         .set_bias_level = wm8994_set_bias_level,
3336
3337         .reg_cache_size = WM8994_CACHE_SIZE,
3338         .reg_cache_default = wm8994_reg_defaults,
3339         .reg_word_size = 2,
3340         .compress_type = SND_SOC_RBTREE_COMPRESSION,
3341 };
3342
3343 static int __devinit wm8994_probe(struct platform_device *pdev)
3344 {
3345         return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
3346                         wm8994_dai, ARRAY_SIZE(wm8994_dai));
3347 }
3348
3349 static int __devexit wm8994_remove(struct platform_device *pdev)
3350 {
3351         snd_soc_unregister_codec(&pdev->dev);
3352         return 0;
3353 }
3354
3355 static struct platform_driver wm8994_codec_driver = {
3356         .driver = {
3357                    .name = "wm8994-codec",
3358                    .owner = THIS_MODULE,
3359                    },
3360         .probe = wm8994_probe,
3361         .remove = __devexit_p(wm8994_remove),
3362 };
3363
3364 static __init int wm8994_init(void)
3365 {
3366         return platform_driver_register(&wm8994_codec_driver);
3367 }
3368 module_init(wm8994_init);
3369
3370 static __exit void wm8994_exit(void)
3371 {
3372         platform_driver_unregister(&wm8994_codec_driver);
3373 }
3374 module_exit(wm8994_exit);
3375
3376
3377 MODULE_DESCRIPTION("ASoC WM8994 driver");
3378 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3379 MODULE_LICENSE("GPL");
3380 MODULE_ALIAS("platform:wm8994-codec");