sound/soc/codecs/wm8962.c

   1 /*
   2  * wm8962.c  --  WM8962 ALSA SoC Audio driver
   3  *
   4  * Copyright 2010 Wolfson Microelectronics plc
   5  *
   6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   7  *
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/gcd.h>
  20 #include <linux/gpio.h>
  21 #include <linux/i2c.h>
  22 #include <linux/input.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/regmap.h>
  25 #include <linux/regulator/consumer.h>
  26 #include <linux/slab.h>
  27 #include <linux/workqueue.h>
  28 #include <sound/core.h>
  29 #include <sound/jack.h>
  30 #include <sound/pcm.h>
  31 #include <sound/pcm_params.h>
  32 #include <sound/soc.h>
  33 #include <sound/initval.h>
  34 #include <sound/tlv.h>
  35 #include <sound/wm8962.h>
  36 #include <trace/events/asoc.h>
  37
  38 #include "wm8962.h"
  39
  40 #define WM8962_NUM_SUPPLIES 8
  41 static const char *wm8962_supply_names[WM8962_NUM_SUPPLIES] = {
  42         "DCVDD",
  43         "DBVDD",
  44         "AVDD",
  45         "CPVDD",
  46         "MICVDD",
  47         "PLLVDD",
  48         "SPKVDD1",
  49         "SPKVDD2",
  50 };
  51
  52 /* codec private data */
  53 struct wm8962_priv {
  54         struct regmap *regmap;
  55         struct snd_soc_codec *codec;
  56
  57         int sysclk;
  58         int sysclk_rate;
  59
  60         int bclk;  /* Desired BCLK */
  61         int lrclk;
  62
  63         struct completion fll_lock;
  64         int fll_src;
  65         int fll_fref;
  66         int fll_fout;
  67
  68         u16 dsp2_ena;
  69
  70         struct delayed_work mic_work;
  71         struct snd_soc_jack *jack;
  72
  73         struct regulator_bulk_data supplies[WM8962_NUM_SUPPLIES];
  74         struct notifier_block disable_nb[WM8962_NUM_SUPPLIES];
  75
  76 #if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE)
  77         struct input_dev *beep;
  78         struct work_struct beep_work;
  79         int beep_rate;
  80 #endif
  81
  82 #ifdef CONFIG_GPIOLIB
  83         struct gpio_chip gpio_chip;
  84 #endif
  85
  86         int irq;
  87 };
  88
  89 /* We can't use the same notifier block for more than one supply and
  90  * there's no way I can see to get from a callback to the caller
  91  * except container_of().
  92  */
  93 #define WM8962_REGULATOR_EVENT(n) \
  94 static int wm8962_regulator_event_##n(struct notifier_block *nb, \
  95                                     unsigned long event, void *data)    \
  96 { \
  97         struct wm8962_priv *wm8962 = container_of(nb, struct wm8962_priv, \
  98                                                   disable_nb[n]); \
  99         if (event & REGULATOR_EVENT_DISABLE) { \
 100                 regcache_mark_dirty(wm8962->regmap);    \
 101         } \
 102         return 0; \
 103 }
 104
 105 WM8962_REGULATOR_EVENT(0)
 106 WM8962_REGULATOR_EVENT(1)
 107 WM8962_REGULATOR_EVENT(2)
 108 WM8962_REGULATOR_EVENT(3)
 109 WM8962_REGULATOR_EVENT(4)
 110 WM8962_REGULATOR_EVENT(5)
 111 WM8962_REGULATOR_EVENT(6)
 112 WM8962_REGULATOR_EVENT(7)
 113
 114 static struct reg_default wm8962_reg[] = {
 115         { 0, 0x009F },   /* R0     - Left Input volume */
 116         { 1, 0x049F },   /* R1     - Right Input volume */
 117         { 2, 0x0000 },   /* R2     - HPOUTL volume */
 118         { 3, 0x0000 },   /* R3     - HPOUTR volume */
 119
 120         { 5, 0x0018 },   /* R5     - ADC & DAC Control 1 */
 121         { 6, 0x2008 },   /* R6     - ADC & DAC Control 2 */
 122         { 7, 0x000A },   /* R7     - Audio Interface 0 */
 123
 124         { 9, 0x0300 },   /* R9     - Audio Interface 1 */
 125         { 10, 0x00C0 },  /* R10    - Left DAC volume */
 126         { 11, 0x00C0 },  /* R11    - Right DAC volume */
 127
 128         { 14, 0x0040 },   /* R14    - Audio Interface 2 */
 129         { 15, 0x6243 },   /* R15    - Software Reset */
 130
 131         { 17, 0x007B },   /* R17    - ALC1 */
 132
 133         { 19, 0x1C32 },   /* R19    - ALC3 */
 134         { 20, 0x3200 },   /* R20    - Noise Gate */
 135         { 21, 0x00C0 },   /* R21    - Left ADC volume */
 136         { 22, 0x00C0 },   /* R22    - Right ADC volume */
 137         { 23, 0x0160 },   /* R23    - Additional control(1) */
 138         { 24, 0x0000 },   /* R24    - Additional control(2) */
 139         { 25, 0x0000 },   /* R25    - Pwr Mgmt (1) */
 140         { 26, 0x0000 },   /* R26    - Pwr Mgmt (2) */
 141         { 27, 0x0010 },   /* R27    - Additional Control (3) */
 142         { 28, 0x0000 },   /* R28    - Anti-pop */
 143
 144         { 30, 0x005E },   /* R30    - Clocking 3 */
 145         { 31, 0x0000 },   /* R31    - Input mixer control (1) */
 146         { 32, 0x0145 },   /* R32    - Left input mixer volume */
 147         { 33, 0x0145 },   /* R33    - Right input mixer volume */
 148         { 34, 0x0009 },   /* R34    - Input mixer control (2) */
 149         { 35, 0x0003 },   /* R35    - Input bias control */
 150         { 37, 0x0008 },   /* R37    - Left input PGA control */
 151         { 38, 0x0008 },   /* R38    - Right input PGA control */
 152
 153         { 40, 0x0000 },   /* R40    - SPKOUTL volume */
 154         { 41, 0x0000 },   /* R41    - SPKOUTR volume */
 155
 156         { 51, 0x0003 },   /* R51    - Class D Control 2 */
 157
 158         { 56, 0x0506 },   /* R56    - Clocking 4 */
 159         { 57, 0x0000 },   /* R57    - DAC DSP Mixing (1) */
 160         { 58, 0x0000 },   /* R58    - DAC DSP Mixing (2) */
 161
 162         { 60, 0x0300 },   /* R60    - DC Servo 0 */
 163         { 61, 0x0300 },   /* R61    - DC Servo 1 */
 164
 165         { 64, 0x0810 },   /* R64    - DC Servo 4 */
 166
 167         { 68, 0x001B },   /* R68    - Analogue PGA Bias */
 168         { 69, 0x0000 },   /* R69    - Analogue HP 0 */
 169
 170         { 71, 0x01FB },   /* R71    - Analogue HP 2 */
 171         { 72, 0x0000 },   /* R72    - Charge Pump 1 */
 172
 173         { 82, 0x0004 },   /* R82    - Charge Pump B */
 174
 175         { 87, 0x0000 },   /* R87    - Write Sequencer Control 1 */
 176
 177         { 90, 0x0000 },   /* R90    - Write Sequencer Control 2 */
 178
 179         { 93, 0x0000 },   /* R93    - Write Sequencer Control 3 */
 180         { 94, 0x0000 },   /* R94    - Control Interface */
 181
 182         { 99, 0x0000 },   /* R99    - Mixer Enables */
 183         { 100, 0x0000 },   /* R100   - Headphone Mixer (1) */
 184         { 101, 0x0000 },   /* R101   - Headphone Mixer (2) */
 185         { 102, 0x013F },   /* R102   - Headphone Mixer (3) */
 186         { 103, 0x013F },   /* R103   - Headphone Mixer (4) */
 187
 188         { 105, 0x0000 },   /* R105   - Speaker Mixer (1) */
 189         { 106, 0x0000 },   /* R106   - Speaker Mixer (2) */
 190         { 107, 0x013F },   /* R107   - Speaker Mixer (3) */
 191         { 108, 0x013F },   /* R108   - Speaker Mixer (4) */
 192         { 109, 0x0003 },   /* R109   - Speaker Mixer (5) */
 193         { 110, 0x0002 },   /* R110   - Beep Generator (1) */
 194
 195         { 115, 0x0006 },   /* R115   - Oscillator Trim (3) */
 196         { 116, 0x0026 },   /* R116   - Oscillator Trim (4) */
 197
 198         { 119, 0x0000 },   /* R119   - Oscillator Trim (7) */
 199
 200         { 124, 0x0011 },   /* R124   - Analogue Clocking1 */
 201         { 125, 0x004B },   /* R125   - Analogue Clocking2 */
 202         { 126, 0x000D },   /* R126   - Analogue Clocking3 */
 203         { 127, 0x0000 },   /* R127   - PLL Software Reset */
 204
 205         { 131, 0x0000 },   /* R131   - PLL 4 */
 206
 207         { 136, 0x0067 },   /* R136   - PLL 9 */
 208         { 137, 0x001C },   /* R137   - PLL 10 */
 209         { 138, 0x0071 },   /* R138   - PLL 11 */
 210         { 139, 0x00C7 },   /* R139   - PLL 12 */
 211         { 140, 0x0067 },   /* R140   - PLL 13 */
 212         { 141, 0x0048 },   /* R141   - PLL 14 */
 213         { 142, 0x0022 },   /* R142   - PLL 15 */
 214         { 143, 0x0097 },   /* R143   - PLL 16 */
 215
 216         { 155, 0x000C },   /* R155   - FLL Control (1) */
 217         { 156, 0x0039 },   /* R156   - FLL Control (2) */
 218         { 157, 0x0180 },   /* R157   - FLL Control (3) */
 219
 220         { 159, 0x0032 },   /* R159   - FLL Control (5) */
 221         { 160, 0x0018 },   /* R160   - FLL Control (6) */
 222         { 161, 0x007D },   /* R161   - FLL Control (7) */
 223         { 162, 0x0008 },   /* R162   - FLL Control (8) */
 224
 225         { 252, 0x0005 },   /* R252   - General test 1 */
 226
 227         { 256, 0x0000 },   /* R256   - DF1 */
 228         { 257, 0x0000 },   /* R257   - DF2 */
 229         { 258, 0x0000 },   /* R258   - DF3 */
 230         { 259, 0x0000 },   /* R259   - DF4 */
 231         { 260, 0x0000 },   /* R260   - DF5 */
 232         { 261, 0x0000 },   /* R261   - DF6 */
 233         { 262, 0x0000 },   /* R262   - DF7 */
 234
 235         { 264, 0x0000 },   /* R264   - LHPF1 */
 236         { 265, 0x0000 },   /* R265   - LHPF2 */
 237
 238         { 268, 0x0000 },   /* R268   - THREED1 */
 239         { 269, 0x0000 },   /* R269   - THREED2 */
 240         { 270, 0x0000 },   /* R270   - THREED3 */
 241         { 271, 0x0000 },   /* R271   - THREED4 */
 242
 243         { 276, 0x000C },   /* R276   - DRC 1 */
 244         { 277, 0x0925 },   /* R277   - DRC 2 */
 245         { 278, 0x0000 },   /* R278   - DRC 3 */
 246         { 279, 0x0000 },   /* R279   - DRC 4 */
 247         { 280, 0x0000 },   /* R280   - DRC 5 */
 248
 249         { 285, 0x0000 },   /* R285   - Tloopback */
 250
 251         { 335, 0x0004 },   /* R335   - EQ1 */
 252         { 336, 0x6318 },   /* R336   - EQ2 */
 253         { 337, 0x6300 },   /* R337   - EQ3 */
 254         { 338, 0x0FCA },   /* R338   - EQ4 */
 255         { 339, 0x0400 },   /* R339   - EQ5 */
 256         { 340, 0x00D8 },   /* R340   - EQ6 */
 257         { 341, 0x1EB5 },   /* R341   - EQ7 */
 258         { 342, 0xF145 },   /* R342   - EQ8 */
 259         { 343, 0x0B75 },   /* R343   - EQ9 */
 260         { 344, 0x01C5 },   /* R344   - EQ10 */
 261         { 345, 0x1C58 },   /* R345   - EQ11 */
 262         { 346, 0xF373 },   /* R346   - EQ12 */
 263         { 347, 0x0A54 },   /* R347   - EQ13 */
 264         { 348, 0x0558 },   /* R348   - EQ14 */
 265         { 349, 0x168E },   /* R349   - EQ15 */
 266         { 350, 0xF829 },   /* R350   - EQ16 */
 267         { 351, 0x07AD },   /* R351   - EQ17 */
 268         { 352, 0x1103 },   /* R352   - EQ18 */
 269         { 353, 0x0564 },   /* R353   - EQ19 */
 270         { 354, 0x0559 },   /* R354   - EQ20 */
 271         { 355, 0x4000 },   /* R355   - EQ21 */
 272         { 356, 0x6318 },   /* R356   - EQ22 */
 273         { 357, 0x6300 },   /* R357   - EQ23 */
 274         { 358, 0x0FCA },   /* R358   - EQ24 */
 275         { 359, 0x0400 },   /* R359   - EQ25 */
 276         { 360, 0x00D8 },   /* R360   - EQ26 */
 277         { 361, 0x1EB5 },   /* R361   - EQ27 */
 278         { 362, 0xF145 },   /* R362   - EQ28 */
 279         { 363, 0x0B75 },   /* R363   - EQ29 */
 280         { 364, 0x01C5 },   /* R364   - EQ30 */
 281         { 365, 0x1C58 },   /* R365   - EQ31 */
 282         { 366, 0xF373 },   /* R366   - EQ32 */
 283         { 367, 0x0A54 },   /* R367   - EQ33 */
 284         { 368, 0x0558 },   /* R368   - EQ34 */
 285         { 369, 0x168E },   /* R369   - EQ35 */
 286         { 370, 0xF829 },   /* R370   - EQ36 */
 287         { 371, 0x07AD },   /* R371   - EQ37 */
 288         { 372, 0x1103 },   /* R372   - EQ38 */
 289         { 373, 0x0564 },   /* R373   - EQ39 */
 290         { 374, 0x0559 },   /* R374   - EQ40 */
 291         { 375, 0x4000 },   /* R375   - EQ41 */
 292
 293         { 513, 0x0000 },   /* R513   - GPIO 2 */
 294         { 514, 0x0000 },   /* R514   - GPIO 3 */
 295
 296         { 516, 0x8100 },   /* R516   - GPIO 5 */
 297         { 517, 0x8100 },   /* R517   - GPIO 6 */
 298
 299         { 568, 0x0030 },   /* R568   - Interrupt Status 1 Mask */
 300         { 569, 0xFFED },   /* R569   - Interrupt Status 2 Mask */
 301
 302         { 576, 0x0000 },   /* R576   - Interrupt Control */
 303
 304         { 584, 0x002D },   /* R584   - IRQ Debounce */
 305
 306         { 586, 0x0000 },   /* R586   -  MICINT Source Pol */
 307
 308         { 768, 0x1C00 },   /* R768   - DSP2 Power Management */
 309
 310         { 8192, 0x0000 },   /* R8192  - DSP2 Instruction RAM 0 */
 311
 312         { 9216, 0x0030 },   /* R9216  - DSP2 Address RAM 2 */
 313         { 9217, 0x0000 },   /* R9217  - DSP2 Address RAM 1 */
 314         { 9218, 0x0000 },   /* R9218  - DSP2 Address RAM 0 */
 315
 316         { 12288, 0x0000 },   /* R12288 - DSP2 Data1 RAM 1 */
 317         { 12289, 0x0000 },   /* R12289 - DSP2 Data1 RAM 0 */
 318
 319         { 13312, 0x0000 },   /* R13312 - DSP2 Data2 RAM 1 */
 320         { 13313, 0x0000 },   /* R13313 - DSP2 Data2 RAM 0 */
 321
 322         { 14336, 0x0000 },   /* R14336 - DSP2 Data3 RAM 1 */
 323         { 14337, 0x0000 },   /* R14337 - DSP2 Data3 RAM 0 */
 324
 325         { 15360, 0x000A },   /* R15360 - DSP2 Coeff RAM 0 */
 326
 327         { 16384, 0x0000 },   /* R16384 - RETUNEADC_SHARED_COEFF_1 */
 328         { 16385, 0x0000 },   /* R16385 - RETUNEADC_SHARED_COEFF_0 */
 329         { 16386, 0x0000 },   /* R16386 - RETUNEDAC_SHARED_COEFF_1 */
 330         { 16387, 0x0000 },   /* R16387 - RETUNEDAC_SHARED_COEFF_0 */
 331         { 16388, 0x0000 },   /* R16388 - SOUNDSTAGE_ENABLES_1 */
 332         { 16389, 0x0000 },   /* R16389 - SOUNDSTAGE_ENABLES_0 */
 333
 334         { 16896, 0x0002 },   /* R16896 - HDBASS_AI_1 */
 335         { 16897, 0xBD12 },   /* R16897 - HDBASS_AI_0 */
 336         { 16898, 0x007C },   /* R16898 - HDBASS_AR_1 */
 337         { 16899, 0x586C },   /* R16899 - HDBASS_AR_0 */
 338         { 16900, 0x0053 },   /* R16900 - HDBASS_B_1 */
 339         { 16901, 0x8121 },   /* R16901 - HDBASS_B_0 */
 340         { 16902, 0x003F },   /* R16902 - HDBASS_K_1 */
 341         { 16903, 0x8BD8 },   /* R16903 - HDBASS_K_0 */
 342         { 16904, 0x0032 },   /* R16904 - HDBASS_N1_1 */
 343         { 16905, 0xF52D },   /* R16905 - HDBASS_N1_0 */
 344         { 16906, 0x0065 },   /* R16906 - HDBASS_N2_1 */
 345         { 16907, 0xAC8C },   /* R16907 - HDBASS_N2_0 */
 346         { 16908, 0x006B },   /* R16908 - HDBASS_N3_1 */
 347         { 16909, 0xE087 },   /* R16909 - HDBASS_N3_0 */
 348         { 16910, 0x0072 },   /* R16910 - HDBASS_N4_1 */
 349         { 16911, 0x1483 },   /* R16911 - HDBASS_N4_0 */
 350         { 16912, 0x0072 },   /* R16912 - HDBASS_N5_1 */
 351         { 16913, 0x1483 },   /* R16913 - HDBASS_N5_0 */
 352         { 16914, 0x0043 },   /* R16914 - HDBASS_X1_1 */
 353         { 16915, 0x3525 },   /* R16915 - HDBASS_X1_0 */
 354         { 16916, 0x0006 },   /* R16916 - HDBASS_X2_1 */
 355         { 16917, 0x6A4A },   /* R16917 - HDBASS_X2_0 */
 356         { 16918, 0x0043 },   /* R16918 - HDBASS_X3_1 */
 357         { 16919, 0x6079 },   /* R16919 - HDBASS_X3_0 */
 358         { 16920, 0x0008 },   /* R16920 - HDBASS_ATK_1 */
 359         { 16921, 0x0000 },   /* R16921 - HDBASS_ATK_0 */
 360         { 16922, 0x0001 },   /* R16922 - HDBASS_DCY_1 */
 361         { 16923, 0x0000 },   /* R16923 - HDBASS_DCY_0 */
 362         { 16924, 0x0059 },   /* R16924 - HDBASS_PG_1 */
 363         { 16925, 0x999A },   /* R16925 - HDBASS_PG_0 */
 364
 365         { 17048, 0x0083 },   /* R17408 - HPF_C_1 */
 366         { 17049, 0x98AD },   /* R17409 - HPF_C_0 */
 367
 368         { 17920, 0x007F },   /* R17920 - ADCL_RETUNE_C1_1 */
 369         { 17921, 0xFFFF },   /* R17921 - ADCL_RETUNE_C1_0 */
 370         { 17922, 0x0000 },   /* R17922 - ADCL_RETUNE_C2_1 */
 371         { 17923, 0x0000 },   /* R17923 - ADCL_RETUNE_C2_0 */
 372         { 17924, 0x0000 },   /* R17924 - ADCL_RETUNE_C3_1 */
 373         { 17925, 0x0000 },   /* R17925 - ADCL_RETUNE_C3_0 */
 374         { 17926, 0x0000 },   /* R17926 - ADCL_RETUNE_C4_1 */
 375         { 17927, 0x0000 },   /* R17927 - ADCL_RETUNE_C4_0 */
 376         { 17928, 0x0000 },   /* R17928 - ADCL_RETUNE_C5_1 */
 377         { 17929, 0x0000 },   /* R17929 - ADCL_RETUNE_C5_0 */
 378         { 17930, 0x0000 },   /* R17930 - ADCL_RETUNE_C6_1 */
 379         { 17931, 0x0000 },   /* R17931 - ADCL_RETUNE_C6_0 */
 380         { 17932, 0x0000 },   /* R17932 - ADCL_RETUNE_C7_1 */
 381         { 17933, 0x0000 },   /* R17933 - ADCL_RETUNE_C7_0 */
 382         { 17934, 0x0000 },   /* R17934 - ADCL_RETUNE_C8_1 */
 383         { 17935, 0x0000 },   /* R17935 - ADCL_RETUNE_C8_0 */
 384         { 17936, 0x0000 },   /* R17936 - ADCL_RETUNE_C9_1 */
 385         { 17937, 0x0000 },   /* R17937 - ADCL_RETUNE_C9_0 */
 386         { 17938, 0x0000 },   /* R17938 - ADCL_RETUNE_C10_1 */
 387         { 17939, 0x0000 },   /* R17939 - ADCL_RETUNE_C10_0 */
 388         { 17940, 0x0000 },   /* R17940 - ADCL_RETUNE_C11_1 */
 389         { 17941, 0x0000 },   /* R17941 - ADCL_RETUNE_C11_0 */
 390         { 17942, 0x0000 },   /* R17942 - ADCL_RETUNE_C12_1 */
 391         { 17943, 0x0000 },   /* R17943 - ADCL_RETUNE_C12_0 */
 392         { 17944, 0x0000 },   /* R17944 - ADCL_RETUNE_C13_1 */
 393         { 17945, 0x0000 },   /* R17945 - ADCL_RETUNE_C13_0 */
 394         { 17946, 0x0000 },   /* R17946 - ADCL_RETUNE_C14_1 */
 395         { 17947, 0x0000 },   /* R17947 - ADCL_RETUNE_C14_0 */
 396         { 17948, 0x0000 },   /* R17948 - ADCL_RETUNE_C15_1 */
 397         { 17949, 0x0000 },   /* R17949 - ADCL_RETUNE_C15_0 */
 398         { 17950, 0x0000 },   /* R17950 - ADCL_RETUNE_C16_1 */
 399         { 17951, 0x0000 },   /* R17951 - ADCL_RETUNE_C16_0 */
 400         { 17952, 0x0000 },   /* R17952 - ADCL_RETUNE_C17_1 */
 401         { 17953, 0x0000 },   /* R17953 - ADCL_RETUNE_C17_0 */
 402         { 17954, 0x0000 },   /* R17954 - ADCL_RETUNE_C18_1 */
 403         { 17955, 0x0000 },   /* R17955 - ADCL_RETUNE_C18_0 */
 404         { 17956, 0x0000 },   /* R17956 - ADCL_RETUNE_C19_1 */
 405         { 17957, 0x0000 },   /* R17957 - ADCL_RETUNE_C19_0 */
 406         { 17958, 0x0000 },   /* R17958 - ADCL_RETUNE_C20_1 */
 407         { 17959, 0x0000 },   /* R17959 - ADCL_RETUNE_C20_0 */
 408         { 17960, 0x0000 },   /* R17960 - ADCL_RETUNE_C21_1 */
 409         { 17961, 0x0000 },   /* R17961 - ADCL_RETUNE_C21_0 */
 410         { 17962, 0x0000 },   /* R17962 - ADCL_RETUNE_C22_1 */
 411         { 17963, 0x0000 },   /* R17963 - ADCL_RETUNE_C22_0 */
 412         { 17964, 0x0000 },   /* R17964 - ADCL_RETUNE_C23_1 */
 413         { 17965, 0x0000 },   /* R17965 - ADCL_RETUNE_C23_0 */
 414         { 17966, 0x0000 },   /* R17966 - ADCL_RETUNE_C24_1 */
 415         { 17967, 0x0000 },   /* R17967 - ADCL_RETUNE_C24_0 */
 416         { 17968, 0x0000 },   /* R17968 - ADCL_RETUNE_C25_1 */
 417         { 17969, 0x0000 },   /* R17969 - ADCL_RETUNE_C25_0 */
 418         { 17970, 0x0000 },   /* R17970 - ADCL_RETUNE_C26_1 */
 419         { 17971, 0x0000 },   /* R17971 - ADCL_RETUNE_C26_0 */
 420         { 17972, 0x0000 },   /* R17972 - ADCL_RETUNE_C27_1 */
 421         { 17973, 0x0000 },   /* R17973 - ADCL_RETUNE_C27_0 */
 422         { 17974, 0x0000 },   /* R17974 - ADCL_RETUNE_C28_1 */
 423         { 17975, 0x0000 },   /* R17975 - ADCL_RETUNE_C28_0 */
 424         { 17976, 0x0000 },   /* R17976 - ADCL_RETUNE_C29_1 */
 425         { 17977, 0x0000 },   /* R17977 - ADCL_RETUNE_C29_0 */
 426         { 17978, 0x0000 },   /* R17978 - ADCL_RETUNE_C30_1 */
 427         { 17979, 0x0000 },   /* R17979 - ADCL_RETUNE_C30_0 */
 428         { 17980, 0x0000 },   /* R17980 - ADCL_RETUNE_C31_1 */
 429         { 17981, 0x0000 },   /* R17981 - ADCL_RETUNE_C31_0 */
 430         { 17982, 0x0000 },   /* R17982 - ADCL_RETUNE_C32_1 */
 431         { 17983, 0x0000 },   /* R17983 - ADCL_RETUNE_C32_0 */
 432
 433         { 18432, 0x0020 },   /* R18432 - RETUNEADC_PG2_1 */
 434         { 18433, 0x0000 },   /* R18433 - RETUNEADC_PG2_0 */
 435         { 18434, 0x0040 },   /* R18434 - RETUNEADC_PG_1 */
 436         { 18435, 0x0000 },   /* R18435 - RETUNEADC_PG_0 */
 437
 438         { 18944, 0x007F },   /* R18944 - ADCR_RETUNE_C1_1 */
 439         { 18945, 0xFFFF },   /* R18945 - ADCR_RETUNE_C1_0 */
 440         { 18946, 0x0000 },   /* R18946 - ADCR_RETUNE_C2_1 */
 441         { 18947, 0x0000 },   /* R18947 - ADCR_RETUNE_C2_0 */
 442         { 18948, 0x0000 },   /* R18948 - ADCR_RETUNE_C3_1 */
 443         { 18949, 0x0000 },   /* R18949 - ADCR_RETUNE_C3_0 */
 444         { 18950, 0x0000 },   /* R18950 - ADCR_RETUNE_C4_1 */
 445         { 18951, 0x0000 },   /* R18951 - ADCR_RETUNE_C4_0 */
 446         { 18952, 0x0000 },   /* R18952 - ADCR_RETUNE_C5_1 */
 447         { 18953, 0x0000 },   /* R18953 - ADCR_RETUNE_C5_0 */
 448         { 18954, 0x0000 },   /* R18954 - ADCR_RETUNE_C6_1 */
 449         { 18955, 0x0000 },   /* R18955 - ADCR_RETUNE_C6_0 */
 450         { 18956, 0x0000 },   /* R18956 - ADCR_RETUNE_C7_1 */
 451         { 18957, 0x0000 },   /* R18957 - ADCR_RETUNE_C7_0 */
 452         { 18958, 0x0000 },   /* R18958 - ADCR_RETUNE_C8_1 */
 453         { 18959, 0x0000 },   /* R18959 - ADCR_RETUNE_C8_0 */
 454         { 18960, 0x0000 },   /* R18960 - ADCR_RETUNE_C9_1 */
 455         { 18961, 0x0000 },   /* R18961 - ADCR_RETUNE_C9_0 */
 456         { 18962, 0x0000 },   /* R18962 - ADCR_RETUNE_C10_1 */
 457         { 18963, 0x0000 },   /* R18963 - ADCR_RETUNE_C10_0 */
 458         { 18964, 0x0000 },   /* R18964 - ADCR_RETUNE_C11_1 */
 459         { 18965, 0x0000 },   /* R18965 - ADCR_RETUNE_C11_0 */
 460         { 18966, 0x0000 },   /* R18966 - ADCR_RETUNE_C12_1 */
 461         { 18967, 0x0000 },   /* R18967 - ADCR_RETUNE_C12_0 */
 462         { 18968, 0x0000 },   /* R18968 - ADCR_RETUNE_C13_1 */
 463         { 18969, 0x0000 },   /* R18969 - ADCR_RETUNE_C13_0 */
 464         { 18970, 0x0000 },   /* R18970 - ADCR_RETUNE_C14_1 */
 465         { 18971, 0x0000 },   /* R18971 - ADCR_RETUNE_C14_0 */
 466         { 18972, 0x0000 },   /* R18972 - ADCR_RETUNE_C15_1 */
 467         { 18973, 0x0000 },   /* R18973 - ADCR_RETUNE_C15_0 */
 468         { 18974, 0x0000 },   /* R18974 - ADCR_RETUNE_C16_1 */
 469         { 18975, 0x0000 },   /* R18975 - ADCR_RETUNE_C16_0 */
 470         { 18976, 0x0000 },   /* R18976 - ADCR_RETUNE_C17_1 */
 471         { 18977, 0x0000 },   /* R18977 - ADCR_RETUNE_C17_0 */
 472         { 18978, 0x0000 },   /* R18978 - ADCR_RETUNE_C18_1 */
 473         { 18979, 0x0000 },   /* R18979 - ADCR_RETUNE_C18_0 */
 474         { 18980, 0x0000 },   /* R18980 - ADCR_RETUNE_C19_1 */
 475         { 18981, 0x0000 },   /* R18981 - ADCR_RETUNE_C19_0 */
 476         { 18982, 0x0000 },   /* R18982 - ADCR_RETUNE_C20_1 */
 477         { 18983, 0x0000 },   /* R18983 - ADCR_RETUNE_C20_0 */
 478         { 18984, 0x0000 },   /* R18984 - ADCR_RETUNE_C21_1 */
 479         { 18985, 0x0000 },   /* R18985 - ADCR_RETUNE_C21_0 */
 480         { 18986, 0x0000 },   /* R18986 - ADCR_RETUNE_C22_1 */
 481         { 18987, 0x0000 },   /* R18987 - ADCR_RETUNE_C22_0 */
 482         { 18988, 0x0000 },   /* R18988 - ADCR_RETUNE_C23_1 */
 483         { 18989, 0x0000 },   /* R18989 - ADCR_RETUNE_C23_0 */
 484         { 18990, 0x0000 },   /* R18990 - ADCR_RETUNE_C24_1 */
 485         { 18991, 0x0000 },   /* R18991 - ADCR_RETUNE_C24_0 */
 486         { 18992, 0x0000 },   /* R18992 - ADCR_RETUNE_C25_1 */
 487         { 18993, 0x0000 },   /* R18993 - ADCR_RETUNE_C25_0 */
 488         { 18994, 0x0000 },   /* R18994 - ADCR_RETUNE_C26_1 */
 489         { 18995, 0x0000 },   /* R18995 - ADCR_RETUNE_C26_0 */
 490         { 18996, 0x0000 },   /* R18996 - ADCR_RETUNE_C27_1 */
 491         { 18997, 0x0000 },   /* R18997 - ADCR_RETUNE_C27_0 */
 492         { 18998, 0x0000 },   /* R18998 - ADCR_RETUNE_C28_1 */
 493         { 18999, 0x0000 },   /* R18999 - ADCR_RETUNE_C28_0 */
 494         { 19000, 0x0000 },   /* R19000 - ADCR_RETUNE_C29_1 */
 495         { 19001, 0x0000 },   /* R19001 - ADCR_RETUNE_C29_0 */
 496         { 19002, 0x0000 },   /* R19002 - ADCR_RETUNE_C30_1 */
 497         { 19003, 0x0000 },   /* R19003 - ADCR_RETUNE_C30_0 */
 498         { 19004, 0x0000 },   /* R19004 - ADCR_RETUNE_C31_1 */
 499         { 19005, 0x0000 },   /* R19005 - ADCR_RETUNE_C31_0 */
 500         { 19006, 0x0000 },   /* R19006 - ADCR_RETUNE_C32_1 */
 501         { 19007, 0x0000 },   /* R19007 - ADCR_RETUNE_C32_0 */
 502
 503         { 19456, 0x007F },   /* R19456 - DACL_RETUNE_C1_1 */
 504         { 19457, 0xFFFF },   /* R19457 - DACL_RETUNE_C1_0 */
 505         { 19458, 0x0000 },   /* R19458 - DACL_RETUNE_C2_1 */
 506         { 19459, 0x0000 },   /* R19459 - DACL_RETUNE_C2_0 */
 507         { 19460, 0x0000 },   /* R19460 - DACL_RETUNE_C3_1 */
 508         { 19461, 0x0000 },   /* R19461 - DACL_RETUNE_C3_0 */
 509         { 19462, 0x0000 },   /* R19462 - DACL_RETUNE_C4_1 */
 510         { 19463, 0x0000 },   /* R19463 - DACL_RETUNE_C4_0 */
 511         { 19464, 0x0000 },   /* R19464 - DACL_RETUNE_C5_1 */
 512         { 19465, 0x0000 },   /* R19465 - DACL_RETUNE_C5_0 */
 513         { 19466, 0x0000 },   /* R19466 - DACL_RETUNE_C6_1 */
 514         { 19467, 0x0000 },   /* R19467 - DACL_RETUNE_C6_0 */
 515         { 19468, 0x0000 },   /* R19468 - DACL_RETUNE_C7_1 */
 516         { 19469, 0x0000 },   /* R19469 - DACL_RETUNE_C7_0 */
 517         { 19470, 0x0000 },   /* R19470 - DACL_RETUNE_C8_1 */
 518         { 19471, 0x0000 },   /* R19471 - DACL_RETUNE_C8_0 */
 519         { 19472, 0x0000 },   /* R19472 - DACL_RETUNE_C9_1 */
 520         { 19473, 0x0000 },   /* R19473 - DACL_RETUNE_C9_0 */
 521         { 19474, 0x0000 },   /* R19474 - DACL_RETUNE_C10_1 */
 522         { 19475, 0x0000 },   /* R19475 - DACL_RETUNE_C10_0 */
 523         { 19476, 0x0000 },   /* R19476 - DACL_RETUNE_C11_1 */
 524         { 19477, 0x0000 },   /* R19477 - DACL_RETUNE_C11_0 */
 525         { 19478, 0x0000 },   /* R19478 - DACL_RETUNE_C12_1 */
 526         { 19479, 0x0000 },   /* R19479 - DACL_RETUNE_C12_0 */
 527         { 19480, 0x0000 },   /* R19480 - DACL_RETUNE_C13_1 */
 528         { 19481, 0x0000 },   /* R19481 - DACL_RETUNE_C13_0 */
 529         { 19482, 0x0000 },   /* R19482 - DACL_RETUNE_C14_1 */
 530         { 19483, 0x0000 },   /* R19483 - DACL_RETUNE_C14_0 */
 531         { 19484, 0x0000 },   /* R19484 - DACL_RETUNE_C15_1 */
 532         { 19485, 0x0000 },   /* R19485 - DACL_RETUNE_C15_0 */
 533         { 19486, 0x0000 },   /* R19486 - DACL_RETUNE_C16_1 */
 534         { 19487, 0x0000 },   /* R19487 - DACL_RETUNE_C16_0 */
 535         { 19488, 0x0000 },   /* R19488 - DACL_RETUNE_C17_1 */
 536         { 19489, 0x0000 },   /* R19489 - DACL_RETUNE_C17_0 */
 537         { 19490, 0x0000 },   /* R19490 - DACL_RETUNE_C18_1 */
 538         { 19491, 0x0000 },   /* R19491 - DACL_RETUNE_C18_0 */
 539         { 19492, 0x0000 },   /* R19492 - DACL_RETUNE_C19_1 */
 540         { 19493, 0x0000 },   /* R19493 - DACL_RETUNE_C19_0 */
 541         { 19494, 0x0000 },   /* R19494 - DACL_RETUNE_C20_1 */
 542         { 19495, 0x0000 },   /* R19495 - DACL_RETUNE_C20_0 */
 543         { 19496, 0x0000 },   /* R19496 - DACL_RETUNE_C21_1 */
 544         { 19497, 0x0000 },   /* R19497 - DACL_RETUNE_C21_0 */
 545         { 19498, 0x0000 },   /* R19498 - DACL_RETUNE_C22_1 */
 546         { 19499, 0x0000 },   /* R19499 - DACL_RETUNE_C22_0 */
 547         { 19500, 0x0000 },   /* R19500 - DACL_RETUNE_C23_1 */
 548         { 19501, 0x0000 },   /* R19501 - DACL_RETUNE_C23_0 */
 549         { 19502, 0x0000 },   /* R19502 - DACL_RETUNE_C24_1 */
 550         { 19503, 0x0000 },   /* R19503 - DACL_RETUNE_C24_0 */
 551         { 19504, 0x0000 },   /* R19504 - DACL_RETUNE_C25_1 */
 552         { 19505, 0x0000 },   /* R19505 - DACL_RETUNE_C25_0 */
 553         { 19506, 0x0000 },   /* R19506 - DACL_RETUNE_C26_1 */
 554         { 19507, 0x0000 },   /* R19507 - DACL_RETUNE_C26_0 */
 555         { 19508, 0x0000 },   /* R19508 - DACL_RETUNE_C27_1 */
 556         { 19509, 0x0000 },   /* R19509 - DACL_RETUNE_C27_0 */
 557         { 19510, 0x0000 },   /* R19510 - DACL_RETUNE_C28_1 */
 558         { 19511, 0x0000 },   /* R19511 - DACL_RETUNE_C28_0 */
 559         { 19512, 0x0000 },   /* R19512 - DACL_RETUNE_C29_1 */
 560         { 19513, 0x0000 },   /* R19513 - DACL_RETUNE_C29_0 */
 561         { 19514, 0x0000 },   /* R19514 - DACL_RETUNE_C30_1 */
 562         { 19515, 0x0000 },   /* R19515 - DACL_RETUNE_C30_0 */
 563         { 19516, 0x0000 },   /* R19516 - DACL_RETUNE_C31_1 */
 564         { 19517, 0x0000 },   /* R19517 - DACL_RETUNE_C31_0 */
 565         { 19518, 0x0000 },   /* R19518 - DACL_RETUNE_C32_1 */
 566         { 19519, 0x0000 },   /* R19519 - DACL_RETUNE_C32_0 */
 567
 568         { 19968, 0x0020 },   /* R19968 - RETUNEDAC_PG2_1 */
 569         { 19969, 0x0000 },   /* R19969 - RETUNEDAC_PG2_0 */
 570         { 19970, 0x0040 },   /* R19970 - RETUNEDAC_PG_1 */
 571         { 19971, 0x0000 },   /* R19971 - RETUNEDAC_PG_0 */
 572
 573         { 20480, 0x007F },   /* R20480 - DACR_RETUNE_C1_1 */
 574         { 20481, 0xFFFF },   /* R20481 - DACR_RETUNE_C1_0 */
 575         { 20482, 0x0000 },   /* R20482 - DACR_RETUNE_C2_1 */
 576         { 20483, 0x0000 },   /* R20483 - DACR_RETUNE_C2_0 */
 577         { 20484, 0x0000 },   /* R20484 - DACR_RETUNE_C3_1 */
 578         { 20485, 0x0000 },   /* R20485 - DACR_RETUNE_C3_0 */
 579         { 20486, 0x0000 },   /* R20486 - DACR_RETUNE_C4_1 */
 580         { 20487, 0x0000 },   /* R20487 - DACR_RETUNE_C4_0 */
 581         { 20488, 0x0000 },   /* R20488 - DACR_RETUNE_C5_1 */
 582         { 20489, 0x0000 },   /* R20489 - DACR_RETUNE_C5_0 */
 583         { 20490, 0x0000 },   /* R20490 - DACR_RETUNE_C6_1 */
 584         { 20491, 0x0000 },   /* R20491 - DACR_RETUNE_C6_0 */
 585         { 20492, 0x0000 },   /* R20492 - DACR_RETUNE_C7_1 */
 586         { 20493, 0x0000 },   /* R20493 - DACR_RETUNE_C7_0 */
 587         { 20494, 0x0000 },   /* R20494 - DACR_RETUNE_C8_1 */
 588         { 20495, 0x0000 },   /* R20495 - DACR_RETUNE_C8_0 */
 589         { 20496, 0x0000 },   /* R20496 - DACR_RETUNE_C9_1 */
 590         { 20497, 0x0000 },   /* R20497 - DACR_RETUNE_C9_0 */
 591         { 20498, 0x0000 },   /* R20498 - DACR_RETUNE_C10_1 */
 592         { 20499, 0x0000 },   /* R20499 - DACR_RETUNE_C10_0 */
 593         { 20500, 0x0000 },   /* R20500 - DACR_RETUNE_C11_1 */
 594         { 20501, 0x0000 },   /* R20501 - DACR_RETUNE_C11_0 */
 595         { 20502, 0x0000 },   /* R20502 - DACR_RETUNE_C12_1 */
 596         { 20503, 0x0000 },   /* R20503 - DACR_RETUNE_C12_0 */
 597         { 20504, 0x0000 },   /* R20504 - DACR_RETUNE_C13_1 */
 598         { 20505, 0x0000 },   /* R20505 - DACR_RETUNE_C13_0 */
 599         { 20506, 0x0000 },   /* R20506 - DACR_RETUNE_C14_1 */
 600         { 20507, 0x0000 },   /* R20507 - DACR_RETUNE_C14_0 */
 601         { 20508, 0x0000 },   /* R20508 - DACR_RETUNE_C15_1 */
 602         { 20509, 0x0000 },   /* R20509 - DACR_RETUNE_C15_0 */
 603         { 20510, 0x0000 },   /* R20510 - DACR_RETUNE_C16_1 */
 604         { 20511, 0x0000 },   /* R20511 - DACR_RETUNE_C16_0 */
 605         { 20512, 0x0000 },   /* R20512 - DACR_RETUNE_C17_1 */
 606         { 20513, 0x0000 },   /* R20513 - DACR_RETUNE_C17_0 */
 607         { 20514, 0x0000 },   /* R20514 - DACR_RETUNE_C18_1 */
 608         { 20515, 0x0000 },   /* R20515 - DACR_RETUNE_C18_0 */
 609         { 20516, 0x0000 },   /* R20516 - DACR_RETUNE_C19_1 */
 610         { 20517, 0x0000 },   /* R20517 - DACR_RETUNE_C19_0 */
 611         { 20518, 0x0000 },   /* R20518 - DACR_RETUNE_C20_1 */
 612         { 20519, 0x0000 },   /* R20519 - DACR_RETUNE_C20_0 */
 613         { 20520, 0x0000 },   /* R20520 - DACR_RETUNE_C21_1 */
 614         { 20521, 0x0000 },   /* R20521 - DACR_RETUNE_C21_0 */
 615         { 20522, 0x0000 },   /* R20522 - DACR_RETUNE_C22_1 */
 616         { 20523, 0x0000 },   /* R20523 - DACR_RETUNE_C22_0 */
 617         { 20524, 0x0000 },   /* R20524 - DACR_RETUNE_C23_1 */
 618         { 20525, 0x0000 },   /* R20525 - DACR_RETUNE_C23_0 */
 619         { 20526, 0x0000 },   /* R20526 - DACR_RETUNE_C24_1 */
 620         { 20527, 0x0000 },   /* R20527 - DACR_RETUNE_C24_0 */
 621         { 20528, 0x0000 },   /* R20528 - DACR_RETUNE_C25_1 */
 622         { 20529, 0x0000 },   /* R20529 - DACR_RETUNE_C25_0 */
 623         { 20530, 0x0000 },   /* R20530 - DACR_RETUNE_C26_1 */
 624         { 20531, 0x0000 },   /* R20531 - DACR_RETUNE_C26_0 */
 625         { 20532, 0x0000 },   /* R20532 - DACR_RETUNE_C27_1 */
 626         { 20533, 0x0000 },   /* R20533 - DACR_RETUNE_C27_0 */
 627         { 20534, 0x0000 },   /* R20534 - DACR_RETUNE_C28_1 */
 628         { 20535, 0x0000 },   /* R20535 - DACR_RETUNE_C28_0 */
 629         { 20536, 0x0000 },   /* R20536 - DACR_RETUNE_C29_1 */
 630         { 20537, 0x0000 },   /* R20537 - DACR_RETUNE_C29_0 */
 631         { 20538, 0x0000 },   /* R20538 - DACR_RETUNE_C30_1 */
 632         { 20539, 0x0000 },   /* R20539 - DACR_RETUNE_C30_0 */
 633         { 20540, 0x0000 },   /* R20540 - DACR_RETUNE_C31_1 */
 634         { 20541, 0x0000 },   /* R20541 - DACR_RETUNE_C31_0 */
 635         { 20542, 0x0000 },   /* R20542 - DACR_RETUNE_C32_1 */
 636         { 20543, 0x0000 },   /* R20543 - DACR_RETUNE_C32_0 */
 637
 638         { 20992, 0x008C },   /* R20992 - VSS_XHD2_1 */
 639         { 20993, 0x0200 },   /* R20993 - VSS_XHD2_0 */
 640         { 20994, 0x0035 },   /* R20994 - VSS_XHD3_1 */
 641         { 20995, 0x0700 },   /* R20995 - VSS_XHD3_0 */
 642         { 20996, 0x003A },   /* R20996 - VSS_XHN1_1 */
 643         { 20997, 0x4100 },   /* R20997 - VSS_XHN1_0 */
 644         { 20998, 0x008B },   /* R20998 - VSS_XHN2_1 */
 645         { 20999, 0x7D00 },   /* R20999 - VSS_XHN2_0 */
 646         { 21000, 0x003A },   /* R21000 - VSS_XHN3_1 */
 647         { 21001, 0x4100 },   /* R21001 - VSS_XHN3_0 */
 648         { 21002, 0x008C },   /* R21002 - VSS_XLA_1 */
 649         { 21003, 0xFEE8 },   /* R21003 - VSS_XLA_0 */
 650         { 21004, 0x0078 },   /* R21004 - VSS_XLB_1 */
 651         { 21005, 0x0000 },   /* R21005 - VSS_XLB_0 */
 652         { 21006, 0x003F },   /* R21006 - VSS_XLG_1 */
 653         { 21007, 0xB260 },   /* R21007 - VSS_XLG_0 */
 654         { 21008, 0x002D },   /* R21008 - VSS_PG2_1 */
 655         { 21009, 0x1818 },   /* R21009 - VSS_PG2_0 */
 656         { 21010, 0x0020 },   /* R21010 - VSS_PG_1 */
 657         { 21011, 0x0000 },   /* R21011 - VSS_PG_0 */
 658         { 21012, 0x00F1 },   /* R21012 - VSS_XTD1_1 */
 659         { 21013, 0x8340 },   /* R21013 - VSS_XTD1_0 */
 660         { 21014, 0x00FB },   /* R21014 - VSS_XTD2_1 */
 661         { 21015, 0x8300 },   /* R21015 - VSS_XTD2_0 */
 662         { 21016, 0x00EE },   /* R21016 - VSS_XTD3_1 */
 663         { 21017, 0xAEC0 },   /* R21017 - VSS_XTD3_0 */
 664         { 21018, 0x00FB },   /* R21018 - VSS_XTD4_1 */
 665         { 21019, 0xAC40 },   /* R21019 - VSS_XTD4_0 */
 666         { 21020, 0x00F1 },   /* R21020 - VSS_XTD5_1 */
 667         { 21021, 0x7F80 },   /* R21021 - VSS_XTD5_0 */
 668         { 21022, 0x00F4 },   /* R21022 - VSS_XTD6_1 */
 669         { 21023, 0x3B40 },   /* R21023 - VSS_XTD6_0 */
 670         { 21024, 0x00F5 },   /* R21024 - VSS_XTD7_1 */
 671         { 21025, 0xFB00 },   /* R21025 - VSS_XTD7_0 */
 672         { 21026, 0x00EA },   /* R21026 - VSS_XTD8_1 */
 673         { 21027, 0x10C0 },   /* R21027 - VSS_XTD8_0 */
 674         { 21028, 0x00FC },   /* R21028 - VSS_XTD9_1 */
 675         { 21029, 0xC580 },   /* R21029 - VSS_XTD9_0 */
 676         { 21030, 0x00E2 },   /* R21030 - VSS_XTD10_1 */
 677         { 21031, 0x75C0 },   /* R21031 - VSS_XTD10_0 */
 678         { 21032, 0x0004 },   /* R21032 - VSS_XTD11_1 */
 679         { 21033, 0xB480 },   /* R21033 - VSS_XTD11_0 */
 680         { 21034, 0x00D4 },   /* R21034 - VSS_XTD12_1 */
 681         { 21035, 0xF980 },   /* R21035 - VSS_XTD12_0 */
 682         { 21036, 0x0004 },   /* R21036 - VSS_XTD13_1 */
 683         { 21037, 0x9140 },   /* R21037 - VSS_XTD13_0 */
 684         { 21038, 0x00D8 },   /* R21038 - VSS_XTD14_1 */
 685         { 21039, 0xA480 },   /* R21039 - VSS_XTD14_0 */
 686         { 21040, 0x0002 },   /* R21040 - VSS_XTD15_1 */
 687         { 21041, 0x3DC0 },   /* R21041 - VSS_XTD15_0 */
 688         { 21042, 0x00CF },   /* R21042 - VSS_XTD16_1 */
 689         { 21043, 0x7A80 },   /* R21043 - VSS_XTD16_0 */
 690         { 21044, 0x00DC },   /* R21044 - VSS_XTD17_1 */
 691         { 21045, 0x0600 },   /* R21045 - VSS_XTD17_0 */
 692         { 21046, 0x00F2 },   /* R21046 - VSS_XTD18_1 */
 693         { 21047, 0xDAC0 },   /* R21047 - VSS_XTD18_0 */
 694         { 21048, 0x00BA },   /* R21048 - VSS_XTD19_1 */
 695         { 21049, 0xF340 },   /* R21049 - VSS_XTD19_0 */
 696         { 21050, 0x000A },   /* R21050 - VSS_XTD20_1 */
 697         { 21051, 0x7940 },   /* R21051 - VSS_XTD20_0 */
 698         { 21052, 0x001C },   /* R21052 - VSS_XTD21_1 */
 699         { 21053, 0x0680 },   /* R21053 - VSS_XTD21_0 */
 700         { 21054, 0x00FD },   /* R21054 - VSS_XTD22_1 */
 701         { 21055, 0x2D00 },   /* R21055 - VSS_XTD22_0 */
 702         { 21056, 0x001C },   /* R21056 - VSS_XTD23_1 */
 703         { 21057, 0xE840 },   /* R21057 - VSS_XTD23_0 */
 704         { 21058, 0x000D },   /* R21058 - VSS_XTD24_1 */
 705         { 21059, 0xDC40 },   /* R21059 - VSS_XTD24_0 */
 706         { 21060, 0x00FC },   /* R21060 - VSS_XTD25_1 */
 707         { 21061, 0x9D00 },   /* R21061 - VSS_XTD25_0 */
 708         { 21062, 0x0009 },   /* R21062 - VSS_XTD26_1 */
 709         { 21063, 0x5580 },   /* R21063 - VSS_XTD26_0 */
 710         { 21064, 0x00FE },   /* R21064 - VSS_XTD27_1 */
 711         { 21065, 0x7E80 },   /* R21065 - VSS_XTD27_0 */
 712         { 21066, 0x000E },   /* R21066 - VSS_XTD28_1 */
 713         { 21067, 0xAB40 },   /* R21067 - VSS_XTD28_0 */
 714         { 21068, 0x00F9 },   /* R21068 - VSS_XTD29_1 */
 715         { 21069, 0x9880 },   /* R21069 - VSS_XTD29_0 */
 716         { 21070, 0x0009 },   /* R21070 - VSS_XTD30_1 */
 717         { 21071, 0x87C0 },   /* R21071 - VSS_XTD30_0 */
 718         { 21072, 0x00FD },   /* R21072 - VSS_XTD31_1 */
 719         { 21073, 0x2C40 },   /* R21073 - VSS_XTD31_0 */
 720         { 21074, 0x0009 },   /* R21074 - VSS_XTD32_1 */
 721         { 21075, 0x4800 },   /* R21075 - VSS_XTD32_0 */
 722         { 21076, 0x0003 },   /* R21076 - VSS_XTS1_1 */
 723         { 21077, 0x5F40 },   /* R21077 - VSS_XTS1_0 */
 724         { 21078, 0x0000 },   /* R21078 - VSS_XTS2_1 */
 725         { 21079, 0x8700 },   /* R21079 - VSS_XTS2_0 */
 726         { 21080, 0x00FA },   /* R21080 - VSS_XTS3_1 */
 727         { 21081, 0xE4C0 },   /* R21081 - VSS_XTS3_0 */
 728         { 21082, 0x0000 },   /* R21082 - VSS_XTS4_1 */
 729         { 21083, 0x0B40 },   /* R21083 - VSS_XTS4_0 */
 730         { 21084, 0x0004 },   /* R21084 - VSS_XTS5_1 */
 731         { 21085, 0xE180 },   /* R21085 - VSS_XTS5_0 */
 732         { 21086, 0x0001 },   /* R21086 - VSS_XTS6_1 */
 733         { 21087, 0x1F40 },   /* R21087 - VSS_XTS6_0 */
 734         { 21088, 0x00F8 },   /* R21088 - VSS_XTS7_1 */
 735         { 21089, 0xB000 },   /* R21089 - VSS_XTS7_0 */
 736         { 21090, 0x00FB },   /* R21090 - VSS_XTS8_1 */
 737         { 21091, 0xCBC0 },   /* R21091 - VSS_XTS8_0 */
 738         { 21092, 0x0004 },   /* R21092 - VSS_XTS9_1 */
 739         { 21093, 0xF380 },   /* R21093 - VSS_XTS9_0 */
 740         { 21094, 0x0007 },   /* R21094 - VSS_XTS10_1 */
 741         { 21095, 0xDF40 },   /* R21095 - VSS_XTS10_0 */
 742         { 21096, 0x00FF },   /* R21096 - VSS_XTS11_1 */
 743         { 21097, 0x0700 },   /* R21097 - VSS_XTS11_0 */
 744         { 21098, 0x00EF },   /* R21098 - VSS_XTS12_1 */
 745         { 21099, 0xD700 },   /* R21099 - VSS_XTS12_0 */
 746         { 21100, 0x00FB },   /* R21100 - VSS_XTS13_1 */
 747         { 21101, 0xAF40 },   /* R21101 - VSS_XTS13_0 */
 748         { 21102, 0x0010 },   /* R21102 - VSS_XTS14_1 */
 749         { 21103, 0x8A80 },   /* R21103 - VSS_XTS14_0 */
 750         { 21104, 0x0011 },   /* R21104 - VSS_XTS15_1 */
 751         { 21105, 0x07C0 },   /* R21105 - VSS_XTS15_0 */
 752         { 21106, 0x00E0 },   /* R21106 - VSS_XTS16_1 */
 753         { 21107, 0x0800 },   /* R21107 - VSS_XTS16_0 */
 754         { 21108, 0x00D2 },   /* R21108 - VSS_XTS17_1 */
 755         { 21109, 0x7600 },   /* R21109 - VSS_XTS17_0 */
 756         { 21110, 0x0020 },   /* R21110 - VSS_XTS18_1 */
 757         { 21111, 0xCF40 },   /* R21111 - VSS_XTS18_0 */
 758         { 21112, 0x0030 },   /* R21112 - VSS_XTS19_1 */
 759         { 21113, 0x2340 },   /* R21113 - VSS_XTS19_0 */
 760         { 21114, 0x00FD },   /* R21114 - VSS_XTS20_1 */
 761         { 21115, 0x69C0 },   /* R21115 - VSS_XTS20_0 */
 762         { 21116, 0x0028 },   /* R21116 - VSS_XTS21_1 */
 763         { 21117, 0x3500 },   /* R21117 - VSS_XTS21_0 */
 764         { 21118, 0x0006 },   /* R21118 - VSS_XTS22_1 */
 765         { 21119, 0x3300 },   /* R21119 - VSS_XTS22_0 */
 766         { 21120, 0x00D9 },   /* R21120 - VSS_XTS23_1 */
 767         { 21121, 0xF6C0 },   /* R21121 - VSS_XTS23_0 */
 768         { 21122, 0x00F3 },   /* R21122 - VSS_XTS24_1 */
 769         { 21123, 0x3340 },   /* R21123 - VSS_XTS24_0 */
 770         { 21124, 0x000F },   /* R21124 - VSS_XTS25_1 */
 771         { 21125, 0x4200 },   /* R21125 - VSS_XTS25_0 */
 772         { 21126, 0x0004 },   /* R21126 - VSS_XTS26_1 */
 773         { 21127, 0x0C80 },   /* R21127 - VSS_XTS26_0 */
 774         { 21128, 0x00FB },   /* R21128 - VSS_XTS27_1 */
 775         { 21129, 0x3F80 },   /* R21129 - VSS_XTS27_0 */
 776         { 21130, 0x00F7 },   /* R21130 - VSS_XTS28_1 */
 777         { 21131, 0x57C0 },   /* R21131 - VSS_XTS28_0 */
 778         { 21132, 0x0003 },   /* R21132 - VSS_XTS29_1 */
 779         { 21133, 0x5400 },   /* R21133 - VSS_XTS29_0 */
 780         { 21134, 0x0000 },   /* R21134 - VSS_XTS30_1 */
 781         { 21135, 0xC6C0 },   /* R21135 - VSS_XTS30_0 */
 782         { 21136, 0x0003 },   /* R21136 - VSS_XTS31_1 */
 783         { 21137, 0x12C0 },   /* R21137 - VSS_XTS31_0 */
 784         { 21138, 0x00FD },   /* R21138 - VSS_XTS32_1 */
 785         { 21139, 0x8580 },   /* R21139 - VSS_XTS32_0 */
 786 };
 787
 788 static bool wm8962_volatile_register(struct device *dev, unsigned int reg)
 789 {
 790         switch (reg) {
 791         case WM8962_CLOCKING1:
 792         case WM8962_CLOCKING2:
 793         case WM8962_SOFTWARE_RESET:
 794         case WM8962_ALC2:
 795         case WM8962_THERMAL_SHUTDOWN_STATUS:
 796         case WM8962_ADDITIONAL_CONTROL_4:
 797         case WM8962_CLASS_D_CONTROL_1:
 798         case WM8962_DC_SERVO_6:
 799         case WM8962_INTERRUPT_STATUS_1:
 800         case WM8962_INTERRUPT_STATUS_2:
 801         case WM8962_DSP2_EXECCONTROL:
 802                 return true;
 803         default:
 804                 return false;
 805         }
 806 }
 807
 808 static bool wm8962_readable_register(struct device *dev, unsigned int reg)
 809 {
 810         switch (reg) {
 811         case WM8962_LEFT_INPUT_VOLUME:
 812         case WM8962_RIGHT_INPUT_VOLUME:
 813         case WM8962_HPOUTL_VOLUME:
 814         case WM8962_HPOUTR_VOLUME:
 815         case WM8962_CLOCKING1:
 816         case WM8962_ADC_DAC_CONTROL_1:
 817         case WM8962_ADC_DAC_CONTROL_2:
 818         case WM8962_AUDIO_INTERFACE_0:
 819         case WM8962_CLOCKING2:
 820         case WM8962_AUDIO_INTERFACE_1:
 821         case WM8962_LEFT_DAC_VOLUME:
 822         case WM8962_RIGHT_DAC_VOLUME:
 823         case WM8962_AUDIO_INTERFACE_2:
 824         case WM8962_SOFTWARE_RESET:
 825         case WM8962_ALC1:
 826         case WM8962_ALC2:
 827         case WM8962_ALC3:
 828         case WM8962_NOISE_GATE:
 829         case WM8962_LEFT_ADC_VOLUME:
 830         case WM8962_RIGHT_ADC_VOLUME:
 831         case WM8962_ADDITIONAL_CONTROL_1:
 832         case WM8962_ADDITIONAL_CONTROL_2:
 833         case WM8962_PWR_MGMT_1:
 834         case WM8962_PWR_MGMT_2:
 835         case WM8962_ADDITIONAL_CONTROL_3:
 836         case WM8962_ANTI_POP:
 837         case WM8962_CLOCKING_3:
 838         case WM8962_INPUT_MIXER_CONTROL_1:
 839         case WM8962_LEFT_INPUT_MIXER_VOLUME:
 840         case WM8962_RIGHT_INPUT_MIXER_VOLUME:
 841         case WM8962_INPUT_MIXER_CONTROL_2:
 842         case WM8962_INPUT_BIAS_CONTROL:
 843         case WM8962_LEFT_INPUT_PGA_CONTROL:
 844         case WM8962_RIGHT_INPUT_PGA_CONTROL:
 845         case WM8962_SPKOUTL_VOLUME:
 846         case WM8962_SPKOUTR_VOLUME:
 847         case WM8962_THERMAL_SHUTDOWN_STATUS:
 848         case WM8962_ADDITIONAL_CONTROL_4:
 849         case WM8962_CLASS_D_CONTROL_1:
 850         case WM8962_CLASS_D_CONTROL_2:
 851         case WM8962_CLOCKING_4:
 852         case WM8962_DAC_DSP_MIXING_1:
 853         case WM8962_DAC_DSP_MIXING_2:
 854         case WM8962_DC_SERVO_0:
 855         case WM8962_DC_SERVO_1:
 856         case WM8962_DC_SERVO_4:
 857         case WM8962_DC_SERVO_6:
 858         case WM8962_ANALOGUE_PGA_BIAS:
 859         case WM8962_ANALOGUE_HP_0:
 860         case WM8962_ANALOGUE_HP_2:
 861         case WM8962_CHARGE_PUMP_1:
 862         case WM8962_CHARGE_PUMP_B:
 863         case WM8962_WRITE_SEQUENCER_CONTROL_1:
 864         case WM8962_WRITE_SEQUENCER_CONTROL_2:
 865         case WM8962_WRITE_SEQUENCER_CONTROL_3:
 866         case WM8962_CONTROL_INTERFACE:
 867         case WM8962_MIXER_ENABLES:
 868         case WM8962_HEADPHONE_MIXER_1:
 869         case WM8962_HEADPHONE_MIXER_2:
 870         case WM8962_HEADPHONE_MIXER_3:
 871         case WM8962_HEADPHONE_MIXER_4:
 872         case WM8962_SPEAKER_MIXER_1:
 873         case WM8962_SPEAKER_MIXER_2:
 874         case WM8962_SPEAKER_MIXER_3:
 875         case WM8962_SPEAKER_MIXER_4:
 876         case WM8962_SPEAKER_MIXER_5:
 877         case WM8962_BEEP_GENERATOR_1:
 878         case WM8962_OSCILLATOR_TRIM_3:
 879         case WM8962_OSCILLATOR_TRIM_4:
 880         case WM8962_OSCILLATOR_TRIM_7:
 881         case WM8962_ANALOGUE_CLOCKING1:
 882         case WM8962_ANALOGUE_CLOCKING2:
 883         case WM8962_ANALOGUE_CLOCKING3:
 884         case WM8962_PLL_SOFTWARE_RESET:
 885         case WM8962_PLL2:
 886         case WM8962_PLL_4:
 887         case WM8962_PLL_9:
 888         case WM8962_PLL_10:
 889         case WM8962_PLL_11:
 890         case WM8962_PLL_12:
 891         case WM8962_PLL_13:
 892         case WM8962_PLL_14:
 893         case WM8962_PLL_15:
 894         case WM8962_PLL_16:
 895         case WM8962_FLL_CONTROL_1:
 896         case WM8962_FLL_CONTROL_2:
 897         case WM8962_FLL_CONTROL_3:
 898         case WM8962_FLL_CONTROL_5:
 899         case WM8962_FLL_CONTROL_6:
 900         case WM8962_FLL_CONTROL_7:
 901         case WM8962_FLL_CONTROL_8:
 902         case WM8962_GENERAL_TEST_1:
 903         case WM8962_DF1:
 904         case WM8962_DF2:
 905         case WM8962_DF3:
 906         case WM8962_DF4:
 907         case WM8962_DF5:
 908         case WM8962_DF6:
 909         case WM8962_DF7:
 910         case WM8962_LHPF1:
 911         case WM8962_LHPF2:
 912         case WM8962_THREED1:
 913         case WM8962_THREED2:
 914         case WM8962_THREED3:
 915         case WM8962_THREED4:
 916         case WM8962_DRC_1:
 917         case WM8962_DRC_2:
 918         case WM8962_DRC_3:
 919         case WM8962_DRC_4:
 920         case WM8962_DRC_5:
 921         case WM8962_TLOOPBACK:
 922         case WM8962_EQ1:
 923         case WM8962_EQ2:
 924         case WM8962_EQ3:
 925         case WM8962_EQ4:
 926         case WM8962_EQ5:
 927         case WM8962_EQ6:
 928         case WM8962_EQ7:
 929         case WM8962_EQ8:
 930         case WM8962_EQ9:
 931         case WM8962_EQ10:
 932         case WM8962_EQ11:
 933         case WM8962_EQ12:
 934         case WM8962_EQ13:
 935         case WM8962_EQ14:
 936         case WM8962_EQ15:
 937         case WM8962_EQ16:
 938         case WM8962_EQ17:
 939         case WM8962_EQ18:
 940         case WM8962_EQ19:
 941         case WM8962_EQ20:
 942         case WM8962_EQ21:
 943         case WM8962_EQ22:
 944         case WM8962_EQ23:
 945         case WM8962_EQ24:
 946         case WM8962_EQ25:
 947         case WM8962_EQ26:
 948         case WM8962_EQ27:
 949         case WM8962_EQ28:
 950         case WM8962_EQ29:
 951         case WM8962_EQ30:
 952         case WM8962_EQ31:
 953         case WM8962_EQ32:
 954         case WM8962_EQ33:
 955         case WM8962_EQ34:
 956         case WM8962_EQ35:
 957         case WM8962_EQ36:
 958         case WM8962_EQ37:
 959         case WM8962_EQ38:
 960         case WM8962_EQ39:
 961         case WM8962_EQ40:
 962         case WM8962_EQ41:
 963         case WM8962_GPIO_BASE:
 964         case WM8962_GPIO_2:
 965         case WM8962_GPIO_3:
 966         case WM8962_GPIO_5:
 967         case WM8962_GPIO_6:
 968         case WM8962_INTERRUPT_STATUS_1:
 969         case WM8962_INTERRUPT_STATUS_2:
 970         case WM8962_INTERRUPT_STATUS_1_MASK:
 971         case WM8962_INTERRUPT_STATUS_2_MASK:
 972         case WM8962_INTERRUPT_CONTROL:
 973         case WM8962_IRQ_DEBOUNCE:
 974         case WM8962_MICINT_SOURCE_POL:
 975         case WM8962_DSP2_POWER_MANAGEMENT:
 976         case WM8962_DSP2_EXECCONTROL:
 977         case WM8962_DSP2_INSTRUCTION_RAM_0:
 978         case WM8962_DSP2_ADDRESS_RAM_2:
 979         case WM8962_DSP2_ADDRESS_RAM_1:
 980         case WM8962_DSP2_ADDRESS_RAM_0:
 981         case WM8962_DSP2_DATA1_RAM_1:
 982         case WM8962_DSP2_DATA1_RAM_0:
 983         case WM8962_DSP2_DATA2_RAM_1:
 984         case WM8962_DSP2_DATA2_RAM_0:
 985         case WM8962_DSP2_DATA3_RAM_1:
 986         case WM8962_DSP2_DATA3_RAM_0:
 987         case WM8962_DSP2_COEFF_RAM_0:
 988         case WM8962_RETUNEADC_SHARED_COEFF_1:
 989         case WM8962_RETUNEADC_SHARED_COEFF_0:
 990         case WM8962_RETUNEDAC_SHARED_COEFF_1:
 991         case WM8962_RETUNEDAC_SHARED_COEFF_0:
 992         case WM8962_SOUNDSTAGE_ENABLES_1:
 993         case WM8962_SOUNDSTAGE_ENABLES_0:
 994         case WM8962_HDBASS_AI_1:
 995         case WM8962_HDBASS_AI_0:
 996         case WM8962_HDBASS_AR_1:
 997         case WM8962_HDBASS_AR_0:
 998         case WM8962_HDBASS_B_1:
 999         case WM8962_HDBASS_B_0:
1000         case WM8962_HDBASS_K_1:
1001         case WM8962_HDBASS_K_0:
1002         case WM8962_HDBASS_N1_1:
1003         case WM8962_HDBASS_N1_0:
1004         case WM8962_HDBASS_N2_1:
1005         case WM8962_HDBASS_N2_0:
1006         case WM8962_HDBASS_N3_1:
1007         case WM8962_HDBASS_N3_0:
1008         case WM8962_HDBASS_N4_1:
1009         case WM8962_HDBASS_N4_0:
1010         case WM8962_HDBASS_N5_1:
1011         case WM8962_HDBASS_N5_0:
1012         case WM8962_HDBASS_X1_1:
1013         case WM8962_HDBASS_X1_0:
1014         case WM8962_HDBASS_X2_1:
1015         case WM8962_HDBASS_X2_0:
1016         case WM8962_HDBASS_X3_1:
1017         case WM8962_HDBASS_X3_0:
1018         case WM8962_HDBASS_ATK_1:
1019         case WM8962_HDBASS_ATK_0:
1020         case WM8962_HDBASS_DCY_1:
1021         case WM8962_HDBASS_DCY_0:
1022         case WM8962_HDBASS_PG_1:
1023         case WM8962_HDBASS_PG_0:
1024         case WM8962_HPF_C_1:
1025         case WM8962_HPF_C_0:
1026         case WM8962_ADCL_RETUNE_C1_1:
1027         case WM8962_ADCL_RETUNE_C1_0:
1028         case WM8962_ADCL_RETUNE_C2_1:
1029         case WM8962_ADCL_RETUNE_C2_0:
1030         case WM8962_ADCL_RETUNE_C3_1:
1031         case WM8962_ADCL_RETUNE_C3_0:
1032         case WM8962_ADCL_RETUNE_C4_1:
1033         case WM8962_ADCL_RETUNE_C4_0:
1034         case WM8962_ADCL_RETUNE_C5_1:
1035         case WM8962_ADCL_RETUNE_C5_0:
1036         case WM8962_ADCL_RETUNE_C6_1:
1037         case WM8962_ADCL_RETUNE_C6_0:
1038         case WM8962_ADCL_RETUNE_C7_1:
1039         case WM8962_ADCL_RETUNE_C7_0:
1040         case WM8962_ADCL_RETUNE_C8_1:
1041         case WM8962_ADCL_RETUNE_C8_0:
1042         case WM8962_ADCL_RETUNE_C9_1:
1043         case WM8962_ADCL_RETUNE_C9_0:
1044         case WM8962_ADCL_RETUNE_C10_1:
1045         case WM8962_ADCL_RETUNE_C10_0:
1046         case WM8962_ADCL_RETUNE_C11_1:
1047         case WM8962_ADCL_RETUNE_C11_0:
1048         case WM8962_ADCL_RETUNE_C12_1:
1049         case WM8962_ADCL_RETUNE_C12_0:
1050         case WM8962_ADCL_RETUNE_C13_1:
1051         case WM8962_ADCL_RETUNE_C13_0:
1052         case WM8962_ADCL_RETUNE_C14_1:
1053         case WM8962_ADCL_RETUNE_C14_0:
1054         case WM8962_ADCL_RETUNE_C15_1:
1055         case WM8962_ADCL_RETUNE_C15_0:
1056         case WM8962_ADCL_RETUNE_C16_1:
1057         case WM8962_ADCL_RETUNE_C16_0:
1058         case WM8962_ADCL_RETUNE_C17_1:
1059         case WM8962_ADCL_RETUNE_C17_0:
1060         case WM8962_ADCL_RETUNE_C18_1:
1061         case WM8962_ADCL_RETUNE_C18_0:
1062         case WM8962_ADCL_RETUNE_C19_1:
1063         case WM8962_ADCL_RETUNE_C19_0:
1064         case WM8962_ADCL_RETUNE_C20_1:
1065         case WM8962_ADCL_RETUNE_C20_0:
1066         case WM8962_ADCL_RETUNE_C21_1:
1067         case WM8962_ADCL_RETUNE_C21_0:
1068         case WM8962_ADCL_RETUNE_C22_1:
1069         case WM8962_ADCL_RETUNE_C22_0:
1070         case WM8962_ADCL_RETUNE_C23_1:
1071         case WM8962_ADCL_RETUNE_C23_0:
1072         case WM8962_ADCL_RETUNE_C24_1:
1073         case WM8962_ADCL_RETUNE_C24_0:
1074         case WM8962_ADCL_RETUNE_C25_1:
1075         case WM8962_ADCL_RETUNE_C25_0:
1076         case WM8962_ADCL_RETUNE_C26_1:
1077         case WM8962_ADCL_RETUNE_C26_0:
1078         case WM8962_ADCL_RETUNE_C27_1:
1079         case WM8962_ADCL_RETUNE_C27_0:
1080         case WM8962_ADCL_RETUNE_C28_1:
1081         case WM8962_ADCL_RETUNE_C28_0:
1082         case WM8962_ADCL_RETUNE_C29_1:
1083         case WM8962_ADCL_RETUNE_C29_0:
1084         case WM8962_ADCL_RETUNE_C30_1:
1085         case WM8962_ADCL_RETUNE_C30_0:
1086         case WM8962_ADCL_RETUNE_C31_1:
1087         case WM8962_ADCL_RETUNE_C31_0:
1088         case WM8962_ADCL_RETUNE_C32_1:
1089         case WM8962_ADCL_RETUNE_C32_0:
1090         case WM8962_RETUNEADC_PG2_1:
1091         case WM8962_RETUNEADC_PG2_0:
1092         case WM8962_RETUNEADC_PG_1:
1093         case WM8962_RETUNEADC_PG_0:
1094         case WM8962_ADCR_RETUNE_C1_1:
1095         case WM8962_ADCR_RETUNE_C1_0:
1096         case WM8962_ADCR_RETUNE_C2_1:
1097         case WM8962_ADCR_RETUNE_C2_0:
1098         case WM8962_ADCR_RETUNE_C3_1:
1099         case WM8962_ADCR_RETUNE_C3_0:
1100         case WM8962_ADCR_RETUNE_C4_1:
1101         case WM8962_ADCR_RETUNE_C4_0:
1102         case WM8962_ADCR_RETUNE_C5_1:
1103         case WM8962_ADCR_RETUNE_C5_0:
1104         case WM8962_ADCR_RETUNE_C6_1:
1105         case WM8962_ADCR_RETUNE_C6_0:
1106         case WM8962_ADCR_RETUNE_C7_1:
1107         case WM8962_ADCR_RETUNE_C7_0:
1108         case WM8962_ADCR_RETUNE_C8_1:
1109         case WM8962_ADCR_RETUNE_C8_0:
1110         case WM8962_ADCR_RETUNE_C9_1:
1111         case WM8962_ADCR_RETUNE_C9_0:
1112         case WM8962_ADCR_RETUNE_C10_1:
1113         case WM8962_ADCR_RETUNE_C10_0:
1114         case WM8962_ADCR_RETUNE_C11_1:
1115         case WM8962_ADCR_RETUNE_C11_0:
1116         case WM8962_ADCR_RETUNE_C12_1:
1117         case WM8962_ADCR_RETUNE_C12_0:
1118         case WM8962_ADCR_RETUNE_C13_1:
1119         case WM8962_ADCR_RETUNE_C13_0:
1120         case WM8962_ADCR_RETUNE_C14_1:
1121         case WM8962_ADCR_RETUNE_C14_0:
1122         case WM8962_ADCR_RETUNE_C15_1:
1123         case WM8962_ADCR_RETUNE_C15_0:
1124         case WM8962_ADCR_RETUNE_C16_1:
1125         case WM8962_ADCR_RETUNE_C16_0:
1126         case WM8962_ADCR_RETUNE_C17_1:
1127         case WM8962_ADCR_RETUNE_C17_0:
1128         case WM8962_ADCR_RETUNE_C18_1:
1129         case WM8962_ADCR_RETUNE_C18_0:
1130         case WM8962_ADCR_RETUNE_C19_1:
1131         case WM8962_ADCR_RETUNE_C19_0:
1132         case WM8962_ADCR_RETUNE_C20_1:
1133         case WM8962_ADCR_RETUNE_C20_0:
1134         case WM8962_ADCR_RETUNE_C21_1:
1135         case WM8962_ADCR_RETUNE_C21_0:
1136         case WM8962_ADCR_RETUNE_C22_1:
1137         case WM8962_ADCR_RETUNE_C22_0:
1138         case WM8962_ADCR_RETUNE_C23_1:
1139         case WM8962_ADCR_RETUNE_C23_0:
1140         case WM8962_ADCR_RETUNE_C24_1:
1141         case WM8962_ADCR_RETUNE_C24_0:
1142         case WM8962_ADCR_RETUNE_C25_1:
1143         case WM8962_ADCR_RETUNE_C25_0:
1144         case WM8962_ADCR_RETUNE_C26_1:
1145         case WM8962_ADCR_RETUNE_C26_0:
1146         case WM8962_ADCR_RETUNE_C27_1:
1147         case WM8962_ADCR_RETUNE_C27_0:
1148         case WM8962_ADCR_RETUNE_C28_1:
1149         case WM8962_ADCR_RETUNE_C28_0:
1150         case WM8962_ADCR_RETUNE_C29_1:
1151         case WM8962_ADCR_RETUNE_C29_0:
1152         case WM8962_ADCR_RETUNE_C30_1:
1153         case WM8962_ADCR_RETUNE_C30_0:
1154         case WM8962_ADCR_RETUNE_C31_1:
1155         case WM8962_ADCR_RETUNE_C31_0:
1156         case WM8962_ADCR_RETUNE_C32_1:
1157         case WM8962_ADCR_RETUNE_C32_0:
1158         case WM8962_DACL_RETUNE_C1_1:
1159         case WM8962_DACL_RETUNE_C1_0:
1160         case WM8962_DACL_RETUNE_C2_1:
1161         case WM8962_DACL_RETUNE_C2_0:
1162         case WM8962_DACL_RETUNE_C3_1:
1163         case WM8962_DACL_RETUNE_C3_0:
1164         case WM8962_DACL_RETUNE_C4_1:
1165         case WM8962_DACL_RETUNE_C4_0:
1166         case WM8962_DACL_RETUNE_C5_1:
1167         case WM8962_DACL_RETUNE_C5_0:
1168         case WM8962_DACL_RETUNE_C6_1:
1169         case WM8962_DACL_RETUNE_C6_0:
1170         case WM8962_DACL_RETUNE_C7_1:
1171         case WM8962_DACL_RETUNE_C7_0:
1172         case WM8962_DACL_RETUNE_C8_1:
1173         case WM8962_DACL_RETUNE_C8_0:
1174         case WM8962_DACL_RETUNE_C9_1:
1175         case WM8962_DACL_RETUNE_C9_0:
1176         case WM8962_DACL_RETUNE_C10_1:
1177         case WM8962_DACL_RETUNE_C10_0:
1178         case WM8962_DACL_RETUNE_C11_1:
1179         case WM8962_DACL_RETUNE_C11_0:
1180         case WM8962_DACL_RETUNE_C12_1:
1181         case WM8962_DACL_RETUNE_C12_0:
1182         case WM8962_DACL_RETUNE_C13_1:
1183         case WM8962_DACL_RETUNE_C13_0:
1184         case WM8962_DACL_RETUNE_C14_1:
1185         case WM8962_DACL_RETUNE_C14_0:
1186         case WM8962_DACL_RETUNE_C15_1:
1187         case WM8962_DACL_RETUNE_C15_0:
1188         case WM8962_DACL_RETUNE_C16_1:
1189         case WM8962_DACL_RETUNE_C16_0:
1190         case WM8962_DACL_RETUNE_C17_1:
1191         case WM8962_DACL_RETUNE_C17_0:
1192         case WM8962_DACL_RETUNE_C18_1:
1193         case WM8962_DACL_RETUNE_C18_0:
1194         case WM8962_DACL_RETUNE_C19_1:
1195         case WM8962_DACL_RETUNE_C19_0:
1196         case WM8962_DACL_RETUNE_C20_1:
1197         case WM8962_DACL_RETUNE_C20_0:
1198         case WM8962_DACL_RETUNE_C21_1:
1199         case WM8962_DACL_RETUNE_C21_0:
1200         case WM8962_DACL_RETUNE_C22_1:
1201         case WM8962_DACL_RETUNE_C22_0:
1202         case WM8962_DACL_RETUNE_C23_1:
1203         case WM8962_DACL_RETUNE_C23_0:
1204         case WM8962_DACL_RETUNE_C24_1:
1205         case WM8962_DACL_RETUNE_C24_0:
1206         case WM8962_DACL_RETUNE_C25_1:
1207         case WM8962_DACL_RETUNE_C25_0:
1208         case WM8962_DACL_RETUNE_C26_1:
1209         case WM8962_DACL_RETUNE_C26_0:
1210         case WM8962_DACL_RETUNE_C27_1:
1211         case WM8962_DACL_RETUNE_C27_0:
1212         case WM8962_DACL_RETUNE_C28_1:
1213         case WM8962_DACL_RETUNE_C28_0:
1214         case WM8962_DACL_RETUNE_C29_1:
1215         case WM8962_DACL_RETUNE_C29_0:
1216         case WM8962_DACL_RETUNE_C30_1:
1217         case WM8962_DACL_RETUNE_C30_0:
1218         case WM8962_DACL_RETUNE_C31_1:
1219         case WM8962_DACL_RETUNE_C31_0:
1220         case WM8962_DACL_RETUNE_C32_1:
1221         case WM8962_DACL_RETUNE_C32_0:
1222         case WM8962_RETUNEDAC_PG2_1:
1223         case WM8962_RETUNEDAC_PG2_0:
1224         case WM8962_RETUNEDAC_PG_1:
1225         case WM8962_RETUNEDAC_PG_0:
1226         case WM8962_DACR_RETUNE_C1_1:
1227         case WM8962_DACR_RETUNE_C1_0:
1228         case WM8962_DACR_RETUNE_C2_1:
1229         case WM8962_DACR_RETUNE_C2_0:
1230         case WM8962_DACR_RETUNE_C3_1:
1231         case WM8962_DACR_RETUNE_C3_0:
1232         case WM8962_DACR_RETUNE_C4_1:
1233         case WM8962_DACR_RETUNE_C4_0:
1234         case WM8962_DACR_RETUNE_C5_1:
1235         case WM8962_DACR_RETUNE_C5_0:
1236         case WM8962_DACR_RETUNE_C6_1:
1237         case WM8962_DACR_RETUNE_C6_0:
1238         case WM8962_DACR_RETUNE_C7_1:
1239         case WM8962_DACR_RETUNE_C7_0:
1240         case WM8962_DACR_RETUNE_C8_1:
1241         case WM8962_DACR_RETUNE_C8_0:
1242         case WM8962_DACR_RETUNE_C9_1:
1243         case WM8962_DACR_RETUNE_C9_0:
1244         case WM8962_DACR_RETUNE_C10_1:
1245         case WM8962_DACR_RETUNE_C10_0:
1246         case WM8962_DACR_RETUNE_C11_1:
1247         case WM8962_DACR_RETUNE_C11_0:
1248         case WM8962_DACR_RETUNE_C12_1:
1249         case WM8962_DACR_RETUNE_C12_0:
1250         case WM8962_DACR_RETUNE_C13_1:
1251         case WM8962_DACR_RETUNE_C13_0:
1252         case WM8962_DACR_RETUNE_C14_1:
1253         case WM8962_DACR_RETUNE_C14_0:
1254         case WM8962_DACR_RETUNE_C15_1:
1255         case WM8962_DACR_RETUNE_C15_0:
1256         case WM8962_DACR_RETUNE_C16_1:
1257         case WM8962_DACR_RETUNE_C16_0:
1258         case WM8962_DACR_RETUNE_C17_1:
1259         case WM8962_DACR_RETUNE_C17_0:
1260         case WM8962_DACR_RETUNE_C18_1:
1261         case WM8962_DACR_RETUNE_C18_0:
1262         case WM8962_DACR_RETUNE_C19_1:
1263         case WM8962_DACR_RETUNE_C19_0:
1264         case WM8962_DACR_RETUNE_C20_1:
1265         case WM8962_DACR_RETUNE_C20_0:
1266         case WM8962_DACR_RETUNE_C21_1:
1267         case WM8962_DACR_RETUNE_C21_0:
1268         case WM8962_DACR_RETUNE_C22_1:
1269         case WM8962_DACR_RETUNE_C22_0:
1270         case WM8962_DACR_RETUNE_C23_1:
1271         case WM8962_DACR_RETUNE_C23_0:
1272         case WM8962_DACR_RETUNE_C24_1:
1273         case WM8962_DACR_RETUNE_C24_0:
1274         case WM8962_DACR_RETUNE_C25_1:
1275         case WM8962_DACR_RETUNE_C25_0:
1276         case WM8962_DACR_RETUNE_C26_1:
1277         case WM8962_DACR_RETUNE_C26_0:
1278         case WM8962_DACR_RETUNE_C27_1:
1279         case WM8962_DACR_RETUNE_C27_0:
1280         case WM8962_DACR_RETUNE_C28_1:
1281         case WM8962_DACR_RETUNE_C28_0:
1282         case WM8962_DACR_RETUNE_C29_1:
1283         case WM8962_DACR_RETUNE_C29_0:
1284         case WM8962_DACR_RETUNE_C30_1:
1285         case WM8962_DACR_RETUNE_C30_0:
1286         case WM8962_DACR_RETUNE_C31_1:
1287         case WM8962_DACR_RETUNE_C31_0:
1288         case WM8962_DACR_RETUNE_C32_1:
1289         case WM8962_DACR_RETUNE_C32_0:
1290         case WM8962_VSS_XHD2_1:
1291         case WM8962_VSS_XHD2_0:
1292         case WM8962_VSS_XHD3_1:
1293         case WM8962_VSS_XHD3_0:
1294         case WM8962_VSS_XHN1_1:
1295         case WM8962_VSS_XHN1_0:
1296         case WM8962_VSS_XHN2_1:
1297         case WM8962_VSS_XHN2_0:
1298         case WM8962_VSS_XHN3_1:
1299         case WM8962_VSS_XHN3_0:
1300         case WM8962_VSS_XLA_1:
1301         case WM8962_VSS_XLA_0:
1302         case WM8962_VSS_XLB_1:
1303         case WM8962_VSS_XLB_0:
1304         case WM8962_VSS_XLG_1:
1305         case WM8962_VSS_XLG_0:
1306         case WM8962_VSS_PG2_1:
1307         case WM8962_VSS_PG2_0:
1308         case WM8962_VSS_PG_1:
1309         case WM8962_VSS_PG_0:
1310         case WM8962_VSS_XTD1_1:
1311         case WM8962_VSS_XTD1_0:
1312         case WM8962_VSS_XTD2_1:
1313         case WM8962_VSS_XTD2_0:
1314         case WM8962_VSS_XTD3_1:
1315         case WM8962_VSS_XTD3_0:
1316         case WM8962_VSS_XTD4_1:
1317         case WM8962_VSS_XTD4_0:
1318         case WM8962_VSS_XTD5_1:
1319         case WM8962_VSS_XTD5_0:
1320         case WM8962_VSS_XTD6_1:
1321         case WM8962_VSS_XTD6_0:
1322         case WM8962_VSS_XTD7_1:
1323         case WM8962_VSS_XTD7_0:
1324         case WM8962_VSS_XTD8_1:
1325         case WM8962_VSS_XTD8_0:
1326         case WM8962_VSS_XTD9_1:
1327         case WM8962_VSS_XTD9_0:
1328         case WM8962_VSS_XTD10_1:
1329         case WM8962_VSS_XTD10_0:
1330         case WM8962_VSS_XTD11_1:
1331         case WM8962_VSS_XTD11_0:
1332         case WM8962_VSS_XTD12_1:
1333         case WM8962_VSS_XTD12_0:
1334         case WM8962_VSS_XTD13_1:
1335         case WM8962_VSS_XTD13_0:
1336         case WM8962_VSS_XTD14_1:
1337         case WM8962_VSS_XTD14_0:
1338         case WM8962_VSS_XTD15_1:
1339         case WM8962_VSS_XTD15_0:
1340         case WM8962_VSS_XTD16_1:
1341         case WM8962_VSS_XTD16_0:
1342         case WM8962_VSS_XTD17_1:
1343         case WM8962_VSS_XTD17_0:
1344         case WM8962_VSS_XTD18_1:
1345         case WM8962_VSS_XTD18_0:
1346         case WM8962_VSS_XTD19_1:
1347         case WM8962_VSS_XTD19_0:
1348         case WM8962_VSS_XTD20_1:
1349         case WM8962_VSS_XTD20_0:
1350         case WM8962_VSS_XTD21_1:
1351         case WM8962_VSS_XTD21_0:
1352         case WM8962_VSS_XTD22_1:
1353         case WM8962_VSS_XTD22_0:
1354         case WM8962_VSS_XTD23_1:
1355         case WM8962_VSS_XTD23_0:
1356         case WM8962_VSS_XTD24_1:
1357         case WM8962_VSS_XTD24_0:
1358         case WM8962_VSS_XTD25_1:
1359         case WM8962_VSS_XTD25_0:
1360         case WM8962_VSS_XTD26_1:
1361         case WM8962_VSS_XTD26_0:
1362         case WM8962_VSS_XTD27_1:
1363         case WM8962_VSS_XTD27_0:
1364         case WM8962_VSS_XTD28_1:
1365         case WM8962_VSS_XTD28_0:
1366         case WM8962_VSS_XTD29_1:
1367         case WM8962_VSS_XTD29_0:
1368         case WM8962_VSS_XTD30_1:
1369         case WM8962_VSS_XTD30_0:
1370         case WM8962_VSS_XTD31_1:
1371         case WM8962_VSS_XTD31_0:
1372         case WM8962_VSS_XTD32_1:
1373         case WM8962_VSS_XTD32_0:
1374         case WM8962_VSS_XTS1_1:
1375         case WM8962_VSS_XTS1_0:
1376         case WM8962_VSS_XTS2_1:
1377         case WM8962_VSS_XTS2_0:
1378         case WM8962_VSS_XTS3_1:
1379         case WM8962_VSS_XTS3_0:
1380         case WM8962_VSS_XTS4_1:
1381         case WM8962_VSS_XTS4_0:
1382         case WM8962_VSS_XTS5_1:
1383         case WM8962_VSS_XTS5_0:
1384         case WM8962_VSS_XTS6_1:
1385         case WM8962_VSS_XTS6_0:
1386         case WM8962_VSS_XTS7_1:
1387         case WM8962_VSS_XTS7_0:
1388         case WM8962_VSS_XTS8_1:
1389         case WM8962_VSS_XTS8_0:
1390         case WM8962_VSS_XTS9_1:
1391         case WM8962_VSS_XTS9_0:
1392         case WM8962_VSS_XTS10_1:
1393         case WM8962_VSS_XTS10_0:
1394         case WM8962_VSS_XTS11_1:
1395         case WM8962_VSS_XTS11_0:
1396         case WM8962_VSS_XTS12_1:
1397         case WM8962_VSS_XTS12_0:
1398         case WM8962_VSS_XTS13_1:
1399         case WM8962_VSS_XTS13_0:
1400         case WM8962_VSS_XTS14_1:
1401         case WM8962_VSS_XTS14_0:
1402         case WM8962_VSS_XTS15_1:
1403         case WM8962_VSS_XTS15_0:
1404         case WM8962_VSS_XTS16_1:
1405         case WM8962_VSS_XTS16_0:
1406         case WM8962_VSS_XTS17_1:
1407         case WM8962_VSS_XTS17_0:
1408         case WM8962_VSS_XTS18_1:
1409         case WM8962_VSS_XTS18_0:
1410         case WM8962_VSS_XTS19_1:
1411         case WM8962_VSS_XTS19_0:
1412         case WM8962_VSS_XTS20_1:
1413         case WM8962_VSS_XTS20_0:
1414         case WM8962_VSS_XTS21_1:
1415         case WM8962_VSS_XTS21_0:
1416         case WM8962_VSS_XTS22_1:
1417         case WM8962_VSS_XTS22_0:
1418         case WM8962_VSS_XTS23_1:
1419         case WM8962_VSS_XTS23_0:
1420         case WM8962_VSS_XTS24_1:
1421         case WM8962_VSS_XTS24_0:
1422         case WM8962_VSS_XTS25_1:
1423         case WM8962_VSS_XTS25_0:
1424         case WM8962_VSS_XTS26_1:
1425         case WM8962_VSS_XTS26_0:
1426         case WM8962_VSS_XTS27_1:
1427         case WM8962_VSS_XTS27_0:
1428         case WM8962_VSS_XTS28_1:
1429         case WM8962_VSS_XTS28_0:
1430         case WM8962_VSS_XTS29_1:
1431         case WM8962_VSS_XTS29_0:
1432         case WM8962_VSS_XTS30_1:
1433         case WM8962_VSS_XTS30_0:
1434         case WM8962_VSS_XTS31_1:
1435         case WM8962_VSS_XTS31_0:
1436         case WM8962_VSS_XTS32_1:
1437         case WM8962_VSS_XTS32_0:
1438                 return true;
1439         default:
1440                 return false;
1441         }
1442 }
1443
1444 static int wm8962_reset(struct wm8962_priv *wm8962)
1445 {
1446         int ret;
1447
1448         ret = regmap_write(wm8962->regmap, WM8962_SOFTWARE_RESET, 0x6243);
1449         if (ret != 0)
1450                 return ret;
1451
1452         return regmap_write(wm8962->regmap, WM8962_PLL_SOFTWARE_RESET, 0);
1453 }
1454
1455 static const DECLARE_TLV_DB_SCALE(inpga_tlv, -2325, 75, 0);
1456 static const DECLARE_TLV_DB_SCALE(mixin_tlv, -1500, 300, 0);
1457 static const unsigned int mixinpga_tlv[] = {
1458         TLV_DB_RANGE_HEAD(5),
1459         0, 1, TLV_DB_SCALE_ITEM(0, 600, 0),
1460         2, 2, TLV_DB_SCALE_ITEM(1300, 1300, 0),
1461         3, 4, TLV_DB_SCALE_ITEM(1800, 200, 0),
1462         5, 5, TLV_DB_SCALE_ITEM(2400, 0, 0),
1463         6, 7, TLV_DB_SCALE_ITEM(2700, 300, 0),
1464 };
1465 static const DECLARE_TLV_DB_SCALE(beep_tlv, -9600, 600, 1);
1466 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
1467 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
1468 static const DECLARE_TLV_DB_SCALE(inmix_tlv, -600, 600, 0);
1469 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
1470 static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
1471 static const DECLARE_TLV_DB_SCALE(hp_tlv, -700, 100, 0);
1472 static const unsigned int classd_tlv[] = {
1473         TLV_DB_RANGE_HEAD(2),
1474         0, 6, TLV_DB_SCALE_ITEM(0, 150, 0),
1475         7, 7, TLV_DB_SCALE_ITEM(1200, 0, 0),
1476 };
1477 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
1478
1479 static int wm8962_dsp2_write_config(struct snd_soc_codec *codec)
1480 {
1481         return 0;
1482 }
1483
1484 static int wm8962_dsp2_set_enable(struct snd_soc_codec *codec, u16 val)
1485 {
1486         u16 adcl = snd_soc_read(codec, WM8962_LEFT_ADC_VOLUME);
1487         u16 adcr = snd_soc_read(codec, WM8962_RIGHT_ADC_VOLUME);
1488         u16 dac = snd_soc_read(codec, WM8962_ADC_DAC_CONTROL_1);
1489
1490         /* Mute the ADCs and DACs */
1491         snd_soc_write(codec, WM8962_LEFT_ADC_VOLUME, 0);
1492         snd_soc_write(codec, WM8962_RIGHT_ADC_VOLUME, WM8962_ADC_VU);
1493         snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1,
1494                             WM8962_DAC_MUTE, WM8962_DAC_MUTE);
1495
1496         snd_soc_write(codec, WM8962_SOUNDSTAGE_ENABLES_0, val);
1497
1498         /* Restore the ADCs and DACs */
1499         snd_soc_write(codec, WM8962_LEFT_ADC_VOLUME, adcl);
1500         snd_soc_write(codec, WM8962_RIGHT_ADC_VOLUME, adcr);
1501         snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1,
1502                             WM8962_DAC_MUTE, dac);
1503
1504         return 0;
1505 }
1506
1507 static int wm8962_dsp2_start(struct snd_soc_codec *codec)
1508 {
1509         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1510
1511         wm8962_dsp2_write_config(codec);
1512
1513         snd_soc_write(codec, WM8962_DSP2_EXECCONTROL, WM8962_DSP2_RUNR);
1514
1515         wm8962_dsp2_set_enable(codec, wm8962->dsp2_ena);
1516
1517         return 0;
1518 }
1519
1520 static int wm8962_dsp2_stop(struct snd_soc_codec *codec)
1521 {
1522         wm8962_dsp2_set_enable(codec, 0);
1523
1524         snd_soc_write(codec, WM8962_DSP2_EXECCONTROL, WM8962_DSP2_STOP);
1525
1526         return 0;
1527 }
1528
1529 #define WM8962_DSP2_ENABLE(xname, xshift) \
1530 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1531         .info = wm8962_dsp2_ena_info, \
1532         .get = wm8962_dsp2_ena_get, .put = wm8962_dsp2_ena_put, \
1533         .private_value = xshift }
1534
1535 static int wm8962_dsp2_ena_info(struct snd_kcontrol *kcontrol,
1536                                 struct snd_ctl_elem_info *uinfo)
1537 {
1538         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1539
1540         uinfo->count = 1;
1541         uinfo->value.integer.min = 0;
1542         uinfo->value.integer.max = 1;
1543
1544         return 0;
1545 }
1546
1547 static int wm8962_dsp2_ena_get(struct snd_kcontrol *kcontrol,
1548                                struct snd_ctl_elem_value *ucontrol)
1549 {
1550         int shift = kcontrol->private_value;
1551         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1552         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1553
1554         ucontrol->value.integer.value[0] = !!(wm8962->dsp2_ena & 1 << shift);
1555
1556         return 0;
1557 }
1558
1559 static int wm8962_dsp2_ena_put(struct snd_kcontrol *kcontrol,
1560                                struct snd_ctl_elem_value *ucontrol)
1561 {
1562         int shift = kcontrol->private_value;
1563         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1564         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1565         int old = wm8962->dsp2_ena;
1566         int ret = 0;
1567         int dsp2_running = snd_soc_read(codec, WM8962_DSP2_POWER_MANAGEMENT) &
1568                 WM8962_DSP2_ENA;
1569
1570         mutex_lock(&codec->mutex);
1571
1572         if (ucontrol->value.integer.value[0])
1573                 wm8962->dsp2_ena |= 1 << shift;
1574         else
1575                 wm8962->dsp2_ena &= ~(1 << shift);
1576
1577         if (wm8962->dsp2_ena == old)
1578                 goto out;
1579
1580         ret = 1;
1581
1582         if (dsp2_running) {
1583                 if (wm8962->dsp2_ena)
1584                         wm8962_dsp2_set_enable(codec, wm8962->dsp2_ena);
1585                 else
1586                         wm8962_dsp2_stop(codec);
1587         }
1588
1589 out:
1590         mutex_unlock(&codec->mutex);
1591
1592         return ret;
1593 }
1594
1595 /* The VU bits for the headphones are in a different register to the mute
1596  * bits and only take effect on the PGA if it is actually powered.
1597  */
1598 static int wm8962_put_hp_sw(struct snd_kcontrol *kcontrol,
1599                             struct snd_ctl_elem_value *ucontrol)
1600 {
1601         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1602         u16 *reg_cache = codec->reg_cache;
1603         int ret;
1604
1605         /* Apply the update (if any) */
1606         ret = snd_soc_put_volsw(kcontrol, ucontrol);
1607         if (ret == 0)
1608                 return 0;
1609
1610         /* If the left PGA is enabled hit that VU bit... */
1611         if (snd_soc_read(codec, WM8962_PWR_MGMT_2) & WM8962_HPOUTL_PGA_ENA)
1612                 return snd_soc_write(codec, WM8962_HPOUTL_VOLUME,
1613                                      reg_cache[WM8962_HPOUTL_VOLUME]);
1614
1615         /* ...otherwise the right.  The VU is stereo. */
1616         if (snd_soc_read(codec, WM8962_PWR_MGMT_2) & WM8962_HPOUTR_PGA_ENA)
1617                 return snd_soc_write(codec, WM8962_HPOUTR_VOLUME,
1618                                      reg_cache[WM8962_HPOUTR_VOLUME]);
1619
1620         return 0;
1621 }
1622
1623 /* The VU bits for the speakers are in a different register to the mute
1624  * bits and only take effect on the PGA if it is actually powered.
1625  */
1626 static int wm8962_put_spk_sw(struct snd_kcontrol *kcontrol,
1627                             struct snd_ctl_elem_value *ucontrol)
1628 {
1629         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1630         int ret;
1631
1632         /* Apply the update (if any) */
1633         ret = snd_soc_put_volsw(kcontrol, ucontrol);
1634         if (ret == 0)
1635                 return 0;
1636
1637         /* If the left PGA is enabled hit that VU bit... */
1638         ret = snd_soc_read(codec, WM8962_PWR_MGMT_2);
1639         if (ret & WM8962_SPKOUTL_PGA_ENA) {
1640                 snd_soc_write(codec, WM8962_SPKOUTL_VOLUME,
1641                               snd_soc_read(codec, WM8962_SPKOUTL_VOLUME));
1642                 return 1;
1643         }
1644
1645         /* ...otherwise the right.  The VU is stereo. */
1646         if (ret & WM8962_SPKOUTR_PGA_ENA)
1647                 snd_soc_write(codec, WM8962_SPKOUTR_VOLUME,
1648                               snd_soc_read(codec, WM8962_SPKOUTR_VOLUME));
1649
1650         return 1;
1651 }
1652
1653 static const char *cap_hpf_mode_text[] = {
1654         "Hi-fi", "Application"
1655 };
1656
1657 static const struct soc_enum cap_hpf_mode =
1658         SOC_ENUM_SINGLE(WM8962_ADC_DAC_CONTROL_2, 10, 2, cap_hpf_mode_text);
1659
1660
1661 static const char *cap_lhpf_mode_text[] = {
1662         "LPF", "HPF"
1663 };
1664
1665 static const struct soc_enum cap_lhpf_mode =
1666         SOC_ENUM_SINGLE(WM8962_LHPF1, 1, 2, cap_lhpf_mode_text);
1667
1668 static const struct snd_kcontrol_new wm8962_snd_controls[] = {
1669 SOC_DOUBLE("Input Mixer Switch", WM8962_INPUT_MIXER_CONTROL_1, 3, 2, 1, 1),
1670
1671 SOC_SINGLE_TLV("MIXINL IN2L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 6, 7, 0,
1672                mixin_tlv),
1673 SOC_SINGLE_TLV("MIXINL PGA Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 3, 7, 0,
1674                mixinpga_tlv),
1675 SOC_SINGLE_TLV("MIXINL IN3L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 0, 7, 0,
1676                mixin_tlv),
1677
1678 SOC_SINGLE_TLV("MIXINR IN2R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 6, 7, 0,
1679                mixin_tlv),
1680 SOC_SINGLE_TLV("MIXINR PGA Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 3, 7, 0,
1681                mixinpga_tlv),
1682 SOC_SINGLE_TLV("MIXINR IN3R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 0, 7, 0,
1683                mixin_tlv),
1684
1685 SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8962_LEFT_ADC_VOLUME,
1686                  WM8962_RIGHT_ADC_VOLUME, 1, 127, 0, digital_tlv),
1687 SOC_DOUBLE_R_TLV("Capture Volume", WM8962_LEFT_INPUT_VOLUME,
1688                  WM8962_RIGHT_INPUT_VOLUME, 0, 63, 0, inpga_tlv),
1689 SOC_DOUBLE_R("Capture Switch", WM8962_LEFT_INPUT_VOLUME,
1690              WM8962_RIGHT_INPUT_VOLUME, 7, 1, 1),
1691 SOC_DOUBLE_R("Capture ZC Switch", WM8962_LEFT_INPUT_VOLUME,
1692              WM8962_RIGHT_INPUT_VOLUME, 6, 1, 1),
1693 SOC_SINGLE("Capture HPF Switch", WM8962_ADC_DAC_CONTROL_1, 0, 1, 1),
1694 SOC_ENUM("Capture HPF Mode", cap_hpf_mode),
1695 SOC_SINGLE("Capture HPF Cutoff", WM8962_ADC_DAC_CONTROL_2, 7, 7, 0),
1696 SOC_SINGLE("Capture LHPF Switch", WM8962_LHPF1, 0, 1, 0),
1697 SOC_ENUM("Capture LHPF Mode", cap_lhpf_mode),
1698
1699 SOC_DOUBLE_R_TLV("Sidetone Volume", WM8962_DAC_DSP_MIXING_1,
1700                  WM8962_DAC_DSP_MIXING_2, 4, 12, 0, st_tlv),
1701
1702 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8962_LEFT_DAC_VOLUME,
1703                  WM8962_RIGHT_DAC_VOLUME, 1, 127, 0, digital_tlv),
1704 SOC_SINGLE("DAC High Performance Switch", WM8962_ADC_DAC_CONTROL_2, 0, 1, 0),
1705 SOC_SINGLE("DAC L/R Swap Switch", WM8962_AUDIO_INTERFACE_0, 5, 1, 0),
1706 SOC_SINGLE("ADC L/R Swap Switch", WM8962_AUDIO_INTERFACE_0, 8, 1, 0),
1707
1708 SOC_SINGLE("ADC High Performance Switch", WM8962_ADDITIONAL_CONTROL_1,
1709            5, 1, 0),
1710
1711 SOC_SINGLE_TLV("Beep Volume", WM8962_BEEP_GENERATOR_1, 4, 15, 0, beep_tlv),
1712
1713 SOC_DOUBLE_R_TLV("Headphone Volume", WM8962_HPOUTL_VOLUME,
1714                  WM8962_HPOUTR_VOLUME, 0, 127, 0, out_tlv),
1715 SOC_DOUBLE_EXT("Headphone Switch", WM8962_PWR_MGMT_2, 1, 0, 1, 1,
1716                snd_soc_get_volsw, wm8962_put_hp_sw),
1717 SOC_DOUBLE_R("Headphone ZC Switch", WM8962_HPOUTL_VOLUME, WM8962_HPOUTR_VOLUME,
1718              7, 1, 0),
1719 SOC_DOUBLE_TLV("Headphone Aux Volume", WM8962_ANALOGUE_HP_2, 3, 6, 7, 0,
1720                hp_tlv),
1721
1722 SOC_DOUBLE_R("Headphone Mixer Switch", WM8962_HEADPHONE_MIXER_3,
1723              WM8962_HEADPHONE_MIXER_4, 8, 1, 1),
1724
1725 SOC_SINGLE_TLV("HPMIXL IN4L Volume", WM8962_HEADPHONE_MIXER_3,
1726                3, 7, 0, bypass_tlv),
1727 SOC_SINGLE_TLV("HPMIXL IN4R Volume", WM8962_HEADPHONE_MIXER_3,
1728                0, 7, 0, bypass_tlv),
1729 SOC_SINGLE_TLV("HPMIXL MIXINL Volume", WM8962_HEADPHONE_MIXER_3,
1730                7, 1, 1, inmix_tlv),
1731 SOC_SINGLE_TLV("HPMIXL MIXINR Volume", WM8962_HEADPHONE_MIXER_3,
1732                6, 1, 1, inmix_tlv),
1733
1734 SOC_SINGLE_TLV("HPMIXR IN4L Volume", WM8962_HEADPHONE_MIXER_4,
1735                3, 7, 0, bypass_tlv),
1736 SOC_SINGLE_TLV("HPMIXR IN4R Volume", WM8962_HEADPHONE_MIXER_4,
1737                0, 7, 0, bypass_tlv),
1738 SOC_SINGLE_TLV("HPMIXR MIXINL Volume", WM8962_HEADPHONE_MIXER_4,
1739                7, 1, 1, inmix_tlv),
1740 SOC_SINGLE_TLV("HPMIXR MIXINR Volume", WM8962_HEADPHONE_MIXER_4,
1741                6, 1, 1, inmix_tlv),
1742
1743 SOC_SINGLE_TLV("Speaker Boost Volume", WM8962_CLASS_D_CONTROL_2, 0, 7, 0,
1744                classd_tlv),
1745
1746 SOC_SINGLE("EQ Switch", WM8962_EQ1, WM8962_EQ_ENA_SHIFT, 1, 0),
1747 SOC_DOUBLE_R_TLV("EQ1 Volume", WM8962_EQ2, WM8962_EQ22,
1748                  WM8962_EQL_B1_GAIN_SHIFT, 31, 0, eq_tlv),
1749 SOC_DOUBLE_R_TLV("EQ2 Volume", WM8962_EQ2, WM8962_EQ22,
1750                  WM8962_EQL_B2_GAIN_SHIFT, 31, 0, eq_tlv),
1751 SOC_DOUBLE_R_TLV("EQ3 Volume", WM8962_EQ2, WM8962_EQ22,
1752                  WM8962_EQL_B3_GAIN_SHIFT, 31, 0, eq_tlv),
1753 SOC_DOUBLE_R_TLV("EQ4 Volume", WM8962_EQ3, WM8962_EQ23,
1754                  WM8962_EQL_B4_GAIN_SHIFT, 31, 0, eq_tlv),
1755 SOC_DOUBLE_R_TLV("EQ5 Volume", WM8962_EQ3, WM8962_EQ23,
1756                  WM8962_EQL_B5_GAIN_SHIFT, 31, 0, eq_tlv),
1757
1758 WM8962_DSP2_ENABLE("VSS Switch", WM8962_VSS_ENA_SHIFT),
1759 WM8962_DSP2_ENABLE("HPF1 Switch", WM8962_HPF1_ENA_SHIFT),
1760 WM8962_DSP2_ENABLE("HPF2 Switch", WM8962_HPF2_ENA_SHIFT),
1761 WM8962_DSP2_ENABLE("HD Bass Switch", WM8962_HDBASS_ENA_SHIFT),
1762 };
1763
1764 static const struct snd_kcontrol_new wm8962_spk_mono_controls[] = {
1765 SOC_SINGLE_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME, 0, 127, 0, out_tlv),
1766 SOC_SINGLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 1, 1,
1767                snd_soc_get_volsw, wm8962_put_spk_sw),
1768 SOC_SINGLE("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, 7, 1, 0),
1769
1770 SOC_SINGLE("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3, 8, 1, 1),
1771 SOC_SINGLE_TLV("Speaker Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
1772                3, 7, 0, bypass_tlv),
1773 SOC_SINGLE_TLV("Speaker Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
1774                0, 7, 0, bypass_tlv),
1775 SOC_SINGLE_TLV("Speaker Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
1776                7, 1, 1, inmix_tlv),
1777 SOC_SINGLE_TLV("Speaker Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
1778                6, 1, 1, inmix_tlv),
1779 SOC_SINGLE_TLV("Speaker Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
1780                7, 1, 0, inmix_tlv),
1781 SOC_SINGLE_TLV("Speaker Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
1782                6, 1, 0, inmix_tlv),
1783 };
1784
1785 static const struct snd_kcontrol_new wm8962_spk_stereo_controls[] = {
1786 SOC_DOUBLE_R_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME,
1787                  WM8962_SPKOUTR_VOLUME, 0, 127, 0, out_tlv),
1788 SOC_DOUBLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 0, 1, 1,
1789                snd_soc_get_volsw, wm8962_put_spk_sw),
1790 SOC_DOUBLE_R("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, WM8962_SPKOUTR_VOLUME,
1791              7, 1, 0),
1792
1793 SOC_DOUBLE_R("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3,
1794              WM8962_SPEAKER_MIXER_4, 8, 1, 1),
1795
1796 SOC_SINGLE_TLV("SPKOUTL Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
1797                3, 7, 0, bypass_tlv),
1798 SOC_SINGLE_TLV("SPKOUTL Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
1799                0, 7, 0, bypass_tlv),
1800 SOC_SINGLE_TLV("SPKOUTL Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
1801                7, 1, 1, inmix_tlv),
1802 SOC_SINGLE_TLV("SPKOUTL Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
1803                6, 1, 1, inmix_tlv),
1804 SOC_SINGLE_TLV("SPKOUTL Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
1805                7, 1, 0, inmix_tlv),
1806 SOC_SINGLE_TLV("SPKOUTL Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
1807                6, 1, 0, inmix_tlv),
1808
1809 SOC_SINGLE_TLV("SPKOUTR Mixer IN4L Volume", WM8962_SPEAKER_MIXER_4,
1810                3, 7, 0, bypass_tlv),
1811 SOC_SINGLE_TLV("SPKOUTR Mixer IN4R Volume", WM8962_SPEAKER_MIXER_4,
1812                0, 7, 0, bypass_tlv),
1813 SOC_SINGLE_TLV("SPKOUTR Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_4,
1814                7, 1, 1, inmix_tlv),
1815 SOC_SINGLE_TLV("SPKOUTR Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_4,
1816                6, 1, 1, inmix_tlv),
1817 SOC_SINGLE_TLV("SPKOUTR Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
1818                5, 1, 0, inmix_tlv),
1819 SOC_SINGLE_TLV("SPKOUTR Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
1820                4, 1, 0, inmix_tlv),
1821 };
1822
1823 static int cp_event(struct snd_soc_dapm_widget *w,
1824                     struct snd_kcontrol *kcontrol, int event)
1825 {
1826         switch (event) {
1827         case SND_SOC_DAPM_POST_PMU:
1828                 msleep(5);
1829                 break;
1830
1831         default:
1832                 BUG();
1833                 return -EINVAL;
1834         }
1835
1836         return 0;
1837 }
1838
1839 static int hp_event(struct snd_soc_dapm_widget *w,
1840                     struct snd_kcontrol *kcontrol, int event)
1841 {
1842         struct snd_soc_codec *codec = w->codec;
1843         int timeout;
1844         int reg;
1845         int expected = (WM8962_DCS_STARTUP_DONE_HP1L |
1846                         WM8962_DCS_STARTUP_DONE_HP1R);
1847
1848         switch (event) {
1849         case SND_SOC_DAPM_POST_PMU:
1850                 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1851                                     WM8962_HP1L_ENA | WM8962_HP1R_ENA,
1852                                     WM8962_HP1L_ENA | WM8962_HP1R_ENA);
1853                 udelay(20);
1854
1855                 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1856                                     WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY,
1857                                     WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY);
1858
1859                 /* Start the DC servo */
1860                 snd_soc_update_bits(codec, WM8962_DC_SERVO_1,
1861                                     WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
1862                                     WM8962_HP1L_DCS_STARTUP |
1863                                     WM8962_HP1R_DCS_STARTUP,
1864                                     WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
1865                                     WM8962_HP1L_DCS_STARTUP |
1866                                     WM8962_HP1R_DCS_STARTUP);
1867
1868                 /* Wait for it to complete, should be well under 100ms */
1869                 timeout = 0;
1870                 do {
1871                         msleep(1);
1872                         reg = snd_soc_read(codec, WM8962_DC_SERVO_6);
1873                         if (reg < 0) {
1874                                 dev_err(codec->dev,
1875                                         "Failed to read DCS status: %d\n",
1876                                         reg);
1877                                 continue;
1878                         }
1879                         dev_dbg(codec->dev, "DCS status: %x\n", reg);
1880                 } while (++timeout < 200 && (reg & expected) != expected);
1881
1882                 if ((reg & expected) != expected)
1883                         dev_err(codec->dev, "DC servo timed out\n");
1884                 else
1885                         dev_dbg(codec->dev, "DC servo complete after %dms\n",
1886                                 timeout);
1887
1888                 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1889                                     WM8962_HP1L_ENA_OUTP |
1890                                     WM8962_HP1R_ENA_OUTP,
1891                                     WM8962_HP1L_ENA_OUTP |
1892                                     WM8962_HP1R_ENA_OUTP);
1893                 udelay(20);
1894
1895                 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1896                                     WM8962_HP1L_RMV_SHORT |
1897                                     WM8962_HP1R_RMV_SHORT,
1898                                     WM8962_HP1L_RMV_SHORT |
1899                                     WM8962_HP1R_RMV_SHORT);
1900                 break;
1901
1902         case SND_SOC_DAPM_PRE_PMD:
1903                 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1904                                     WM8962_HP1L_RMV_SHORT |
1905                                     WM8962_HP1R_RMV_SHORT, 0);
1906
1907                 udelay(20);
1908
1909                 snd_soc_update_bits(codec, WM8962_DC_SERVO_1,
1910                                     WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
1911                                     WM8962_HP1L_DCS_STARTUP |
1912                                     WM8962_HP1R_DCS_STARTUP,
1913                                     0);
1914
1915                 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1916                                     WM8962_HP1L_ENA | WM8962_HP1R_ENA |
1917                                     WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY |
1918                                     WM8962_HP1L_ENA_OUTP |
1919                                     WM8962_HP1R_ENA_OUTP, 0);
1920
1921                 break;
1922
1923         default:
1924                 BUG();
1925                 return -EINVAL;
1926
1927         }
1928
1929         return 0;
1930 }
1931
1932 /* VU bits for the output PGAs only take effect while the PGA is powered */
1933 static int out_pga_event(struct snd_soc_dapm_widget *w,
1934                          struct snd_kcontrol *kcontrol, int event)
1935 {
1936         struct snd_soc_codec *codec = w->codec;
1937         int reg;
1938
1939         switch (w->shift) {
1940         case WM8962_HPOUTR_PGA_ENA_SHIFT:
1941                 reg = WM8962_HPOUTR_VOLUME;
1942                 break;
1943         case WM8962_HPOUTL_PGA_ENA_SHIFT:
1944                 reg = WM8962_HPOUTL_VOLUME;
1945                 break;
1946         case WM8962_SPKOUTR_PGA_ENA_SHIFT:
1947                 reg = WM8962_SPKOUTR_VOLUME;
1948                 break;
1949         case WM8962_SPKOUTL_PGA_ENA_SHIFT:
1950                 reg = WM8962_SPKOUTL_VOLUME;
1951                 break;
1952         default:
1953                 BUG();
1954                 return -EINVAL;
1955         }
1956
1957         switch (event) {
1958         case SND_SOC_DAPM_POST_PMU:
1959                 return snd_soc_write(codec, reg, snd_soc_read(codec, reg));
1960         default:
1961                 BUG();
1962                 return -EINVAL;
1963         }
1964 }
1965
1966 static int dsp2_event(struct snd_soc_dapm_widget *w,
1967                       struct snd_kcontrol *kcontrol, int event)
1968 {
1969         struct snd_soc_codec *codec = w->codec;
1970         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1971
1972         switch (event) {
1973         case SND_SOC_DAPM_POST_PMU:
1974                 if (wm8962->dsp2_ena)
1975                         wm8962_dsp2_start(codec);
1976                 break;
1977
1978         case SND_SOC_DAPM_PRE_PMD:
1979                 if (wm8962->dsp2_ena)
1980                         wm8962_dsp2_stop(codec);
1981                 break;
1982
1983         default:
1984                 BUG();
1985                 return -EINVAL;
1986         }
1987
1988         return 0;
1989 }
1990
1991 static const char *st_text[] = { "None", "Left", "Right" };
1992
1993 static const struct soc_enum str_enum =
1994         SOC_ENUM_SINGLE(WM8962_DAC_DSP_MIXING_1, 2, 3, st_text);
1995
1996 static const struct snd_kcontrol_new str_mux =
1997         SOC_DAPM_ENUM("Right Sidetone", str_enum);
1998
1999 static const struct soc_enum stl_enum =
2000         SOC_ENUM_SINGLE(WM8962_DAC_DSP_MIXING_2, 2, 3, st_text);
2001
2002 static const struct snd_kcontrol_new stl_mux =
2003         SOC_DAPM_ENUM("Left Sidetone", stl_enum);
2004
2005 static const char *outmux_text[] = { "DAC", "Mixer" };
2006
2007 static const struct soc_enum spkoutr_enum =
2008         SOC_ENUM_SINGLE(WM8962_SPEAKER_MIXER_2, 7, 2, outmux_text);
2009
2010 static const struct snd_kcontrol_new spkoutr_mux =
2011         SOC_DAPM_ENUM("SPKOUTR Mux", spkoutr_enum);
2012
2013 static const struct soc_enum spkoutl_enum =
2014         SOC_ENUM_SINGLE(WM8962_SPEAKER_MIXER_1, 7, 2, outmux_text);
2015
2016 static const struct snd_kcontrol_new spkoutl_mux =
2017         SOC_DAPM_ENUM("SPKOUTL Mux", spkoutl_enum);
2018
2019 static const struct soc_enum hpoutr_enum =
2020         SOC_ENUM_SINGLE(WM8962_HEADPHONE_MIXER_2, 7, 2, outmux_text);
2021
2022 static const struct snd_kcontrol_new hpoutr_mux =
2023         SOC_DAPM_ENUM("HPOUTR Mux", hpoutr_enum);
2024
2025 static const struct soc_enum hpoutl_enum =
2026         SOC_ENUM_SINGLE(WM8962_HEADPHONE_MIXER_1, 7, 2, outmux_text);
2027
2028 static const struct snd_kcontrol_new hpoutl_mux =
2029         SOC_DAPM_ENUM("HPOUTL Mux", hpoutl_enum);
2030
2031 static const struct snd_kcontrol_new inpgal[] = {
2032 SOC_DAPM_SINGLE("IN1L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 3, 1, 0),
2033 SOC_DAPM_SINGLE("IN2L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 2, 1, 0),
2034 SOC_DAPM_SINGLE("IN3L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 1, 1, 0),
2035 SOC_DAPM_SINGLE("IN4L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 0, 1, 0),
2036 };
2037
2038 static const struct snd_kcontrol_new inpgar[] = {
2039 SOC_DAPM_SINGLE("IN1R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 3, 1, 0),
2040 SOC_DAPM_SINGLE("IN2R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 2, 1, 0),
2041 SOC_DAPM_SINGLE("IN3R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 1, 1, 0),
2042 SOC_DAPM_SINGLE("IN4R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 0, 1, 0),
2043 };
2044
2045 static const struct snd_kcontrol_new mixinl[] = {
2046 SOC_DAPM_SINGLE("IN2L Switch", WM8962_INPUT_MIXER_CONTROL_2, 5, 1, 0),
2047 SOC_DAPM_SINGLE("IN3L Switch", WM8962_INPUT_MIXER_CONTROL_2, 4, 1, 0),
2048 SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 3, 1, 0),
2049 };
2050
2051 static const struct snd_kcontrol_new mixinr[] = {
2052 SOC_DAPM_SINGLE("IN2R Switch", WM8962_INPUT_MIXER_CONTROL_2, 2, 1, 0),
2053 SOC_DAPM_SINGLE("IN3R Switch", WM8962_INPUT_MIXER_CONTROL_2, 1, 1, 0),
2054 SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 0, 1, 0),
2055 };
2056
2057 static const struct snd_kcontrol_new hpmixl[] = {
2058 SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_1, 5, 1, 0),
2059 SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_1, 4, 1, 0),
2060 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_1, 3, 1, 0),
2061 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_1, 2, 1, 0),
2062 SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_1, 1, 1, 0),
2063 SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_1, 0, 1, 0),
2064 };
2065
2066 static const struct snd_kcontrol_new hpmixr[] = {
2067 SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_2, 5, 1, 0),
2068 SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_2, 4, 1, 0),
2069 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_2, 3, 1, 0),
2070 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_2, 2, 1, 0),
2071 SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_2, 1, 1, 0),
2072 SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_2, 0, 1, 0),
2073 };
2074
2075 static const struct snd_kcontrol_new spkmixl[] = {
2076 SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_1, 5, 1, 0),
2077 SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_1, 4, 1, 0),
2078 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_1, 3, 1, 0),
2079 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_1, 2, 1, 0),
2080 SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_1, 1, 1, 0),
2081 SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_1, 0, 1, 0),
2082 };
2083
2084 static const struct snd_kcontrol_new spkmixr[] = {
2085 SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_2, 5, 1, 0),
2086 SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_2, 4, 1, 0),
2087 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_2, 3, 1, 0),
2088 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_2, 2, 1, 0),
2089 SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_2, 1, 1, 0),
2090 SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_2, 0, 1, 0),
2091 };
2092
2093 static const struct snd_soc_dapm_widget wm8962_dapm_widgets[] = {
2094 SND_SOC_DAPM_INPUT("IN1L"),
2095 SND_SOC_DAPM_INPUT("IN1R"),
2096 SND_SOC_DAPM_INPUT("IN2L"),
2097 SND_SOC_DAPM_INPUT("IN2R"),
2098 SND_SOC_DAPM_INPUT("IN3L"),
2099 SND_SOC_DAPM_INPUT("IN3R"),
2100 SND_SOC_DAPM_INPUT("IN4L"),
2101 SND_SOC_DAPM_INPUT("IN4R"),
2102 SND_SOC_DAPM_SIGGEN("Beep"),
2103 SND_SOC_DAPM_INPUT("DMICDAT"),
2104
2105 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8962_PWR_MGMT_1, 1, 0, NULL, 0),
2106
2107 SND_SOC_DAPM_SUPPLY("Class G", WM8962_CHARGE_PUMP_B, 0, 1, NULL, 0),
2108 SND_SOC_DAPM_SUPPLY("SYSCLK", WM8962_CLOCKING2, 5, 0, NULL, 0),
2109 SND_SOC_DAPM_SUPPLY("Charge Pump", WM8962_CHARGE_PUMP_1, 0, 0, cp_event,
2110                     SND_SOC_DAPM_POST_PMU),
2111 SND_SOC_DAPM_SUPPLY("TOCLK", WM8962_ADDITIONAL_CONTROL_1, 0, 0, NULL, 0),
2112 SND_SOC_DAPM_SUPPLY_S("DSP2", 1, WM8962_DSP2_POWER_MANAGEMENT,
2113                       WM8962_DSP2_ENA_SHIFT, 0, dsp2_event,
2114                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2115 SND_SOC_DAPM_SUPPLY("TEMP_HP", WM8962_ADDITIONAL_CONTROL_4, 2, 0, NULL, 0),
2116 SND_SOC_DAPM_SUPPLY("TEMP_SPK", WM8962_ADDITIONAL_CONTROL_4, 1, 0, NULL, 0),
2117
2118 SND_SOC_DAPM_MIXER("INPGAL", WM8962_LEFT_INPUT_PGA_CONTROL, 4, 0,
2119                    inpgal, ARRAY_SIZE(inpgal)),
2120 SND_SOC_DAPM_MIXER("INPGAR", WM8962_RIGHT_INPUT_PGA_CONTROL, 4, 0,
2121                    inpgar, ARRAY_SIZE(inpgar)),
2122 SND_SOC_DAPM_MIXER("MIXINL", WM8962_PWR_MGMT_1, 5, 0,
2123                    mixinl, ARRAY_SIZE(mixinl)),
2124 SND_SOC_DAPM_MIXER("MIXINR", WM8962_PWR_MGMT_1, 4, 0,
2125                    mixinr, ARRAY_SIZE(mixinr)),
2126
2127 SND_SOC_DAPM_AIF_IN("DMIC_ENA", NULL, 0, WM8962_PWR_MGMT_1, 10, 0),
2128
2129 SND_SOC_DAPM_ADC("ADCL", "Capture", WM8962_PWR_MGMT_1, 3, 0),
2130 SND_SOC_DAPM_ADC("ADCR", "Capture", WM8962_PWR_MGMT_1, 2, 0),
2131
2132 SND_SOC_DAPM_MUX("STL", SND_SOC_NOPM, 0, 0, &stl_mux),
2133 SND_SOC_DAPM_MUX("STR", SND_SOC_NOPM, 0, 0, &str_mux),
2134
2135 SND_SOC_DAPM_DAC("DACL", "Playback", WM8962_PWR_MGMT_2, 8, 0),
2136 SND_SOC_DAPM_DAC("DACR", "Playback", WM8962_PWR_MGMT_2, 7, 0),
2137
2138 SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
2139 SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
2140
2141 SND_SOC_DAPM_MIXER("HPMIXL", WM8962_MIXER_ENABLES, 3, 0,
2142                    hpmixl, ARRAY_SIZE(hpmixl)),
2143 SND_SOC_DAPM_MIXER("HPMIXR", WM8962_MIXER_ENABLES, 2, 0,
2144                    hpmixr, ARRAY_SIZE(hpmixr)),
2145
2146 SND_SOC_DAPM_MUX_E("HPOUTL PGA", WM8962_PWR_MGMT_2, 6, 0, &hpoutl_mux,
2147                    out_pga_event, SND_SOC_DAPM_POST_PMU),
2148 SND_SOC_DAPM_MUX_E("HPOUTR PGA", WM8962_PWR_MGMT_2, 5, 0, &hpoutr_mux,
2149                    out_pga_event, SND_SOC_DAPM_POST_PMU),
2150
2151 SND_SOC_DAPM_PGA_E("HPOUT", SND_SOC_NOPM, 0, 0, NULL, 0, hp_event,
2152                    SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2153
2154 SND_SOC_DAPM_OUTPUT("HPOUTL"),
2155 SND_SOC_DAPM_OUTPUT("HPOUTR"),
2156 };
2157
2158 static const struct snd_soc_dapm_widget wm8962_dapm_spk_mono_widgets[] = {
2159 SND_SOC_DAPM_MIXER("Speaker Mixer", WM8962_MIXER_ENABLES, 1, 0,
2160                    spkmixl, ARRAY_SIZE(spkmixl)),
2161 SND_SOC_DAPM_MUX_E("Speaker PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
2162                    out_pga_event, SND_SOC_DAPM_POST_PMU),
2163 SND_SOC_DAPM_PGA("Speaker Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0),
2164 SND_SOC_DAPM_OUTPUT("SPKOUT"),
2165 };
2166
2167 static const struct snd_soc_dapm_widget wm8962_dapm_spk_stereo_widgets[] = {
2168 SND_SOC_DAPM_MIXER("SPKOUTL Mixer", WM8962_MIXER_ENABLES, 1, 0,
2169                    spkmixl, ARRAY_SIZE(spkmixl)),
2170 SND_SOC_DAPM_MIXER("SPKOUTR Mixer", WM8962_MIXER_ENABLES, 0, 0,
2171                    spkmixr, ARRAY_SIZE(spkmixr)),
2172
2173 SND_SOC_DAPM_MUX_E("SPKOUTL PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
2174                    out_pga_event, SND_SOC_DAPM_POST_PMU),
2175 SND_SOC_DAPM_MUX_E("SPKOUTR PGA", WM8962_PWR_MGMT_2, 3, 0, &spkoutr_mux,
2176                    out_pga_event, SND_SOC_DAPM_POST_PMU),
2177
2178 SND_SOC_DAPM_PGA("SPKOUTR Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0),
2179 SND_SOC_DAPM_PGA("SPKOUTL Output", WM8962_CLASS_D_CONTROL_1, 6, 0, NULL, 0),
2180
2181 SND_SOC_DAPM_OUTPUT("SPKOUTL"),
2182 SND_SOC_DAPM_OUTPUT("SPKOUTR"),
2183 };
2184
2185 static const struct snd_soc_dapm_route wm8962_intercon[] = {
2186         { "INPGAL", "IN1L Switch", "IN1L" },
2187         { "INPGAL", "IN2L Switch", "IN2L" },
2188         { "INPGAL", "IN3L Switch", "IN3L" },
2189         { "INPGAL", "IN4L Switch", "IN4L" },
2190
2191         { "INPGAR", "IN1R Switch", "IN1R" },
2192         { "INPGAR", "IN2R Switch", "IN2R" },
2193         { "INPGAR", "IN3R Switch", "IN3R" },
2194         { "INPGAR", "IN4R Switch", "IN4R" },
2195
2196         { "MIXINL", "IN2L Switch", "IN2L" },
2197         { "MIXINL", "IN3L Switch", "IN3L" },
2198         { "MIXINL", "PGA Switch", "INPGAL" },
2199
2200         { "MIXINR", "IN2R Switch", "IN2R" },
2201         { "MIXINR", "IN3R Switch", "IN3R" },
2202         { "MIXINR", "PGA Switch", "INPGAR" },
2203
2204         { "MICBIAS", NULL, "SYSCLK" },
2205
2206         { "DMIC_ENA", NULL, "DMICDAT" },
2207
2208         { "ADCL", NULL, "SYSCLK" },
2209         { "ADCL", NULL, "TOCLK" },
2210         { "ADCL", NULL, "MIXINL" },
2211         { "ADCL", NULL, "DMIC_ENA" },
2212         { "ADCL", NULL, "DSP2" },
2213
2214         { "ADCR", NULL, "SYSCLK" },
2215         { "ADCR", NULL, "TOCLK" },
2216         { "ADCR", NULL, "MIXINR" },
2217         { "ADCR", NULL, "DMIC_ENA" },
2218         { "ADCR", NULL, "DSP2" },
2219
2220         { "STL", "Left", "ADCL" },
2221         { "STL", "Right", "ADCR" },
2222         { "STL", NULL, "Class G" },
2223
2224         { "STR", "Left", "ADCL" },
2225         { "STR", "Right", "ADCR" },
2226         { "STR", NULL, "Class G" },
2227
2228         { "DACL", NULL, "SYSCLK" },
2229         { "DACL", NULL, "TOCLK" },
2230         { "DACL", NULL, "Beep" },
2231         { "DACL", NULL, "STL" },
2232         { "DACL", NULL, "DSP2" },
2233
2234         { "DACR", NULL, "SYSCLK" },
2235         { "DACR", NULL, "TOCLK" },
2236         { "DACR", NULL, "Beep" },
2237         { "DACR", NULL, "STR" },
2238         { "DACR", NULL, "DSP2" },
2239
2240         { "HPMIXL", "IN4L Switch", "IN4L" },
2241         { "HPMIXL", "IN4R Switch", "IN4R" },
2242         { "HPMIXL", "DACL Switch", "DACL" },
2243         { "HPMIXL", "DACR Switch", "DACR" },
2244         { "HPMIXL", "MIXINL Switch", "MIXINL" },
2245         { "HPMIXL", "MIXINR Switch", "MIXINR" },
2246
2247         { "HPMIXR", "IN4L Switch", "IN4L" },
2248         { "HPMIXR", "IN4R Switch", "IN4R" },
2249         { "HPMIXR", "DACL Switch", "DACL" },
2250         { "HPMIXR", "DACR Switch", "DACR" },
2251         { "HPMIXR", "MIXINL Switch", "MIXINL" },
2252         { "HPMIXR", "MIXINR Switch", "MIXINR" },
2253
2254         { "Left Bypass", NULL, "HPMIXL" },
2255         { "Left Bypass", NULL, "Class G" },
2256
2257         { "Right Bypass", NULL, "HPMIXR" },
2258         { "Right Bypass", NULL, "Class G" },
2259
2260         { "HPOUTL PGA", "Mixer", "Left Bypass" },
2261         { "HPOUTL PGA", "DAC", "DACL" },
2262
2263         { "HPOUTR PGA", "Mixer", "Right Bypass" },
2264         { "HPOUTR PGA", "DAC", "DACR" },
2265
2266         { "HPOUT", NULL, "HPOUTL PGA" },
2267         { "HPOUT", NULL, "HPOUTR PGA" },
2268         { "HPOUT", NULL, "Charge Pump" },
2269         { "HPOUT", NULL, "SYSCLK" },
2270         { "HPOUT", NULL, "TOCLK" },
2271
2272         { "HPOUTL", NULL, "HPOUT" },
2273         { "HPOUTR", NULL, "HPOUT" },
2274
2275         { "HPOUTL", NULL, "TEMP_HP" },
2276         { "HPOUTR", NULL, "TEMP_HP" },
2277 };
2278
2279 static const struct snd_soc_dapm_route wm8962_spk_mono_intercon[] = {
2280         { "Speaker Mixer", "IN4L Switch", "IN4L" },
2281         { "Speaker Mixer", "IN4R Switch", "IN4R" },
2282         { "Speaker Mixer", "DACL Switch", "DACL" },
2283         { "Speaker Mixer", "DACR Switch", "DACR" },
2284         { "Speaker Mixer", "MIXINL Switch", "MIXINL" },
2285         { "Speaker Mixer", "MIXINR Switch", "MIXINR" },
2286
2287         { "Speaker PGA", "Mixer", "Speaker Mixer" },
2288         { "Speaker PGA", "DAC", "DACL" },
2289
2290         { "Speaker Output", NULL, "Speaker PGA" },
2291         { "Speaker Output", NULL, "SYSCLK" },
2292         { "Speaker Output", NULL, "TOCLK" },
2293         { "Speaker Output", NULL, "TEMP_SPK" },
2294
2295         { "SPKOUT", NULL, "Speaker Output" },
2296 };
2297
2298 static const struct snd_soc_dapm_route wm8962_spk_stereo_intercon[] = {
2299         { "SPKOUTL Mixer", "IN4L Switch", "IN4L" },
2300         { "SPKOUTL Mixer", "IN4R Switch", "IN4R" },
2301         { "SPKOUTL Mixer", "DACL Switch", "DACL" },
2302         { "SPKOUTL Mixer", "DACR Switch", "DACR" },
2303         { "SPKOUTL Mixer", "MIXINL Switch", "MIXINL" },
2304         { "SPKOUTL Mixer", "MIXINR Switch", "MIXINR" },
2305
2306         { "SPKOUTR Mixer", "IN4L Switch", "IN4L" },
2307         { "SPKOUTR Mixer", "IN4R Switch", "IN4R" },
2308         { "SPKOUTR Mixer", "DACL Switch", "DACL" },
2309         { "SPKOUTR Mixer", "DACR Switch", "DACR" },
2310         { "SPKOUTR Mixer", "MIXINL Switch", "MIXINL" },
2311         { "SPKOUTR Mixer", "MIXINR Switch", "MIXINR" },
2312
2313         { "SPKOUTL PGA", "Mixer", "SPKOUTL Mixer" },
2314         { "SPKOUTL PGA", "DAC", "DACL" },
2315
2316         { "SPKOUTR PGA", "Mixer", "SPKOUTR Mixer" },
2317         { "SPKOUTR PGA", "DAC", "DACR" },
2318
2319         { "SPKOUTL Output", NULL, "SPKOUTL PGA" },
2320         { "SPKOUTL Output", NULL, "SYSCLK" },
2321         { "SPKOUTL Output", NULL, "TOCLK" },
2322         { "SPKOUTL Output", NULL, "TEMP_SPK" },
2323
2324         { "SPKOUTR Output", NULL, "SPKOUTR PGA" },
2325         { "SPKOUTR Output", NULL, "SYSCLK" },
2326         { "SPKOUTR Output", NULL, "TOCLK" },
2327         { "SPKOUTR Output", NULL, "TEMP_SPK" },
2328
2329         { "SPKOUTL", NULL, "SPKOUTL Output" },
2330         { "SPKOUTR", NULL, "SPKOUTR Output" },
2331 };
2332
2333 static int wm8962_add_widgets(struct snd_soc_codec *codec)
2334 {
2335         struct wm8962_pdata *pdata = dev_get_platdata(codec->dev);
2336         struct snd_soc_dapm_context *dapm = &codec->dapm;
2337
2338         snd_soc_add_codec_controls(codec, wm8962_snd_controls,
2339                              ARRAY_SIZE(wm8962_snd_controls));
2340         if (pdata && pdata->spk_mono)
2341                 snd_soc_add_codec_controls(codec, wm8962_spk_mono_controls,
2342                                      ARRAY_SIZE(wm8962_spk_mono_controls));
2343         else
2344                 snd_soc_add_codec_controls(codec, wm8962_spk_stereo_controls,
2345                                      ARRAY_SIZE(wm8962_spk_stereo_controls));
2346
2347
2348         snd_soc_dapm_new_controls(dapm, wm8962_dapm_widgets,
2349                                   ARRAY_SIZE(wm8962_dapm_widgets));
2350         if (pdata && pdata->spk_mono)
2351                 snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_mono_widgets,
2352                                           ARRAY_SIZE(wm8962_dapm_spk_mono_widgets));
2353         else
2354                 snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_stereo_widgets,
2355                                           ARRAY_SIZE(wm8962_dapm_spk_stereo_widgets));
2356
2357         snd_soc_dapm_add_routes(dapm, wm8962_intercon,
2358                                 ARRAY_SIZE(wm8962_intercon));
2359         if (pdata && pdata->spk_mono)
2360                 snd_soc_dapm_add_routes(dapm, wm8962_spk_mono_intercon,
2361                                         ARRAY_SIZE(wm8962_spk_mono_intercon));
2362         else
2363                 snd_soc_dapm_add_routes(dapm, wm8962_spk_stereo_intercon,
2364                                         ARRAY_SIZE(wm8962_spk_stereo_intercon));
2365
2366
2367         snd_soc_dapm_disable_pin(dapm, "Beep");
2368
2369         return 0;
2370 }
2371
2372 /* -1 for reserved values */
2373 static const int bclk_divs[] = {
2374         1, -1, 2, 3, 4, -1, 6, 8, -1, 12, 16, 24, -1, 32, 32, 32
2375 };
2376
2377 static const int sysclk_rates[] = {
2378         64, 128, 192, 256, 384, 512, 768, 1024, 1408, 1536, 3072, 6144
2379 };
2380
2381 static void wm8962_configure_bclk(struct snd_soc_codec *codec)
2382 {
2383         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2384         int dspclk, i;
2385         int clocking2 = 0;
2386         int clocking4 = 0;
2387         int aif2 = 0;
2388
2389         if (!wm8962->sysclk_rate) {
2390                 dev_dbg(codec->dev, "No SYSCLK configured\n");
2391                 return;
2392         }
2393
2394         if (!wm8962->bclk || !wm8962->lrclk) {
2395                 dev_dbg(codec->dev, "No audio clocks configured\n");
2396                 return;
2397         }
2398
2399         for (i = 0; i < ARRAY_SIZE(sysclk_rates); i++) {
2400                 if (sysclk_rates[i] == wm8962->sysclk_rate / wm8962->lrclk) {
2401                         clocking4 |= i << WM8962_SYSCLK_RATE_SHIFT;
2402                         break;
2403                 }
2404         }
2405
2406         if (i == ARRAY_SIZE(sysclk_rates)) {
2407                 dev_err(codec->dev, "Unsupported sysclk ratio %d\n",
2408                         wm8962->sysclk_rate / wm8962->lrclk);
2409                 return;
2410         }
2411
2412         dev_dbg(codec->dev, "Selected sysclk ratio %d\n", sysclk_rates[i]);
2413
2414         snd_soc_update_bits(codec, WM8962_CLOCKING_4,
2415                             WM8962_SYSCLK_RATE_MASK, clocking4);
2416
2417         dspclk = snd_soc_read(codec, WM8962_CLOCKING1);
2418         if (dspclk < 0) {
2419                 dev_err(codec->dev, "Failed to read DSPCLK: %d\n", dspclk);
2420                 return;
2421         }
2422
2423         dspclk = (dspclk & WM8962_DSPCLK_DIV_MASK) >> WM8962_DSPCLK_DIV_SHIFT;
2424         switch (dspclk) {
2425         case 0:
2426                 dspclk = wm8962->sysclk_rate;
2427                 break;
2428         case 1:
2429                 dspclk = wm8962->sysclk_rate / 2;
2430                 break;
2431         case 2:
2432                 dspclk = wm8962->sysclk_rate / 4;
2433                 break;
2434         default:
2435                 dev_warn(codec->dev, "Unknown DSPCLK divisor read back\n");
2436                 dspclk = wm8962->sysclk;
2437         }
2438
2439         dev_dbg(codec->dev, "DSPCLK is %dHz, BCLK %d\n", dspclk, wm8962->bclk);
2440
2441         /* We're expecting an exact match */
2442         for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2443                 if (bclk_divs[i] < 0)
2444                         continue;
2445
2446                 if (dspclk / bclk_divs[i] == wm8962->bclk) {
2447                         dev_dbg(codec->dev, "Selected BCLK_DIV %d for %dHz\n",
2448                                 bclk_divs[i], wm8962->bclk);
2449                         clocking2 |= i;
2450                         break;
2451                 }
2452         }
2453         if (i == ARRAY_SIZE(bclk_divs)) {
2454                 dev_err(codec->dev, "Unsupported BCLK ratio %d\n",
2455                         dspclk / wm8962->bclk);
2456                 return;
2457         }
2458
2459         aif2 |= wm8962->bclk / wm8962->lrclk;
2460         dev_dbg(codec->dev, "Selected LRCLK divisor %d for %dHz\n",
2461                 wm8962->bclk / wm8962->lrclk, wm8962->lrclk);
2462
2463         snd_soc_update_bits(codec, WM8962_CLOCKING2,
2464                             WM8962_BCLK_DIV_MASK, clocking2);
2465         snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_2,
2466                             WM8962_AIF_RATE_MASK, aif2);
2467 }
2468
2469 static int wm8962_set_bias_level(struct snd_soc_codec *codec,
2470                                  enum snd_soc_bias_level level)
2471 {
2472         if (level == codec->dapm.bias_level)
2473                 return 0;
2474
2475         switch (level) {
2476         case SND_SOC_BIAS_ON:
2477                 break;
2478
2479         case SND_SOC_BIAS_PREPARE:
2480                 /* VMID 2*50k */
2481                 snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
2482                                     WM8962_VMID_SEL_MASK, 0x80);
2483
2484                 wm8962_configure_bclk(codec);
2485                 break;
2486
2487         case SND_SOC_BIAS_STANDBY:
2488                 /* VMID 2*250k */
2489                 snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
2490                                     WM8962_VMID_SEL_MASK, 0x100);
2491                 break;
2492
2493         case SND_SOC_BIAS_OFF:
2494                 break;
2495         }
2496
2497         codec->dapm.bias_level = level;
2498         return 0;
2499 }
2500
2501 static const struct {
2502         int rate;
2503         int reg;
2504 } sr_vals[] = {
2505         { 48000, 0 },
2506         { 44100, 0 },
2507         { 32000, 1 },
2508         { 22050, 2 },
2509         { 24000, 2 },
2510         { 16000, 3 },
2511         { 11025, 4 },
2512         { 12000, 4 },
2513         { 8000,  5 },
2514         { 88200, 6 },
2515         { 96000, 6 },
2516 };
2517
2518 static int wm8962_hw_params(struct snd_pcm_substream *substream,
2519                             struct snd_pcm_hw_params *params,
2520                             struct snd_soc_dai *dai)
2521 {
2522         struct snd_soc_pcm_runtime *rtd = substream->private_data;
2523         struct snd_soc_codec *codec = rtd->codec;
2524         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2525         int i;
2526         int aif0 = 0;
2527         int adctl3 = 0;
2528
2529         wm8962->bclk = snd_soc_params_to_bclk(params);
2530         if (params_channels(params) == 1)
2531                 wm8962->bclk *= 2;
2532
2533         wm8962->lrclk = params_rate(params);
2534
2535         for (i = 0; i < ARRAY_SIZE(sr_vals); i++) {
2536                 if (sr_vals[i].rate == wm8962->lrclk) {
2537                         adctl3 |= sr_vals[i].reg;
2538                         break;
2539                 }
2540         }
2541         if (i == ARRAY_SIZE(sr_vals)) {
2542                 dev_err(codec->dev, "Unsupported rate %dHz\n", wm8962->lrclk);
2543                 return -EINVAL;
2544         }
2545
2546         if (wm8962->lrclk % 8000 == 0)
2547                 adctl3 |= WM8962_SAMPLE_RATE_INT_MODE;
2548
2549         switch (params_format(params)) {
2550         case SNDRV_PCM_FORMAT_S16_LE:
2551                 break;
2552         case SNDRV_PCM_FORMAT_S20_3LE:
2553                 aif0 |= 0x4;
2554                 break;
2555         case SNDRV_PCM_FORMAT_S24_LE:
2556                 aif0 |= 0x8;
2557                 break;
2558         case SNDRV_PCM_FORMAT_S32_LE:
2559                 aif0 |= 0xc;
2560                 break;
2561         default:
2562                 return -EINVAL;
2563         }
2564
2565         snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_0,
2566                             WM8962_WL_MASK, aif0);
2567         snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_3,
2568                             WM8962_SAMPLE_RATE_INT_MODE |
2569                             WM8962_SAMPLE_RATE_MASK, adctl3);
2570
2571         if (codec->dapm.bias_level == SND_SOC_BIAS_ON)
2572                 wm8962_configure_bclk(codec);
2573
2574         return 0;
2575 }
2576
2577 static int wm8962_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
2578                                  unsigned int freq, int dir)
2579 {
2580         struct snd_soc_codec *codec = dai->codec;
2581         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2582         int src;
2583
2584         switch (clk_id) {
2585         case WM8962_SYSCLK_MCLK:
2586                 wm8962->sysclk = WM8962_SYSCLK_MCLK;
2587                 src = 0;
2588                 break;
2589         case WM8962_SYSCLK_FLL:
2590                 wm8962->sysclk = WM8962_SYSCLK_FLL;
2591                 src = 1 << WM8962_SYSCLK_SRC_SHIFT;
2592                 break;
2593         default:
2594                 return -EINVAL;
2595         }
2596
2597         snd_soc_update_bits(codec, WM8962_CLOCKING2, WM8962_SYSCLK_SRC_MASK,
2598                             src);
2599
2600         wm8962->sysclk_rate = freq;
2601
2602         wm8962_configure_bclk(codec);
2603
2604         return 0;
2605 }
2606
2607 static int wm8962_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2608 {
2609         struct snd_soc_codec *codec = dai->codec;
2610         int aif0 = 0;
2611
2612         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2613         case SND_SOC_DAIFMT_DSP_B:
2614                 aif0 |= WM8962_LRCLK_INV | 3;
2615         case SND_SOC_DAIFMT_DSP_A:
2616                 aif0 |= 3;
2617
2618                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2619                 case SND_SOC_DAIFMT_NB_NF:
2620                 case SND_SOC_DAIFMT_IB_NF:
2621                         break;
2622                 default:
2623                         return -EINVAL;
2624                 }
2625                 break;
2626
2627         case SND_SOC_DAIFMT_RIGHT_J:
2628                 break;
2629         case SND_SOC_DAIFMT_LEFT_J:
2630                 aif0 |= 1;
2631                 break;
2632         case SND_SOC_DAIFMT_I2S:
2633                 aif0 |= 2;
2634                 break;
2635         default:
2636                 return -EINVAL;
2637         }
2638
2639         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2640         case SND_SOC_DAIFMT_NB_NF:
2641                 break;
2642         case SND_SOC_DAIFMT_IB_NF:
2643                 aif0 |= WM8962_BCLK_INV;
2644                 break;
2645         case SND_SOC_DAIFMT_NB_IF:
2646                 aif0 |= WM8962_LRCLK_INV;
2647                 break;
2648         case SND_SOC_DAIFMT_IB_IF:
2649                 aif0 |= WM8962_BCLK_INV | WM8962_LRCLK_INV;
2650                 break;
2651         default:
2652                 return -EINVAL;
2653         }
2654
2655         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2656         case SND_SOC_DAIFMT_CBM_CFM:
2657                 aif0 |= WM8962_MSTR;
2658                 break;
2659         case SND_SOC_DAIFMT_CBS_CFS:
2660                 break;
2661         default:
2662                 return -EINVAL;
2663         }
2664
2665         snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_0,
2666                             WM8962_FMT_MASK | WM8962_BCLK_INV | WM8962_MSTR |
2667                             WM8962_LRCLK_INV, aif0);
2668
2669         return 0;
2670 }
2671
2672 struct _fll_div {
2673         u16 fll_fratio;
2674         u16 fll_outdiv;
2675         u16 fll_refclk_div;
2676         u16 n;
2677         u16 theta;
2678         u16 lambda;
2679 };
2680
2681 /* The size in bits of the FLL divide multiplied by 10
2682  * to allow rounding later */
2683 #define FIXED_FLL_SIZE ((1 << 16) * 10)
2684
2685 static struct {
2686         unsigned int min;
2687         unsigned int max;
2688         u16 fll_fratio;
2689         int ratio;
2690 } fll_fratios[] = {
2691         {       0,    64000, 4, 16 },
2692         {   64000,   128000, 3,  8 },
2693         {  128000,   256000, 2,  4 },
2694         {  256000,  1000000, 1,  2 },
2695         { 1000000, 13500000, 0,  1 },
2696 };
2697
2698 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
2699                        unsigned int Fout)
2700 {
2701         unsigned int target;
2702         unsigned int div;
2703         unsigned int fratio, gcd_fll;
2704         int i;
2705
2706         /* Fref must be <=13.5MHz */
2707         div = 1;
2708         fll_div->fll_refclk_div = 0;
2709         while ((Fref / div) > 13500000) {
2710                 div *= 2;
2711                 fll_div->fll_refclk_div++;
2712
2713                 if (div > 4) {
2714                         pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
2715                                Fref);
2716                         return -EINVAL;
2717                 }
2718         }
2719
2720         pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
2721
2722         /* Apply the division for our remaining calculations */
2723         Fref /= div;
2724
2725         /* Fvco should be 90-100MHz; don't check the upper bound */
2726         div = 2;
2727         while (Fout * div < 90000000) {
2728                 div++;
2729                 if (div > 64) {
2730                         pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
2731                                Fout);
2732                         return -EINVAL;
2733                 }
2734         }
2735         target = Fout * div;
2736         fll_div->fll_outdiv = div - 1;
2737
2738         pr_debug("FLL Fvco=%dHz\n", target);
2739
2740         /* Find an appropriate FLL_FRATIO and factor it out of the target */
2741         for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
2742                 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
2743                         fll_div->fll_fratio = fll_fratios[i].fll_fratio;
2744                         fratio = fll_fratios[i].ratio;
2745                         break;
2746                 }
2747         }
2748         if (i == ARRAY_SIZE(fll_fratios)) {
2749                 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
2750                 return -EINVAL;
2751         }
2752
2753         fll_div->n = target / (fratio * Fref);
2754
2755         if (target % Fref == 0) {
2756                 fll_div->theta = 0;
2757                 fll_div->lambda = 0;
2758         } else {
2759                 gcd_fll = gcd(target, fratio * Fref);
2760
2761                 fll_div->theta = (target - (fll_div->n * fratio * Fref))
2762                         / gcd_fll;
2763                 fll_div->lambda = (fratio * Fref) / gcd_fll;
2764         }
2765
2766         pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
2767                  fll_div->n, fll_div->theta, fll_div->lambda);
2768         pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
2769                  fll_div->fll_fratio, fll_div->fll_outdiv,
2770                  fll_div->fll_refclk_div);
2771
2772         return 0;
2773 }
2774
2775 static int wm8962_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
2776                           unsigned int Fref, unsigned int Fout)
2777 {
2778         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2779         struct _fll_div fll_div;
2780         unsigned long timeout;
2781         int ret;
2782         int fll1 = 0;
2783
2784         /* Any change? */
2785         if (source == wm8962->fll_src && Fref == wm8962->fll_fref &&
2786             Fout == wm8962->fll_fout)
2787                 return 0;
2788
2789         if (Fout == 0) {
2790                 dev_dbg(codec->dev, "FLL disabled\n");
2791
2792                 wm8962->fll_fref = 0;
2793                 wm8962->fll_fout = 0;
2794
2795                 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
2796                                     WM8962_FLL_ENA, 0);
2797
2798                 pm_runtime_put(codec->dev);
2799
2800                 return 0;
2801         }
2802
2803         ret = fll_factors(&fll_div, Fref, Fout);
2804         if (ret != 0)
2805                 return ret;
2806
2807         /* Parameters good, disable so we can reprogram */
2808         snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0);
2809
2810         switch (fll_id) {
2811         case WM8962_FLL_MCLK:
2812         case WM8962_FLL_BCLK:
2813         case WM8962_FLL_OSC:
2814                 fll1 |= (fll_id - 1) << WM8962_FLL_REFCLK_SRC_SHIFT;
2815                 break;
2816         case WM8962_FLL_INT:
2817                 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
2818                                     WM8962_FLL_OSC_ENA, WM8962_FLL_OSC_ENA);
2819                 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_5,
2820                                     WM8962_FLL_FRC_NCO, WM8962_FLL_FRC_NCO);
2821                 break;
2822         default:
2823                 dev_err(codec->dev, "Unknown FLL source %d\n", ret);
2824                 return -EINVAL;
2825         }
2826
2827         if (fll_div.theta || fll_div.lambda)
2828                 fll1 |= WM8962_FLL_FRAC;
2829
2830         /* Stop the FLL while we reconfigure */
2831         snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0);
2832
2833         snd_soc_update_bits(codec, WM8962_FLL_CONTROL_2,
2834                             WM8962_FLL_OUTDIV_MASK |
2835                             WM8962_FLL_REFCLK_DIV_MASK,
2836                             (fll_div.fll_outdiv << WM8962_FLL_OUTDIV_SHIFT) |
2837                             (fll_div.fll_refclk_div));
2838
2839         snd_soc_update_bits(codec, WM8962_FLL_CONTROL_3,
2840                             WM8962_FLL_FRATIO_MASK, fll_div.fll_fratio);
2841
2842         snd_soc_write(codec, WM8962_FLL_CONTROL_6, fll_div.theta);
2843         snd_soc_write(codec, WM8962_FLL_CONTROL_7, fll_div.lambda);
2844         snd_soc_write(codec, WM8962_FLL_CONTROL_8, fll_div.n);
2845
2846         try_wait_for_completion(&wm8962->fll_lock);
2847
2848         pm_runtime_get_sync(codec->dev);
2849
2850         snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
2851                             WM8962_FLL_FRAC | WM8962_FLL_REFCLK_SRC_MASK |
2852                             WM8962_FLL_ENA, fll1 | WM8962_FLL_ENA);
2853
2854         dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
2855
2856         ret = 0;
2857
2858         if (fll1 & WM8962_FLL_ENA) {
2859                 /* This should be a massive overestimate but go even
2860                  * higher if we'll error out
2861                  */
2862                 if (wm8962->irq)
2863                         timeout = msecs_to_jiffies(5);
2864                 else
2865                         timeout = msecs_to_jiffies(1);
2866
2867                 timeout = wait_for_completion_timeout(&wm8962->fll_lock,
2868                                                       timeout);
2869
2870                 if (timeout == 0 && wm8962->irq) {
2871                         dev_err(codec->dev, "FLL lock timed out");
2872                         ret = -ETIMEDOUT;
2873                 }
2874         }
2875
2876         wm8962->fll_fref = Fref;
2877         wm8962->fll_fout = Fout;
2878         wm8962->fll_src = source;
2879
2880         return ret;
2881 }
2882
2883 static int wm8962_mute(struct snd_soc_dai *dai, int mute)
2884 {
2885         struct snd_soc_codec *codec = dai->codec;
2886         int val;
2887
2888         if (mute)
2889                 val = WM8962_DAC_MUTE;
2890         else
2891                 val = 0;
2892
2893         return snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1,
2894                                    WM8962_DAC_MUTE, val);
2895 }
2896
2897 #define WM8962_RATES SNDRV_PCM_RATE_8000_96000
2898
2899 #define WM8962_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2900                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2901
2902 static const struct snd_soc_dai_ops wm8962_dai_ops = {
2903         .hw_params = wm8962_hw_params,
2904         .set_sysclk = wm8962_set_dai_sysclk,
2905         .set_fmt = wm8962_set_dai_fmt,
2906         .digital_mute = wm8962_mute,
2907 };
2908
2909 static struct snd_soc_dai_driver wm8962_dai = {
2910         .name = "wm8962",
2911         .playback = {
2912                 .stream_name = "Playback",
2913                 .channels_min = 1,
2914                 .channels_max = 2,
2915                 .rates = WM8962_RATES,
2916                 .formats = WM8962_FORMATS,
2917         },
2918         .capture = {
2919                 .stream_name = "Capture",
2920                 .channels_min = 1,
2921                 .channels_max = 2,
2922                 .rates = WM8962_RATES,
2923                 .formats = WM8962_FORMATS,
2924         },
2925         .ops = &wm8962_dai_ops,
2926         .symmetric_rates = 1,
2927 };
2928
2929 static void wm8962_mic_work(struct work_struct *work)
2930 {
2931         struct wm8962_priv *wm8962 = container_of(work,
2932                                                   struct wm8962_priv,
2933                                                   mic_work.work);
2934         struct snd_soc_codec *codec = wm8962->codec;
2935         int status = 0;
2936         int irq_pol = 0;
2937         int reg;
2938
2939         reg = snd_soc_read(codec, WM8962_ADDITIONAL_CONTROL_4);
2940
2941         if (reg & WM8962_MICDET_STS) {
2942                 status |= SND_JACK_MICROPHONE;
2943                 irq_pol |= WM8962_MICD_IRQ_POL;
2944         }
2945
2946         if (reg & WM8962_MICSHORT_STS) {
2947                 status |= SND_JACK_BTN_0;
2948                 irq_pol |= WM8962_MICSCD_IRQ_POL;
2949         }
2950
2951         snd_soc_jack_report(wm8962->jack, status,
2952                             SND_JACK_MICROPHONE | SND_JACK_BTN_0);
2953
2954         snd_soc_update_bits(codec, WM8962_MICINT_SOURCE_POL,
2955                             WM8962_MICSCD_IRQ_POL |
2956                             WM8962_MICD_IRQ_POL, irq_pol);
2957 }
2958
2959 static irqreturn_t wm8962_irq(int irq, void *data)
2960 {
2961         struct device *dev = data;
2962         struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
2963         unsigned int mask;
2964         unsigned int active;
2965         int reg, ret;
2966
2967         ret = regmap_read(wm8962->regmap, WM8962_INTERRUPT_STATUS_2_MASK,
2968                           &mask);
2969         if (ret != 0) {
2970                 dev_err(dev, "Failed to read interrupt mask: %d\n",
2971                         ret);
2972                 return IRQ_NONE;
2973         }
2974
2975         ret = regmap_read(wm8962->regmap, WM8962_INTERRUPT_STATUS_2, &active);
2976         if (ret != 0) {
2977                 dev_err(dev, "Failed to read interrupt: %d\n", ret);
2978                 return IRQ_NONE;
2979         }
2980
2981         active &= ~mask;
2982
2983         if (!active)
2984                 return IRQ_NONE;
2985
2986         /* Acknowledge the interrupts */
2987         ret = regmap_write(wm8962->regmap, WM8962_INTERRUPT_STATUS_2, active);
2988         if (ret != 0)
2989                 dev_warn(dev, "Failed to ack interrupt: %d\n", ret);
2990
2991         if (active & WM8962_FLL_LOCK_EINT) {
2992                 dev_dbg(dev, "FLL locked\n");
2993                 complete(&wm8962->fll_lock);
2994         }
2995
2996         if (active & WM8962_FIFOS_ERR_EINT)
2997                 dev_err(dev, "FIFO error\n");
2998
2999         if (active & WM8962_TEMP_SHUT_EINT) {
3000                 dev_crit(dev, "Thermal shutdown\n");
3001
3002                 ret = regmap_read(wm8962->regmap,
3003                                   WM8962_THERMAL_SHUTDOWN_STATUS,  &reg);
3004                 if (ret != 0) {
3005                         dev_warn(dev, "Failed to read thermal status: %d\n",
3006                                  ret);
3007                         reg = 0;
3008                 }
3009
3010                 if (reg & WM8962_TEMP_ERR_HP)
3011                         dev_crit(dev, "Headphone thermal error\n");
3012                 if (reg & WM8962_TEMP_WARN_HP)
3013                         dev_crit(dev, "Headphone thermal warning\n");
3014                 if (reg & WM8962_TEMP_ERR_SPK)
3015                         dev_crit(dev, "Speaker thermal error\n");
3016                 if (reg & WM8962_TEMP_WARN_SPK)
3017                         dev_crit(dev, "Speaker thermal warning\n");
3018         }
3019
3020         if (active & (WM8962_MICSCD_EINT | WM8962_MICD_EINT)) {
3021                 dev_dbg(dev, "Microphone event detected\n");
3022
3023 #ifndef CONFIG_SND_SOC_WM8962_MODULE
3024                 trace_snd_soc_jack_irq(dev_name(dev));
3025 #endif
3026
3027                 pm_wakeup_event(dev, 300);
3028
3029                 schedule_delayed_work(&wm8962->mic_work,
3030                                       msecs_to_jiffies(250));
3031         }
3032
3033         return IRQ_HANDLED;
3034 }
3035
3036 /**
3037  * wm8962_mic_detect - Enable microphone detection via the WM8962 IRQ
3038  *
3039  * @codec:  WM8962 codec
3040  * @jack:   jack to report detection events on
3041  *
3042  * Enable microphone detection via IRQ on the WM8962.  If GPIOs are
3043  * being used to bring out signals to the processor then only platform
3044  * data configuration is needed for WM8962 and processor GPIOs should
3045  * be configured using snd_soc_jack_add_gpios() instead.
3046  *
3047  * If no jack is supplied detection will be disabled.
3048  */
3049 int wm8962_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack)
3050 {
3051         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3052         int irq_mask, enable;
3053
3054         wm8962->jack = jack;
3055         if (jack) {
3056                 irq_mask = 0;
3057                 enable = WM8962_MICDET_ENA;
3058         } else {
3059                 irq_mask = WM8962_MICD_EINT | WM8962_MICSCD_EINT;
3060                 enable = 0;
3061         }
3062
3063         snd_soc_update_bits(codec, WM8962_INTERRUPT_STATUS_2_MASK,
3064                             WM8962_MICD_EINT | WM8962_MICSCD_EINT, irq_mask);
3065         snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_4,
3066                             WM8962_MICDET_ENA, enable);
3067
3068         /* Send an initial empty report */
3069         snd_soc_jack_report(wm8962->jack, 0,
3070                             SND_JACK_MICROPHONE | SND_JACK_BTN_0);
3071
3072         if (jack) {
3073                 snd_soc_dapm_force_enable_pin(&codec->dapm, "SYSCLK");
3074                 snd_soc_dapm_force_enable_pin(&codec->dapm, "MICBIAS");
3075         } else {
3076                 snd_soc_dapm_disable_pin(&codec->dapm, "SYSCLK");
3077                 snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS");
3078         }
3079
3080         return 0;
3081 }
3082 EXPORT_SYMBOL_GPL(wm8962_mic_detect);
3083
3084 #if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE)
3085 static int beep_rates[] = {
3086         500, 1000, 2000, 4000,
3087 };
3088
3089 static void wm8962_beep_work(struct work_struct *work)
3090 {
3091         struct wm8962_priv *wm8962 =
3092                 container_of(work, struct wm8962_priv, beep_work);
3093         struct snd_soc_codec *codec = wm8962->codec;
3094         struct snd_soc_dapm_context *dapm = &codec->dapm;
3095         int i;
3096         int reg = 0;
3097         int best = 0;
3098
3099         if (wm8962->beep_rate) {
3100                 for (i = 0; i < ARRAY_SIZE(beep_rates); i++) {
3101                         if (abs(wm8962->beep_rate - beep_rates[i]) <
3102                             abs(wm8962->beep_rate - beep_rates[best]))
3103                                 best = i;
3104                 }
3105
3106                 dev_dbg(codec->dev, "Set beep rate %dHz for requested %dHz\n",
3107                         beep_rates[best], wm8962->beep_rate);
3108
3109                 reg = WM8962_BEEP_ENA | (best << WM8962_BEEP_RATE_SHIFT);
3110
3111                 snd_soc_dapm_enable_pin(dapm, "Beep");
3112         } else {
3113                 dev_dbg(codec->dev, "Disabling beep\n");
3114                 snd_soc_dapm_disable_pin(dapm, "Beep");
3115         }
3116
3117         snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1,
3118                             WM8962_BEEP_ENA | WM8962_BEEP_RATE_MASK, reg);
3119
3120         snd_soc_dapm_sync(dapm);
3121 }
3122
3123 /* For usability define a way of injecting beep events for the device -
3124  * many systems will not have a keyboard.
3125  */
3126 static int wm8962_beep_event(struct input_dev *dev, unsigned int type,
3127                              unsigned int code, int hz)
3128 {
3129         struct snd_soc_codec *codec = input_get_drvdata(dev);
3130         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3131
3132         dev_dbg(codec->dev, "Beep event %x %x\n", code, hz);
3133
3134         switch (code) {
3135         case SND_BELL:
3136                 if (hz)
3137                         hz = 1000;
3138         case SND_TONE:
3139                 break;
3140         default:
3141                 return -1;
3142         }
3143
3144         /* Kick the beep from a workqueue */
3145         wm8962->beep_rate = hz;
3146         schedule_work(&wm8962->beep_work);
3147         return 0;
3148 }
3149
3150 static ssize_t wm8962_beep_set(struct device *dev,
3151                                struct device_attribute *attr,
3152                                const char *buf, size_t count)
3153 {
3154         struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3155         long int time;
3156         int ret;
3157
3158         ret = strict_strtol(buf, 10, &time);
3159         if (ret != 0)
3160                 return ret;
3161
3162         input_event(wm8962->beep, EV_SND, SND_TONE, time);
3163
3164         return count;
3165 }
3166
3167 static DEVICE_ATTR(beep, 0200, NULL, wm8962_beep_set);
3168
3169 static void wm8962_init_beep(struct snd_soc_codec *codec)
3170 {
3171         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3172         int ret;
3173
3174         wm8962->beep = input_allocate_device();
3175         if (!wm8962->beep) {
3176                 dev_err(codec->dev, "Failed to allocate beep device\n");
3177                 return;
3178         }
3179
3180         INIT_WORK(&wm8962->beep_work, wm8962_beep_work);
3181         wm8962->beep_rate = 0;
3182
3183         wm8962->beep->name = "WM8962 Beep Generator";
3184         wm8962->beep->phys = dev_name(codec->dev);
3185         wm8962->beep->id.bustype = BUS_I2C;
3186
3187         wm8962->beep->evbit[0] = BIT_MASK(EV_SND);
3188         wm8962->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE);
3189         wm8962->beep->event = wm8962_beep_event;
3190         wm8962->beep->dev.parent = codec->dev;
3191         input_set_drvdata(wm8962->beep, codec);
3192
3193         ret = input_register_device(wm8962->beep);
3194         if (ret != 0) {
3195                 input_free_device(wm8962->beep);
3196                 wm8962->beep = NULL;
3197                 dev_err(codec->dev, "Failed to register beep device\n");
3198         }
3199
3200         ret = device_create_file(codec->dev, &dev_attr_beep);
3201         if (ret != 0) {
3202                 dev_err(codec->dev, "Failed to create keyclick file: %d\n",
3203                         ret);
3204         }
3205 }
3206
3207 static void wm8962_free_beep(struct snd_soc_codec *codec)
3208 {
3209         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3210
3211         device_remove_file(codec->dev, &dev_attr_beep);
3212         input_unregister_device(wm8962->beep);
3213         cancel_work_sync(&wm8962->beep_work);
3214         wm8962->beep = NULL;
3215
3216         snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1, WM8962_BEEP_ENA,0);
3217 }
3218 #else
3219 static void wm8962_init_beep(struct snd_soc_codec *codec)
3220 {
3221 }
3222
3223 static void wm8962_free_beep(struct snd_soc_codec *codec)
3224 {
3225 }
3226 #endif
3227
3228 static void wm8962_set_gpio_mode(struct snd_soc_codec *codec, int gpio)
3229 {
3230         int mask = 0;
3231         int val = 0;
3232
3233         /* Some of the GPIOs are behind MFP configuration and need to
3234          * be put into GPIO mode. */
3235         switch (gpio) {
3236         case 2:
3237                 mask = WM8962_CLKOUT2_SEL_MASK;
3238                 val = 1 << WM8962_CLKOUT2_SEL_SHIFT;
3239                 break;
3240         case 3:
3241                 mask = WM8962_CLKOUT3_SEL_MASK;
3242                 val = 1 << WM8962_CLKOUT3_SEL_SHIFT;
3243                 break;
3244         default:
3245                 break;
3246         }
3247
3248         if (mask)
3249                 snd_soc_update_bits(codec, WM8962_ANALOGUE_CLOCKING1,
3250                                     mask, val);
3251 }
3252
3253 #ifdef CONFIG_GPIOLIB
3254 static inline struct wm8962_priv *gpio_to_wm8962(struct gpio_chip *chip)
3255 {
3256         return container_of(chip, struct wm8962_priv, gpio_chip);
3257 }
3258
3259 static int wm8962_gpio_request(struct gpio_chip *chip, unsigned offset)
3260 {
3261         struct wm8962_priv *wm8962 = gpio_to_wm8962(chip);
3262         struct snd_soc_codec *codec = wm8962->codec;
3263
3264         /* The WM8962 GPIOs aren't linearly numbered.  For simplicity
3265          * we export linear numbers and error out if the unsupported
3266          * ones are requsted.
3267          */
3268         switch (offset + 1) {
3269         case 2:
3270         case 3:
3271         case 5:
3272         case 6:
3273                 break;
3274         default:
3275                 return -EINVAL;
3276         }
3277
3278         wm8962_set_gpio_mode(codec, offset + 1);
3279
3280         return 0;
3281 }
3282
3283 static void wm8962_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
3284 {
3285         struct wm8962_priv *wm8962 = gpio_to_wm8962(chip);
3286         struct snd_soc_codec *codec = wm8962->codec;
3287
3288         snd_soc_update_bits(codec, WM8962_GPIO_BASE + offset,
3289                             WM8962_GP2_LVL, !!value << WM8962_GP2_LVL_SHIFT);
3290 }
3291
3292 static int wm8962_gpio_direction_out(struct gpio_chip *chip,
3293                                      unsigned offset, int value)
3294 {
3295         struct wm8962_priv *wm8962 = gpio_to_wm8962(chip);
3296         struct snd_soc_codec *codec = wm8962->codec;
3297         int ret, val;
3298
3299         /* Force function 1 (logic output) */
3300         val = (1 << WM8962_GP2_FN_SHIFT) | (value << WM8962_GP2_LVL_SHIFT);
3301
3302         ret = snd_soc_update_bits(codec, WM8962_GPIO_BASE + offset,
3303                                   WM8962_GP2_FN_MASK | WM8962_GP2_LVL, val);
3304         if (ret < 0)
3305                 return ret;
3306
3307         return 0;
3308 }
3309
3310 static struct gpio_chip wm8962_template_chip = {
3311         .label                  = "wm8962",
3312         .owner                  = THIS_MODULE,
3313         .request                = wm8962_gpio_request,
3314         .direction_output       = wm8962_gpio_direction_out,
3315         .set                    = wm8962_gpio_set,
3316         .can_sleep              = 1,
3317 };
3318
3319 static void wm8962_init_gpio(struct snd_soc_codec *codec)
3320 {
3321         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3322         struct wm8962_pdata *pdata = dev_get_platdata(codec->dev);
3323         int ret;
3324
3325         wm8962->gpio_chip = wm8962_template_chip;
3326         wm8962->gpio_chip.ngpio = WM8962_MAX_GPIO;
3327         wm8962->gpio_chip.dev = codec->dev;
3328
3329         if (pdata && pdata->gpio_base)
3330                 wm8962->gpio_chip.base = pdata->gpio_base;
3331         else
3332                 wm8962->gpio_chip.base = -1;
3333
3334         ret = gpiochip_add(&wm8962->gpio_chip);
3335         if (ret != 0)
3336                 dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret);
3337 }
3338
3339 static void wm8962_free_gpio(struct snd_soc_codec *codec)
3340 {
3341         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3342         int ret;
3343
3344         ret = gpiochip_remove(&wm8962->gpio_chip);
3345         if (ret != 0)
3346                 dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret);
3347 }
3348 #else
3349 static void wm8962_init_gpio(struct snd_soc_codec *codec)
3350 {
3351 }
3352
3353 static void wm8962_free_gpio(struct snd_soc_codec *codec)
3354 {
3355 }
3356 #endif
3357
3358 static int wm8962_probe(struct snd_soc_codec *codec)
3359 {
3360         int ret;
3361         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3362         struct wm8962_pdata *pdata = dev_get_platdata(codec->dev);
3363         u16 *reg_cache = codec->reg_cache;
3364         int i, trigger, irq_pol;
3365         bool dmicclk, dmicdat;
3366
3367         wm8962->codec = codec;
3368         codec->control_data = wm8962->regmap;
3369
3370         ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
3371         if (ret != 0) {
3372                 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
3373                 return ret;
3374         }
3375
3376         wm8962->disable_nb[0].notifier_call = wm8962_regulator_event_0;
3377         wm8962->disable_nb[1].notifier_call = wm8962_regulator_event_1;
3378         wm8962->disable_nb[2].notifier_call = wm8962_regulator_event_2;
3379         wm8962->disable_nb[3].notifier_call = wm8962_regulator_event_3;
3380         wm8962->disable_nb[4].notifier_call = wm8962_regulator_event_4;
3381         wm8962->disable_nb[5].notifier_call = wm8962_regulator_event_5;
3382         wm8962->disable_nb[6].notifier_call = wm8962_regulator_event_6;
3383         wm8962->disable_nb[7].notifier_call = wm8962_regulator_event_7;
3384
3385         /* This should really be moved into the regulator core */
3386         for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++) {
3387                 ret = regulator_register_notifier(wm8962->supplies[i].consumer,
3388                                                   &wm8962->disable_nb[i]);
3389                 if (ret != 0) {
3390                         dev_err(codec->dev,
3391                                 "Failed to register regulator notifier: %d\n",
3392                                 ret);
3393                 }
3394         }
3395
3396         /* SYSCLK defaults to on; make sure it is off so we can safely
3397          * write to registers if the device is declocked.
3398          */
3399         snd_soc_update_bits(codec, WM8962_CLOCKING2, WM8962_SYSCLK_ENA, 0);
3400
3401         /* Ensure we have soft control over all registers */
3402         snd_soc_update_bits(codec, WM8962_CLOCKING2,
3403                             WM8962_CLKREG_OVD, WM8962_CLKREG_OVD);
3404
3405         /* Ensure that the oscillator and PLLs are disabled */
3406         snd_soc_update_bits(codec, WM8962_PLL2,
3407                             WM8962_OSC_ENA | WM8962_PLL2_ENA | WM8962_PLL3_ENA,
3408                             0);
3409
3410         if (pdata) {
3411                 /* Apply static configuration for GPIOs */
3412                 for (i = 0; i < ARRAY_SIZE(pdata->gpio_init); i++)
3413                         if (pdata->gpio_init[i]) {
3414                                 wm8962_set_gpio_mode(codec, i + 1);
3415                                 snd_soc_write(codec, 0x200 + i,
3416                                               pdata->gpio_init[i] & 0xffff);
3417                         }
3418
3419                 /* Put the speakers into mono mode? */
3420                 if (pdata->spk_mono)
3421                         reg_cache[WM8962_CLASS_D_CONTROL_2]
3422                                 |= WM8962_SPK_MONO;
3423
3424                 /* Micbias setup, detection enable and detection
3425                  * threasholds. */
3426                 if (pdata->mic_cfg)
3427                         snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_4,
3428                                             WM8962_MICDET_ENA |
3429                                             WM8962_MICDET_THR_MASK |
3430                                             WM8962_MICSHORT_THR_MASK |
3431                                             WM8962_MICBIAS_LVL,
3432                                             pdata->mic_cfg);
3433         }
3434
3435         /* Latch volume update bits */
3436         snd_soc_update_bits(codec, WM8962_LEFT_INPUT_VOLUME,
3437                             WM8962_IN_VU, WM8962_IN_VU);
3438         snd_soc_update_bits(codec, WM8962_RIGHT_INPUT_VOLUME,
3439                             WM8962_IN_VU, WM8962_IN_VU);
3440         snd_soc_update_bits(codec, WM8962_LEFT_ADC_VOLUME,
3441                             WM8962_ADC_VU, WM8962_ADC_VU);
3442         snd_soc_update_bits(codec, WM8962_RIGHT_ADC_VOLUME,
3443                             WM8962_ADC_VU, WM8962_ADC_VU);
3444         snd_soc_update_bits(codec, WM8962_LEFT_DAC_VOLUME,
3445                             WM8962_DAC_VU, WM8962_DAC_VU);
3446         snd_soc_update_bits(codec, WM8962_RIGHT_DAC_VOLUME,
3447                             WM8962_DAC_VU, WM8962_DAC_VU);
3448         snd_soc_update_bits(codec, WM8962_SPKOUTL_VOLUME,
3449                             WM8962_SPKOUT_VU, WM8962_SPKOUT_VU);
3450         snd_soc_update_bits(codec, WM8962_SPKOUTR_VOLUME,
3451                             WM8962_SPKOUT_VU, WM8962_SPKOUT_VU);
3452         snd_soc_update_bits(codec, WM8962_HPOUTL_VOLUME,
3453                             WM8962_HPOUT_VU, WM8962_HPOUT_VU);
3454         snd_soc_update_bits(codec, WM8962_HPOUTR_VOLUME,
3455                             WM8962_HPOUT_VU, WM8962_HPOUT_VU);
3456
3457         /* Stereo control for EQ */
3458         snd_soc_update_bits(codec, WM8962_EQ1, WM8962_EQ_SHARED_COEFF, 0);
3459
3460         /* Don't debouce interrupts so we don't need SYSCLK */
3461         snd_soc_update_bits(codec, WM8962_IRQ_DEBOUNCE,
3462                             WM8962_FLL_LOCK_DB | WM8962_PLL3_LOCK_DB |
3463                             WM8962_PLL2_LOCK_DB | WM8962_TEMP_SHUT_DB,
3464                             0);
3465
3466         wm8962_add_widgets(codec);
3467
3468         /* Save boards having to disable DMIC when not in use */
3469         dmicclk = false;
3470         dmicdat = false;
3471         for (i = 0; i < WM8962_MAX_GPIO; i++) {
3472                 switch (snd_soc_read(codec, WM8962_GPIO_BASE + i)
3473                         & WM8962_GP2_FN_MASK) {
3474                 case WM8962_GPIO_FN_DMICCLK:
3475                         dmicclk = true;
3476                         break;
3477                 case WM8962_GPIO_FN_DMICDAT:
3478                         dmicdat = true;
3479                         break;
3480                 default:
3481                         break;
3482                 }
3483         }
3484         if (!dmicclk || !dmicdat) {
3485                 dev_dbg(codec->dev, "DMIC not in use, disabling\n");
3486                 snd_soc_dapm_nc_pin(&codec->dapm, "DMICDAT");
3487         }
3488         if (dmicclk != dmicdat)
3489                 dev_warn(codec->dev, "DMIC GPIOs partially configured\n");
3490
3491         wm8962_init_beep(codec);
3492         wm8962_init_gpio(codec);
3493
3494         if (wm8962->irq) {
3495                 if (pdata && pdata->irq_active_low) {
3496                         trigger = IRQF_TRIGGER_LOW;
3497                         irq_pol = WM8962_IRQ_POL;
3498                 } else {
3499                         trigger = IRQF_TRIGGER_HIGH;
3500                         irq_pol = 0;
3501                 }
3502
3503                 snd_soc_update_bits(codec, WM8962_INTERRUPT_CONTROL,
3504                                     WM8962_IRQ_POL, irq_pol);
3505
3506                 ret = request_threaded_irq(wm8962->irq, NULL, wm8962_irq,
3507                                            trigger | IRQF_ONESHOT,
3508                                            "wm8962", codec->dev);
3509                 if (ret != 0) {
3510                         dev_err(codec->dev, "Failed to request IRQ %d: %d\n",
3511                                 wm8962->irq, ret);
3512                         wm8962->irq = 0;
3513                         /* Non-fatal */
3514                 } else {
3515                         /* Enable some IRQs by default */
3516                         snd_soc_update_bits(codec,
3517                                             WM8962_INTERRUPT_STATUS_2_MASK,
3518                                             WM8962_FLL_LOCK_EINT |
3519                                             WM8962_TEMP_SHUT_EINT |
3520                                             WM8962_FIFOS_ERR_EINT, 0);
3521                 }
3522         }
3523
3524         return 0;
3525 }
3526
3527 static int wm8962_remove(struct snd_soc_codec *codec)
3528 {
3529         struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3530         int i;
3531
3532         if (wm8962->irq)
3533                 free_irq(wm8962->irq, codec);
3534
3535         cancel_delayed_work_sync(&wm8962->mic_work);
3536
3537         wm8962_free_gpio(codec);
3538         wm8962_free_beep(codec);
3539         for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++)
3540                 regulator_unregister_notifier(wm8962->supplies[i].consumer,
3541                                               &wm8962->disable_nb[i]);
3542
3543         return 0;
3544 }
3545
3546 static struct snd_soc_codec_driver soc_codec_dev_wm8962 = {
3547         .probe =        wm8962_probe,
3548         .remove =       wm8962_remove,
3549         .set_bias_level = wm8962_set_bias_level,
3550         .set_pll = wm8962_set_fll,
3551         .idle_bias_off = true,
3552 };
3553
3554 /* Improve power consumption for IN4 DC measurement mode */
3555 static const struct reg_default wm8962_dc_measure[] = {
3556         { 0xfd, 0x1 },
3557         { 0xcc, 0x40 },
3558         { 0xfd, 0 },
3559 };
3560
3561 static const struct regmap_config wm8962_regmap = {
3562         .reg_bits = 16,
3563         .val_bits = 16,
3564
3565         .max_register = WM8962_MAX_REGISTER,
3566         .reg_defaults = wm8962_reg,
3567         .num_reg_defaults = ARRAY_SIZE(wm8962_reg),
3568         .volatile_reg = wm8962_volatile_register,
3569         .readable_reg = wm8962_readable_register,
3570         .cache_type = REGCACHE_RBTREE,
3571 };
3572
3573 static __devinit int wm8962_i2c_probe(struct i2c_client *i2c,
3574                                       const struct i2c_device_id *id)
3575 {
3576         struct wm8962_pdata *pdata = dev_get_platdata(&i2c->dev);
3577         struct wm8962_priv *wm8962;
3578         unsigned int reg;
3579         int ret, i;
3580
3581         wm8962 = devm_kzalloc(&i2c->dev, sizeof(struct wm8962_priv),
3582                               GFP_KERNEL);
3583         if (wm8962 == NULL)
3584                 return -ENOMEM;
3585
3586         i2c_set_clientdata(i2c, wm8962);
3587
3588         INIT_DELAYED_WORK(&wm8962->mic_work, wm8962_mic_work);
3589         init_completion(&wm8962->fll_lock);
3590         wm8962->irq = i2c->irq;
3591
3592         for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++)
3593                 wm8962->supplies[i].supply = wm8962_supply_names[i];
3594
3595         ret = regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8962->supplies),
3596                                  wm8962->supplies);
3597         if (ret != 0) {
3598                 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
3599                 goto err;
3600         }
3601
3602         ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
3603                                     wm8962->supplies);
3604         if (ret != 0) {
3605                 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
3606                 goto err_get;
3607         }
3608
3609         wm8962->regmap = regmap_init_i2c(i2c, &wm8962_regmap);
3610         if (IS_ERR(wm8962->regmap)) {
3611                 ret = PTR_ERR(wm8962->regmap);
3612                 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
3613                 goto err_enable;
3614         }
3615
3616         /*
3617          * We haven't marked the chip revision as volatile due to
3618          * sharing a register with the right input volume; explicitly
3619          * bypass the cache to read it.
3620          */
3621         regcache_cache_bypass(wm8962->regmap, true);
3622
3623         ret = regmap_read(wm8962->regmap, WM8962_SOFTWARE_RESET, &reg);
3624         if (ret < 0) {
3625                 dev_err(&i2c->dev, "Failed to read ID register\n");
3626                 goto err_regmap;
3627         }
3628         if (reg != 0x6243) {
3629                 dev_err(&i2c->dev,
3630                         "Device is not a WM8962, ID %x != 0x6243\n", reg);
3631                 ret = -EINVAL;
3632                 goto err_regmap;
3633         }
3634
3635         ret = regmap_read(wm8962->regmap, WM8962_RIGHT_INPUT_VOLUME, &reg);
3636         if (ret < 0) {
3637                 dev_err(&i2c->dev, "Failed to read device revision: %d\n",
3638                         ret);
3639                 goto err_regmap;
3640         }
3641
3642         dev_info(&i2c->dev, "customer id %x revision %c\n",
3643                  (reg & WM8962_CUST_ID_MASK) >> WM8962_CUST_ID_SHIFT,
3644                  ((reg & WM8962_CHIP_REV_MASK) >> WM8962_CHIP_REV_SHIFT)
3645                  + 'A');
3646
3647         regcache_cache_bypass(wm8962->regmap, false);
3648
3649         ret = wm8962_reset(wm8962);
3650         if (ret < 0) {
3651                 dev_err(&i2c->dev, "Failed to issue reset\n");
3652                 goto err_regmap;
3653         }
3654
3655         if (pdata && pdata->in4_dc_measure) {
3656                 ret = regmap_register_patch(wm8962->regmap,
3657                                             wm8962_dc_measure,
3658                                             ARRAY_SIZE(wm8962_dc_measure));
3659                 if (ret != 0)
3660                         dev_err(&i2c->dev,
3661                                 "Failed to configure for DC mesurement: %d\n",
3662                                 ret);
3663         }
3664
3665         pm_runtime_enable(&i2c->dev);
3666         pm_request_idle(&i2c->dev);
3667
3668         ret = snd_soc_register_codec(&i2c->dev,
3669                                      &soc_codec_dev_wm8962, &wm8962_dai, 1);
3670         if (ret < 0)
3671                 goto err_regmap;
3672
3673         /* The drivers should power up as needed */
3674         regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
3675
3676         return 0;
3677
3678 err_regmap:
3679         regmap_exit(wm8962->regmap);
3680 err_enable:
3681         regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
3682 err_get:
3683         regulator_bulk_free(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
3684 err:
3685         return ret;
3686 }
3687
3688 static __devexit int wm8962_i2c_remove(struct i2c_client *client)
3689 {
3690         struct wm8962_priv *wm8962 = dev_get_drvdata(&client->dev);
3691
3692         snd_soc_unregister_codec(&client->dev);
3693         regmap_exit(wm8962->regmap);
3694         regulator_bulk_free(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
3695         return 0;
3696 }
3697
3698 #ifdef CONFIG_PM_RUNTIME
3699 static int wm8962_runtime_resume(struct device *dev)
3700 {
3701         struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3702         int ret;
3703
3704         ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
3705                                     wm8962->supplies);
3706         if (ret != 0) {
3707                 dev_err(dev,
3708                         "Failed to enable supplies: %d\n", ret);
3709                 return ret;
3710         }
3711
3712         regcache_cache_only(wm8962->regmap, false);
3713         regcache_sync(wm8962->regmap);
3714
3715         regmap_update_bits(wm8962->regmap, WM8962_ANTI_POP,
3716                            WM8962_STARTUP_BIAS_ENA | WM8962_VMID_BUF_ENA,
3717                            WM8962_STARTUP_BIAS_ENA | WM8962_VMID_BUF_ENA);
3718
3719         /* Bias enable at 2*50k for ramp */
3720         regmap_update_bits(wm8962->regmap, WM8962_PWR_MGMT_1,
3721                            WM8962_VMID_SEL_MASK | WM8962_BIAS_ENA,
3722                            WM8962_BIAS_ENA | 0x180);
3723
3724         msleep(5);
3725
3726         /* VMID back to 2x250k for standby */
3727         regmap_update_bits(wm8962->regmap, WM8962_PWR_MGMT_1,
3728                            WM8962_VMID_SEL_MASK, 0x100);
3729
3730         return 0;
3731 }
3732
3733 static int wm8962_runtime_suspend(struct device *dev)
3734 {
3735         struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3736
3737         regmap_update_bits(wm8962->regmap, WM8962_PWR_MGMT_1,
3738                            WM8962_VMID_SEL_MASK | WM8962_BIAS_ENA, 0);
3739
3740         regmap_update_bits(wm8962->regmap, WM8962_ANTI_POP,
3741                            WM8962_STARTUP_BIAS_ENA |
3742                            WM8962_VMID_BUF_ENA, 0);
3743
3744         regcache_cache_only(wm8962->regmap, true);
3745
3746         regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies),
3747                                wm8962->supplies);
3748
3749         return 0;
3750 }
3751 #endif
3752
3753 static struct dev_pm_ops wm8962_pm = {
3754         SET_RUNTIME_PM_OPS(wm8962_runtime_suspend, wm8962_runtime_resume, NULL)
3755 };
3756
3757 static const struct i2c_device_id wm8962_i2c_id[] = {
3758         { "wm8962", 0 },
3759         { }
3760 };
3761 MODULE_DEVICE_TABLE(i2c, wm8962_i2c_id);
3762
3763 static struct i2c_driver wm8962_i2c_driver = {
3764         .driver = {
3765                 .name = "wm8962",
3766                 .owner = THIS_MODULE,
3767                 .pm = &wm8962_pm,
3768         },
3769         .probe =    wm8962_i2c_probe,
3770         .remove =   __devexit_p(wm8962_i2c_remove),
3771         .id_table = wm8962_i2c_id,
3772 };
3773
3774 module_i2c_driver(wm8962_i2c_driver);
3775
3776 MODULE_DESCRIPTION("ASoC WM8962 driver");
3777 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3778 MODULE_LICENSE("GPL");