sound/soc/codecs/wm8904.c

   1 /*
   2  * wm8904.c  --  WM8904 ALSA SoC Audio driver
   3  *
   4  * Copyright 2009 Wolfson Microelectronics plc
   5  *
   6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   7  *
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/i2c.h>
  20 #include <linux/regmap.h>
  21 #include <linux/regulator/consumer.h>
  22 #include <linux/slab.h>
  23 #include <sound/core.h>
  24 #include <sound/pcm.h>
  25 #include <sound/pcm_params.h>
  26 #include <sound/soc.h>
  27 #include <sound/initval.h>
  28 #include <sound/tlv.h>
  29 #include <sound/wm8904.h>
  30
  31 #include "wm8904.h"
  32
  33 enum wm8904_type {
  34         WM8904,
  35         WM8912,
  36 };
  37
  38 #define WM8904_NUM_DCS_CHANNELS 4
  39
  40 #define WM8904_NUM_SUPPLIES 5
  41 static const char *wm8904_supply_names[WM8904_NUM_SUPPLIES] = {
  42         "DCVDD",
  43         "DBVDD",
  44         "AVDD",
  45         "CPVDD",
  46         "MICVDD",
  47 };
  48
  49 /* codec private data */
  50 struct wm8904_priv {
  51         struct regmap *regmap;
  52
  53         enum wm8904_type devtype;
  54
  55         struct regulator_bulk_data supplies[WM8904_NUM_SUPPLIES];
  56
  57         struct wm8904_pdata *pdata;
  58
  59         int deemph;
  60
  61         /* Platform provided DRC configuration */
  62         const char **drc_texts;
  63         int drc_cfg;
  64         struct soc_enum drc_enum;
  65
  66         /* Platform provided ReTune mobile configuration */
  67         int num_retune_mobile_texts;
  68         const char **retune_mobile_texts;
  69         int retune_mobile_cfg;
  70         struct soc_enum retune_mobile_enum;
  71
  72         /* FLL setup */
  73         int fll_src;
  74         int fll_fref;
  75         int fll_fout;
  76
  77         /* Clocking configuration */
  78         unsigned int mclk_rate;
  79         int sysclk_src;
  80         unsigned int sysclk_rate;
  81
  82         int tdm_width;
  83         int tdm_slots;
  84         int bclk;
  85         int fs;
  86
  87         /* DC servo configuration - cached offset values */
  88         int dcs_state[WM8904_NUM_DCS_CHANNELS];
  89 };
  90
  91 static const struct reg_default wm8904_reg_defaults[] = {
  92         { 4,   0x0018 },     /* R4   - Bias Control 0 */
  93         { 5,   0x0000 },     /* R5   - VMID Control 0 */
  94         { 6,   0x0000 },     /* R6   - Mic Bias Control 0 */
  95         { 7,   0x0000 },     /* R7   - Mic Bias Control 1 */
  96         { 8,   0x0001 },     /* R8   - Analogue DAC 0 */
  97         { 9,   0x9696 },     /* R9   - mic Filter Control */
  98         { 10,  0x0001 },     /* R10  - Analogue ADC 0 */
  99         { 12,  0x0000 },     /* R12  - Power Management 0 */
 100         { 14,  0x0000 },     /* R14  - Power Management 2 */
 101         { 15,  0x0000 },     /* R15  - Power Management 3 */
 102         { 18,  0x0000 },     /* R18  - Power Management 6 */
 103         { 19,  0x945E },     /* R20  - Clock Rates 0 */
 104         { 21,  0x0C05 },     /* R21  - Clock Rates 1 */
 105         { 22,  0x0006 },     /* R22  - Clock Rates 2 */
 106         { 24,  0x0050 },     /* R24  - Audio Interface 0 */
 107         { 25,  0x000A },     /* R25  - Audio Interface 1 */
 108         { 26,  0x00E4 },     /* R26  - Audio Interface 2 */
 109         { 27,  0x0040 },     /* R27  - Audio Interface 3 */
 110         { 30,  0x00C0 },     /* R30  - DAC Digital Volume Left */
 111         { 31,  0x00C0 },     /* R31  - DAC Digital Volume Right */
 112         { 32,  0x0000 },     /* R32  - DAC Digital 0 */
 113         { 33,  0x0008 },     /* R33  - DAC Digital 1 */
 114         { 36,  0x00C0 },     /* R36  - ADC Digital Volume Left */
 115         { 37,  0x00C0 },     /* R37  - ADC Digital Volume Right */
 116         { 38,  0x0010 },     /* R38  - ADC Digital 0 */
 117         { 39,  0x0000 },     /* R39  - Digital Microphone 0 */
 118         { 40,  0x01AF },     /* R40  - DRC 0 */
 119         { 41,  0x3248 },     /* R41  - DRC 1 */
 120         { 42,  0x0000 },     /* R42  - DRC 2 */
 121         { 43,  0x0000 },     /* R43  - DRC 3 */
 122         { 44,  0x0085 },     /* R44  - Analogue Left Input 0 */
 123         { 45,  0x0085 },     /* R45  - Analogue Right Input 0 */
 124         { 46,  0x0044 },     /* R46  - Analogue Left Input 1 */
 125         { 47,  0x0044 },     /* R47  - Analogue Right Input 1 */
 126         { 57,  0x002D },     /* R57  - Analogue OUT1 Left */
 127         { 58,  0x002D },     /* R58  - Analogue OUT1 Right */
 128         { 59,  0x0039 },     /* R59  - Analogue OUT2 Left */
 129         { 60,  0x0039 },     /* R60  - Analogue OUT2 Right */
 130         { 61,  0x0000 },     /* R61  - Analogue OUT12 ZC */
 131         { 67,  0x0000 },     /* R67  - DC Servo 0 */
 132         { 69,  0xAAAA },     /* R69  - DC Servo 2 */
 133         { 71,  0xAAAA },     /* R71  - DC Servo 4 */
 134         { 72,  0xAAAA },     /* R72  - DC Servo 5 */
 135         { 90,  0x0000 },     /* R90  - Analogue HP 0 */
 136         { 94,  0x0000 },     /* R94  - Analogue Lineout 0 */
 137         { 98,  0x0000 },     /* R98  - Charge Pump 0 */
 138         { 104, 0x0004 },     /* R104 - Class W 0 */
 139         { 108, 0x0000 },     /* R108 - Write Sequencer 0 */
 140         { 109, 0x0000 },     /* R109 - Write Sequencer 1 */
 141         { 110, 0x0000 },     /* R110 - Write Sequencer 2 */
 142         { 111, 0x0000 },     /* R111 - Write Sequencer 3 */
 143         { 112, 0x0000 },     /* R112 - Write Sequencer 4 */
 144         { 116, 0x0000 },     /* R116 - FLL Control 1 */
 145         { 117, 0x0007 },     /* R117 - FLL Control 2 */
 146         { 118, 0x0000 },     /* R118 - FLL Control 3 */
 147         { 119, 0x2EE0 },     /* R119 - FLL Control 4 */
 148         { 120, 0x0004 },     /* R120 - FLL Control 5 */
 149         { 121, 0x0014 },     /* R121 - GPIO Control 1 */
 150         { 122, 0x0010 },     /* R122 - GPIO Control 2 */
 151         { 123, 0x0010 },     /* R123 - GPIO Control 3 */
 152         { 124, 0x0000 },     /* R124 - GPIO Control 4 */
 153         { 126, 0x0000 },     /* R126 - Digital Pulls */
 154         { 128, 0xFFFF },     /* R128 - Interrupt Status Mask */
 155         { 129, 0x0000 },     /* R129 - Interrupt Polarity */
 156         { 130, 0x0000 },     /* R130 - Interrupt Debounce */
 157         { 134, 0x0000 },     /* R134 - EQ1 */
 158         { 135, 0x000C },     /* R135 - EQ2 */
 159         { 136, 0x000C },     /* R136 - EQ3 */
 160         { 137, 0x000C },     /* R137 - EQ4 */
 161         { 138, 0x000C },     /* R138 - EQ5 */
 162         { 139, 0x000C },     /* R139 - EQ6 */
 163         { 140, 0x0FCA },     /* R140 - EQ7 */
 164         { 141, 0x0400 },     /* R141 - EQ8 */
 165         { 142, 0x00D8 },     /* R142 - EQ9 */
 166         { 143, 0x1EB5 },     /* R143 - EQ10 */
 167         { 144, 0xF145 },     /* R144 - EQ11 */
 168         { 145, 0x0B75 },     /* R145 - EQ12 */
 169         { 146, 0x01C5 },     /* R146 - EQ13 */
 170         { 147, 0x1C58 },     /* R147 - EQ14 */
 171         { 148, 0xF373 },     /* R148 - EQ15 */
 172         { 149, 0x0A54 },     /* R149 - EQ16 */
 173         { 150, 0x0558 },     /* R150 - EQ17 */
 174         { 151, 0x168E },     /* R151 - EQ18 */
 175         { 152, 0xF829 },     /* R152 - EQ19 */
 176         { 153, 0x07AD },     /* R153 - EQ20 */
 177         { 154, 0x1103 },     /* R154 - EQ21 */
 178         { 155, 0x0564 },     /* R155 - EQ22 */
 179         { 156, 0x0559 },     /* R156 - EQ23 */
 180         { 157, 0x4000 },     /* R157 - EQ24 */
 181         { 161, 0x0000 },     /* R161 - Control Interface Test 1 */
 182         { 204, 0x0000 },     /* R204 - Analogue Output Bias 0 */
 183         { 247, 0x0000 },     /* R247 - FLL NCO Test 0 */
 184         { 248, 0x0019 },     /* R248 - FLL NCO Test 1 */
 185 };
 186
 187 static bool wm8904_volatile_register(struct device *dev, unsigned int reg)
 188 {
 189         switch (reg) {
 190         case WM8904_SW_RESET_AND_ID:
 191         case WM8904_REVISION:
 192         case WM8904_DC_SERVO_1:
 193         case WM8904_DC_SERVO_6:
 194         case WM8904_DC_SERVO_7:
 195         case WM8904_DC_SERVO_8:
 196         case WM8904_DC_SERVO_9:
 197         case WM8904_DC_SERVO_READBACK_0:
 198         case WM8904_INTERRUPT_STATUS:
 199                 return true;
 200         default:
 201                 return false;
 202         }
 203 }
 204
 205 static bool wm8904_readable_register(struct device *dev, unsigned int reg)
 206 {
 207         switch (reg) {
 208         case WM8904_SW_RESET_AND_ID:
 209         case WM8904_REVISION:
 210         case WM8904_BIAS_CONTROL_0:
 211         case WM8904_VMID_CONTROL_0:
 212         case WM8904_MIC_BIAS_CONTROL_0:
 213         case WM8904_MIC_BIAS_CONTROL_1:
 214         case WM8904_ANALOGUE_DAC_0:
 215         case WM8904_MIC_FILTER_CONTROL:
 216         case WM8904_ANALOGUE_ADC_0:
 217         case WM8904_POWER_MANAGEMENT_0:
 218         case WM8904_POWER_MANAGEMENT_2:
 219         case WM8904_POWER_MANAGEMENT_3:
 220         case WM8904_POWER_MANAGEMENT_6:
 221         case WM8904_CLOCK_RATES_0:
 222         case WM8904_CLOCK_RATES_1:
 223         case WM8904_CLOCK_RATES_2:
 224         case WM8904_AUDIO_INTERFACE_0:
 225         case WM8904_AUDIO_INTERFACE_1:
 226         case WM8904_AUDIO_INTERFACE_2:
 227         case WM8904_AUDIO_INTERFACE_3:
 228         case WM8904_DAC_DIGITAL_VOLUME_LEFT:
 229         case WM8904_DAC_DIGITAL_VOLUME_RIGHT:
 230         case WM8904_DAC_DIGITAL_0:
 231         case WM8904_DAC_DIGITAL_1:
 232         case WM8904_ADC_DIGITAL_VOLUME_LEFT:
 233         case WM8904_ADC_DIGITAL_VOLUME_RIGHT:
 234         case WM8904_ADC_DIGITAL_0:
 235         case WM8904_DIGITAL_MICROPHONE_0:
 236         case WM8904_DRC_0:
 237         case WM8904_DRC_1:
 238         case WM8904_DRC_2:
 239         case WM8904_DRC_3:
 240         case WM8904_ANALOGUE_LEFT_INPUT_0:
 241         case WM8904_ANALOGUE_RIGHT_INPUT_0:
 242         case WM8904_ANALOGUE_LEFT_INPUT_1:
 243         case WM8904_ANALOGUE_RIGHT_INPUT_1:
 244         case WM8904_ANALOGUE_OUT1_LEFT:
 245         case WM8904_ANALOGUE_OUT1_RIGHT:
 246         case WM8904_ANALOGUE_OUT2_LEFT:
 247         case WM8904_ANALOGUE_OUT2_RIGHT:
 248         case WM8904_ANALOGUE_OUT12_ZC:
 249         case WM8904_DC_SERVO_0:
 250         case WM8904_DC_SERVO_1:
 251         case WM8904_DC_SERVO_2:
 252         case WM8904_DC_SERVO_4:
 253         case WM8904_DC_SERVO_5:
 254         case WM8904_DC_SERVO_6:
 255         case WM8904_DC_SERVO_7:
 256         case WM8904_DC_SERVO_8:
 257         case WM8904_DC_SERVO_9:
 258         case WM8904_DC_SERVO_READBACK_0:
 259         case WM8904_ANALOGUE_HP_0:
 260         case WM8904_ANALOGUE_LINEOUT_0:
 261         case WM8904_CHARGE_PUMP_0:
 262         case WM8904_CLASS_W_0:
 263         case WM8904_WRITE_SEQUENCER_0:
 264         case WM8904_WRITE_SEQUENCER_1:
 265         case WM8904_WRITE_SEQUENCER_2:
 266         case WM8904_WRITE_SEQUENCER_3:
 267         case WM8904_WRITE_SEQUENCER_4:
 268         case WM8904_FLL_CONTROL_1:
 269         case WM8904_FLL_CONTROL_2:
 270         case WM8904_FLL_CONTROL_3:
 271         case WM8904_FLL_CONTROL_4:
 272         case WM8904_FLL_CONTROL_5:
 273         case WM8904_GPIO_CONTROL_1:
 274         case WM8904_GPIO_CONTROL_2:
 275         case WM8904_GPIO_CONTROL_3:
 276         case WM8904_GPIO_CONTROL_4:
 277         case WM8904_DIGITAL_PULLS:
 278         case WM8904_INTERRUPT_STATUS:
 279         case WM8904_INTERRUPT_STATUS_MASK:
 280         case WM8904_INTERRUPT_POLARITY:
 281         case WM8904_INTERRUPT_DEBOUNCE:
 282         case WM8904_EQ1:
 283         case WM8904_EQ2:
 284         case WM8904_EQ3:
 285         case WM8904_EQ4:
 286         case WM8904_EQ5:
 287         case WM8904_EQ6:
 288         case WM8904_EQ7:
 289         case WM8904_EQ8:
 290         case WM8904_EQ9:
 291         case WM8904_EQ10:
 292         case WM8904_EQ11:
 293         case WM8904_EQ12:
 294         case WM8904_EQ13:
 295         case WM8904_EQ14:
 296         case WM8904_EQ15:
 297         case WM8904_EQ16:
 298         case WM8904_EQ17:
 299         case WM8904_EQ18:
 300         case WM8904_EQ19:
 301         case WM8904_EQ20:
 302         case WM8904_EQ21:
 303         case WM8904_EQ22:
 304         case WM8904_EQ23:
 305         case WM8904_EQ24:
 306         case WM8904_CONTROL_INTERFACE_TEST_1:
 307         case WM8904_ADC_TEST_0:
 308         case WM8904_ANALOGUE_OUTPUT_BIAS_0:
 309         case WM8904_FLL_NCO_TEST_0:
 310         case WM8904_FLL_NCO_TEST_1:
 311                 return true;
 312         default:
 313                 return true;
 314         }
 315 }
 316
 317 static int wm8904_reset(struct snd_soc_codec *codec)
 318 {
 319         return snd_soc_write(codec, WM8904_SW_RESET_AND_ID, 0);
 320 }
 321
 322 static int wm8904_configure_clocking(struct snd_soc_codec *codec)
 323 {
 324         struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
 325         unsigned int clock0, clock2, rate;
 326
 327         /* Gate the clock while we're updating to avoid misclocking */
 328         clock2 = snd_soc_read(codec, WM8904_CLOCK_RATES_2);
 329         snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
 330                             WM8904_SYSCLK_SRC, 0);
 331
 332         /* This should be done on init() for bypass paths */
 333         switch (wm8904->sysclk_src) {
 334         case WM8904_CLK_MCLK:
 335                 dev_dbg(codec->dev, "Using %dHz MCLK\n", wm8904->mclk_rate);
 336
 337                 clock2 &= ~WM8904_SYSCLK_SRC;
 338                 rate = wm8904->mclk_rate;
 339
 340                 /* Ensure the FLL is stopped */
 341                 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
 342                                     WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
 343                 break;
 344
 345         case WM8904_CLK_FLL:
 346                 dev_dbg(codec->dev, "Using %dHz FLL clock\n",
 347                         wm8904->fll_fout);
 348
 349                 clock2 |= WM8904_SYSCLK_SRC;
 350                 rate = wm8904->fll_fout;
 351                 break;
 352
 353         default:
 354                 dev_err(codec->dev, "System clock not configured\n");
 355                 return -EINVAL;
 356         }
 357
 358         /* SYSCLK shouldn't be over 13.5MHz */
 359         if (rate > 13500000) {
 360                 clock0 = WM8904_MCLK_DIV;
 361                 wm8904->sysclk_rate = rate / 2;
 362         } else {
 363                 clock0 = 0;
 364                 wm8904->sysclk_rate = rate;
 365         }
 366
 367         snd_soc_update_bits(codec, WM8904_CLOCK_RATES_0, WM8904_MCLK_DIV,
 368                             clock0);
 369
 370         snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
 371                             WM8904_CLK_SYS_ENA | WM8904_SYSCLK_SRC, clock2);
 372
 373         dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm8904->sysclk_rate);
 374
 375         return 0;
 376 }
 377
 378 static void wm8904_set_drc(struct snd_soc_codec *codec)
 379 {
 380         struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
 381         struct wm8904_pdata *pdata = wm8904->pdata;
 382         int save, i;
 383
 384         /* Save any enables; the configuration should clear them. */
 385         save = snd_soc_read(codec, WM8904_DRC_0);
 386
 387         for (i = 0; i < WM8904_DRC_REGS; i++)
 388                 snd_soc_update_bits(codec, WM8904_DRC_0 + i, 0xffff,
 389                                     pdata->drc_cfgs[wm8904->drc_cfg].regs[i]);
 390
 391         /* Reenable the DRC */
 392         snd_soc_update_bits(codec, WM8904_DRC_0,
 393                             WM8904_DRC_ENA | WM8904_DRC_DAC_PATH, save);
 394 }
 395
 396 static int wm8904_put_drc_enum(struct snd_kcontrol *kcontrol,
 397                                struct snd_ctl_elem_value *ucontrol)
 398 {
 399         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 400         struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
 401         struct wm8904_pdata *pdata = wm8904->pdata;
 402         int value = ucontrol->value.integer.value[0];
 403
 404         if (value >= pdata->num_drc_cfgs)
 405                 return -EINVAL;
 406
 407         wm8904->drc_cfg = value;
 408
 409         wm8904_set_drc(codec);
 410
 411         return 0;
 412 }
 413
 414 static int wm8904_get_drc_enum(struct snd_kcontrol *kcontrol,
 415                                struct snd_ctl_elem_value *ucontrol)
 416 {
 417         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 418         struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
 419
 420         ucontrol->value.enumerated.item[0] = wm8904->drc_cfg;
 421
 422         return 0;
 423 }
 424
 425 static void wm8904_set_retune_mobile(struct snd_soc_codec *codec)
 426 {
 427         struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
 428         struct wm8904_pdata *pdata = wm8904->pdata;
 429         int best, best_val, save, i, cfg;
 430
 431         if (!pdata || !wm8904->num_retune_mobile_texts)
 432                 return;
 433
 434         /* Find the version of the currently selected configuration
 435          * with the nearest sample rate. */
 436         cfg = wm8904->retune_mobile_cfg;
 437         best = 0;
 438         best_val = INT_MAX;
 439         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
 440                 if (strcmp(pdata->retune_mobile_cfgs[i].name,
 441                            wm8904->retune_mobile_texts[cfg]) == 0 &&
 442                     abs(pdata->retune_mobile_cfgs[i].rate
 443                         - wm8904->fs) < best_val) {
 444                         best = i;
 445                         best_val = abs(pdata->retune_mobile_cfgs[i].rate
 446                                        - wm8904->fs);
 447                 }
 448         }
 449
 450         dev_dbg(codec->dev, "ReTune Mobile %s/%dHz for %dHz sample rate\n",
 451                 pdata->retune_mobile_cfgs[best].name,
 452                 pdata->retune_mobile_cfgs[best].rate,
 453                 wm8904->fs);
 454
 455         /* The EQ will be disabled while reconfiguring it, remember the
 456          * current configuration.
 457          */
 458         save = snd_soc_read(codec, WM8904_EQ1);
 459
 460         for (i = 0; i < WM8904_EQ_REGS; i++)
 461                 snd_soc_update_bits(codec, WM8904_EQ1 + i, 0xffff,
 462                                 pdata->retune_mobile_cfgs[best].regs[i]);
 463
 464         snd_soc_update_bits(codec, WM8904_EQ1, WM8904_EQ_ENA, save);
 465 }
 466
 467 static int wm8904_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 468                                          struct snd_ctl_elem_value *ucontrol)
 469 {
 470         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 471         struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
 472         struct wm8904_pdata *pdata = wm8904->pdata;
 473         int value = ucontrol->value.integer.value[0];
 474
 475         if (value >= pdata->num_retune_mobile_cfgs)
 476                 return -EINVAL;
 477
 478         wm8904->retune_mobile_cfg = value;
 479
 480         wm8904_set_retune_mobile(codec);
 481
 482         return 0;
 483 }
 484
 485 static int wm8904_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 486                                          struct snd_ctl_elem_value *ucontrol)
 487 {
 488         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 489         struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
 490
 491         ucontrol->value.enumerated.item[0] = wm8904->retune_mobile_cfg;
 492
 493         return 0;
 494 }
 495
 496 static int deemph_settings[] = { 0, 32000, 44100, 48000 };
 497
 498 static int wm8904_set_deemph(struct snd_soc_codec *codec)
 499 {
 500         struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
 501         int val, i, best;
 502
 503         /* If we're using deemphasis select the nearest available sample
 504          * rate.
 505          */
 506         if (wm8904->deemph) {
 507                 best = 1;
 508                 for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) {
 509                         if (abs(deemph_settings[i] - wm8904->fs) <
 510                             abs(deemph_settings[best] - wm8904->fs))
 511                                 best = i;
 512                 }
 513
 514                 val = best << WM8904_DEEMPH_SHIFT;
 515         } else {
 516                 val = 0;
 517         }
 518
 519         dev_dbg(codec->dev, "Set deemphasis %d\n", val);
 520
 521         return snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1,
 522                                    WM8904_DEEMPH_MASK, val);
 523 }
 524
 525 static int wm8904_get_deemph(struct snd_kcontrol *kcontrol,
 526                              struct snd_ctl_elem_value *ucontrol)
 527 {
 528         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 529         struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
 530
 531         ucontrol->value.enumerated.item[0] = wm8904->deemph;
 532         return 0;
 533 }
 534
 535 static int wm8904_put_deemph(struct snd_kcontrol *kcontrol,
 536                               struct snd_ctl_elem_value *ucontrol)
 537 {
 538         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 539         struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
 540         int deemph = ucontrol->value.enumerated.item[0];
 541
 542         if (deemph > 1)
 543                 return -EINVAL;
 544
 545         wm8904->deemph = deemph;
 546
 547         return wm8904_set_deemph(codec);
 548 }
 549
 550 static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
 551 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
 552 static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
 553 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);
 554 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
 555
 556 static const char *input_mode_text[] = {
 557         "Single-Ended", "Differential Line", "Differential Mic"
 558 };
 559
 560 static const struct soc_enum lin_mode =
 561         SOC_ENUM_SINGLE(WM8904_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text);
 562
 563 static const struct soc_enum rin_mode =
 564         SOC_ENUM_SINGLE(WM8904_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text);
 565
 566 static const char *hpf_mode_text[] = {
 567         "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
 568 };
 569
 570 static const struct soc_enum hpf_mode =
 571         SOC_ENUM_SINGLE(WM8904_ADC_DIGITAL_0, 5, 4, hpf_mode_text);
 572
 573 static int wm8904_adc_osr_put(struct snd_kcontrol *kcontrol,
 574                               struct snd_ctl_elem_value *ucontrol)
 575 {
 576         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 577         unsigned int val;
 578         int ret;
 579
 580         ret = snd_soc_put_volsw(kcontrol, ucontrol);
 581         if (ret < 0)
 582                 return ret;
 583
 584         if (ucontrol->value.integer.value[0])
 585                 val = 0;
 586         else
 587                 val = WM8904_ADC_128_OSR_TST_MODE | WM8904_ADC_BIASX1P5;
 588
 589         snd_soc_update_bits(codec, WM8904_ADC_TEST_0,
 590                             WM8904_ADC_128_OSR_TST_MODE | WM8904_ADC_BIASX1P5,
 591                             val);
 592
 593         return ret;
 594 }
 595
 596 static const struct snd_kcontrol_new wm8904_adc_snd_controls[] = {
 597 SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8904_ADC_DIGITAL_VOLUME_LEFT,
 598                  WM8904_ADC_DIGITAL_VOLUME_RIGHT, 1, 119, 0, digital_tlv),
 599
 600 SOC_ENUM("Left Caputure Mode", lin_mode),
 601 SOC_ENUM("Right Capture Mode", rin_mode),
 602
 603 /* No TLV since it depends on mode */
 604 SOC_DOUBLE_R("Capture Volume", WM8904_ANALOGUE_LEFT_INPUT_0,
 605              WM8904_ANALOGUE_RIGHT_INPUT_0, 0, 31, 0),
 606 SOC_DOUBLE_R("Capture Switch", WM8904_ANALOGUE_LEFT_INPUT_0,
 607              WM8904_ANALOGUE_RIGHT_INPUT_0, 7, 1, 1),
 608
 609 SOC_SINGLE("High Pass Filter Switch", WM8904_ADC_DIGITAL_0, 4, 1, 0),
 610 SOC_ENUM("High Pass Filter Mode", hpf_mode),
 611
 612 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
 613         .name = "ADC 128x OSR Switch",
 614         .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,
 615         .put = wm8904_adc_osr_put,
 616         .private_value = SOC_SINGLE_VALUE(WM8904_ANALOGUE_ADC_0, 0, 1, 0),
 617 },
 618 };
 619
 620 static const char *drc_path_text[] = {
 621         "ADC", "DAC"
 622 };
 623
 624 static const struct soc_enum drc_path =
 625         SOC_ENUM_SINGLE(WM8904_DRC_0, 14, 2, drc_path_text);
 626
 627 static const struct snd_kcontrol_new wm8904_dac_snd_controls[] = {
 628 SOC_SINGLE_TLV("Digital Playback Boost Volume",
 629                WM8904_AUDIO_INTERFACE_0, 9, 3, 0, dac_boost_tlv),
 630 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8904_DAC_DIGITAL_VOLUME_LEFT,
 631                  WM8904_DAC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv),
 632
 633 SOC_DOUBLE_R_TLV("Headphone Volume", WM8904_ANALOGUE_OUT1_LEFT,
 634                  WM8904_ANALOGUE_OUT1_RIGHT, 0, 63, 0, out_tlv),
 635 SOC_DOUBLE_R("Headphone Switch", WM8904_ANALOGUE_OUT1_LEFT,
 636              WM8904_ANALOGUE_OUT1_RIGHT, 8, 1, 1),
 637 SOC_DOUBLE_R("Headphone ZC Switch", WM8904_ANALOGUE_OUT1_LEFT,
 638              WM8904_ANALOGUE_OUT1_RIGHT, 6, 1, 0),
 639
 640 SOC_DOUBLE_R_TLV("Line Output Volume", WM8904_ANALOGUE_OUT2_LEFT,
 641                  WM8904_ANALOGUE_OUT2_RIGHT, 0, 63, 0, out_tlv),
 642 SOC_DOUBLE_R("Line Output Switch", WM8904_ANALOGUE_OUT2_LEFT,
 643              WM8904_ANALOGUE_OUT2_RIGHT, 8, 1, 1),
 644 SOC_DOUBLE_R("Line Output ZC Switch", WM8904_ANALOGUE_OUT2_LEFT,
 645              WM8904_ANALOGUE_OUT2_RIGHT, 6, 1, 0),
 646
 647 SOC_SINGLE("EQ Switch", WM8904_EQ1, 0, 1, 0),
 648 SOC_SINGLE("DRC Switch", WM8904_DRC_0, 15, 1, 0),
 649 SOC_ENUM("DRC Path", drc_path),
 650 SOC_SINGLE("DAC OSRx2 Switch", WM8904_DAC_DIGITAL_1, 6, 1, 0),
 651 SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0,
 652                     wm8904_get_deemph, wm8904_put_deemph),
 653 };
 654
 655 static const struct snd_kcontrol_new wm8904_snd_controls[] = {
 656 SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8904_DAC_DIGITAL_0, 4, 8, 15, 0,
 657                sidetone_tlv),
 658 };
 659
 660 static const struct snd_kcontrol_new wm8904_eq_controls[] = {
 661 SOC_SINGLE_TLV("EQ1 Volume", WM8904_EQ2, 0, 24, 0, eq_tlv),
 662 SOC_SINGLE_TLV("EQ2 Volume", WM8904_EQ3, 0, 24, 0, eq_tlv),
 663 SOC_SINGLE_TLV("EQ3 Volume", WM8904_EQ4, 0, 24, 0, eq_tlv),
 664 SOC_SINGLE_TLV("EQ4 Volume", WM8904_EQ5, 0, 24, 0, eq_tlv),
 665 SOC_SINGLE_TLV("EQ5 Volume", WM8904_EQ6, 0, 24, 0, eq_tlv),
 666 };
 667
 668 static int cp_event(struct snd_soc_dapm_widget *w,
 669                     struct snd_kcontrol *kcontrol, int event)
 670 {
 671         BUG_ON(event != SND_SOC_DAPM_POST_PMU);
 672
 673         /* Maximum startup time */
 674         udelay(500);
 675
 676         return 0;
 677 }
 678
 679 static int sysclk_event(struct snd_soc_dapm_widget *w,
 680                          struct snd_kcontrol *kcontrol, int event)
 681 {
 682         struct snd_soc_codec *codec = w->codec;
 683         struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
 684
 685         switch (event) {
 686         case SND_SOC_DAPM_PRE_PMU:
 687                 /* If we're using the FLL then we only start it when
 688                  * required; we assume that the configuration has been
 689                  * done previously and all we need to do is kick it
 690                  * off.
 691                  */
 692                 switch (wm8904->sysclk_src) {
 693                 case WM8904_CLK_FLL:
 694                         snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
 695                                             WM8904_FLL_OSC_ENA,
 696                                             WM8904_FLL_OSC_ENA);
 697
 698                         snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
 699                                             WM8904_FLL_ENA,
 700                                             WM8904_FLL_ENA);
 701                         break;
 702
 703                 default:
 704                         break;
 705                 }
 706                 break;
 707
 708         case SND_SOC_DAPM_POST_PMD:
 709                 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
 710                                     WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
 711                 break;
 712         }
 713
 714         return 0;
 715 }
 716
 717 static int out_pga_event(struct snd_soc_dapm_widget *w,
 718                          struct snd_kcontrol *kcontrol, int event)
 719 {
 720         struct snd_soc_codec *codec = w->codec;
 721         struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
 722         int reg, val;
 723         int dcs_mask;
 724         int dcs_l, dcs_r;
 725         int dcs_l_reg, dcs_r_reg;
 726         int timeout;
 727         int pwr_reg;
 728
 729         /* This code is shared between HP and LINEOUT; we do all our
 730          * power management in stereo pairs to avoid latency issues so
 731          * we reuse shift to identify which rather than strcmp() the
 732          * name. */
 733         reg = w->shift;
 734
 735         switch (reg) {
 736         case WM8904_ANALOGUE_HP_0:
 737                 pwr_reg = WM8904_POWER_MANAGEMENT_2;
 738                 dcs_mask = WM8904_DCS_ENA_CHAN_0 | WM8904_DCS_ENA_CHAN_1;
 739                 dcs_r_reg = WM8904_DC_SERVO_8;
 740                 dcs_l_reg = WM8904_DC_SERVO_9;
 741                 dcs_l = 0;
 742                 dcs_r = 1;
 743                 break;
 744         case WM8904_ANALOGUE_LINEOUT_0:
 745                 pwr_reg = WM8904_POWER_MANAGEMENT_3;
 746                 dcs_mask = WM8904_DCS_ENA_CHAN_2 | WM8904_DCS_ENA_CHAN_3;
 747                 dcs_r_reg = WM8904_DC_SERVO_6;
 748                 dcs_l_reg = WM8904_DC_SERVO_7;
 749                 dcs_l = 2;
 750                 dcs_r = 3;
 751                 break;
 752         default:
 753                 BUG();
 754                 return -EINVAL;
 755         }
 756
 757         switch (event) {
 758         case SND_SOC_DAPM_PRE_PMU:
 759                 /* Power on the PGAs */
 760                 snd_soc_update_bits(codec, pwr_reg,
 761                                     WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA,
 762                                     WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA);
 763
 764                 /* Power on the amplifier */
 765                 snd_soc_update_bits(codec, reg,
 766                                     WM8904_HPL_ENA | WM8904_HPR_ENA,
 767                                     WM8904_HPL_ENA | WM8904_HPR_ENA);
 768
 769
 770                 /* Enable the first stage */
 771                 snd_soc_update_bits(codec, reg,
 772                                     WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY,
 773                                     WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY);
 774
 775                 /* Power up the DC servo */
 776                 snd_soc_update_bits(codec, WM8904_DC_SERVO_0,
 777                                     dcs_mask, dcs_mask);
 778
 779                 /* Either calibrate the DC servo or restore cached state
 780                  * if we have that.
 781                  */
 782                 if (wm8904->dcs_state[dcs_l] || wm8904->dcs_state[dcs_r]) {
 783                         dev_dbg(codec->dev, "Restoring DC servo state\n");
 784
 785                         snd_soc_write(codec, dcs_l_reg,
 786                                       wm8904->dcs_state[dcs_l]);
 787                         snd_soc_write(codec, dcs_r_reg,
 788                                       wm8904->dcs_state[dcs_r]);
 789
 790                         snd_soc_write(codec, WM8904_DC_SERVO_1, dcs_mask);
 791
 792                         timeout = 20;
 793                 } else {
 794                         dev_dbg(codec->dev, "Calibrating DC servo\n");
 795
 796                         snd_soc_write(codec, WM8904_DC_SERVO_1,
 797                                 dcs_mask << WM8904_DCS_TRIG_STARTUP_0_SHIFT);
 798
 799                         timeout = 500;
 800                 }
 801
 802                 /* Wait for DC servo to complete */
 803                 dcs_mask <<= WM8904_DCS_CAL_COMPLETE_SHIFT;
 804                 do {
 805                         val = snd_soc_read(codec, WM8904_DC_SERVO_READBACK_0);
 806                         if ((val & dcs_mask) == dcs_mask)
 807                                 break;
 808
 809                         msleep(1);
 810                 } while (--timeout);
 811
 812                 if ((val & dcs_mask) != dcs_mask)
 813                         dev_warn(codec->dev, "DC servo timed out\n");
 814                 else
 815                         dev_dbg(codec->dev, "DC servo ready\n");
 816
 817                 /* Enable the output stage */
 818                 snd_soc_update_bits(codec, reg,
 819                                     WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP,
 820                                     WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP);
 821                 break;
 822
 823         case SND_SOC_DAPM_POST_PMU:
 824                 /* Unshort the output itself */
 825                 snd_soc_update_bits(codec, reg,
 826                                     WM8904_HPL_RMV_SHORT |
 827                                     WM8904_HPR_RMV_SHORT,
 828                                     WM8904_HPL_RMV_SHORT |
 829                                     WM8904_HPR_RMV_SHORT);
 830
 831                 break;
 832
 833         case SND_SOC_DAPM_PRE_PMD:
 834                 /* Short the output */
 835                 snd_soc_update_bits(codec, reg,
 836                                     WM8904_HPL_RMV_SHORT |
 837                                     WM8904_HPR_RMV_SHORT, 0);
 838                 break;
 839
 840         case SND_SOC_DAPM_POST_PMD:
 841                 /* Cache the DC servo configuration; this will be
 842                  * invalidated if we change the configuration. */
 843                 wm8904->dcs_state[dcs_l] = snd_soc_read(codec, dcs_l_reg);
 844                 wm8904->dcs_state[dcs_r] = snd_soc_read(codec, dcs_r_reg);
 845
 846                 snd_soc_update_bits(codec, WM8904_DC_SERVO_0,
 847                                     dcs_mask, 0);
 848
 849                 /* Disable the amplifier input and output stages */
 850                 snd_soc_update_bits(codec, reg,
 851                                     WM8904_HPL_ENA | WM8904_HPR_ENA |
 852                                     WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY |
 853                                     WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP,
 854                                     0);
 855
 856                 /* PGAs too */
 857                 snd_soc_update_bits(codec, pwr_reg,
 858                                     WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA,
 859                                     0);
 860                 break;
 861         }
 862
 863         return 0;
 864 }
 865
 866 static const char *lin_text[] = {
 867         "IN1L", "IN2L", "IN3L"
 868 };
 869
 870 static const struct soc_enum lin_enum =
 871         SOC_ENUM_SINGLE(WM8904_ANALOGUE_LEFT_INPUT_1, 2, 3, lin_text);
 872
 873 static const struct snd_kcontrol_new lin_mux =
 874         SOC_DAPM_ENUM("Left Capture Mux", lin_enum);
 875
 876 static const struct soc_enum lin_inv_enum =
 877         SOC_ENUM_SINGLE(WM8904_ANALOGUE_LEFT_INPUT_1, 4, 3, lin_text);
 878
 879 static const struct snd_kcontrol_new lin_inv_mux =
 880         SOC_DAPM_ENUM("Left Capture Inveting Mux", lin_inv_enum);
 881
 882 static const char *rin_text[] = {
 883         "IN1R", "IN2R", "IN3R"
 884 };
 885
 886 static const struct soc_enum rin_enum =
 887         SOC_ENUM_SINGLE(WM8904_ANALOGUE_RIGHT_INPUT_1, 2, 3, rin_text);
 888
 889 static const struct snd_kcontrol_new rin_mux =
 890         SOC_DAPM_ENUM("Right Capture Mux", rin_enum);
 891
 892 static const struct soc_enum rin_inv_enum =
 893         SOC_ENUM_SINGLE(WM8904_ANALOGUE_RIGHT_INPUT_1, 4, 3, rin_text);
 894
 895 static const struct snd_kcontrol_new rin_inv_mux =
 896         SOC_DAPM_ENUM("Right Capture Inveting Mux", rin_inv_enum);
 897
 898 static const char *aif_text[] = {
 899         "Left", "Right"
 900 };
 901
 902 static const struct soc_enum aifoutl_enum =
 903         SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 7, 2, aif_text);
 904
 905 static const struct snd_kcontrol_new aifoutl_mux =
 906         SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum);
 907
 908 static const struct soc_enum aifoutr_enum =
 909         SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 6, 2, aif_text);
 910
 911 static const struct snd_kcontrol_new aifoutr_mux =
 912         SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum);
 913
 914 static const struct soc_enum aifinl_enum =
 915         SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 5, 2, aif_text);
 916
 917 static const struct snd_kcontrol_new aifinl_mux =
 918         SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum);
 919
 920 static const struct soc_enum aifinr_enum =
 921         SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 4, 2, aif_text);
 922
 923 static const struct snd_kcontrol_new aifinr_mux =
 924         SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum);
 925
 926 static const struct snd_soc_dapm_widget wm8904_core_dapm_widgets[] = {
 927 SND_SOC_DAPM_SUPPLY("SYSCLK", WM8904_CLOCK_RATES_2, 2, 0, sysclk_event,
 928                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
 929 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8904_CLOCK_RATES_2, 1, 0, NULL, 0),
 930 SND_SOC_DAPM_SUPPLY("TOCLK", WM8904_CLOCK_RATES_2, 0, 0, NULL, 0),
 931 };
 932
 933 static const struct snd_soc_dapm_widget wm8904_adc_dapm_widgets[] = {
 934 SND_SOC_DAPM_INPUT("IN1L"),
 935 SND_SOC_DAPM_INPUT("IN1R"),
 936 SND_SOC_DAPM_INPUT("IN2L"),
 937 SND_SOC_DAPM_INPUT("IN2R"),
 938 SND_SOC_DAPM_INPUT("IN3L"),
 939 SND_SOC_DAPM_INPUT("IN3R"),
 940
 941 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8904_MIC_BIAS_CONTROL_0, 0, 0, NULL, 0),
 942
 943 SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lin_mux),
 944 SND_SOC_DAPM_MUX("Left Capture Inverting Mux", SND_SOC_NOPM, 0, 0,
 945                  &lin_inv_mux),
 946 SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rin_mux),
 947 SND_SOC_DAPM_MUX("Right Capture Inverting Mux", SND_SOC_NOPM, 0, 0,
 948                  &rin_inv_mux),
 949
 950 SND_SOC_DAPM_PGA("Left Capture PGA", WM8904_POWER_MANAGEMENT_0, 1, 0,
 951                  NULL, 0),
 952 SND_SOC_DAPM_PGA("Right Capture PGA", WM8904_POWER_MANAGEMENT_0, 0, 0,
 953                  NULL, 0),
 954
 955 SND_SOC_DAPM_ADC("ADCL", NULL, WM8904_POWER_MANAGEMENT_6, 1, 0),
 956 SND_SOC_DAPM_ADC("ADCR", NULL, WM8904_POWER_MANAGEMENT_6, 0, 0),
 957
 958 SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM, 0, 0, &aifoutl_mux),
 959 SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM, 0, 0, &aifoutr_mux),
 960
 961 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0),
 962 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0),
 963 };
 964
 965 static const struct snd_soc_dapm_widget wm8904_dac_dapm_widgets[] = {
 966 SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0),
 967 SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0),
 968
 969 SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &aifinl_mux),
 970 SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &aifinr_mux),
 971
 972 SND_SOC_DAPM_DAC("DACL", NULL, WM8904_POWER_MANAGEMENT_6, 3, 0),
 973 SND_SOC_DAPM_DAC("DACR", NULL, WM8904_POWER_MANAGEMENT_6, 2, 0),
 974
 975 SND_SOC_DAPM_SUPPLY("Charge pump", WM8904_CHARGE_PUMP_0, 0, 0, cp_event,
 976                     SND_SOC_DAPM_POST_PMU),
 977
 978 SND_SOC_DAPM_PGA("HPL PGA", SND_SOC_NOPM, 1, 0, NULL, 0),
 979 SND_SOC_DAPM_PGA("HPR PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
 980
 981 SND_SOC_DAPM_PGA("LINEL PGA", SND_SOC_NOPM, 1, 0, NULL, 0),
 982 SND_SOC_DAPM_PGA("LINER PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
 983
 984 SND_SOC_DAPM_PGA_E("Headphone Output", SND_SOC_NOPM, WM8904_ANALOGUE_HP_0,
 985                    0, NULL, 0, out_pga_event,
 986                    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
 987                    SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
 988 SND_SOC_DAPM_PGA_E("Line Output", SND_SOC_NOPM, WM8904_ANALOGUE_LINEOUT_0,
 989                    0, NULL, 0, out_pga_event,
 990                    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
 991                    SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
 992
 993 SND_SOC_DAPM_OUTPUT("HPOUTL"),
 994 SND_SOC_DAPM_OUTPUT("HPOUTR"),
 995 SND_SOC_DAPM_OUTPUT("LINEOUTL"),
 996 SND_SOC_DAPM_OUTPUT("LINEOUTR"),
 997 };
 998
 999 static const char *out_mux_text[] = {
1000         "DAC", "Bypass"
1001 };
1002
1003 static const struct soc_enum hpl_enum =
1004         SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 3, 2, out_mux_text);
1005
1006 static const struct snd_kcontrol_new hpl_mux =
1007         SOC_DAPM_ENUM("HPL Mux", hpl_enum);
1008
1009 static const struct soc_enum hpr_enum =
1010         SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 2, 2, out_mux_text);
1011
1012 static const struct snd_kcontrol_new hpr_mux =
1013         SOC_DAPM_ENUM("HPR Mux", hpr_enum);
1014
1015 static const struct soc_enum linel_enum =
1016         SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 1, 2, out_mux_text);
1017
1018 static const struct snd_kcontrol_new linel_mux =
1019         SOC_DAPM_ENUM("LINEL Mux", linel_enum);
1020
1021 static const struct soc_enum liner_enum =
1022         SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 0, 2, out_mux_text);
1023
1024 static const struct snd_kcontrol_new liner_mux =
1025         SOC_DAPM_ENUM("LINEL Mux", liner_enum);
1026
1027 static const char *sidetone_text[] = {
1028         "None", "Left", "Right"
1029 };
1030
1031 static const struct soc_enum dacl_sidetone_enum =
1032         SOC_ENUM_SINGLE(WM8904_DAC_DIGITAL_0, 2, 3, sidetone_text);
1033
1034 static const struct snd_kcontrol_new dacl_sidetone_mux =
1035         SOC_DAPM_ENUM("Left Sidetone Mux", dacl_sidetone_enum);
1036
1037 static const struct soc_enum dacr_sidetone_enum =
1038         SOC_ENUM_SINGLE(WM8904_DAC_DIGITAL_0, 0, 3, sidetone_text);
1039
1040 static const struct snd_kcontrol_new dacr_sidetone_mux =
1041         SOC_DAPM_ENUM("Right Sidetone Mux", dacr_sidetone_enum);
1042
1043 static const struct snd_soc_dapm_widget wm8904_dapm_widgets[] = {
1044 SND_SOC_DAPM_SUPPLY("Class G", WM8904_CLASS_W_0, 0, 1, NULL, 0),
1045 SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
1046 SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
1047
1048 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &dacl_sidetone_mux),
1049 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &dacr_sidetone_mux),
1050
1051 SND_SOC_DAPM_MUX("HPL Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1052 SND_SOC_DAPM_MUX("HPR Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1053 SND_SOC_DAPM_MUX("LINEL Mux", SND_SOC_NOPM, 0, 0, &linel_mux),
1054 SND_SOC_DAPM_MUX("LINER Mux", SND_SOC_NOPM, 0, 0, &liner_mux),
1055 };
1056
1057 static const struct snd_soc_dapm_route core_intercon[] = {
1058         { "CLK_DSP", NULL, "SYSCLK" },
1059         { "TOCLK", NULL, "SYSCLK" },
1060 };
1061
1062 static const struct snd_soc_dapm_route adc_intercon[] = {
1063         { "Left Capture Mux", "IN1L", "IN1L" },
1064         { "Left Capture Mux", "IN2L", "IN2L" },
1065         { "Left Capture Mux", "IN3L", "IN3L" },
1066
1067         { "Left Capture Inverting Mux", "IN1L", "IN1L" },
1068         { "Left Capture Inverting Mux", "IN2L", "IN2L" },
1069         { "Left Capture Inverting Mux", "IN3L", "IN3L" },
1070
1071         { "Right Capture Mux", "IN1R", "IN1R" },
1072         { "Right Capture Mux", "IN2R", "IN2R" },
1073         { "Right Capture Mux", "IN3R", "IN3R" },
1074
1075         { "Right Capture Inverting Mux", "IN1R", "IN1R" },
1076         { "Right Capture Inverting Mux", "IN2R", "IN2R" },
1077         { "Right Capture Inverting Mux", "IN3R", "IN3R" },
1078
1079         { "Left Capture PGA", NULL, "Left Capture Mux" },
1080         { "Left Capture PGA", NULL, "Left Capture Inverting Mux" },
1081
1082         { "Right Capture PGA", NULL, "Right Capture Mux" },
1083         { "Right Capture PGA", NULL, "Right Capture Inverting Mux" },
1084
1085         { "AIFOUTL", "Left",  "ADCL" },
1086         { "AIFOUTL", "Right", "ADCR" },
1087         { "AIFOUTR", "Left",  "ADCL" },
1088         { "AIFOUTR", "Right", "ADCR" },
1089
1090         { "ADCL", NULL, "CLK_DSP" },
1091         { "ADCL", NULL, "Left Capture PGA" },
1092
1093         { "ADCR", NULL, "CLK_DSP" },
1094         { "ADCR", NULL, "Right Capture PGA" },
1095 };
1096
1097 static const struct snd_soc_dapm_route dac_intercon[] = {
1098         { "DACL", "Right", "AIFINR" },
1099         { "DACL", "Left",  "AIFINL" },
1100         { "DACL", NULL, "CLK_DSP" },
1101
1102         { "DACR", "Right", "AIFINR" },
1103         { "DACR", "Left",  "AIFINL" },
1104         { "DACR", NULL, "CLK_DSP" },
1105
1106         { "Charge pump", NULL, "SYSCLK" },
1107
1108         { "Headphone Output", NULL, "HPL PGA" },
1109         { "Headphone Output", NULL, "HPR PGA" },
1110         { "Headphone Output", NULL, "Charge pump" },
1111         { "Headphone Output", NULL, "TOCLK" },
1112
1113         { "Line Output", NULL, "LINEL PGA" },
1114         { "Line Output", NULL, "LINER PGA" },
1115         { "Line Output", NULL, "Charge pump" },
1116         { "Line Output", NULL, "TOCLK" },
1117
1118         { "HPOUTL", NULL, "Headphone Output" },
1119         { "HPOUTR", NULL, "Headphone Output" },
1120
1121         { "LINEOUTL", NULL, "Line Output" },
1122         { "LINEOUTR", NULL, "Line Output" },
1123 };
1124
1125 static const struct snd_soc_dapm_route wm8904_intercon[] = {
1126         { "Left Sidetone", "Left", "ADCL" },
1127         { "Left Sidetone", "Right", "ADCR" },
1128         { "DACL", NULL, "Left Sidetone" },
1129
1130         { "Right Sidetone", "Left", "ADCL" },
1131         { "Right Sidetone", "Right", "ADCR" },
1132         { "DACR", NULL, "Right Sidetone" },
1133
1134         { "Left Bypass", NULL, "Class G" },
1135         { "Left Bypass", NULL, "Left Capture PGA" },
1136
1137         { "Right Bypass", NULL, "Class G" },
1138         { "Right Bypass", NULL, "Right Capture PGA" },
1139
1140         { "HPL Mux", "DAC", "DACL" },
1141         { "HPL Mux", "Bypass", "Left Bypass" },
1142
1143         { "HPR Mux", "DAC", "DACR" },
1144         { "HPR Mux", "Bypass", "Right Bypass" },
1145
1146         { "LINEL Mux", "DAC", "DACL" },
1147         { "LINEL Mux", "Bypass", "Left Bypass" },
1148
1149         { "LINER Mux", "DAC", "DACR" },
1150         { "LINER Mux", "Bypass", "Right Bypass" },
1151
1152         { "HPL PGA", NULL, "HPL Mux" },
1153         { "HPR PGA", NULL, "HPR Mux" },
1154
1155         { "LINEL PGA", NULL, "LINEL Mux" },
1156         { "LINER PGA", NULL, "LINER Mux" },
1157 };
1158
1159 static const struct snd_soc_dapm_route wm8912_intercon[] = {
1160         { "HPL PGA", NULL, "DACL" },
1161         { "HPR PGA", NULL, "DACR" },
1162
1163         { "LINEL PGA", NULL, "DACL" },
1164         { "LINER PGA", NULL, "DACR" },
1165 };
1166
1167 static int wm8904_add_widgets(struct snd_soc_codec *codec)
1168 {
1169         struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
1170         struct snd_soc_dapm_context *dapm = &codec->dapm;
1171
1172         snd_soc_dapm_new_controls(dapm, wm8904_core_dapm_widgets,
1173                                   ARRAY_SIZE(wm8904_core_dapm_widgets));
1174         snd_soc_dapm_add_routes(dapm, core_intercon,
1175                                 ARRAY_SIZE(core_intercon));
1176
1177         switch (wm8904->devtype) {
1178         case WM8904:
1179                 snd_soc_add_codec_controls(codec, wm8904_adc_snd_controls,
1180                                      ARRAY_SIZE(wm8904_adc_snd_controls));
1181                 snd_soc_add_codec_controls(codec, wm8904_dac_snd_controls,
1182                                      ARRAY_SIZE(wm8904_dac_snd_controls));
1183                 snd_soc_add_codec_controls(codec, wm8904_snd_controls,
1184                                      ARRAY_SIZE(wm8904_snd_controls));
1185
1186                 snd_soc_dapm_new_controls(dapm, wm8904_adc_dapm_widgets,
1187                                           ARRAY_SIZE(wm8904_adc_dapm_widgets));
1188                 snd_soc_dapm_new_controls(dapm, wm8904_dac_dapm_widgets,
1189                                           ARRAY_SIZE(wm8904_dac_dapm_widgets));
1190                 snd_soc_dapm_new_controls(dapm, wm8904_dapm_widgets,
1191                                           ARRAY_SIZE(wm8904_dapm_widgets));
1192
1193                 snd_soc_dapm_add_routes(dapm, core_intercon,
1194                                         ARRAY_SIZE(core_intercon));
1195                 snd_soc_dapm_add_routes(dapm, adc_intercon,
1196                                         ARRAY_SIZE(adc_intercon));
1197                 snd_soc_dapm_add_routes(dapm, dac_intercon,
1198                                         ARRAY_SIZE(dac_intercon));
1199                 snd_soc_dapm_add_routes(dapm, wm8904_intercon,
1200                                         ARRAY_SIZE(wm8904_intercon));
1201                 break;
1202
1203         case WM8912:
1204                 snd_soc_add_codec_controls(codec, wm8904_dac_snd_controls,
1205                                      ARRAY_SIZE(wm8904_dac_snd_controls));
1206
1207                 snd_soc_dapm_new_controls(dapm, wm8904_dac_dapm_widgets,
1208                                           ARRAY_SIZE(wm8904_dac_dapm_widgets));
1209
1210                 snd_soc_dapm_add_routes(dapm, dac_intercon,
1211                                         ARRAY_SIZE(dac_intercon));
1212                 snd_soc_dapm_add_routes(dapm, wm8912_intercon,
1213                                         ARRAY_SIZE(wm8912_intercon));
1214                 break;
1215         }
1216
1217         snd_soc_dapm_new_widgets(dapm);
1218         return 0;
1219 }
1220
1221 static struct {
1222         int ratio;
1223         unsigned int clk_sys_rate;
1224 } clk_sys_rates[] = {
1225         {   64,  0 },
1226         {  128,  1 },
1227         {  192,  2 },
1228         {  256,  3 },
1229         {  384,  4 },
1230         {  512,  5 },
1231         {  786,  6 },
1232         { 1024,  7 },
1233         { 1408,  8 },
1234         { 1536,  9 },
1235 };
1236
1237 static struct {
1238         int rate;
1239         int sample_rate;
1240 } sample_rates[] = {
1241         { 8000,  0  },
1242         { 11025, 1  },
1243         { 12000, 1  },
1244         { 16000, 2  },
1245         { 22050, 3  },
1246         { 24000, 3  },
1247         { 32000, 4  },
1248         { 44100, 5  },
1249         { 48000, 5  },
1250 };
1251
1252 static struct {
1253         int div; /* *10 due to .5s */
1254         int bclk_div;
1255 } bclk_divs[] = {
1256         { 10,  0  },
1257         { 15,  1  },
1258         { 20,  2  },
1259         { 30,  3  },
1260         { 40,  4  },
1261         { 50,  5  },
1262         { 55,  6  },
1263         { 60,  7  },
1264         { 80,  8  },
1265         { 100, 9  },
1266         { 110, 10 },
1267         { 120, 11 },
1268         { 160, 12 },
1269         { 200, 13 },
1270         { 220, 14 },
1271         { 240, 16 },
1272         { 200, 17 },
1273         { 320, 18 },
1274         { 440, 19 },
1275         { 480, 20 },
1276 };
1277
1278
1279 static int wm8904_hw_params(struct snd_pcm_substream *substream,
1280                             struct snd_pcm_hw_params *params,
1281                             struct snd_soc_dai *dai)
1282 {
1283         struct snd_soc_codec *codec = dai->codec;
1284         struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
1285         int ret, i, best, best_val, cur_val;
1286         unsigned int aif1 = 0;
1287         unsigned int aif2 = 0;
1288         unsigned int aif3 = 0;
1289         unsigned int clock1 = 0;
1290         unsigned int dac_digital1 = 0;
1291
1292         /* What BCLK do we need? */
1293         wm8904->fs = params_rate(params);
1294         if (wm8904->tdm_slots) {
1295                 dev_dbg(codec->dev, "Configuring for %d %d bit TDM slots\n",
1296                         wm8904->tdm_slots, wm8904->tdm_width);
1297                 wm8904->bclk = snd_soc_calc_bclk(wm8904->fs,
1298                                                  wm8904->tdm_width, 2,
1299                                                  wm8904->tdm_slots);
1300         } else {
1301                 wm8904->bclk = snd_soc_params_to_bclk(params);
1302         }
1303
1304         switch (params_format(params)) {
1305         case SNDRV_PCM_FORMAT_S16_LE:
1306                 break;
1307         case SNDRV_PCM_FORMAT_S20_3LE:
1308                 aif1 |= 0x40;
1309                 break;
1310         case SNDRV_PCM_FORMAT_S24_LE:
1311                 aif1 |= 0x80;
1312                 break;
1313         case SNDRV_PCM_FORMAT_S32_LE:
1314                 aif1 |= 0xc0;
1315                 break;
1316         default:
1317                 return -EINVAL;
1318         }
1319
1320
1321         dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm8904->bclk);
1322
1323         ret = wm8904_configure_clocking(codec);
1324         if (ret != 0)
1325                 return ret;
1326
1327         /* Select nearest CLK_SYS_RATE */
1328         best = 0;
1329         best_val = abs((wm8904->sysclk_rate / clk_sys_rates[0].ratio)
1330                        - wm8904->fs);
1331         for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
1332                 cur_val = abs((wm8904->sysclk_rate /
1333                                clk_sys_rates[i].ratio) - wm8904->fs);
1334                 if (cur_val < best_val) {
1335                         best = i;
1336                         best_val = cur_val;
1337                 }
1338         }
1339         dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n",
1340                 clk_sys_rates[best].ratio);
1341         clock1 |= (clk_sys_rates[best].clk_sys_rate
1342                    << WM8904_CLK_SYS_RATE_SHIFT);
1343
1344         /* SAMPLE_RATE */
1345         best = 0;
1346         best_val = abs(wm8904->fs - sample_rates[0].rate);
1347         for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1348                 /* Closest match */
1349                 cur_val = abs(wm8904->fs - sample_rates[i].rate);
1350                 if (cur_val < best_val) {
1351                         best = i;
1352                         best_val = cur_val;
1353                 }
1354         }
1355         dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n",
1356                 sample_rates[best].rate);
1357         clock1 |= (sample_rates[best].sample_rate
1358                    << WM8904_SAMPLE_RATE_SHIFT);
1359
1360         /* Enable sloping stopband filter for low sample rates */
1361         if (wm8904->fs <= 24000)
1362                 dac_digital1 |= WM8904_DAC_SB_FILT;
1363
1364         /* BCLK_DIV */
1365         best = 0;
1366         best_val = INT_MAX;
1367         for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1368                 cur_val = ((wm8904->sysclk_rate * 10) / bclk_divs[i].div)
1369                         - wm8904->bclk;
1370                 if (cur_val < 0) /* Table is sorted */
1371                         break;
1372                 if (cur_val < best_val) {
1373                         best = i;
1374                         best_val = cur_val;
1375                 }
1376         }
1377         wm8904->bclk = (wm8904->sysclk_rate * 10) / bclk_divs[best].div;
1378         dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
1379                 bclk_divs[best].div, wm8904->bclk);
1380         aif2 |= bclk_divs[best].bclk_div;
1381
1382         /* LRCLK is a simple fraction of BCLK */
1383         dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm8904->bclk / wm8904->fs);
1384         aif3 |= wm8904->bclk / wm8904->fs;
1385
1386         /* Apply the settings */
1387         snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1,
1388                             WM8904_DAC_SB_FILT, dac_digital1);
1389         snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1,
1390                             WM8904_AIF_WL_MASK, aif1);
1391         snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_2,
1392                             WM8904_BCLK_DIV_MASK, aif2);
1393         snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_3,
1394                             WM8904_LRCLK_RATE_MASK, aif3);
1395         snd_soc_update_bits(codec, WM8904_CLOCK_RATES_1,
1396                             WM8904_SAMPLE_RATE_MASK |
1397                             WM8904_CLK_SYS_RATE_MASK, clock1);
1398
1399         /* Update filters for the new settings */
1400         wm8904_set_retune_mobile(codec);
1401         wm8904_set_deemph(codec);
1402
1403         return 0;
1404 }
1405
1406
1407 static int wm8904_set_sysclk(struct snd_soc_dai *dai, int clk_id,
1408                              unsigned int freq, int dir)
1409 {
1410         struct snd_soc_codec *codec = dai->codec;
1411         struct wm8904_priv *priv = snd_soc_codec_get_drvdata(codec);
1412
1413         switch (clk_id) {
1414         case WM8904_CLK_MCLK:
1415                 priv->sysclk_src = clk_id;
1416                 priv->mclk_rate = freq;
1417                 break;
1418
1419         case WM8904_CLK_FLL:
1420                 priv->sysclk_src = clk_id;
1421                 break;
1422
1423         default:
1424                 return -EINVAL;
1425         }
1426
1427         dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
1428
1429         wm8904_configure_clocking(codec);
1430
1431         return 0;
1432 }
1433
1434 static int wm8904_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1435 {
1436         struct snd_soc_codec *codec = dai->codec;
1437         unsigned int aif1 = 0;
1438         unsigned int aif3 = 0;
1439
1440         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1441         case SND_SOC_DAIFMT_CBS_CFS:
1442                 break;
1443         case SND_SOC_DAIFMT_CBS_CFM:
1444                 aif3 |= WM8904_LRCLK_DIR;
1445                 break;
1446         case SND_SOC_DAIFMT_CBM_CFS:
1447                 aif1 |= WM8904_BCLK_DIR;
1448                 break;
1449         case SND_SOC_DAIFMT_CBM_CFM:
1450                 aif1 |= WM8904_BCLK_DIR;
1451                 aif3 |= WM8904_LRCLK_DIR;
1452                 break;
1453         default:
1454                 return -EINVAL;
1455         }
1456
1457         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1458         case SND_SOC_DAIFMT_DSP_B:
1459                 aif1 |= WM8904_AIF_LRCLK_INV;
1460         case SND_SOC_DAIFMT_DSP_A:
1461                 aif1 |= 0x3;
1462                 break;
1463         case SND_SOC_DAIFMT_I2S:
1464                 aif1 |= 0x2;
1465                 break;
1466         case SND_SOC_DAIFMT_RIGHT_J:
1467                 break;
1468         case SND_SOC_DAIFMT_LEFT_J:
1469                 aif1 |= 0x1;
1470                 break;
1471         default:
1472                 return -EINVAL;
1473         }
1474
1475         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1476         case SND_SOC_DAIFMT_DSP_A:
1477         case SND_SOC_DAIFMT_DSP_B:
1478                 /* frame inversion not valid for DSP modes */
1479                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1480                 case SND_SOC_DAIFMT_NB_NF:
1481                         break;
1482                 case SND_SOC_DAIFMT_IB_NF:
1483                         aif1 |= WM8904_AIF_BCLK_INV;
1484                         break;
1485                 default:
1486                         return -EINVAL;
1487                 }
1488                 break;
1489
1490         case SND_SOC_DAIFMT_I2S:
1491         case SND_SOC_DAIFMT_RIGHT_J:
1492         case SND_SOC_DAIFMT_LEFT_J:
1493                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1494                 case SND_SOC_DAIFMT_NB_NF:
1495                         break;
1496                 case SND_SOC_DAIFMT_IB_IF:
1497                         aif1 |= WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV;
1498                         break;
1499                 case SND_SOC_DAIFMT_IB_NF:
1500                         aif1 |= WM8904_AIF_BCLK_INV;
1501                         break;
1502                 case SND_SOC_DAIFMT_NB_IF:
1503                         aif1 |= WM8904_AIF_LRCLK_INV;
1504                         break;
1505                 default:
1506                         return -EINVAL;
1507                 }
1508                 break;
1509         default:
1510                 return -EINVAL;
1511         }
1512
1513         snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1,
1514                             WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV |
1515                             WM8904_AIF_FMT_MASK | WM8904_BCLK_DIR, aif1);
1516         snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_3,
1517                             WM8904_LRCLK_DIR, aif3);
1518
1519         return 0;
1520 }
1521
1522
1523 static int wm8904_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1524                                unsigned int rx_mask, int slots, int slot_width)
1525 {
1526         struct snd_soc_codec *codec = dai->codec;
1527         struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
1528         int aif1 = 0;
1529
1530         /* Don't need to validate anything if we're turning off TDM */
1531         if (slots == 0)
1532                 goto out;
1533
1534         /* Note that we allow configurations we can't handle ourselves -
1535          * for example, we can generate clocks for slots 2 and up even if
1536          * we can't use those slots ourselves.
1537          */
1538         aif1 |= WM8904_AIFADC_TDM | WM8904_AIFDAC_TDM;
1539
1540         switch (rx_mask) {
1541         case 3:
1542                 break;
1543         case 0xc:
1544                 aif1 |= WM8904_AIFADC_TDM_CHAN;
1545                 break;
1546         default:
1547                 return -EINVAL;
1548         }
1549
1550
1551         switch (tx_mask) {
1552         case 3:
1553                 break;
1554         case 0xc:
1555                 aif1 |= WM8904_AIFDAC_TDM_CHAN;
1556                 break;
1557         default:
1558                 return -EINVAL;
1559         }
1560
1561 out:
1562         wm8904->tdm_width = slot_width;
1563         wm8904->tdm_slots = slots / 2;
1564
1565         snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1,
1566                             WM8904_AIFADC_TDM | WM8904_AIFADC_TDM_CHAN |
1567                             WM8904_AIFDAC_TDM | WM8904_AIFDAC_TDM_CHAN, aif1);
1568
1569         return 0;
1570 }
1571
1572 struct _fll_div {
1573         u16 fll_fratio;
1574         u16 fll_outdiv;
1575         u16 fll_clk_ref_div;
1576         u16 n;
1577         u16 k;
1578 };
1579
1580 /* The size in bits of the FLL divide multiplied by 10
1581  * to allow rounding later */
1582 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1583
1584 static struct {
1585         unsigned int min;
1586         unsigned int max;
1587         u16 fll_fratio;
1588         int ratio;
1589 } fll_fratios[] = {
1590         {       0,    64000, 4, 16 },
1591         {   64000,   128000, 3,  8 },
1592         {  128000,   256000, 2,  4 },
1593         {  256000,  1000000, 1,  2 },
1594         { 1000000, 13500000, 0,  1 },
1595 };
1596
1597 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
1598                        unsigned int Fout)
1599 {
1600         u64 Kpart;
1601         unsigned int K, Ndiv, Nmod, target;
1602         unsigned int div;
1603         int i;
1604
1605         /* Fref must be <=13.5MHz */
1606         div = 1;
1607         fll_div->fll_clk_ref_div = 0;
1608         while ((Fref / div) > 13500000) {
1609                 div *= 2;
1610                 fll_div->fll_clk_ref_div++;
1611
1612                 if (div > 8) {
1613                         pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
1614                                Fref);
1615                         return -EINVAL;
1616                 }
1617         }
1618
1619         pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
1620
1621         /* Apply the division for our remaining calculations */
1622         Fref /= div;
1623
1624         /* Fvco should be 90-100MHz; don't check the upper bound */
1625         div = 4;
1626         while (Fout * div < 90000000) {
1627                 div++;
1628                 if (div > 64) {
1629                         pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
1630                                Fout);
1631                         return -EINVAL;
1632                 }
1633         }
1634         target = Fout * div;
1635         fll_div->fll_outdiv = div - 1;
1636
1637         pr_debug("Fvco=%dHz\n", target);
1638
1639         /* Find an appropriate FLL_FRATIO and factor it out of the target */
1640         for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
1641                 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
1642                         fll_div->fll_fratio = fll_fratios[i].fll_fratio;
1643                         target /= fll_fratios[i].ratio;
1644                         break;
1645                 }
1646         }
1647         if (i == ARRAY_SIZE(fll_fratios)) {
1648                 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
1649                 return -EINVAL;
1650         }
1651
1652         /* Now, calculate N.K */
1653         Ndiv = target / Fref;
1654
1655         fll_div->n = Ndiv;
1656         Nmod = target % Fref;
1657         pr_debug("Nmod=%d\n", Nmod);
1658
1659         /* Calculate fractional part - scale up so we can round. */
1660         Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1661
1662         do_div(Kpart, Fref);
1663
1664         K = Kpart & 0xFFFFFFFF;
1665
1666         if ((K % 10) >= 5)
1667                 K += 5;
1668
1669         /* Move down to proper range now rounding is done */
1670         fll_div->k = K / 10;
1671
1672         pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
1673                  fll_div->n, fll_div->k,
1674                  fll_div->fll_fratio, fll_div->fll_outdiv,
1675                  fll_div->fll_clk_ref_div);
1676
1677         return 0;
1678 }
1679
1680 static int wm8904_set_fll(struct snd_soc_dai *dai, int fll_id, int source,
1681                           unsigned int Fref, unsigned int Fout)
1682 {
1683         struct snd_soc_codec *codec = dai->codec;
1684         struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
1685         struct _fll_div fll_div;
1686         int ret, val;
1687         int clock2, fll1;
1688
1689         /* Any change? */
1690         if (source == wm8904->fll_src && Fref == wm8904->fll_fref &&
1691             Fout == wm8904->fll_fout)
1692                 return 0;
1693
1694         clock2 = snd_soc_read(codec, WM8904_CLOCK_RATES_2);
1695
1696         if (Fout == 0) {
1697                 dev_dbg(codec->dev, "FLL disabled\n");
1698
1699                 wm8904->fll_fref = 0;
1700                 wm8904->fll_fout = 0;
1701
1702                 /* Gate SYSCLK to avoid glitches */
1703                 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
1704                                     WM8904_CLK_SYS_ENA, 0);
1705
1706                 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
1707                                     WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
1708
1709                 goto out;
1710         }
1711
1712         /* Validate the FLL ID */
1713         switch (source) {
1714         case WM8904_FLL_MCLK:
1715         case WM8904_FLL_LRCLK:
1716         case WM8904_FLL_BCLK:
1717                 ret = fll_factors(&fll_div, Fref, Fout);
1718                 if (ret != 0)
1719                         return ret;
1720                 break;
1721
1722         case WM8904_FLL_FREE_RUNNING:
1723                 dev_dbg(codec->dev, "Using free running FLL\n");
1724                 /* Force 12MHz and output/4 for now */
1725                 Fout = 12000000;
1726                 Fref = 12000000;
1727
1728                 memset(&fll_div, 0, sizeof(fll_div));
1729                 fll_div.fll_outdiv = 3;
1730                 break;
1731
1732         default:
1733                 dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id);
1734                 return -EINVAL;
1735         }
1736
1737         /* Save current state then disable the FLL and SYSCLK to avoid
1738          * misclocking */
1739         fll1 = snd_soc_read(codec, WM8904_FLL_CONTROL_1);
1740         snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
1741                             WM8904_CLK_SYS_ENA, 0);
1742         snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
1743                             WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
1744
1745         /* Unlock forced oscilator control to switch it on/off */
1746         snd_soc_update_bits(codec, WM8904_CONTROL_INTERFACE_TEST_1,
1747                             WM8904_USER_KEY, WM8904_USER_KEY);
1748
1749         if (fll_id == WM8904_FLL_FREE_RUNNING) {
1750                 val = WM8904_FLL_FRC_NCO;
1751         } else {
1752                 val = 0;
1753         }
1754
1755         snd_soc_update_bits(codec, WM8904_FLL_NCO_TEST_1, WM8904_FLL_FRC_NCO,
1756                             val);
1757         snd_soc_update_bits(codec, WM8904_CONTROL_INTERFACE_TEST_1,
1758                             WM8904_USER_KEY, 0);
1759
1760         switch (fll_id) {
1761         case WM8904_FLL_MCLK:
1762                 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5,
1763                                     WM8904_FLL_CLK_REF_SRC_MASK, 0);
1764                 break;
1765
1766         case WM8904_FLL_LRCLK:
1767                 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5,
1768                                     WM8904_FLL_CLK_REF_SRC_MASK, 1);
1769                 break;
1770
1771         case WM8904_FLL_BCLK:
1772                 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5,
1773                                     WM8904_FLL_CLK_REF_SRC_MASK, 2);
1774                 break;
1775         }
1776
1777         if (fll_div.k)
1778                 val = WM8904_FLL_FRACN_ENA;
1779         else
1780                 val = 0;
1781         snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
1782                             WM8904_FLL_FRACN_ENA, val);
1783
1784         snd_soc_update_bits(codec, WM8904_FLL_CONTROL_2,
1785                             WM8904_FLL_OUTDIV_MASK | WM8904_FLL_FRATIO_MASK,
1786                             (fll_div.fll_outdiv << WM8904_FLL_OUTDIV_SHIFT) |
1787                             (fll_div.fll_fratio << WM8904_FLL_FRATIO_SHIFT));
1788
1789         snd_soc_write(codec, WM8904_FLL_CONTROL_3, fll_div.k);
1790
1791         snd_soc_update_bits(codec, WM8904_FLL_CONTROL_4, WM8904_FLL_N_MASK,
1792                             fll_div.n << WM8904_FLL_N_SHIFT);
1793
1794         snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5,
1795                             WM8904_FLL_CLK_REF_DIV_MASK,
1796                             fll_div.fll_clk_ref_div
1797                             << WM8904_FLL_CLK_REF_DIV_SHIFT);
1798
1799         dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
1800
1801         wm8904->fll_fref = Fref;
1802         wm8904->fll_fout = Fout;
1803         wm8904->fll_src = source;
1804
1805         /* Enable the FLL if it was previously active */
1806         snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
1807                             WM8904_FLL_OSC_ENA, fll1);
1808         snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
1809                             WM8904_FLL_ENA, fll1);
1810
1811 out:
1812         /* Reenable SYSCLK if it was previously active */
1813         snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
1814                             WM8904_CLK_SYS_ENA, clock2);
1815
1816         return 0;
1817 }
1818
1819 static int wm8904_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1820 {
1821         struct snd_soc_codec *codec = codec_dai->codec;
1822         int val;
1823
1824         if (mute)
1825                 val = WM8904_DAC_MUTE;
1826         else
1827                 val = 0;
1828
1829         snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1, WM8904_DAC_MUTE, val);
1830
1831         return 0;
1832 }
1833
1834 static int wm8904_set_bias_level(struct snd_soc_codec *codec,
1835                                  enum snd_soc_bias_level level)
1836 {
1837         struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
1838         int ret;
1839
1840         switch (level) {
1841         case SND_SOC_BIAS_ON:
1842                 break;
1843
1844         case SND_SOC_BIAS_PREPARE:
1845                 /* VMID resistance 2*50k */
1846                 snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0,
1847                                     WM8904_VMID_RES_MASK,
1848                                     0x1 << WM8904_VMID_RES_SHIFT);
1849
1850                 /* Normal bias current */
1851                 snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0,
1852                                     WM8904_ISEL_MASK, 2 << WM8904_ISEL_SHIFT);
1853                 break;
1854
1855         case SND_SOC_BIAS_STANDBY:
1856                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1857                         ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies),
1858                                                     wm8904->supplies);
1859                         if (ret != 0) {
1860                                 dev_err(codec->dev,
1861                                         "Failed to enable supplies: %d\n",
1862                                         ret);
1863                                 return ret;
1864                         }
1865
1866                         regcache_cache_only(wm8904->regmap, false);
1867                         regcache_sync(wm8904->regmap);
1868
1869                         /* Enable bias */
1870                         snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0,
1871                                             WM8904_BIAS_ENA, WM8904_BIAS_ENA);
1872
1873                         /* Enable VMID, VMID buffering, 2*5k resistance */
1874                         snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0,
1875                                             WM8904_VMID_ENA |
1876                                             WM8904_VMID_RES_MASK,
1877                                             WM8904_VMID_ENA |
1878                                             0x3 << WM8904_VMID_RES_SHIFT);
1879
1880                         /* Let VMID ramp */
1881                         msleep(1);
1882                 }
1883
1884                 /* Maintain VMID with 2*250k */
1885                 snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0,
1886                                     WM8904_VMID_RES_MASK,
1887                                     0x2 << WM8904_VMID_RES_SHIFT);
1888
1889                 /* Bias current *0.5 */
1890                 snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0,
1891                                     WM8904_ISEL_MASK, 0);
1892                 break;
1893
1894         case SND_SOC_BIAS_OFF:
1895                 /* Turn off VMID */
1896                 snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0,
1897                                     WM8904_VMID_RES_MASK | WM8904_VMID_ENA, 0);
1898
1899                 /* Stop bias generation */
1900                 snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0,
1901                                     WM8904_BIAS_ENA, 0);
1902
1903                 regcache_cache_only(wm8904->regmap, true);
1904                 regcache_mark_dirty(wm8904->regmap);
1905
1906                 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies),
1907                                        wm8904->supplies);
1908                 break;
1909         }
1910         codec->dapm.bias_level = level;
1911         return 0;
1912 }
1913
1914 #define WM8904_RATES SNDRV_PCM_RATE_8000_96000
1915
1916 #define WM8904_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1917                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1918
1919 static const struct snd_soc_dai_ops wm8904_dai_ops = {
1920         .set_sysclk = wm8904_set_sysclk,
1921         .set_fmt = wm8904_set_fmt,
1922         .set_tdm_slot = wm8904_set_tdm_slot,
1923         .set_pll = wm8904_set_fll,
1924         .hw_params = wm8904_hw_params,
1925         .digital_mute = wm8904_digital_mute,
1926 };
1927
1928 static struct snd_soc_dai_driver wm8904_dai = {
1929         .name = "wm8904-hifi",
1930         .playback = {
1931                 .stream_name = "Playback",
1932                 .channels_min = 2,
1933                 .channels_max = 2,
1934                 .rates = WM8904_RATES,
1935                 .formats = WM8904_FORMATS,
1936         },
1937         .capture = {
1938                 .stream_name = "Capture",
1939                 .channels_min = 2,
1940                 .channels_max = 2,
1941                 .rates = WM8904_RATES,
1942                 .formats = WM8904_FORMATS,
1943         },
1944         .ops = &wm8904_dai_ops,
1945         .symmetric_rates = 1,
1946 };
1947
1948 #ifdef CONFIG_PM
1949 static int wm8904_suspend(struct snd_soc_codec *codec)
1950 {
1951         wm8904_set_bias_level(codec, SND_SOC_BIAS_OFF);
1952
1953         return 0;
1954 }
1955
1956 static int wm8904_resume(struct snd_soc_codec *codec)
1957 {
1958         wm8904_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1959
1960         return 0;
1961 }
1962 #else
1963 #define wm8904_suspend NULL
1964 #define wm8904_resume NULL
1965 #endif
1966
1967 static void wm8904_handle_retune_mobile_pdata(struct snd_soc_codec *codec)
1968 {
1969         struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
1970         struct wm8904_pdata *pdata = wm8904->pdata;
1971         struct snd_kcontrol_new control =
1972                 SOC_ENUM_EXT("EQ Mode",
1973                              wm8904->retune_mobile_enum,
1974                              wm8904_get_retune_mobile_enum,
1975                              wm8904_put_retune_mobile_enum);
1976         int ret, i, j;
1977         const char **t;
1978
1979         /* We need an array of texts for the enum API but the number
1980          * of texts is likely to be less than the number of
1981          * configurations due to the sample rate dependency of the
1982          * configurations. */
1983         wm8904->num_retune_mobile_texts = 0;
1984         wm8904->retune_mobile_texts = NULL;
1985         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
1986                 for (j = 0; j < wm8904->num_retune_mobile_texts; j++) {
1987                         if (strcmp(pdata->retune_mobile_cfgs[i].name,
1988                                    wm8904->retune_mobile_texts[j]) == 0)
1989                                 break;
1990                 }
1991
1992                 if (j != wm8904->num_retune_mobile_texts)
1993                         continue;
1994
1995                 /* Expand the array... */
1996                 t = krealloc(wm8904->retune_mobile_texts,
1997                              sizeof(char *) *
1998                              (wm8904->num_retune_mobile_texts + 1),
1999                              GFP_KERNEL);
2000                 if (t == NULL)
2001                         continue;
2002
2003                 /* ...store the new entry... */
2004                 t[wm8904->num_retune_mobile_texts] =
2005                         pdata->retune_mobile_cfgs[i].name;
2006
2007                 /* ...and remember the new version. */
2008                 wm8904->num_retune_mobile_texts++;
2009                 wm8904->retune_mobile_texts = t;
2010         }
2011
2012         dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2013                 wm8904->num_retune_mobile_texts);
2014
2015         wm8904->retune_mobile_enum.max = wm8904->num_retune_mobile_texts;
2016         wm8904->retune_mobile_enum.texts = wm8904->retune_mobile_texts;
2017
2018         ret = snd_soc_add_codec_controls(codec, &control, 1);
2019         if (ret != 0)
2020                 dev_err(codec->dev,
2021                         "Failed to add ReTune Mobile control: %d\n", ret);
2022 }
2023
2024 static void wm8904_handle_pdata(struct snd_soc_codec *codec)
2025 {
2026         struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
2027         struct wm8904_pdata *pdata = wm8904->pdata;
2028         int ret, i;
2029
2030         if (!pdata) {
2031                 snd_soc_add_codec_controls(codec, wm8904_eq_controls,
2032                                      ARRAY_SIZE(wm8904_eq_controls));
2033                 return;
2034         }
2035
2036         dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2037
2038         if (pdata->num_drc_cfgs) {
2039                 struct snd_kcontrol_new control =
2040                         SOC_ENUM_EXT("DRC Mode", wm8904->drc_enum,
2041                                      wm8904_get_drc_enum, wm8904_put_drc_enum);
2042
2043                 /* We need an array of texts for the enum API */
2044                 wm8904->drc_texts = kmalloc(sizeof(char *)
2045                                             * pdata->num_drc_cfgs, GFP_KERNEL);
2046                 if (!wm8904->drc_texts) {
2047                         dev_err(codec->dev,
2048                                 "Failed to allocate %d DRC config texts\n",
2049                                 pdata->num_drc_cfgs);
2050                         return;
2051                 }
2052
2053                 for (i = 0; i < pdata->num_drc_cfgs; i++)
2054                         wm8904->drc_texts[i] = pdata->drc_cfgs[i].name;
2055
2056                 wm8904->drc_enum.max = pdata->num_drc_cfgs;
2057                 wm8904->drc_enum.texts = wm8904->drc_texts;
2058
2059                 ret = snd_soc_add_codec_controls(codec, &control, 1);
2060                 if (ret != 0)
2061                         dev_err(codec->dev,
2062                                 "Failed to add DRC mode control: %d\n", ret);
2063
2064                 wm8904_set_drc(codec);
2065         }
2066
2067         dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
2068                 pdata->num_retune_mobile_cfgs);
2069
2070         if (pdata->num_retune_mobile_cfgs)
2071                 wm8904_handle_retune_mobile_pdata(codec);
2072         else
2073                 snd_soc_add_codec_controls(codec, wm8904_eq_controls,
2074                                      ARRAY_SIZE(wm8904_eq_controls));
2075 }
2076
2077
2078 static int wm8904_probe(struct snd_soc_codec *codec)
2079 {
2080         struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
2081         struct wm8904_pdata *pdata = wm8904->pdata;
2082         int ret, i;
2083
2084         codec->control_data = wm8904->regmap;
2085
2086         switch (wm8904->devtype) {
2087         case WM8904:
2088                 break;
2089         case WM8912:
2090                 memset(&wm8904_dai.capture, 0, sizeof(wm8904_dai.capture));
2091                 break;
2092         default:
2093                 dev_err(codec->dev, "Unknown device type %d\n",
2094                         wm8904->devtype);
2095                 return -EINVAL;
2096         }
2097
2098         ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_REGMAP);
2099         if (ret != 0) {
2100                 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
2101                 return ret;
2102         }
2103
2104         for (i = 0; i < ARRAY_SIZE(wm8904->supplies); i++)
2105                 wm8904->supplies[i].supply = wm8904_supply_names[i];
2106
2107         ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8904->supplies),
2108                                  wm8904->supplies);
2109         if (ret != 0) {
2110                 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
2111                 return ret;
2112         }
2113
2114         ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies),
2115                                     wm8904->supplies);
2116         if (ret != 0) {
2117                 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
2118                 goto err_get;
2119         }
2120
2121         ret = snd_soc_read(codec, WM8904_SW_RESET_AND_ID);
2122         if (ret < 0) {
2123                 dev_err(codec->dev, "Failed to read ID register\n");
2124                 goto err_enable;
2125         }
2126         if (ret != 0x8904) {
2127                 dev_err(codec->dev, "Device is not a WM8904, ID is %x\n", ret);
2128                 ret = -EINVAL;
2129                 goto err_enable;
2130         }
2131
2132         ret = snd_soc_read(codec, WM8904_REVISION);
2133         if (ret < 0) {
2134                 dev_err(codec->dev, "Failed to read device revision: %d\n",
2135                         ret);
2136                 goto err_enable;
2137         }
2138         dev_info(codec->dev, "revision %c\n", ret + 'A');
2139
2140         ret = wm8904_reset(codec);
2141         if (ret < 0) {
2142                 dev_err(codec->dev, "Failed to issue reset\n");
2143                 goto err_enable;
2144         }
2145
2146         regcache_cache_only(wm8904->regmap, true);
2147         /* Change some default settings - latch VU and enable ZC */
2148         snd_soc_update_bits(codec, WM8904_ADC_DIGITAL_VOLUME_LEFT,
2149                             WM8904_ADC_VU, WM8904_ADC_VU);
2150         snd_soc_update_bits(codec, WM8904_ADC_DIGITAL_VOLUME_RIGHT,
2151                             WM8904_ADC_VU, WM8904_ADC_VU);
2152         snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_VOLUME_LEFT,
2153                             WM8904_DAC_VU, WM8904_DAC_VU);
2154         snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_VOLUME_RIGHT,
2155                             WM8904_DAC_VU, WM8904_DAC_VU);
2156         snd_soc_update_bits(codec, WM8904_ANALOGUE_OUT1_LEFT,
2157                             WM8904_HPOUT_VU | WM8904_HPOUTLZC,
2158                             WM8904_HPOUT_VU | WM8904_HPOUTLZC);
2159         snd_soc_update_bits(codec, WM8904_ANALOGUE_OUT1_RIGHT,
2160                             WM8904_HPOUT_VU | WM8904_HPOUTRZC,
2161                             WM8904_HPOUT_VU | WM8904_HPOUTRZC);
2162         snd_soc_update_bits(codec, WM8904_ANALOGUE_OUT2_LEFT,
2163                             WM8904_LINEOUT_VU | WM8904_LINEOUTLZC,
2164                             WM8904_LINEOUT_VU | WM8904_LINEOUTLZC);
2165         snd_soc_update_bits(codec, WM8904_ANALOGUE_OUT2_RIGHT,
2166                             WM8904_LINEOUT_VU | WM8904_LINEOUTRZC,
2167                             WM8904_LINEOUT_VU | WM8904_LINEOUTRZC);
2168         snd_soc_update_bits(codec, WM8904_CLOCK_RATES_0,
2169                             WM8904_SR_MODE, 0);
2170
2171         /* Apply configuration from the platform data. */
2172         if (wm8904->pdata) {
2173                 for (i = 0; i < WM8904_GPIO_REGS; i++) {
2174                         if (!pdata->gpio_cfg[i])
2175                                 continue;
2176
2177                         regmap_update_bits(wm8904->regmap,
2178                                            WM8904_GPIO_CONTROL_1 + i,
2179                                            0xffff,
2180                                            pdata->gpio_cfg[i]);
2181                 }
2182
2183                 /* Zero is the default value for these anyway */
2184                 for (i = 0; i < WM8904_MIC_REGS; i++)
2185                         regmap_update_bits(wm8904->regmap,
2186                                            WM8904_MIC_BIAS_CONTROL_0 + i,
2187                                            0xffff,
2188                                            pdata->mic_cfg[i]);
2189         }
2190
2191         /* Set Class W by default - this will be managed by the Class
2192          * G widget at runtime where bypass paths are available.
2193          */
2194         snd_soc_update_bits(codec, WM8904_CLASS_W_0,
2195                             WM8904_CP_DYN_PWR, WM8904_CP_DYN_PWR);
2196
2197         /* Use normal bias source */
2198         snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0,
2199                             WM8904_POBCTRL, 0);
2200
2201         wm8904_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2202
2203         /* Bias level configuration will have done an extra enable */
2204         regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies);
2205
2206         wm8904_handle_pdata(codec);
2207
2208         wm8904_add_widgets(codec);
2209
2210         return 0;
2211
2212 err_enable:
2213         regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies);
2214 err_get:
2215         regulator_bulk_free(ARRAY_SIZE(wm8904->supplies), wm8904->supplies);
2216         return ret;
2217 }
2218
2219 static int wm8904_remove(struct snd_soc_codec *codec)
2220 {
2221         struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
2222
2223         wm8904_set_bias_level(codec, SND_SOC_BIAS_OFF);
2224         regulator_bulk_free(ARRAY_SIZE(wm8904->supplies), wm8904->supplies);
2225         kfree(wm8904->retune_mobile_texts);
2226         kfree(wm8904->drc_texts);
2227
2228         return 0;
2229 }
2230
2231 static struct snd_soc_codec_driver soc_codec_dev_wm8904 = {
2232         .probe =        wm8904_probe,
2233         .remove =       wm8904_remove,
2234         .suspend =      wm8904_suspend,
2235         .resume =       wm8904_resume,
2236         .set_bias_level = wm8904_set_bias_level,
2237         .idle_bias_off = true,
2238 };
2239
2240 static const struct regmap_config wm8904_regmap = {
2241         .reg_bits = 8,
2242         .val_bits = 16,
2243
2244         .max_register = WM8904_MAX_REGISTER,
2245         .volatile_reg = wm8904_volatile_register,
2246         .readable_reg = wm8904_readable_register,
2247
2248         .cache_type = REGCACHE_RBTREE,
2249         .reg_defaults = wm8904_reg_defaults,
2250         .num_reg_defaults = ARRAY_SIZE(wm8904_reg_defaults),
2251 };
2252
2253 static __devinit int wm8904_i2c_probe(struct i2c_client *i2c,
2254                                       const struct i2c_device_id *id)
2255 {
2256         struct wm8904_priv *wm8904;
2257         int ret;
2258
2259         wm8904 = devm_kzalloc(&i2c->dev, sizeof(struct wm8904_priv),
2260                               GFP_KERNEL);
2261         if (wm8904 == NULL)
2262                 return -ENOMEM;
2263
2264         wm8904->regmap = regmap_init_i2c(i2c, &wm8904_regmap);
2265         if (IS_ERR(wm8904->regmap)) {
2266                 ret = PTR_ERR(wm8904->regmap);
2267                 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2268                         ret);
2269                 return ret;
2270         }
2271
2272         wm8904->devtype = id->driver_data;
2273         i2c_set_clientdata(i2c, wm8904);
2274         wm8904->pdata = i2c->dev.platform_data;
2275
2276         ret = snd_soc_register_codec(&i2c->dev,
2277                         &soc_codec_dev_wm8904, &wm8904_dai, 1);
2278         if (ret != 0)
2279                 goto err;
2280
2281         return 0;
2282
2283 err:
2284         regmap_exit(wm8904->regmap);
2285         return ret;
2286 }
2287
2288 static __devexit int wm8904_i2c_remove(struct i2c_client *client)
2289 {
2290         struct wm8904_priv *wm8904 = i2c_get_clientdata(client);
2291         snd_soc_unregister_codec(&client->dev);
2292         regmap_exit(wm8904->regmap);
2293         return 0;
2294 }
2295
2296 static const struct i2c_device_id wm8904_i2c_id[] = {
2297         { "wm8904", WM8904 },
2298         { "wm8912", WM8912 },
2299         { "wm8918", WM8904 },   /* Actually a subset, updates to follow */
2300         { }
2301 };
2302 MODULE_DEVICE_TABLE(i2c, wm8904_i2c_id);
2303
2304 static struct i2c_driver wm8904_i2c_driver = {
2305         .driver = {
2306                 .name = "wm8904",
2307                 .owner = THIS_MODULE,
2308         },
2309         .probe =    wm8904_i2c_probe,
2310         .remove =   __devexit_p(wm8904_i2c_remove),
2311         .id_table = wm8904_i2c_id,
2312 };
2313
2314 static int __init wm8904_modinit(void)
2315 {
2316         int ret = 0;
2317         ret = i2c_add_driver(&wm8904_i2c_driver);
2318         if (ret != 0) {
2319                 printk(KERN_ERR "Failed to register wm8904 I2C driver: %d\n",
2320                        ret);
2321         }
2322         return ret;
2323 }
2324 module_init(wm8904_modinit);
2325
2326 static void __exit wm8904_exit(void)
2327 {
2328         i2c_del_driver(&wm8904_i2c_driver);
2329 }
2330 module_exit(wm8904_exit);
2331
2332 MODULE_DESCRIPTION("ASoC WM8904 driver");
2333 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2334 MODULE_LICENSE("GPL");