sound/soc/codecs/wm8350.c

   1 /*
   2  * wm8350.c -- WM8350 ALSA SoC audio driver
   3  *
   4  * Copyright (C) 2007, 2008 Wolfson Microelectronics PLC.
   5  *
   6  * Author: Liam Girdwood <lg@opensource.wolfsonmicro.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/moduleparam.h>
  15 #include <linux/init.h>
  16 #include <linux/delay.h>
  17 #include <linux/pm.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/mfd/wm8350/audio.h>
  20 #include <linux/mfd/wm8350/core.h>
  21 #include <linux/regulator/consumer.h>
  22 #include <sound/core.h>
  23 #include <sound/pcm.h>
  24 #include <sound/pcm_params.h>
  25 #include <sound/soc.h>
  26 #include <sound/soc-dapm.h>
  27 #include <sound/initval.h>
  28 #include <sound/tlv.h>
  29
  30 #include "wm8350.h"
  31
  32 #define WM8350_OUTn_0dB 0x39
  33
  34 #define WM8350_RAMP_NONE        0
  35 #define WM8350_RAMP_UP          1
  36 #define WM8350_RAMP_DOWN        2
  37
  38 /* We only include the analogue supplies here; the digital supplies
  39  * need to be available well before this driver can be probed.
  40  */
  41 static const char *supply_names[] = {
  42         "AVDD",
  43         "HPVDD",
  44 };
  45
  46 struct wm8350_output {
  47         u16 active;
  48         u16 left_vol;
  49         u16 right_vol;
  50         u16 ramp;
  51         u16 mute;
  52 };
  53
  54 struct wm8350_jack_data {
  55         struct snd_soc_jack *jack;
  56         int report;
  57 };
  58
  59 struct wm8350_data {
  60         struct snd_soc_codec codec;
  61         struct wm8350_output out1;
  62         struct wm8350_output out2;
  63         struct wm8350_jack_data hpl;
  64         struct wm8350_jack_data hpr;
  65         struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)];
  66 };
  67
  68 static unsigned int wm8350_codec_cache_read(struct snd_soc_codec *codec,
  69                                             unsigned int reg)
  70 {
  71         struct wm8350 *wm8350 = codec->control_data;
  72         return wm8350->reg_cache[reg];
  73 }
  74
  75 static unsigned int wm8350_codec_read(struct snd_soc_codec *codec,
  76                                       unsigned int reg)
  77 {
  78         struct wm8350 *wm8350 = codec->control_data;
  79         return wm8350_reg_read(wm8350, reg);
  80 }
  81
  82 static int wm8350_codec_write(struct snd_soc_codec *codec, unsigned int reg,
  83                               unsigned int value)
  84 {
  85         struct wm8350 *wm8350 = codec->control_data;
  86         return wm8350_reg_write(wm8350, reg, value);
  87 }
  88
  89 /*
  90  * Ramp OUT1 PGA volume to minimise pops at stream startup and shutdown.
  91  */
  92 static inline int wm8350_out1_ramp_step(struct snd_soc_codec *codec)
  93 {
  94         struct wm8350_data *wm8350_data = codec->private_data;
  95         struct wm8350_output *out1 = &wm8350_data->out1;
  96         struct wm8350 *wm8350 = codec->control_data;
  97         int left_complete = 0, right_complete = 0;
  98         u16 reg, val;
  99
 100         /* left channel */
 101         reg = wm8350_reg_read(wm8350, WM8350_LOUT1_VOLUME);
 102         val = (reg & WM8350_OUT1L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
 103
 104         if (out1->ramp == WM8350_RAMP_UP) {
 105                 /* ramp step up */
 106                 if (val < out1->left_vol) {
 107                         val++;
 108                         reg &= ~WM8350_OUT1L_VOL_MASK;
 109                         wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME,
 110                                          reg | (val << WM8350_OUT1L_VOL_SHIFT));
 111                 } else
 112                         left_complete = 1;
 113         } else if (out1->ramp == WM8350_RAMP_DOWN) {
 114                 /* ramp step down */
 115                 if (val > 0) {
 116                         val--;
 117                         reg &= ~WM8350_OUT1L_VOL_MASK;
 118                         wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME,
 119                                          reg | (val << WM8350_OUT1L_VOL_SHIFT));
 120                 } else
 121                         left_complete = 1;
 122         } else
 123                 return 1;
 124
 125         /* right channel */
 126         reg = wm8350_reg_read(wm8350, WM8350_ROUT1_VOLUME);
 127         val = (reg & WM8350_OUT1R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
 128         if (out1->ramp == WM8350_RAMP_UP) {
 129                 /* ramp step up */
 130                 if (val < out1->right_vol) {
 131                         val++;
 132                         reg &= ~WM8350_OUT1R_VOL_MASK;
 133                         wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME,
 134                                          reg | (val << WM8350_OUT1R_VOL_SHIFT));
 135                 } else
 136                         right_complete = 1;
 137         } else if (out1->ramp == WM8350_RAMP_DOWN) {
 138                 /* ramp step down */
 139                 if (val > 0) {
 140                         val--;
 141                         reg &= ~WM8350_OUT1R_VOL_MASK;
 142                         wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME,
 143                                          reg | (val << WM8350_OUT1R_VOL_SHIFT));
 144                 } else
 145                         right_complete = 1;
 146         }
 147
 148         /* only hit the update bit if either volume has changed this step */
 149         if (!left_complete || !right_complete)
 150                 wm8350_set_bits(wm8350, WM8350_LOUT1_VOLUME, WM8350_OUT1_VU);
 151
 152         return left_complete & right_complete;
 153 }
 154
 155 /*
 156  * Ramp OUT2 PGA volume to minimise pops at stream startup and shutdown.
 157  */
 158 static inline int wm8350_out2_ramp_step(struct snd_soc_codec *codec)
 159 {
 160         struct wm8350_data *wm8350_data = codec->private_data;
 161         struct wm8350_output *out2 = &wm8350_data->out2;
 162         struct wm8350 *wm8350 = codec->control_data;
 163         int left_complete = 0, right_complete = 0;
 164         u16 reg, val;
 165
 166         /* left channel */
 167         reg = wm8350_reg_read(wm8350, WM8350_LOUT2_VOLUME);
 168         val = (reg & WM8350_OUT2L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
 169         if (out2->ramp == WM8350_RAMP_UP) {
 170                 /* ramp step up */
 171                 if (val < out2->left_vol) {
 172                         val++;
 173                         reg &= ~WM8350_OUT2L_VOL_MASK;
 174                         wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME,
 175                                          reg | (val << WM8350_OUT1L_VOL_SHIFT));
 176                 } else
 177                         left_complete = 1;
 178         } else if (out2->ramp == WM8350_RAMP_DOWN) {
 179                 /* ramp step down */
 180                 if (val > 0) {
 181                         val--;
 182                         reg &= ~WM8350_OUT2L_VOL_MASK;
 183                         wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME,
 184                                          reg | (val << WM8350_OUT1L_VOL_SHIFT));
 185                 } else
 186                         left_complete = 1;
 187         } else
 188                 return 1;
 189
 190         /* right channel */
 191         reg = wm8350_reg_read(wm8350, WM8350_ROUT2_VOLUME);
 192         val = (reg & WM8350_OUT2R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
 193         if (out2->ramp == WM8350_RAMP_UP) {
 194                 /* ramp step up */
 195                 if (val < out2->right_vol) {
 196                         val++;
 197                         reg &= ~WM8350_OUT2R_VOL_MASK;
 198                         wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME,
 199                                          reg | (val << WM8350_OUT1R_VOL_SHIFT));
 200                 } else
 201                         right_complete = 1;
 202         } else if (out2->ramp == WM8350_RAMP_DOWN) {
 203                 /* ramp step down */
 204                 if (val > 0) {
 205                         val--;
 206                         reg &= ~WM8350_OUT2R_VOL_MASK;
 207                         wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME,
 208                                          reg | (val << WM8350_OUT1R_VOL_SHIFT));
 209                 } else
 210                         right_complete = 1;
 211         }
 212
 213         /* only hit the update bit if either volume has changed this step */
 214         if (!left_complete || !right_complete)
 215                 wm8350_set_bits(wm8350, WM8350_LOUT2_VOLUME, WM8350_OUT2_VU);
 216
 217         return left_complete & right_complete;
 218 }
 219
 220 /*
 221  * This work ramps both output PGAs at stream start/stop time to
 222  * minimise pop associated with DAPM power switching.
 223  * It's best to enable Zero Cross when ramping occurs to minimise any
 224  * zipper noises.
 225  */
 226 static void wm8350_pga_work(struct work_struct *work)
 227 {
 228         struct snd_soc_codec *codec =
 229             container_of(work, struct snd_soc_codec, delayed_work.work);
 230         struct wm8350_data *wm8350_data = codec->private_data;
 231         struct wm8350_output *out1 = &wm8350_data->out1,
 232             *out2 = &wm8350_data->out2;
 233         int i, out1_complete, out2_complete;
 234
 235         /* do we need to ramp at all ? */
 236         if (out1->ramp == WM8350_RAMP_NONE && out2->ramp == WM8350_RAMP_NONE)
 237                 return;
 238
 239         /* PGA volumes have 6 bits of resolution to ramp */
 240         for (i = 0; i <= 63; i++) {
 241                 out1_complete = 1, out2_complete = 1;
 242                 if (out1->ramp != WM8350_RAMP_NONE)
 243                         out1_complete = wm8350_out1_ramp_step(codec);
 244                 if (out2->ramp != WM8350_RAMP_NONE)
 245                         out2_complete = wm8350_out2_ramp_step(codec);
 246
 247                 /* ramp finished ? */
 248                 if (out1_complete && out2_complete)
 249                         break;
 250
 251                 /* we need to delay longer on the up ramp */
 252                 if (out1->ramp == WM8350_RAMP_UP ||
 253                     out2->ramp == WM8350_RAMP_UP) {
 254                         /* delay is longer over 0dB as increases are larger */
 255                         if (i >= WM8350_OUTn_0dB)
 256                                 schedule_timeout_interruptible(msecs_to_jiffies
 257                                                                (2));
 258                         else
 259                                 schedule_timeout_interruptible(msecs_to_jiffies
 260                                                                (1));
 261                 } else
 262                         udelay(50);     /* doesn't matter if we delay longer */
 263         }
 264
 265         out1->ramp = WM8350_RAMP_NONE;
 266         out2->ramp = WM8350_RAMP_NONE;
 267 }
 268
 269 /*
 270  * WM8350 Controls
 271  */
 272
 273 static int pga_event(struct snd_soc_dapm_widget *w,
 274                      struct snd_kcontrol *kcontrol, int event)
 275 {
 276         struct snd_soc_codec *codec = w->codec;
 277         struct wm8350_data *wm8350_data = codec->private_data;
 278         struct wm8350_output *out;
 279
 280         switch (w->shift) {
 281         case 0:
 282         case 1:
 283                 out = &wm8350_data->out1;
 284                 break;
 285         case 2:
 286         case 3:
 287                 out = &wm8350_data->out2;
 288                 break;
 289
 290         default:
 291                 BUG();
 292                 return -1;
 293         }
 294
 295         switch (event) {
 296         case SND_SOC_DAPM_POST_PMU:
 297                 out->ramp = WM8350_RAMP_UP;
 298                 out->active = 1;
 299
 300                 if (!delayed_work_pending(&codec->delayed_work))
 301                         schedule_delayed_work(&codec->delayed_work,
 302                                               msecs_to_jiffies(1));
 303                 break;
 304
 305         case SND_SOC_DAPM_PRE_PMD:
 306                 out->ramp = WM8350_RAMP_DOWN;
 307                 out->active = 0;
 308
 309                 if (!delayed_work_pending(&codec->delayed_work))
 310                         schedule_delayed_work(&codec->delayed_work,
 311                                               msecs_to_jiffies(1));
 312                 break;
 313         }
 314
 315         return 0;
 316 }
 317
 318 static int wm8350_put_volsw_2r_vu(struct snd_kcontrol *kcontrol,
 319                                   struct snd_ctl_elem_value *ucontrol)
 320 {
 321         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 322         struct wm8350_data *wm8350_priv = codec->private_data;
 323         struct wm8350_output *out = NULL;
 324         struct soc_mixer_control *mc =
 325                 (struct soc_mixer_control *)kcontrol->private_value;
 326         int ret;
 327         unsigned int reg = mc->reg;
 328         u16 val;
 329
 330         /* For OUT1 and OUT2 we shadow the values and only actually write
 331          * them out when active in order to ensure the amplifier comes on
 332          * as quietly as possible. */
 333         switch (reg) {
 334         case WM8350_LOUT1_VOLUME:
 335                 out = &wm8350_priv->out1;
 336                 break;
 337         case WM8350_LOUT2_VOLUME:
 338                 out = &wm8350_priv->out2;
 339                 break;
 340         default:
 341                 break;
 342         }
 343
 344         if (out) {
 345                 out->left_vol = ucontrol->value.integer.value[0];
 346                 out->right_vol = ucontrol->value.integer.value[1];
 347                 if (!out->active)
 348                         return 1;
 349         }
 350
 351         ret = snd_soc_put_volsw_2r(kcontrol, ucontrol);
 352         if (ret < 0)
 353                 return ret;
 354
 355         /* now hit the volume update bits (always bit 8) */
 356         val = wm8350_codec_read(codec, reg);
 357         wm8350_codec_write(codec, reg, val | WM8350_OUT1_VU);
 358         return 1;
 359 }
 360
 361 static int wm8350_get_volsw_2r(struct snd_kcontrol *kcontrol,
 362                                struct snd_ctl_elem_value *ucontrol)
 363 {
 364         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 365         struct wm8350_data *wm8350_priv = codec->private_data;
 366         struct wm8350_output *out1 = &wm8350_priv->out1;
 367         struct wm8350_output *out2 = &wm8350_priv->out2;
 368         struct soc_mixer_control *mc =
 369                 (struct soc_mixer_control *)kcontrol->private_value;
 370         unsigned int reg = mc->reg;
 371
 372         /* If these are cached registers use the cache */
 373         switch (reg) {
 374         case WM8350_LOUT1_VOLUME:
 375                 ucontrol->value.integer.value[0] = out1->left_vol;
 376                 ucontrol->value.integer.value[1] = out1->right_vol;
 377                 return 0;
 378
 379         case WM8350_LOUT2_VOLUME:
 380                 ucontrol->value.integer.value[0] = out2->left_vol;
 381                 ucontrol->value.integer.value[1] = out2->right_vol;
 382                 return 0;
 383
 384         default:
 385                 break;
 386         }
 387
 388         return snd_soc_get_volsw_2r(kcontrol, ucontrol);
 389 }
 390
 391 /* double control with volume update */
 392 #define SOC_WM8350_DOUBLE_R_TLV(xname, reg_left, reg_right, xshift, xmax, \
 393                                 xinvert, tlv_array) \
 394 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
 395         .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
 396                 SNDRV_CTL_ELEM_ACCESS_READWRITE | \
 397                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
 398         .tlv.p = (tlv_array), \
 399         .info = snd_soc_info_volsw_2r, \
 400         .get = wm8350_get_volsw_2r, .put = wm8350_put_volsw_2r_vu, \
 401         .private_value = (unsigned long)&(struct soc_mixer_control) \
 402                 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
 403                  .rshift = xshift, .max = xmax, .invert = xinvert}, }
 404
 405 static const char *wm8350_deemp[] = { "None", "32kHz", "44.1kHz", "48kHz" };
 406 static const char *wm8350_pol[] = { "Normal", "Inv R", "Inv L", "Inv L & R" };
 407 static const char *wm8350_dacmutem[] = { "Normal", "Soft" };
 408 static const char *wm8350_dacmutes[] = { "Fast", "Slow" };
 409 static const char *wm8350_dacfilter[] = { "Normal", "Sloping" };
 410 static const char *wm8350_adcfilter[] = { "None", "High Pass" };
 411 static const char *wm8350_adchp[] = { "44.1kHz", "8kHz", "16kHz", "32kHz" };
 412 static const char *wm8350_lr[] = { "Left", "Right" };
 413
 414 static const struct soc_enum wm8350_enum[] = {
 415         SOC_ENUM_SINGLE(WM8350_DAC_CONTROL, 4, 4, wm8350_deemp),
 416         SOC_ENUM_SINGLE(WM8350_DAC_CONTROL, 0, 4, wm8350_pol),
 417         SOC_ENUM_SINGLE(WM8350_DAC_MUTE_VOLUME, 14, 2, wm8350_dacmutem),
 418         SOC_ENUM_SINGLE(WM8350_DAC_MUTE_VOLUME, 13, 2, wm8350_dacmutes),
 419         SOC_ENUM_SINGLE(WM8350_DAC_MUTE_VOLUME, 12, 2, wm8350_dacfilter),
 420         SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 15, 2, wm8350_adcfilter),
 421         SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 8, 4, wm8350_adchp),
 422         SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 0, 4, wm8350_pol),
 423         SOC_ENUM_SINGLE(WM8350_INPUT_MIXER_VOLUME, 15, 2, wm8350_lr),
 424 };
 425
 426 static DECLARE_TLV_DB_LINEAR(pre_amp_tlv, -1200, 3525);
 427 static DECLARE_TLV_DB_LINEAR(out_pga_tlv, -5700, 600);
 428 static DECLARE_TLV_DB_SCALE(dac_pcm_tlv, -7163, 36, 1);
 429 static DECLARE_TLV_DB_SCALE(adc_pcm_tlv, -12700, 50, 1);
 430 static DECLARE_TLV_DB_SCALE(out_mix_tlv, -1500, 300, 1);
 431
 432 static const unsigned int capture_sd_tlv[] = {
 433         TLV_DB_RANGE_HEAD(2),
 434         0, 12, TLV_DB_SCALE_ITEM(-3600, 300, 1),
 435         13, 15, TLV_DB_SCALE_ITEM(0, 0, 0),
 436 };
 437
 438 static const struct snd_kcontrol_new wm8350_snd_controls[] = {
 439         SOC_ENUM("Playback Deemphasis", wm8350_enum[0]),
 440         SOC_ENUM("Playback DAC Inversion", wm8350_enum[1]),
 441         SOC_WM8350_DOUBLE_R_TLV("Playback PCM Volume",
 442                                 WM8350_DAC_DIGITAL_VOLUME_L,
 443                                 WM8350_DAC_DIGITAL_VOLUME_R,
 444                                 0, 255, 0, dac_pcm_tlv),
 445         SOC_ENUM("Playback PCM Mute Function", wm8350_enum[2]),
 446         SOC_ENUM("Playback PCM Mute Speed", wm8350_enum[3]),
 447         SOC_ENUM("Playback PCM Filter", wm8350_enum[4]),
 448         SOC_ENUM("Capture PCM Filter", wm8350_enum[5]),
 449         SOC_ENUM("Capture PCM HP Filter", wm8350_enum[6]),
 450         SOC_ENUM("Capture ADC Inversion", wm8350_enum[7]),
 451         SOC_WM8350_DOUBLE_R_TLV("Capture PCM Volume",
 452                                 WM8350_ADC_DIGITAL_VOLUME_L,
 453                                 WM8350_ADC_DIGITAL_VOLUME_R,
 454                                 0, 255, 0, adc_pcm_tlv),
 455         SOC_DOUBLE_TLV("Capture Sidetone Volume",
 456                        WM8350_ADC_DIVIDER,
 457                        8, 4, 15, 1, capture_sd_tlv),
 458         SOC_WM8350_DOUBLE_R_TLV("Capture Volume",
 459                                 WM8350_LEFT_INPUT_VOLUME,
 460                                 WM8350_RIGHT_INPUT_VOLUME,
 461                                 2, 63, 0, pre_amp_tlv),
 462         SOC_DOUBLE_R("Capture ZC Switch",
 463                      WM8350_LEFT_INPUT_VOLUME,
 464                      WM8350_RIGHT_INPUT_VOLUME, 13, 1, 0),
 465         SOC_SINGLE_TLV("Left Input Left Sidetone Volume",
 466                        WM8350_OUTPUT_LEFT_MIXER_VOLUME, 1, 7, 0, out_mix_tlv),
 467         SOC_SINGLE_TLV("Left Input Right Sidetone Volume",
 468                        WM8350_OUTPUT_LEFT_MIXER_VOLUME,
 469                        5, 7, 0, out_mix_tlv),
 470         SOC_SINGLE_TLV("Left Input Bypass Volume",
 471                        WM8350_OUTPUT_LEFT_MIXER_VOLUME,
 472                        9, 7, 0, out_mix_tlv),
 473         SOC_SINGLE_TLV("Right Input Left Sidetone Volume",
 474                        WM8350_OUTPUT_RIGHT_MIXER_VOLUME,
 475                        1, 7, 0, out_mix_tlv),
 476         SOC_SINGLE_TLV("Right Input Right Sidetone Volume",
 477                        WM8350_OUTPUT_RIGHT_MIXER_VOLUME,
 478                        5, 7, 0, out_mix_tlv),
 479         SOC_SINGLE_TLV("Right Input Bypass Volume",
 480                        WM8350_OUTPUT_RIGHT_MIXER_VOLUME,
 481                        13, 7, 0, out_mix_tlv),
 482         SOC_SINGLE("Left Input Mixer +20dB Switch",
 483                    WM8350_INPUT_MIXER_VOLUME_L, 0, 1, 0),
 484         SOC_SINGLE("Right Input Mixer +20dB Switch",
 485                    WM8350_INPUT_MIXER_VOLUME_R, 0, 1, 0),
 486         SOC_SINGLE_TLV("Out4 Capture Volume",
 487                        WM8350_INPUT_MIXER_VOLUME,
 488                        1, 7, 0, out_mix_tlv),
 489         SOC_WM8350_DOUBLE_R_TLV("Out1 Playback Volume",
 490                                 WM8350_LOUT1_VOLUME,
 491                                 WM8350_ROUT1_VOLUME,
 492                                 2, 63, 0, out_pga_tlv),
 493         SOC_DOUBLE_R("Out1 Playback ZC Switch",
 494                      WM8350_LOUT1_VOLUME,
 495                      WM8350_ROUT1_VOLUME, 13, 1, 0),
 496         SOC_WM8350_DOUBLE_R_TLV("Out2 Playback Volume",
 497                                 WM8350_LOUT2_VOLUME,
 498                                 WM8350_ROUT2_VOLUME,
 499                                 2, 63, 0, out_pga_tlv),
 500         SOC_DOUBLE_R("Out2 Playback ZC Switch", WM8350_LOUT2_VOLUME,
 501                      WM8350_ROUT2_VOLUME, 13, 1, 0),
 502         SOC_SINGLE("Out2 Right Invert Switch", WM8350_ROUT2_VOLUME, 10, 1, 0),
 503         SOC_SINGLE_TLV("Out2 Beep Volume", WM8350_BEEP_VOLUME,
 504                        5, 7, 0, out_mix_tlv),
 505
 506         SOC_DOUBLE_R("Out1 Playback Switch",
 507                      WM8350_LOUT1_VOLUME,
 508                      WM8350_ROUT1_VOLUME,
 509                      14, 1, 1),
 510         SOC_DOUBLE_R("Out2 Playback Switch",
 511                      WM8350_LOUT2_VOLUME,
 512                      WM8350_ROUT2_VOLUME,
 513                      14, 1, 1),
 514 };
 515
 516 /*
 517  * DAPM Controls
 518  */
 519
 520 /* Left Playback Mixer */
 521 static const struct snd_kcontrol_new wm8350_left_play_mixer_controls[] = {
 522         SOC_DAPM_SINGLE("Playback Switch",
 523                         WM8350_LEFT_MIXER_CONTROL, 11, 1, 0),
 524         SOC_DAPM_SINGLE("Left Bypass Switch",
 525                         WM8350_LEFT_MIXER_CONTROL, 2, 1, 0),
 526         SOC_DAPM_SINGLE("Right Playback Switch",
 527                         WM8350_LEFT_MIXER_CONTROL, 12, 1, 0),
 528         SOC_DAPM_SINGLE("Left Sidetone Switch",
 529                         WM8350_LEFT_MIXER_CONTROL, 0, 1, 0),
 530         SOC_DAPM_SINGLE("Right Sidetone Switch",
 531                         WM8350_LEFT_MIXER_CONTROL, 1, 1, 0),
 532 };
 533
 534 /* Right Playback Mixer */
 535 static const struct snd_kcontrol_new wm8350_right_play_mixer_controls[] = {
 536         SOC_DAPM_SINGLE("Playback Switch",
 537                         WM8350_RIGHT_MIXER_CONTROL, 12, 1, 0),
 538         SOC_DAPM_SINGLE("Right Bypass Switch",
 539                         WM8350_RIGHT_MIXER_CONTROL, 3, 1, 0),
 540         SOC_DAPM_SINGLE("Left Playback Switch",
 541                         WM8350_RIGHT_MIXER_CONTROL, 11, 1, 0),
 542         SOC_DAPM_SINGLE("Left Sidetone Switch",
 543                         WM8350_RIGHT_MIXER_CONTROL, 0, 1, 0),
 544         SOC_DAPM_SINGLE("Right Sidetone Switch",
 545                         WM8350_RIGHT_MIXER_CONTROL, 1, 1, 0),
 546 };
 547
 548 /* Out4 Mixer */
 549 static const struct snd_kcontrol_new wm8350_out4_mixer_controls[] = {
 550         SOC_DAPM_SINGLE("Right Playback Switch",
 551                         WM8350_OUT4_MIXER_CONTROL, 12, 1, 0),
 552         SOC_DAPM_SINGLE("Left Playback Switch",
 553                         WM8350_OUT4_MIXER_CONTROL, 11, 1, 0),
 554         SOC_DAPM_SINGLE("Right Capture Switch",
 555                         WM8350_OUT4_MIXER_CONTROL, 9, 1, 0),
 556         SOC_DAPM_SINGLE("Out3 Playback Switch",
 557                         WM8350_OUT4_MIXER_CONTROL, 2, 1, 0),
 558         SOC_DAPM_SINGLE("Right Mixer Switch",
 559                         WM8350_OUT4_MIXER_CONTROL, 1, 1, 0),
 560         SOC_DAPM_SINGLE("Left Mixer Switch",
 561                         WM8350_OUT4_MIXER_CONTROL, 0, 1, 0),
 562 };
 563
 564 /* Out3 Mixer */
 565 static const struct snd_kcontrol_new wm8350_out3_mixer_controls[] = {
 566         SOC_DAPM_SINGLE("Left Playback Switch",
 567                         WM8350_OUT3_MIXER_CONTROL, 11, 1, 0),
 568         SOC_DAPM_SINGLE("Left Capture Switch",
 569                         WM8350_OUT3_MIXER_CONTROL, 8, 1, 0),
 570         SOC_DAPM_SINGLE("Out4 Playback Switch",
 571                         WM8350_OUT3_MIXER_CONTROL, 3, 1, 0),
 572         SOC_DAPM_SINGLE("Left Mixer Switch",
 573                         WM8350_OUT3_MIXER_CONTROL, 0, 1, 0),
 574 };
 575
 576 /* Left Input Mixer */
 577 static const struct snd_kcontrol_new wm8350_left_capt_mixer_controls[] = {
 578         SOC_DAPM_SINGLE_TLV("L2 Capture Volume",
 579                             WM8350_INPUT_MIXER_VOLUME_L, 1, 7, 0, out_mix_tlv),
 580         SOC_DAPM_SINGLE_TLV("L3 Capture Volume",
 581                             WM8350_INPUT_MIXER_VOLUME_L, 9, 7, 0, out_mix_tlv),
 582         SOC_DAPM_SINGLE("PGA Capture Switch",
 583                         WM8350_LEFT_INPUT_VOLUME, 14, 1, 0),
 584 };
 585
 586 /* Right Input Mixer */
 587 static const struct snd_kcontrol_new wm8350_right_capt_mixer_controls[] = {
 588         SOC_DAPM_SINGLE_TLV("L2 Capture Volume",
 589                             WM8350_INPUT_MIXER_VOLUME_R, 5, 7, 0, out_mix_tlv),
 590         SOC_DAPM_SINGLE_TLV("L3 Capture Volume",
 591                             WM8350_INPUT_MIXER_VOLUME_R, 13, 7, 0, out_mix_tlv),
 592         SOC_DAPM_SINGLE("PGA Capture Switch",
 593                         WM8350_RIGHT_INPUT_VOLUME, 14, 1, 0),
 594 };
 595
 596 /* Left Mic Mixer */
 597 static const struct snd_kcontrol_new wm8350_left_mic_mixer_controls[] = {
 598         SOC_DAPM_SINGLE("INN Capture Switch", WM8350_INPUT_CONTROL, 1, 1, 0),
 599         SOC_DAPM_SINGLE("INP Capture Switch", WM8350_INPUT_CONTROL, 0, 1, 0),
 600         SOC_DAPM_SINGLE("IN2 Capture Switch", WM8350_INPUT_CONTROL, 2, 1, 0),
 601 };
 602
 603 /* Right Mic Mixer */
 604 static const struct snd_kcontrol_new wm8350_right_mic_mixer_controls[] = {
 605         SOC_DAPM_SINGLE("INN Capture Switch", WM8350_INPUT_CONTROL, 9, 1, 0),
 606         SOC_DAPM_SINGLE("INP Capture Switch", WM8350_INPUT_CONTROL, 8, 1, 0),
 607         SOC_DAPM_SINGLE("IN2 Capture Switch", WM8350_INPUT_CONTROL, 10, 1, 0),
 608 };
 609
 610 /* Beep Switch */
 611 static const struct snd_kcontrol_new wm8350_beep_switch_controls =
 612 SOC_DAPM_SINGLE("Switch", WM8350_BEEP_VOLUME, 15, 1, 1);
 613
 614 /* Out4 Capture Mux */
 615 static const struct snd_kcontrol_new wm8350_out4_capture_controls =
 616 SOC_DAPM_ENUM("Route", wm8350_enum[8]);
 617
 618 static const struct snd_soc_dapm_widget wm8350_dapm_widgets[] = {
 619
 620         SND_SOC_DAPM_PGA("IN3R PGA", WM8350_POWER_MGMT_2, 11, 0, NULL, 0),
 621         SND_SOC_DAPM_PGA("IN3L PGA", WM8350_POWER_MGMT_2, 10, 0, NULL, 0),
 622         SND_SOC_DAPM_PGA_E("Right Out2 PGA", WM8350_POWER_MGMT_3, 3, 0, NULL,
 623                            0, pga_event,
 624                            SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 625         SND_SOC_DAPM_PGA_E("Left Out2 PGA", WM8350_POWER_MGMT_3, 2, 0, NULL, 0,
 626                            pga_event,
 627                            SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 628         SND_SOC_DAPM_PGA_E("Right Out1 PGA", WM8350_POWER_MGMT_3, 1, 0, NULL,
 629                            0, pga_event,
 630                            SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 631         SND_SOC_DAPM_PGA_E("Left Out1 PGA", WM8350_POWER_MGMT_3, 0, 0, NULL, 0,
 632                            pga_event,
 633                            SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 634
 635         SND_SOC_DAPM_MIXER("Right Capture Mixer", WM8350_POWER_MGMT_2,
 636                            7, 0, &wm8350_right_capt_mixer_controls[0],
 637                            ARRAY_SIZE(wm8350_right_capt_mixer_controls)),
 638
 639         SND_SOC_DAPM_MIXER("Left Capture Mixer", WM8350_POWER_MGMT_2,
 640                            6, 0, &wm8350_left_capt_mixer_controls[0],
 641                            ARRAY_SIZE(wm8350_left_capt_mixer_controls)),
 642
 643         SND_SOC_DAPM_MIXER("Out4 Mixer", WM8350_POWER_MGMT_2, 5, 0,
 644                            &wm8350_out4_mixer_controls[0],
 645                            ARRAY_SIZE(wm8350_out4_mixer_controls)),
 646
 647         SND_SOC_DAPM_MIXER("Out3 Mixer", WM8350_POWER_MGMT_2, 4, 0,
 648                            &wm8350_out3_mixer_controls[0],
 649                            ARRAY_SIZE(wm8350_out3_mixer_controls)),
 650
 651         SND_SOC_DAPM_MIXER("Right Playback Mixer", WM8350_POWER_MGMT_2, 1, 0,
 652                            &wm8350_right_play_mixer_controls[0],
 653                            ARRAY_SIZE(wm8350_right_play_mixer_controls)),
 654
 655         SND_SOC_DAPM_MIXER("Left Playback Mixer", WM8350_POWER_MGMT_2, 0, 0,
 656                            &wm8350_left_play_mixer_controls[0],
 657                            ARRAY_SIZE(wm8350_left_play_mixer_controls)),
 658
 659         SND_SOC_DAPM_MIXER("Left Mic Mixer", WM8350_POWER_MGMT_2, 8, 0,
 660                            &wm8350_left_mic_mixer_controls[0],
 661                            ARRAY_SIZE(wm8350_left_mic_mixer_controls)),
 662
 663         SND_SOC_DAPM_MIXER("Right Mic Mixer", WM8350_POWER_MGMT_2, 9, 0,
 664                            &wm8350_right_mic_mixer_controls[0],
 665                            ARRAY_SIZE(wm8350_right_mic_mixer_controls)),
 666
 667         /* virtual mixer for Beep and Out2R */
 668         SND_SOC_DAPM_MIXER("Out2 Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
 669
 670         SND_SOC_DAPM_SWITCH("Beep", WM8350_POWER_MGMT_3, 7, 0,
 671                             &wm8350_beep_switch_controls),
 672
 673         SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
 674                          WM8350_POWER_MGMT_4, 3, 0),
 675         SND_SOC_DAPM_ADC("Left ADC", "Left Capture",
 676                          WM8350_POWER_MGMT_4, 2, 0),
 677         SND_SOC_DAPM_DAC("Right DAC", "Right Playback",
 678                          WM8350_POWER_MGMT_4, 5, 0),
 679         SND_SOC_DAPM_DAC("Left DAC", "Left Playback",
 680                          WM8350_POWER_MGMT_4, 4, 0),
 681
 682         SND_SOC_DAPM_MICBIAS("Mic Bias", WM8350_POWER_MGMT_1, 4, 0),
 683
 684         SND_SOC_DAPM_MUX("Out4 Capture Channel", SND_SOC_NOPM, 0, 0,
 685                          &wm8350_out4_capture_controls),
 686
 687         SND_SOC_DAPM_OUTPUT("OUT1R"),
 688         SND_SOC_DAPM_OUTPUT("OUT1L"),
 689         SND_SOC_DAPM_OUTPUT("OUT2R"),
 690         SND_SOC_DAPM_OUTPUT("OUT2L"),
 691         SND_SOC_DAPM_OUTPUT("OUT3"),
 692         SND_SOC_DAPM_OUTPUT("OUT4"),
 693
 694         SND_SOC_DAPM_INPUT("IN1RN"),
 695         SND_SOC_DAPM_INPUT("IN1RP"),
 696         SND_SOC_DAPM_INPUT("IN2R"),
 697         SND_SOC_DAPM_INPUT("IN1LP"),
 698         SND_SOC_DAPM_INPUT("IN1LN"),
 699         SND_SOC_DAPM_INPUT("IN2L"),
 700         SND_SOC_DAPM_INPUT("IN3R"),
 701         SND_SOC_DAPM_INPUT("IN3L"),
 702 };
 703
 704 static const struct snd_soc_dapm_route audio_map[] = {
 705
 706         /* left playback mixer */
 707         {"Left Playback Mixer", "Playback Switch", "Left DAC"},
 708         {"Left Playback Mixer", "Left Bypass Switch", "IN3L PGA"},
 709         {"Left Playback Mixer", "Right Playback Switch", "Right DAC"},
 710         {"Left Playback Mixer", "Left Sidetone Switch", "Left Mic Mixer"},
 711         {"Left Playback Mixer", "Right Sidetone Switch", "Right Mic Mixer"},
 712
 713         /* right playback mixer */
 714         {"Right Playback Mixer", "Playback Switch", "Right DAC"},
 715         {"Right Playback Mixer", "Right Bypass Switch", "IN3R PGA"},
 716         {"Right Playback Mixer", "Left Playback Switch", "Left DAC"},
 717         {"Right Playback Mixer", "Left Sidetone Switch", "Left Mic Mixer"},
 718         {"Right Playback Mixer", "Right Sidetone Switch", "Right Mic Mixer"},
 719
 720         /* out4 playback mixer */
 721         {"Out4 Mixer", "Right Playback Switch", "Right DAC"},
 722         {"Out4 Mixer", "Left Playback Switch", "Left DAC"},
 723         {"Out4 Mixer", "Right Capture Switch", "Right Capture Mixer"},
 724         {"Out4 Mixer", "Out3 Playback Switch", "Out3 Mixer"},
 725         {"Out4 Mixer", "Right Mixer Switch", "Right Playback Mixer"},
 726         {"Out4 Mixer", "Left Mixer Switch", "Left Playback Mixer"},
 727         {"OUT4", NULL, "Out4 Mixer"},
 728
 729         /* out3 playback mixer */
 730         {"Out3 Mixer", "Left Playback Switch", "Left DAC"},
 731         {"Out3 Mixer", "Left Capture Switch", "Left Capture Mixer"},
 732         {"Out3 Mixer", "Left Mixer Switch", "Left Playback Mixer"},
 733         {"Out3 Mixer", "Out4 Playback Switch", "Out4 Mixer"},
 734         {"OUT3", NULL, "Out3 Mixer"},
 735
 736         /* out2 */
 737         {"Right Out2 PGA", NULL, "Right Playback Mixer"},
 738         {"Left Out2 PGA", NULL, "Left Playback Mixer"},
 739         {"OUT2L", NULL, "Left Out2 PGA"},
 740         {"OUT2R", NULL, "Right Out2 PGA"},
 741
 742         /* out1 */
 743         {"Right Out1 PGA", NULL, "Right Playback Mixer"},
 744         {"Left Out1 PGA", NULL, "Left Playback Mixer"},
 745         {"OUT1L", NULL, "Left Out1 PGA"},
 746         {"OUT1R", NULL, "Right Out1 PGA"},
 747
 748         /* ADCs */
 749         {"Left ADC", NULL, "Left Capture Mixer"},
 750         {"Right ADC", NULL, "Right Capture Mixer"},
 751
 752         /* Left capture mixer */
 753         {"Left Capture Mixer", "L2 Capture Volume", "IN2L"},
 754         {"Left Capture Mixer", "L3 Capture Volume", "IN3L PGA"},
 755         {"Left Capture Mixer", "PGA Capture Switch", "Left Mic Mixer"},
 756         {"Left Capture Mixer", NULL, "Out4 Capture Channel"},
 757
 758         /* Right capture mixer */
 759         {"Right Capture Mixer", "L2 Capture Volume", "IN2R"},
 760         {"Right Capture Mixer", "L3 Capture Volume", "IN3R PGA"},
 761         {"Right Capture Mixer", "PGA Capture Switch", "Right Mic Mixer"},
 762         {"Right Capture Mixer", NULL, "Out4 Capture Channel"},
 763
 764         /* L3 Inputs */
 765         {"IN3L PGA", NULL, "IN3L"},
 766         {"IN3R PGA", NULL, "IN3R"},
 767
 768         /* Left Mic mixer */
 769         {"Left Mic Mixer", "INN Capture Switch", "IN1LN"},
 770         {"Left Mic Mixer", "INP Capture Switch", "IN1LP"},
 771         {"Left Mic Mixer", "IN2 Capture Switch", "IN2L"},
 772
 773         /* Right Mic mixer */
 774         {"Right Mic Mixer", "INN Capture Switch", "IN1RN"},
 775         {"Right Mic Mixer", "INP Capture Switch", "IN1RP"},
 776         {"Right Mic Mixer", "IN2 Capture Switch", "IN2R"},
 777
 778         /* out 4 capture */
 779         {"Out4 Capture Channel", NULL, "Out4 Mixer"},
 780
 781         /* Beep */
 782         {"Beep", NULL, "IN3R PGA"},
 783 };
 784
 785 static int wm8350_add_controls(struct snd_soc_codec *codec)
 786 {
 787         int err, i;
 788
 789         for (i = 0; i < ARRAY_SIZE(wm8350_snd_controls); i++) {
 790                 err = snd_ctl_add(codec->card,
 791                                   snd_soc_cnew(&wm8350_snd_controls[i],
 792                                                codec, NULL));
 793                 if (err < 0)
 794                         return err;
 795         }
 796
 797         return 0;
 798 }
 799
 800 static int wm8350_add_widgets(struct snd_soc_codec *codec)
 801 {
 802         int ret;
 803
 804         ret = snd_soc_dapm_new_controls(codec,
 805                                         wm8350_dapm_widgets,
 806                                         ARRAY_SIZE(wm8350_dapm_widgets));
 807         if (ret != 0) {
 808                 dev_err(codec->dev, "dapm control register failed\n");
 809                 return ret;
 810         }
 811
 812         /* set up audio paths */
 813         ret = snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
 814         if (ret != 0) {
 815                 dev_err(codec->dev, "DAPM route register failed\n");
 816                 return ret;
 817         }
 818
 819         return snd_soc_dapm_new_widgets(codec);
 820 }
 821
 822 static int wm8350_set_dai_sysclk(struct snd_soc_dai *codec_dai,
 823                                  int clk_id, unsigned int freq, int dir)
 824 {
 825         struct snd_soc_codec *codec = codec_dai->codec;
 826         struct wm8350 *wm8350 = codec->control_data;
 827         u16 fll_4;
 828
 829         switch (clk_id) {
 830         case WM8350_MCLK_SEL_MCLK:
 831                 wm8350_clear_bits(wm8350, WM8350_CLOCK_CONTROL_1,
 832                                   WM8350_MCLK_SEL);
 833                 break;
 834         case WM8350_MCLK_SEL_PLL_MCLK:
 835         case WM8350_MCLK_SEL_PLL_DAC:
 836         case WM8350_MCLK_SEL_PLL_ADC:
 837         case WM8350_MCLK_SEL_PLL_32K:
 838                 wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_1,
 839                                 WM8350_MCLK_SEL);
 840                 fll_4 = wm8350_codec_read(codec, WM8350_FLL_CONTROL_4) &
 841                     ~WM8350_FLL_CLK_SRC_MASK;
 842                 wm8350_codec_write(codec, WM8350_FLL_CONTROL_4, fll_4 | clk_id);
 843                 break;
 844         }
 845
 846         /* MCLK direction */
 847         if (dir == WM8350_MCLK_DIR_OUT)
 848                 wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_2,
 849                                 WM8350_MCLK_DIR);
 850         else
 851                 wm8350_clear_bits(wm8350, WM8350_CLOCK_CONTROL_2,
 852                                   WM8350_MCLK_DIR);
 853
 854         return 0;
 855 }
 856
 857 static int wm8350_set_clkdiv(struct snd_soc_dai *codec_dai, int div_id, int div)
 858 {
 859         struct snd_soc_codec *codec = codec_dai->codec;
 860         u16 val;
 861
 862         switch (div_id) {
 863         case WM8350_ADC_CLKDIV:
 864                 val = wm8350_codec_read(codec, WM8350_ADC_DIVIDER) &
 865                     ~WM8350_ADC_CLKDIV_MASK;
 866                 wm8350_codec_write(codec, WM8350_ADC_DIVIDER, val | div);
 867                 break;
 868         case WM8350_DAC_CLKDIV:
 869                 val = wm8350_codec_read(codec, WM8350_DAC_CLOCK_CONTROL) &
 870                     ~WM8350_DAC_CLKDIV_MASK;
 871                 wm8350_codec_write(codec, WM8350_DAC_CLOCK_CONTROL, val | div);
 872                 break;
 873         case WM8350_BCLK_CLKDIV:
 874                 val = wm8350_codec_read(codec, WM8350_CLOCK_CONTROL_1) &
 875                     ~WM8350_BCLK_DIV_MASK;
 876                 wm8350_codec_write(codec, WM8350_CLOCK_CONTROL_1, val | div);
 877                 break;
 878         case WM8350_OPCLK_CLKDIV:
 879                 val = wm8350_codec_read(codec, WM8350_CLOCK_CONTROL_1) &
 880                     ~WM8350_OPCLK_DIV_MASK;
 881                 wm8350_codec_write(codec, WM8350_CLOCK_CONTROL_1, val | div);
 882                 break;
 883         case WM8350_SYS_CLKDIV:
 884                 val = wm8350_codec_read(codec, WM8350_CLOCK_CONTROL_1) &
 885                     ~WM8350_MCLK_DIV_MASK;
 886                 wm8350_codec_write(codec, WM8350_CLOCK_CONTROL_1, val | div);
 887                 break;
 888         case WM8350_DACLR_CLKDIV:
 889                 val = wm8350_codec_read(codec, WM8350_DAC_LR_RATE) &
 890                     ~WM8350_DACLRC_RATE_MASK;
 891                 wm8350_codec_write(codec, WM8350_DAC_LR_RATE, val | div);
 892                 break;
 893         case WM8350_ADCLR_CLKDIV:
 894                 val = wm8350_codec_read(codec, WM8350_ADC_LR_RATE) &
 895                     ~WM8350_ADCLRC_RATE_MASK;
 896                 wm8350_codec_write(codec, WM8350_ADC_LR_RATE, val | div);
 897                 break;
 898         default:
 899                 return -EINVAL;
 900         }
 901
 902         return 0;
 903 }
 904
 905 static int wm8350_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
 906 {
 907         struct snd_soc_codec *codec = codec_dai->codec;
 908         u16 iface = wm8350_codec_read(codec, WM8350_AI_FORMATING) &
 909             ~(WM8350_AIF_BCLK_INV | WM8350_AIF_LRCLK_INV | WM8350_AIF_FMT_MASK);
 910         u16 master = wm8350_codec_read(codec, WM8350_AI_DAC_CONTROL) &
 911             ~WM8350_BCLK_MSTR;
 912         u16 dac_lrc = wm8350_codec_read(codec, WM8350_DAC_LR_RATE) &
 913             ~WM8350_DACLRC_ENA;
 914         u16 adc_lrc = wm8350_codec_read(codec, WM8350_ADC_LR_RATE) &
 915             ~WM8350_ADCLRC_ENA;
 916
 917         /* set master/slave audio interface */
 918         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 919         case SND_SOC_DAIFMT_CBM_CFM:
 920                 master |= WM8350_BCLK_MSTR;
 921                 dac_lrc |= WM8350_DACLRC_ENA;
 922                 adc_lrc |= WM8350_ADCLRC_ENA;
 923                 break;
 924         case SND_SOC_DAIFMT_CBS_CFS:
 925                 break;
 926         default:
 927                 return -EINVAL;
 928         }
 929
 930         /* interface format */
 931         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 932         case SND_SOC_DAIFMT_I2S:
 933                 iface |= 0x2 << 8;
 934                 break;
 935         case SND_SOC_DAIFMT_RIGHT_J:
 936                 break;
 937         case SND_SOC_DAIFMT_LEFT_J:
 938                 iface |= 0x1 << 8;
 939                 break;
 940         case SND_SOC_DAIFMT_DSP_A:
 941                 iface |= 0x3 << 8;
 942                 break;
 943         case SND_SOC_DAIFMT_DSP_B:
 944                 iface |= 0x3 << 8;      /* lg not sure which mode */
 945                 break;
 946         default:
 947                 return -EINVAL;
 948         }
 949
 950         /* clock inversion */
 951         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 952         case SND_SOC_DAIFMT_NB_NF:
 953                 break;
 954         case SND_SOC_DAIFMT_IB_IF:
 955                 iface |= WM8350_AIF_LRCLK_INV | WM8350_AIF_BCLK_INV;
 956                 break;
 957         case SND_SOC_DAIFMT_IB_NF:
 958                 iface |= WM8350_AIF_BCLK_INV;
 959                 break;
 960         case SND_SOC_DAIFMT_NB_IF:
 961                 iface |= WM8350_AIF_LRCLK_INV;
 962                 break;
 963         default:
 964                 return -EINVAL;
 965         }
 966
 967         wm8350_codec_write(codec, WM8350_AI_FORMATING, iface);
 968         wm8350_codec_write(codec, WM8350_AI_DAC_CONTROL, master);
 969         wm8350_codec_write(codec, WM8350_DAC_LR_RATE, dac_lrc);
 970         wm8350_codec_write(codec, WM8350_ADC_LR_RATE, adc_lrc);
 971         return 0;
 972 }
 973
 974 static int wm8350_pcm_trigger(struct snd_pcm_substream *substream,
 975                               int cmd, struct snd_soc_dai *codec_dai)
 976 {
 977         struct snd_soc_codec *codec = codec_dai->codec;
 978         int master = wm8350_codec_cache_read(codec, WM8350_AI_DAC_CONTROL) &
 979             WM8350_BCLK_MSTR;
 980         int enabled = 0;
 981
 982         /* Check that the DACs or ADCs are enabled since they are
 983          * required for LRC in master mode. The DACs or ADCs need a
 984          * valid audio path i.e. pin -> ADC or DAC -> pin before
 985          * the LRC will be enabled in master mode. */
 986         if (!master && cmd != SNDRV_PCM_TRIGGER_START)
 987                 return 0;
 988
 989         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
 990                 enabled = wm8350_codec_cache_read(codec, WM8350_POWER_MGMT_4) &
 991                     (WM8350_ADCR_ENA | WM8350_ADCL_ENA);
 992         } else {
 993                 enabled = wm8350_codec_cache_read(codec, WM8350_POWER_MGMT_4) &
 994                     (WM8350_DACR_ENA | WM8350_DACL_ENA);
 995         }
 996
 997         if (!enabled) {
 998                 dev_err(codec->dev,
 999                        "%s: invalid audio path - no clocks available\n",
1000                        __func__);
1001                 return -EINVAL;
1002         }
1003         return 0;
1004 }
1005
1006 static int wm8350_pcm_hw_params(struct snd_pcm_substream *substream,
1007                                 struct snd_pcm_hw_params *params,
1008                                 struct snd_soc_dai *codec_dai)
1009 {
1010         struct snd_soc_codec *codec = codec_dai->codec;
1011         u16 iface = wm8350_codec_read(codec, WM8350_AI_FORMATING) &
1012             ~WM8350_AIF_WL_MASK;
1013
1014         /* bit size */
1015         switch (params_format(params)) {
1016         case SNDRV_PCM_FORMAT_S16_LE:
1017                 break;
1018         case SNDRV_PCM_FORMAT_S20_3LE:
1019                 iface |= 0x1 << 10;
1020                 break;
1021         case SNDRV_PCM_FORMAT_S24_LE:
1022                 iface |= 0x2 << 10;
1023                 break;
1024         case SNDRV_PCM_FORMAT_S32_LE:
1025                 iface |= 0x3 << 10;
1026                 break;
1027         }
1028
1029         wm8350_codec_write(codec, WM8350_AI_FORMATING, iface);
1030         return 0;
1031 }
1032
1033 static int wm8350_mute(struct snd_soc_dai *dai, int mute)
1034 {
1035         struct snd_soc_codec *codec = dai->codec;
1036         struct wm8350 *wm8350 = codec->control_data;
1037
1038         if (mute)
1039                 wm8350_set_bits(wm8350, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA);
1040         else
1041                 wm8350_clear_bits(wm8350, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA);
1042         return 0;
1043 }
1044
1045 /* FLL divisors */
1046 struct _fll_div {
1047         int div;                /* FLL_OUTDIV */
1048         int n;
1049         int k;
1050         int ratio;              /* FLL_FRATIO */
1051 };
1052
1053 /* The size in bits of the fll divide multiplied by 10
1054  * to allow rounding later */
1055 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1056
1057 static inline int fll_factors(struct _fll_div *fll_div, unsigned int input,
1058                               unsigned int output)
1059 {
1060         u64 Kpart;
1061         unsigned int t1, t2, K, Nmod;
1062
1063         if (output >= 2815250 && output <= 3125000)
1064                 fll_div->div = 0x4;
1065         else if (output >= 5625000 && output <= 6250000)
1066                 fll_div->div = 0x3;
1067         else if (output >= 11250000 && output <= 12500000)
1068                 fll_div->div = 0x2;
1069         else if (output >= 22500000 && output <= 25000000)
1070                 fll_div->div = 0x1;
1071         else {
1072                 printk(KERN_ERR "wm8350: fll freq %d out of range\n", output);
1073                 return -EINVAL;
1074         }
1075
1076         if (input > 48000)
1077                 fll_div->ratio = 1;
1078         else
1079                 fll_div->ratio = 8;
1080
1081         t1 = output * (1 << (fll_div->div + 1));
1082         t2 = input * fll_div->ratio;
1083
1084         fll_div->n = t1 / t2;
1085         Nmod = t1 % t2;
1086
1087         if (Nmod) {
1088                 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1089                 do_div(Kpart, t2);
1090                 K = Kpart & 0xFFFFFFFF;
1091
1092                 /* Check if we need to round */
1093                 if ((K % 10) >= 5)
1094                         K += 5;
1095
1096                 /* Move down to proper range now rounding is done */
1097                 K /= 10;
1098                 fll_div->k = K;
1099         } else
1100                 fll_div->k = 0;
1101
1102         return 0;
1103 }
1104
1105 static int wm8350_set_fll(struct snd_soc_dai *codec_dai,
1106                           int pll_id, unsigned int freq_in,
1107                           unsigned int freq_out)
1108 {
1109         struct snd_soc_codec *codec = codec_dai->codec;
1110         struct wm8350 *wm8350 = codec->control_data;
1111         struct _fll_div fll_div;
1112         int ret = 0;
1113         u16 fll_1, fll_4;
1114
1115         /* power down FLL - we need to do this for reconfiguration */
1116         wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4,
1117                           WM8350_FLL_ENA | WM8350_FLL_OSC_ENA);
1118
1119         if (freq_out == 0 || freq_in == 0)
1120                 return ret;
1121
1122         ret = fll_factors(&fll_div, freq_in, freq_out);
1123         if (ret < 0)
1124                 return ret;
1125         dev_dbg(wm8350->dev,
1126                 "FLL in %d FLL out %d N 0x%x K 0x%x div %d ratio %d",
1127                 freq_in, freq_out, fll_div.n, fll_div.k, fll_div.div,
1128                 fll_div.ratio);
1129
1130         /* set up N.K & dividers */
1131         fll_1 = wm8350_codec_read(codec, WM8350_FLL_CONTROL_1) &
1132             ~(WM8350_FLL_OUTDIV_MASK | WM8350_FLL_RSP_RATE_MASK | 0xc000);
1133         wm8350_codec_write(codec, WM8350_FLL_CONTROL_1,
1134                            fll_1 | (fll_div.div << 8) | 0x50);
1135         wm8350_codec_write(codec, WM8350_FLL_CONTROL_2,
1136                            (fll_div.ratio << 11) | (fll_div.
1137                                                     n & WM8350_FLL_N_MASK));
1138         wm8350_codec_write(codec, WM8350_FLL_CONTROL_3, fll_div.k);
1139         fll_4 = wm8350_codec_read(codec, WM8350_FLL_CONTROL_4) &
1140             ~(WM8350_FLL_FRAC | WM8350_FLL_SLOW_LOCK_REF);
1141         wm8350_codec_write(codec, WM8350_FLL_CONTROL_4,
1142                            fll_4 | (fll_div.k ? WM8350_FLL_FRAC : 0) |
1143                            (fll_div.ratio == 8 ? WM8350_FLL_SLOW_LOCK_REF : 0));
1144
1145         /* power FLL on */
1146         wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_FLL_OSC_ENA);
1147         wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_FLL_ENA);
1148
1149         return 0;
1150 }
1151
1152 static int wm8350_set_bias_level(struct snd_soc_codec *codec,
1153                                  enum snd_soc_bias_level level)
1154 {
1155         struct wm8350 *wm8350 = codec->control_data;
1156         struct wm8350_data *priv = codec->private_data;
1157         struct wm8350_audio_platform_data *platform =
1158                 wm8350->codec.platform_data;
1159         u16 pm1;
1160         int ret;
1161
1162         switch (level) {
1163         case SND_SOC_BIAS_ON:
1164                 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1165                     ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK);
1166                 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1167                                  pm1 | WM8350_VMID_50K |
1168                                  platform->codec_current_on << 14);
1169                 break;
1170
1171         case SND_SOC_BIAS_PREPARE:
1172                 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1);
1173                 pm1 &= ~WM8350_VMID_MASK;
1174                 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1175                                  pm1 | WM8350_VMID_50K);
1176                 break;
1177
1178         case SND_SOC_BIAS_STANDBY:
1179                 if (codec->bias_level == SND_SOC_BIAS_OFF) {
1180                         ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies),
1181                                                     priv->supplies);
1182                         if (ret != 0)
1183                                 return ret;
1184
1185                         /* Enable the system clock */
1186                         wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4,
1187                                         WM8350_SYSCLK_ENA);
1188
1189                         /* mute DAC & outputs */
1190                         wm8350_set_bits(wm8350, WM8350_DAC_MUTE,
1191                                         WM8350_DAC_MUTE_ENA);
1192
1193                         /* discharge cap memory */
1194                         wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1195                                          platform->dis_out1 |
1196                                          (platform->dis_out2 << 2) |
1197                                          (platform->dis_out3 << 4) |
1198                                          (platform->dis_out4 << 6));
1199
1200                         /* wait for discharge */
1201                         schedule_timeout_interruptible(msecs_to_jiffies
1202                                                        (platform->
1203                                                         cap_discharge_msecs));
1204
1205                         /* enable antipop */
1206                         wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1207                                          (platform->vmid_s_curve << 8));
1208
1209                         /* ramp up vmid */
1210                         wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1211                                          (platform->
1212                                           codec_current_charge << 14) |
1213                                          WM8350_VMID_5K | WM8350_VMIDEN |
1214                                          WM8350_VBUFEN);
1215
1216                         /* wait for vmid */
1217                         schedule_timeout_interruptible(msecs_to_jiffies
1218                                                        (platform->
1219                                                         vmid_charge_msecs));
1220
1221                         /* turn on vmid 300k  */
1222                         pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1223                             ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK);
1224                         pm1 |= WM8350_VMID_300K |
1225                                 (platform->codec_current_standby << 14);
1226                         wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1227                                          pm1);
1228
1229
1230                         /* enable analogue bias */
1231                         pm1 |= WM8350_BIASEN;
1232                         wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1);
1233
1234                         /* disable antipop */
1235                         wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 0);
1236
1237                 } else {
1238                         /* turn on vmid 300k and reduce current */
1239                         pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1240                             ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK);
1241                         wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1242                                          pm1 | WM8350_VMID_300K |
1243                                          (platform->
1244                                           codec_current_standby << 14));
1245
1246                 }
1247                 break;
1248
1249         case SND_SOC_BIAS_OFF:
1250
1251                 /* mute DAC & enable outputs */
1252                 wm8350_set_bits(wm8350, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA);
1253
1254                 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_3,
1255                                 WM8350_OUT1L_ENA | WM8350_OUT1R_ENA |
1256                                 WM8350_OUT2L_ENA | WM8350_OUT2R_ENA);
1257
1258                 /* enable anti pop S curve */
1259                 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1260                                  (platform->vmid_s_curve << 8));
1261
1262                 /* turn off vmid  */
1263                 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1264                     ~WM8350_VMIDEN;
1265                 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1);
1266
1267                 /* wait */
1268                 schedule_timeout_interruptible(msecs_to_jiffies
1269                                                (platform->
1270                                                 vmid_discharge_msecs));
1271
1272                 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1273                                  (platform->vmid_s_curve << 8) |
1274                                  platform->dis_out1 |
1275                                  (platform->dis_out2 << 2) |
1276                                  (platform->dis_out3 << 4) |
1277                                  (platform->dis_out4 << 6));
1278
1279                 /* turn off VBuf and drain */
1280                 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1281                     ~(WM8350_VBUFEN | WM8350_VMID_MASK);
1282                 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1283                                  pm1 | WM8350_OUTPUT_DRAIN_EN);
1284
1285                 /* wait */
1286                 schedule_timeout_interruptible(msecs_to_jiffies
1287                                                (platform->drain_msecs));
1288
1289                 pm1 &= ~WM8350_BIASEN;
1290                 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1);
1291
1292                 /* disable anti-pop */
1293                 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 0);
1294
1295                 wm8350_clear_bits(wm8350, WM8350_LOUT1_VOLUME,
1296                                   WM8350_OUT1L_ENA);
1297                 wm8350_clear_bits(wm8350, WM8350_ROUT1_VOLUME,
1298                                   WM8350_OUT1R_ENA);
1299                 wm8350_clear_bits(wm8350, WM8350_LOUT2_VOLUME,
1300                                   WM8350_OUT2L_ENA);
1301                 wm8350_clear_bits(wm8350, WM8350_ROUT2_VOLUME,
1302                                   WM8350_OUT2R_ENA);
1303
1304                 /* disable clock gen */
1305                 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4,
1306                                   WM8350_SYSCLK_ENA);
1307
1308                 regulator_bulk_disable(ARRAY_SIZE(priv->supplies),
1309                                        priv->supplies);
1310                 break;
1311         }
1312         codec->bias_level = level;
1313         return 0;
1314 }
1315
1316 static int wm8350_suspend(struct platform_device *pdev, pm_message_t state)
1317 {
1318         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1319         struct snd_soc_codec *codec = socdev->codec;
1320
1321         wm8350_set_bias_level(codec, SND_SOC_BIAS_OFF);
1322         return 0;
1323 }
1324
1325 static int wm8350_resume(struct platform_device *pdev)
1326 {
1327         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1328         struct snd_soc_codec *codec = socdev->codec;
1329
1330         wm8350_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1331
1332         if (codec->suspend_bias_level == SND_SOC_BIAS_ON)
1333                 wm8350_set_bias_level(codec, SND_SOC_BIAS_ON);
1334
1335         return 0;
1336 }
1337
1338 static void wm8350_hp_jack_handler(struct wm8350 *wm8350, int irq, void *data)
1339 {
1340         struct wm8350_data *priv = data;
1341         u16 reg;
1342         int report;
1343         int mask;
1344         struct wm8350_jack_data *jack = NULL;
1345
1346         switch (irq) {
1347         case WM8350_IRQ_CODEC_JCK_DET_L:
1348                 jack = &priv->hpl;
1349                 mask = WM8350_JACK_L_LVL;
1350                 break;
1351
1352         case WM8350_IRQ_CODEC_JCK_DET_R:
1353                 jack = &priv->hpr;
1354                 mask = WM8350_JACK_R_LVL;
1355                 break;
1356
1357         default:
1358                 BUG();
1359         }
1360
1361         if (!jack->jack) {
1362                 dev_warn(wm8350->dev, "Jack interrupt called with no jack\n");
1363                 return;
1364         }
1365
1366         /* Debounce */
1367         msleep(200);
1368
1369         reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS);
1370         if (reg & mask)
1371                 report = jack->report;
1372         else
1373                 report = 0;
1374
1375         snd_soc_jack_report(jack->jack, report, jack->report);
1376 }
1377
1378 /**
1379  * wm8350_hp_jack_detect - Enable headphone jack detection.
1380  *
1381  * @codec:  WM8350 codec
1382  * @which:  left or right jack detect signal
1383  * @jack:   jack to report detection events on
1384  * @report: value to report
1385  *
1386  * Enables the headphone jack detection of the WM8350.
1387  */
1388 int wm8350_hp_jack_detect(struct snd_soc_codec *codec, enum wm8350_jack which,
1389                           struct snd_soc_jack *jack, int report)
1390 {
1391         struct wm8350_data *priv = codec->private_data;
1392         struct wm8350 *wm8350 = codec->control_data;
1393         int irq;
1394         int ena;
1395
1396         switch (which) {
1397         case WM8350_JDL:
1398                 priv->hpl.jack = jack;
1399                 priv->hpl.report = report;
1400                 irq = WM8350_IRQ_CODEC_JCK_DET_L;
1401                 ena = WM8350_JDL_ENA;
1402                 break;
1403
1404         case WM8350_JDR:
1405                 priv->hpr.jack = jack;
1406                 priv->hpr.report = report;
1407                 irq = WM8350_IRQ_CODEC_JCK_DET_R;
1408                 ena = WM8350_JDR_ENA;
1409                 break;
1410
1411         default:
1412                 return -EINVAL;
1413         }
1414
1415         wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA);
1416         wm8350_set_bits(wm8350, WM8350_JACK_DETECT, ena);
1417
1418         /* Sync status */
1419         wm8350_hp_jack_handler(wm8350, irq, priv);
1420
1421         wm8350_unmask_irq(wm8350, irq);
1422
1423         return 0;
1424 }
1425 EXPORT_SYMBOL_GPL(wm8350_hp_jack_detect);
1426
1427 static struct snd_soc_codec *wm8350_codec;
1428
1429 static int wm8350_probe(struct platform_device *pdev)
1430 {
1431         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1432         struct snd_soc_codec *codec;
1433         struct wm8350 *wm8350;
1434         struct wm8350_data *priv;
1435         int ret;
1436         struct wm8350_output *out1;
1437         struct wm8350_output *out2;
1438
1439         BUG_ON(!wm8350_codec);
1440
1441         socdev->codec = wm8350_codec;
1442         codec = socdev->codec;
1443         wm8350 = codec->control_data;
1444         priv = codec->private_data;
1445
1446         /* Enable the codec */
1447         wm8350_set_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
1448
1449         /* Enable robust clocking mode in ADC */
1450         wm8350_codec_write(codec, WM8350_SECURITY, 0xa7);
1451         wm8350_codec_write(codec, 0xde, 0x13);
1452         wm8350_codec_write(codec, WM8350_SECURITY, 0);
1453
1454         /* read OUT1 & OUT2 volumes */
1455         out1 = &priv->out1;
1456         out2 = &priv->out2;
1457         out1->left_vol = (wm8350_reg_read(wm8350, WM8350_LOUT1_VOLUME) &
1458                           WM8350_OUT1L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
1459         out1->right_vol = (wm8350_reg_read(wm8350, WM8350_ROUT1_VOLUME) &
1460                            WM8350_OUT1R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
1461         out2->left_vol = (wm8350_reg_read(wm8350, WM8350_LOUT2_VOLUME) &
1462                           WM8350_OUT2L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
1463         out2->right_vol = (wm8350_reg_read(wm8350, WM8350_ROUT2_VOLUME) &
1464                            WM8350_OUT2R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
1465         wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME, 0);
1466         wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME, 0);
1467         wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME, 0);
1468         wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME, 0);
1469
1470         /* Latch VU bits & mute */
1471         wm8350_set_bits(wm8350, WM8350_LOUT1_VOLUME,
1472                         WM8350_OUT1_VU | WM8350_OUT1L_MUTE);
1473         wm8350_set_bits(wm8350, WM8350_LOUT2_VOLUME,
1474                         WM8350_OUT2_VU | WM8350_OUT2L_MUTE);
1475         wm8350_set_bits(wm8350, WM8350_ROUT1_VOLUME,
1476                         WM8350_OUT1_VU | WM8350_OUT1R_MUTE);
1477         wm8350_set_bits(wm8350, WM8350_ROUT2_VOLUME,
1478                         WM8350_OUT2_VU | WM8350_OUT2R_MUTE);
1479
1480         wm8350_mask_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L);
1481         wm8350_mask_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R);
1482         wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L,
1483                             wm8350_hp_jack_handler, priv);
1484         wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R,
1485                             wm8350_hp_jack_handler, priv);
1486
1487         ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1488         if (ret < 0) {
1489                 dev_err(&pdev->dev, "failed to create pcms\n");
1490                 return ret;
1491         }
1492
1493         wm8350_add_controls(codec);
1494         wm8350_add_widgets(codec);
1495
1496         wm8350_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1497
1498         ret = snd_soc_init_card(socdev);
1499         if (ret < 0) {
1500                 dev_err(&pdev->dev, "failed to register card\n");
1501                 goto card_err;
1502         }
1503
1504         return 0;
1505
1506 card_err:
1507         snd_soc_free_pcms(socdev);
1508         snd_soc_dapm_free(socdev);
1509         return ret;
1510 }
1511
1512 static int wm8350_remove(struct platform_device *pdev)
1513 {
1514         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1515         struct snd_soc_codec *codec = socdev->codec;
1516         struct wm8350 *wm8350 = codec->control_data;
1517         struct wm8350_data *priv = codec->private_data;
1518         int ret;
1519
1520         wm8350_clear_bits(wm8350, WM8350_JACK_DETECT,
1521                           WM8350_JDL_ENA | WM8350_JDR_ENA);
1522         wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA);
1523
1524         wm8350_mask_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L);
1525         wm8350_mask_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R);
1526         wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L);
1527         wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R);
1528
1529         priv->hpl.jack = NULL;
1530         priv->hpr.jack = NULL;
1531
1532         /* cancel any work waiting to be queued. */
1533         ret = cancel_delayed_work(&codec->delayed_work);
1534
1535         /* if there was any work waiting then we run it now and
1536          * wait for its completion */
1537         if (ret) {
1538                 schedule_delayed_work(&codec->delayed_work, 0);
1539                 flush_scheduled_work();
1540         }
1541
1542         wm8350_set_bias_level(codec, SND_SOC_BIAS_OFF);
1543
1544         wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
1545
1546         return 0;
1547 }
1548
1549 #define WM8350_RATES (SNDRV_PCM_RATE_8000_96000)
1550
1551 #define WM8350_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1552                         SNDRV_PCM_FMTBIT_S20_3LE |\
1553                         SNDRV_PCM_FMTBIT_S24_LE)
1554
1555 struct snd_soc_dai wm8350_dai = {
1556         .name = "WM8350",
1557         .playback = {
1558                 .stream_name = "Playback",
1559                 .channels_min = 1,
1560                 .channels_max = 2,
1561                 .rates = WM8350_RATES,
1562                 .formats = WM8350_FORMATS,
1563         },
1564         .capture = {
1565                  .stream_name = "Capture",
1566                  .channels_min = 1,
1567                  .channels_max = 2,
1568                  .rates = WM8350_RATES,
1569                  .formats = WM8350_FORMATS,
1570          },
1571         .ops = {
1572                  .hw_params = wm8350_pcm_hw_params,
1573                  .digital_mute = wm8350_mute,
1574                  .trigger = wm8350_pcm_trigger,
1575                  .set_fmt = wm8350_set_dai_fmt,
1576                  .set_sysclk = wm8350_set_dai_sysclk,
1577                  .set_pll = wm8350_set_fll,
1578                  .set_clkdiv = wm8350_set_clkdiv,
1579          },
1580 };
1581 EXPORT_SYMBOL_GPL(wm8350_dai);
1582
1583 struct snd_soc_codec_device soc_codec_dev_wm8350 = {
1584         .probe =        wm8350_probe,
1585         .remove =       wm8350_remove,
1586         .suspend =      wm8350_suspend,
1587         .resume =       wm8350_resume,
1588 };
1589 EXPORT_SYMBOL_GPL(soc_codec_dev_wm8350);
1590
1591 static int wm8350_codec_probe(struct platform_device *pdev)
1592 {
1593         struct wm8350 *wm8350 = platform_get_drvdata(pdev);
1594         struct wm8350_data *priv;
1595         struct snd_soc_codec *codec;
1596         int ret, i;
1597
1598         if (wm8350->codec.platform_data == NULL) {
1599                 dev_err(&pdev->dev, "No audio platform data supplied\n");
1600                 return -EINVAL;
1601         }
1602
1603         priv = kzalloc(sizeof(struct wm8350_data), GFP_KERNEL);
1604         if (priv == NULL)
1605                 return -ENOMEM;
1606
1607         for (i = 0; i < ARRAY_SIZE(supply_names); i++)
1608                 priv->supplies[i].supply = supply_names[i];
1609
1610         ret = regulator_bulk_get(wm8350->dev, ARRAY_SIZE(priv->supplies),
1611                                  priv->supplies);
1612         if (ret != 0)
1613                 goto err_priv;
1614
1615         codec = &priv->codec;
1616         wm8350->codec.codec = codec;
1617
1618         wm8350_dai.dev = &pdev->dev;
1619
1620         mutex_init(&codec->mutex);
1621         INIT_LIST_HEAD(&codec->dapm_widgets);
1622         INIT_LIST_HEAD(&codec->dapm_paths);
1623         codec->dev = &pdev->dev;
1624         codec->name = "WM8350";
1625         codec->owner = THIS_MODULE;
1626         codec->read = wm8350_codec_read;
1627         codec->write = wm8350_codec_write;
1628         codec->bias_level = SND_SOC_BIAS_OFF;
1629         codec->set_bias_level = wm8350_set_bias_level;
1630         codec->dai = &wm8350_dai;
1631         codec->num_dai = 1;
1632         codec->reg_cache_size = WM8350_MAX_REGISTER;
1633         codec->private_data = priv;
1634         codec->control_data = wm8350;
1635
1636         /* Put the codec into reset if it wasn't already */
1637         wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
1638
1639         INIT_DELAYED_WORK(&codec->delayed_work, wm8350_pga_work);
1640         ret = snd_soc_register_codec(codec);
1641         if (ret != 0)
1642                 goto err_supply;
1643
1644         wm8350_codec = codec;
1645
1646         ret = snd_soc_register_dai(&wm8350_dai);
1647         if (ret != 0)
1648                 goto err_codec;
1649         return 0;
1650
1651 err_codec:
1652         snd_soc_unregister_codec(codec);
1653 err_supply:
1654         regulator_bulk_free(ARRAY_SIZE(priv->supplies), priv->supplies);
1655 err_priv:
1656         kfree(priv);
1657         wm8350_codec = NULL;
1658         return ret;
1659 }
1660
1661 static int __devexit wm8350_codec_remove(struct platform_device *pdev)
1662 {
1663         struct wm8350 *wm8350 = platform_get_drvdata(pdev);
1664         struct snd_soc_codec *codec = wm8350->codec.codec;
1665         struct wm8350_data *priv = codec->private_data;
1666
1667         snd_soc_unregister_dai(&wm8350_dai);
1668         snd_soc_unregister_codec(codec);
1669         regulator_bulk_free(ARRAY_SIZE(priv->supplies), priv->supplies);
1670         kfree(priv);
1671         wm8350_codec = NULL;
1672         return 0;
1673 }
1674
1675 static struct platform_driver wm8350_codec_driver = {
1676         .driver = {
1677                    .name = "wm8350-codec",
1678                    .owner = THIS_MODULE,
1679                    },
1680         .probe = wm8350_codec_probe,
1681         .remove = __devexit_p(wm8350_codec_remove),
1682 };
1683
1684 static __init int wm8350_init(void)
1685 {
1686         return platform_driver_register(&wm8350_codec_driver);
1687 }
1688 module_init(wm8350_init);
1689
1690 static __exit void wm8350_exit(void)
1691 {
1692         platform_driver_unregister(&wm8350_codec_driver);
1693 }
1694 module_exit(wm8350_exit);
1695
1696 MODULE_DESCRIPTION("ASoC WM8350 driver");
1697 MODULE_AUTHOR("Liam Girdwood");
1698 MODULE_LICENSE("GPL");
1699 MODULE_ALIAS("platform:wm8350-codec");