2 * rt5623.h -- RT5623 ALSA SoC audio driver
4 * Copyright 2011 Realtek Microelectronics
5 * Author: Johnny Hsu <johnnyhsu@realtek.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
15 #define RT5623_RESET 0x00
16 #define RT5623_SPK_OUT_VOL 0x02
17 #define RT5623_HP_OUT_VOL 0x04
18 #define RT5623_MONO_AUX_OUT_VOL 0x06
19 #define RT5623_AUXIN_VOL 0x08
20 #define RT5623_LINE_IN_VOL 0x0a
21 #define RT5623_STEREO_DAC_VOL 0x0c
22 #define RT5623_MIC_VOL 0x0e
23 #define RT5623_MIC_ROUTING_CTRL 0x10
24 #define RT5623_ADC_REC_GAIN 0x12
25 #define RT5623_ADC_REC_MIXER 0x14
26 #define RT5623_SOFT_VOL_CTRL_TIME 0x16
27 #define RT5623_OUTPUT_MIXER_CTRL 0x1c
28 #define RT5623_MIC_CTRL 0x22
29 #define RT5623_AUDIO_INTERFACE 0x34
30 #define RT5623_STEREO_AD_DA_CLK_CTRL 0x36
31 #define RT5623_COMPANDING_CTRL 0x38
32 #define RT5623_PWR_MANAG_ADD1 0x3a
33 #define RT5623_PWR_MANAG_ADD2 0x3c
34 #define RT5623_PWR_MANAG_ADD3 0x3e
35 #define RT5623_ADD_CTRL_REG 0x40
36 #define RT5623_GLOBAL_CLK_CTRL_REG 0x42
37 #define RT5623_PLL_CTRL 0x44
38 #define RT5623_GPIO_OUTPUT_PIN_CTRL 0x4a
39 #define RT5623_GPIO_PIN_CONFIG 0x4c
40 #define RT5623_GPIO_PIN_POLARITY 0x4e
41 #define RT5623_GPIO_PIN_STICKY 0x50
42 #define RT5623_GPIO_PIN_WAKEUP 0x52
43 #define RT5623_GPIO_PIN_STATUS 0x54
44 #define RT5623_GPIO_PIN_SHARING 0x56
45 #define RT5623_OVER_TEMP_CURR_STATUS 0x58
46 #define RT5623_JACK_DET_CTRL 0x5a
47 #define RT5623_MISC_CTRL 0x5e
48 #define RT5623_PSEDUEO_SPATIAL_CTRL 0x60
49 #define RT5623_EQ_CTRL 0x62
50 #define RT5623_EQ_MODE_ENABLE 0x66
51 #define RT5623_AVC_CTRL 0x68
52 #define RT5623_HID_CTRL_INDEX 0x6a
53 #define RT5623_HID_CTRL_DATA 0x6c
54 #define RT5623_VENDOR_ID1 0x7c
55 #define RT5623_VENDOR_ID2 0x7e
57 /* global definition */
58 #define RT5623_L_MUTE (0x1 << 15)
59 #define RT5623_L_MUTE_SFT 15
60 #define RT5623_L_ZC (0x1 << 14)
61 #define RT5623_L_SM (0x1 << 13)
62 #define RT5623_L_VOL_MASK (0x1f << 8)
63 #define RT5623_L_VOL_SFT 8
64 #define RT5623_ADCL_VOL_SFT 7
65 #define RT5623_R_MUTE (0x1 << 7)
66 #define RT5623_R_MUTE_SFT 7
67 #define RT5623_R_ZC (0x1 << 6)
68 #define RT5623_R_VOL_MASK (0x1f)
69 #define RT5623_R_VOL_SFT 0
70 #define RT5623_M_HPMIX (0x1 << 15)
71 #define RT5623_M_SPKMIX (0x1 << 14)
72 #define RT5623_M_MONOMIX (0x1 << 13)
73 #define RT5623_SPK_CLASS_AB 0
74 #define RT5623_SPK_CLASS_D 1
76 /* AUXIN Volume (0x08) */
77 #define RT5623_M_AXI_TO_HPM (0x1 << 15)
78 #define RT5623_M_AXI_TO_HPM_SFT 15
79 #define RT5623_M_AXI_TO_SPKM (0x1 << 14)
80 #define RT5623_M_AXI_TO_SPKM_SFT 14
81 #define RT5623_M_AXI_TO_MOM (0x1 << 13)
82 #define RT5623_M_AXI_TO_MOM_SFT 13
84 /* LINE_IN Volume (0x0a) */
85 #define RT5623_M_LINEIN_TO_HPM (0x1 << 15)
86 #define RT5623_M_LINEIN_TO_HPM_SFT 15
87 #define RT5623_M_LINEIN_TO_SPKM (0x1 << 14)
88 #define RT5623_M_LINEIN_TO_SPKM_SFT 14
89 #define RT5623_M_LINEIN_TO_MOM (0x1 << 13)
90 #define RT5623_M_LINEIN_TO_MOM_SFT 13
92 /* Stereo DAC Volume (0x0c) */
93 #define RT5623_M_DAC_TO_HPM (0x1 << 15)
94 #define RT5623_M_DAC_TO_HPM_SFT 15
95 #define RT5623_M_DAC_TO_SPKM (0x1 << 14)
96 #define RT5623_M_DAC_TO_SPKM_SFT 14
97 #define RT5623_M_DAC_TO_MOM (0x1 << 13)
98 #define RT5623_M_DAC_TO_MOM_SFT 13
100 /* Mic Routing Control(0x10) */
101 #define RT5623_M_MIC1_TO_HP_MIXER (0x1 << 15)
102 #define RT5623_M_MIC1_TO_HP_MIXER_SFT 15
103 #define RT5623_M_MIC1_TO_SPK_MIXER (0x1 << 14)
104 #define RT5623_M_MIC1_TO_SPK_MIXER_SFT 14
105 #define RT5623_M_MIC1_TO_MONO_MIXER (0x1 << 13)
106 #define RT5623_M_MIC1_TO_MONO_MIXER_SFT 13
107 #define RT5623_MIC1_DIFF_INPUT_CTRL (0x1 << 12)
108 #define RT5623_MIC1_DIFF_INPUT_CTRL_SFT 12
109 #define RT5623_M_MIC2_TO_HP_MIXER (0x1 << 7)
110 #define RT5623_M_MIC2_TO_HP_MIXER_SFT 7
111 #define RT5623_M_MIC2_TO_SPK_MIXER (0x1 << 6)
112 #define RT5623_M_MIC2_TO_SPK_MIXER_SFT 6
113 #define RT5623_M_MIC2_TO_MONO_MIXER (0x1 << 5)
114 #define RT5623_M_MIC2_TO_MONO_MIXER_SFT 5
115 #define RT5623_MIC2_DIFF_INPUT_CTRL (0x1 << 4)
116 #define RT5623_MIC2_DIFF_INPUT_CTRL_SFT 4
118 /* ADC Record Gain (0x12) */
119 #define RT5623_M_ADC_L_TO_HP_MIXER (0x1 << 15)
120 #define RT5623_M_ADC_L_TO_HP_MIXER_SFT 15
121 #define RT5623_M_ADC_R_TO_HP_MIXER (0x1 << 14)
122 #define RT5623_M_ADC_R_TO_HP_MIXER_SFT 14
123 #define RT5623_M_ADC_L_TO_MONO_MIXER (0x1 << 13)
124 #define RT5623_M_ADC_L_TO_MONO_MIXER_SFT 13
125 #define RT5623_M_ADC_R_TO_MONO_MIXER (0x1 << 12)
126 #define RT5623_M_ADC_R_TO_MONO_MIXER_SFT 12
127 #define RT5623_ADC_L_GAIN_MASK (0x1f << 7)
128 #define RT5623_ADC_L_ZC_DET (0x1 << 6)
129 #define RT5623_ADC_R_ZC_DET (0x1 << 5)
130 #define RT5623_ADC_R_GAIN_MASK (0x1f << 0)
132 /* ADC Input Mixer Control (0x14) */
133 #define RT5623_M_MIC1_TO_ADC_L_MIXER (0x1 << 14)
134 #define RT5623_M_MIC1_TO_ADC_L_MIXER_SFT 14
135 #define RT5623_M_MIC2_TO_ADC_L_MIXER (0x1 << 13)
136 #define RT5623_M_MIC2_TO_ADC_L_MIXER_SFT 13
137 #define RT5623_M_LINEIN_L_TO_ADC_L_MIXER (0x1 << 12)
138 #define RT5623_M_LINEIN_L_TO_ADC_L_MIXER_SFT 12
139 #define RT5623_M_AUXIN_L_TO_ADC_L_MIXER (0x1 << 11)
140 #define RT5623_M_AUXIN_L_TO_ADC_L_MIXER_SFT 11
141 #define RT5623_M_HPMIXER_L_TO_ADC_L_MIXER (0x1 << 10)
142 #define RT5623_M_HPMIXER_L_TO_ADC_L_MIXER_SFT 10
143 #define RT5623_M_SPKMIXER_L_TO_ADC_L_MIXER (0x1 << 9)
144 #define RT5623_M_SPKMIXER_L_TO_ADC_L_MIXER_SFT 9
145 #define RT5623_M_MONOMIXER_L_TO_ADC_L_MIXER (0x1 << 8)
146 #define RT5623_M_MONOMIXER_L_TO_ADC_L_MIXER_SFT 8
147 #define RT5623_M_MIC1_TO_ADC_R_MIXER (0x1 << 6)
148 #define RT5623_M_MIC1_TO_ADC_R_MIXER_SFT 6
149 #define RT5623_M_MIC2_TO_ADC_R_MIXER (0x1 << 5)
150 #define RT5623_M_MIC2_TO_ADC_R_MIXER_SFT 5
151 #define RT5623_M_LINEIN_R_TO_ADC_R_MIXER (0x1 << 4)
152 #define RT5623_M_LINEIN_R_TO_ADC_R_MIXER_SFT 4
153 #define RT5623_M_AUXIN_R_TO_ADC_R_MIXER (0x1 << 3)
154 #define RT5623_M_AUXIN_R_TO_ADC_R_MIXER_SFT 3
155 #define RT5623_M_HPMIXER_R_TO_ADC_R_MIXER (0x1 << 2)
156 #define RT5623_M_HPMIXER_R_TO_ADC_R_MIXER_SFT 2
157 #define RT5623_M_SPKMIXER_R_TO_ADC_R_MIXER (0x1 << 1)
158 #define RT5623_M_SPKMIXER_R_TO_ADC_R_MIXER_SFT 1
159 #define RT5623_M_MONOMIXER_R_TO_ADC_R_MIXER (0x1 << 0)
160 #define RT5623_M_MONOMIXER_R_TO_ADC_R_MIXER_SFT 0
162 /* Output Mixer Control(0x1c) */
163 #define RT5623_SPKOUT_N_SOUR_MASK (0x3 << 14)
164 #define RT5623_SPKOUT_N_SOUR_SFT 14
165 #define RT5623_SPKOUT_N_SOUR_LN (0x2 << 14)
166 #define RT5623_SPKOUT_N_SOUR_RP (0x1 << 14)
167 #define RT5623_SPKOUT_N_SOUR_RN (0x0 << 14)
168 #define RT5623_SPK_OUTPUT_CLASS_MASK (0x1 << 13)
169 #define RT5623_SPK_OUTPUT_CLASS_SFT 13
170 #define RT5623_SPK_OUTPUT_CLASS_AB (0x0 << 13)
171 #define RT5623_SPK_OUTPUT_CLASS_D (0x1 << 13)
172 #define RT5623_SPK_CLASS_AB_S_AMP (0x0 << 12)
173 #define RT5623_SPK_CALSS_AB_W_AMP (0x1 << 12)
174 #define RT5623_SPKOUT_INPUT_SEL_MASK (0x3 << 10)
175 #define RT5623_SPKOUT_INPUT_SEL_SFT 10
176 #define RT5623_SPKOUT_INPUT_SEL_MONOMIXER (0x3 << 10)
177 #define RT5623_SPKOUT_INPUT_SEL_SPKMIXER (0x2 << 10)
178 #define RT5623_SPKOUT_INPUT_SEL_HPMIXER (0x1 << 10)
179 #define RT5623_SPKOUT_INPUT_SEL_VMID (0x0 << 10)
180 #define RT5623_HPL_INPUT_SEL_HPLMIXER_MASK (0x1 << 9)
181 #define RT5623_HPL_INPUT_SEL_HPLMIXER_SFT 9
182 #define RT5623_HPL_INPUT_SEL_HPLMIXER (0x1 << 9)
183 #define RT5623_HPR_INPUT_SEL_HPRMIXER_MASK (0x1 << 8)
184 #define RT5623_HPR_INPUT_SEL_HPRMIXER_SFT 8
185 #define RT5623_HPR_INPUT_SEL_HPRMIXER (0x1 << 8)
186 #define RT5623_MONO_AUX_INPUT_SEL_MASK (0x3 << 6)
187 #define RT5623_MONO_AUX_INPUT_SEL_SFT 6
188 #define RT5623_MONO_AUX_INPUT_SEL_MONO (0x3 << 6)
189 #define RT5623_MONO_AUX_INPUT_SEL_SPK (0x2 << 6)
190 #define RT5623_MONO_AUX_INPUT_SEL_HP (0x1 << 6)
191 #define RT5623_MONO_AUX_INPUT_SEL_VMID (0x0 << 6)
193 /* Micphone Control define(0x22) */
194 #define RT5623_MIC1 1
195 #define RT5623_MIC2 2
196 #define RT5623_MIC_BIAS_90_PRECNET_AVDD 1
197 #define RT5623_MIC_BIAS_75_PRECNET_AVDD 2
198 #define RT5623_MIC1_BOOST_CTRL_MASK (0x3 << 10)
199 #define RT5623_MIC1_BOOST_CTRL_SFT 10
200 #define RT5623_MIC1_BOOST_CTRL_BYPASS 0x0 << 10)
201 #define RT5623_MIC1_BOOST_CTRL_20DB (0x1 << 10)
202 #define RT5623_MIC1_BOOST_CTRL_30DB (0x2 << 10)
203 #define RT5623_MIC1_BOOST_CTRL_40DB (0x3 << 10)
204 #define RT5623_MIC2_BOOST_CTRL_MASK (0x3 << 8)
205 #define RT5623_MIC2_BOOST_CTRL_SFT 8
206 #define RT5623_MIC2_BOOST_CTRL_BYPASS (0x0 << 8)
207 #define RT5623_MIC2_BOOST_CTRL_20DB (0x1 << 8)
208 #define RT5623_MIC2_BOOST_CTRL_30DB (0x2 << 8)
209 #define RT5623_MIC2_BOOST_CTRL_40DB (0x3 << 8)
210 #define RT5623_MICBIAS_VOLT_CTRL_MASK (0x1 << 5)
211 #define RT5623_MICBIAS_VOLT_CTRL_90P (0x0 << 5)
212 #define RT5623_MICBIAS_VOLT_CTRL_75P (0x1 << 5)
213 #define RT5623_MICBIAS_SHORT_CURR_DET_MASK (0x3)
214 #define RT5623_MICBIAS_SHORT_CURR_DET_600UA (0x0)
215 #define RT5623_MICBIAS_SHORT_CURR_DET_1200UA (0x1)
216 #define RT5623_MICBIAS_SHORT_CURR_DET_1800UA (0x2)
218 /* Audio Interface (0x34) */
219 #define RT5623_SDP_MASTER_MODE (0x0 << 15)
220 #define RT5623_SDP_SLAVE_MODE (0x1 << 15)
221 #define RT5623_I2S_PCM_MODE (0x1 << 14)
222 #define RT5623_MAIN_I2S_BCLK_POL_CTRL (0x1 << 7)
223 /* 0:ADC data appear at left phase of LRCK
224 * 1:ADC data appear at right phase of LRCK
226 #define RT5623_ADC_DATA_L_R_SWAP (0x1 << 5)
227 /* 0:DAC data appear at left phase of LRCK
228 * 1:DAC data appear at right phase of LRCK
230 #define RT5623_DAC_DATA_L_R_SWAP (0x1 << 4)
231 #define RT5623_I2S_DL_MASK (0x3 << 2)
232 #define RT5623_I2S_DL_16 (0x0 << 2)
233 #define RT5623_I2S_DL_20 (0x1 << 2)
234 #define RT5623_I2S_DL_24 (0x2 << 2)
235 #define RT5623_I2S_DL_32 (0x3 << 2)
236 #define RT5623_I2S_DF_MASK (0x3)
237 #define RT5623_I2S_DF_I2S (0x0)
238 #define RT5623_I2S_DF_RIGHT (0x1)
239 #define RT5623_I2S_DF_LEFT (0x2)
240 #define RT5623_I2S_DF_PCM (0x3)
242 /* Stereo AD/DA Clock Control(0x36h) */
243 #define RT5623_I2S_PRE_DIV_MASK (0x7 << 12)
244 #define RT5623_I2S_PRE_DIV_1 (0x0 << 12)
245 #define RT5623_I2S_PRE_DIV_2 (0x1 << 12)
246 #define RT5623_I2S_PRE_DIV_4 (0x2 << 12)
247 #define RT5623_I2S_PRE_DIV_8 (0x3 << 12)
248 #define RT5623_I2S_PRE_DIV_16 (0x4 << 12)
249 #define RT5623_I2S_PRE_DIV_32 (0x5 << 12)
250 #define RT5623_I2S_SCLK_DIV_MASK (0x7 << 9)
251 #define RT5623_I2S_SCLK_DIV_1 (0x0 << 9)
252 #define RT5623_I2S_SCLK_DIV_2 (0x1 << 9)
253 #define RT5623_I2S_SCLK_DIV_3 (0x2 << 9)
254 #define RT5623_I2S_SCLK_DIV_4 (0x3 << 9)
255 #define RT5623_I2S_SCLK_DIV_6 (0x4 << 9)
256 #define RT5623_I2S_SCLK_DIV_8 (0x5 << 9)
257 #define RT5623_I2S_SCLK_DIV_12 (0x6 << 9)
258 #define RT5623_I2S_SCLK_DIV_16 (0x7 << 9)
259 #define RT5623_I2S_WCLK_DIV_PRE_MASK (0xF << 5)
260 #define RT5623_I2S_WCLK_PRE_DIV_1 (0x0 << 5)
261 #define RT5623_I2S_WCLK_PRE_DIV_2 (0x1 << 5)
262 #define RT5623_I2S_WCLK_PRE_DIV_3 (0x2 << 5)
263 #define RT5623_I2S_WCLK_PRE_DIV_4 (0x3 << 5)
264 #define RT5623_I2S_WCLK_PRE_DIV_5 (0x4 << 5)
265 #define RT5623_I2S_WCLK_PRE_DIV_6 (0x5 << 5)
266 #define RT5623_I2S_WCLK_PRE_DIV_7 (0x6 << 5)
267 #define RT5623_I2S_WCLK_PRE_DIV_8 (0x7 << 5)
268 #define RT5623_I2S_WCLK_DIV_MASK (0x7 << 2)
269 #define RT5623_I2S_WCLK_DIV_2 (0x0 << 2)
270 #define RT5623_I2S_WCLK_DIV_4 (0x1 << 2)
271 #define RT5623_I2S_WCLK_DIV_8 (0x2 << 2)
272 #define RT5623_I2S_WCLK_DIV_16 (0x3 << 2)
273 #define RT5623_I2S_WCLK_DIV_32 (0x4 << 2)
274 #define RT5623_ADDA_FILTER_CLK_SEL_256FS (0 << 1)
275 #define RT5623_ADDA_FILTER_CLK_SEL_384FS (1 << 1)
276 #define RT5623_ADDA_OSR_SEL_64FS (0)
277 #define RT5623_ADDA_OSR_SEL_128FS (1)
279 /* Power managment addition 1 (0x3a) */
280 #define RT5623_PWR_MAIN_I2S_EN (0x1 << 15)
281 #define RT5623_PWR_MAIN_I2S_EN_BIT 15
282 #define RT5623_PWR_ZC_DET_PD_EN (0x1 << 14)
283 #define RT5623_PWR_ZC_DET_PD_EN_BIT 14
284 #define RT5623_PWR_MIC1_BIAS_EN (0x1 << 11)
285 #define RT5623_PWR_MIC1_BIAS_EN_BIT 11
286 #define RT5623_PWR_SHORT_CURR_DET_EN (0x1 << 10)
287 #define RT5623_PWR_SHORT_CURR_DET_EN_BIT 10
288 #define RT5623_PWR_SOFTGEN_EN (0x1 << 8)
289 #define RT5623_PWR_SOFTGEN_EN_BIT 8
290 #define RT5623_PWR_DEPOP_BUF_HP (0x1 << 6)
291 #define RT5623_PWR_DEPOP_BUF_HP_BIT 6
292 #define RT5623_PWR_HP_OUT_AMP (0x1 << 5)
293 #define RT5623_PWR_HP_OUT_AMP_BIT 5
294 #define RT5623_PWR_HP_OUT_ENH_AMP (0x1 << 4)
295 #define RT5623_PWR_HP_OUT_ENH_AMP_BIT 4
296 #define RT5623_PWR_DEPOP_BUF_AUX (0x1 << 2)
297 #define RT5623_PWR_DEPOP_BUF_AUX_BIT 2
298 #define RT5623_PWR_AUX_OUT_AMP (0x1 << 1)
299 #define RT5623_PWR_AUX_OUT_AMP_BIT 1
300 #define RT5623_PWR_AUX_OUT_ENH_AMP (0x1)
301 #define RT5623_PWR_AUX_OUT_ENH_AMP_BIT 0
303 /* Power managment addition 2 (0x3c) */
304 #define RT5623_PWR_CLASS_AB (0x1 << 15)
305 #define RT5623_PWR_CLASS_AB_BIT 15
306 #define RT5623_PWR_CLASS_D (0x1 << 14)
307 #define RT5623_PWR_CLASS_D_BIT 14
308 #define RT5623_PWR_VREF (0x1 << 13)
309 #define RT5623_PWR_VREF_BIT 13
310 #define RT5623_PWR_PLL (0x1 << 12)
311 #define RT5623_PWR_PLL_BIT 12
312 #define RT5623_PWR_DAC_REF_CIR (0x1 << 10)
313 #define RT5623_PWR_DAC_REF_CIR_BIT 10
314 #define RT5623_PWR_L_DAC_CLK (0x1 << 9)
315 #define RT5623_PWR_L_DAC_CLK_BIT 9
316 #define RT5623_PWR_R_DAC_CLK (0x1 << 8)
317 #define RT5623_PWR_R_DAC_CLK_BIT 8
318 #define RT5623_PWR_L_ADC_CLK_GAIN (0x1 << 7)
319 #define RT5623_PWR_L_ADC_CLK_GAIN_BIT 7
320 #define RT5623_PWR_R_ADC_CLK_GAIN (0x1 << 6)
321 #define RT5623_PWR_R_ADC_CLK_GAIN_BIT 6
322 #define RT5623_PWR_L_HP_MIXER (0x1 << 5)
323 #define RT5623_PWR_L_HP_MIXER_BIT 5
324 #define RT5623_PWR_R_HP_MIXER (0x1 << 4)
325 #define RT5623_PWR_R_HP_MIXER_BIT 4
326 #define RT5623_PWR_SPK_MIXER (0x1 << 3)
327 #define RT5623_PWR_SPK_MIXER_BIT 3
328 #define RT5623_PWR_MONO_MIXER (0x1 << 2)
329 #define RT5623_PWR_MONO_MIXER_BIT 2
330 #define RT5623_PWR_L_ADC_REC_MIXER (0x1 << 1)
331 #define RT5623_PWR_L_ADC_REC_MIXER_BIT 1
332 #define RT5623_PWR_R_ADC_REC_MIXER (0x1)
333 #define RT5623_PWR_R_ADC_REC_MIXER_BIT 0
335 /* Power managment addition 3 (0x3e) */
336 #define RT5623_PWR_MAIN_BIAS (0x1 << 15)
337 #define RT5623_PWR_MAIN_BIAS_BIT 15
338 #define RT5623_PWR_AUXOUT_L_VOL_AMP (0x1 << 14)
339 #define RT5623_PWR_AUXOUT_L_VOL_AMP_BIT 14
340 #define RT5623_PWR_AUXOUT_R_VOL_AMP (0x1 << 13)
341 #define RT5623_PWR_AUXOUT_R_VOL_AMP_BIT 13
342 #define RT5623_PWR_SPK_OUT (0x1 << 12)
343 #define RT5623_PWR_SPK_OUT_BIT 12
344 #define RT5623_PWR_HP_L_OUT_VOL (0x1 << 10)
345 #define RT5623_PWR_HP_L_OUT_VOL_BIT 10
346 #define RT5623_PWR_HP_R_OUT_VOL (0x1 << 9)
347 #define RT5623_PWR_HP_R_OUT_VOL_BIT 9
348 #define RT5623_PWR_LINEIN_L_VOL (0x1 << 7)
349 #define RT5623_PWR_LINEIN_L_VOL_BIT 7
350 #define RT5623_PWR_LINEIN_R_VOL (0x1 << 6)
351 #define RT5623_PWR_LINEIN_R_VOL_BIT 6
352 #define RT5623_PWR_AUXIN_L_VOL (0x1 << 5)
353 #define RT5623_PWR_AUXIN_L_VOL_BIT 5
354 #define RT5623_PWR_AUXIN_R_VOL (0x1 << 4)
355 #define RT5623_PWR_AUXIN_R_VOL_BIT 4
356 #define RT5623_PWR_MIC1_FUN_CTRL (0x1 << 3)
357 #define RT5623_PWR_MIC1_FUN_CTRL_BIT 3
358 #define RT5623_PWR_MIC2_FUN_CTRL (0x1 << 2)
359 #define RT5623_PWR_MIC2_FUN_CTRL_BIT 2
360 #define RT5623_PWR_MIC1_BOOST_MIXER (0x1 << 1)
361 #define RT5623_PWR_MIC1_BOOST_MIXER_BIT 1
362 #define RT5623_PWR_MIC2_BOOST_MIXER (0x1)
363 #define RT5623_PWR_MIC2_BOOST_MIXER_BIT 0
365 /* Additional Control Register (0x40) */
366 #define RT5623_AUXOUT_SEL_DIFF (0x1 << 15)
367 #define RT5623_AUXOUT_SEL_SE (0x1 << 15)
368 #define RT5623_SPK_AB_AMP_CTRL_MASK (0x7 << 12)
369 #define RT5623_SPK_AB_AMP_CTRL_RATIO_225 (0x0 << 12)
370 #define RT5623_SPK_AB_AMP_CTRL_RATIO_200 (0x1 << 12)
371 #define RT5623_SPK_AB_AMP_CTRL_RATIO_175 (0x2 << 12)
372 #define RT5623_SPK_AB_AMP_CTRL_RATIO_150 (0x3 << 12)
373 #define RT5623_SPK_AB_AMP_CTRL_RATIO_125 (0x4 << 12)
374 #define RT5623_SPK_AB_AMP_CTRL_RATIO_100 (0x5 << 12)
375 #define RT5623_SPK_D_AMP_CTRL_MASK (0x3 << 10)
376 #define RT5623_SPK_D_AMP_CTRL_RATIO_175 (0x0 << 10)
377 #define RT5623_SPK_D_AMP_CTRL_RATIO_150 (0x1 << 10)
378 #define RT5623_SPK_D_AMP_CTRL_RATIO_125 (0x2 << 10)
379 #define RT5623_SPK_D_AMP_CTRL_RATIO_100 (0x3 << 10)
380 #define RT5623_STEREO_DAC_HI_PASS_FILTER_EN (0x1 << 9)
381 #define RT5623_STEREO_ADC_HI_PASS_FILTER_EN (0x1 << 8)
382 #define RT5623_DIG_VOL_BOOST_MASK (0x3 << 4)
383 #define RT5623_DIG_VOL_BOOST_0DB (0x0 << 4)
384 #define RT5623_DIG_VOL_BOOST_6DB (0x1 << 4)
385 #define RT5623_DIG_VOL_BOOST_12DB (0x2 << 4)
386 #define RT5623_DIG_VOL_BOOST_18DB (0x3 << 4)
388 /* Global Clock Control Register (0x42) */
389 #define RT5623_SYSCLK_SOUR_SEL_MASK (0x1 << 15)
390 #define RT5623_SYSCLK_SOUR_SEL_MCLK (0x0 << 15)
391 #define RT5623_SYSCLK_SOUR_SEL_PLL (0x1 << 15)
392 #define RT5623_PLLCLK_SOUR_SEL_MCLK (0x0 << 14)
393 #define RT5623_PLLCLK_SOUR_SEL_BITCLK (0x1 << 14)
394 #define RT5623_PLLCLK_DIV_RATIO_MASK (0x3 << 1)
395 #define RT5623_PLLCLK_DIV_RATIO_DIV1 (0x0 << 1)
396 #define RT5623_PLLCLK_DIV_RATIO_DIV2 (0x1 << 1)
397 #define RT5623_PLLCLK_DIV_RATIO_DIV4 (0x2 << 1)
398 #define RT5623_PLLCLK_DIV_RATIO_DIV8 (0x3 << 1)
399 #define PLLCLK_PRE_DIV1 (0x0)
400 #define PLLCLK_PRE_DIV2 (0x1)
402 /* GPIO Pin Configuration (0x4c) */
403 #define RT5623_GPIO_PIN_MASK (0x1 << 1)
404 #define RT5623_GPIO_PIN_SET_INPUT (0x1 << 1)
405 #define RT5623_GPIO_PIN_SET_OUTPUT (0x0 << 1)
407 /* Pin Sharing (0x56) */
408 #define RT5623_LINEIN_L_PIN_SHARING (0x1 << 15)
409 #define RT5623_LINEIN_L_PIN_AS_LINEIN_L (0x0 << 15)
410 #define RT5623_LINEIN_L_PIN_AS_JD1 (0x1 << 15)
411 #define RT5623_LINEIN_R_PIN_SHARING (0x1 << 14)
412 #define RT5623_LINEIN_R_PIN_AS_LINEIN_R (0x0 << 14)
413 #define RT5623_LINEIN_R_PIN_AS_JD2 (0x1 << 14)
414 #define RT5623_GPIO_PIN_SHARE (0x3)
415 #define RT5623_GPIO_PIN_AS_GPIO (0x0)
416 #define RT5623_GPIO_PIN_AS_IRQOUT (0x1)
417 #define RT5623_GPIO_PIN_AS_PLLOUT (0x3)
419 /* Jack Detect Control Register (0x5a) */
420 #define RT5623_JACK_DETECT_MASK (0x3 << 14)
421 #define RT5623_JACK_DETECT_USE_JD2 (0x3 << 14)
422 #define RT5623_JACK_DETECT_USE_JD1 (0x2 << 14)
423 #define RT5623_JACK_DETECT_USE_GPIO (0x1 << 14)
424 #define RT5623_JACK_DETECT_OFF (0x0 << 14)
425 #define RT5623_SPK_EN_IN_HI (0x1 << 11)
426 #define RT5623_AUX_R_EN_IN_HI (0x1 << 10)
427 #define RT5623_AUX_L_EN_IN_HI (0x1 << 9)
428 #define RT5623_HP_EN_IN_HI (0x1 << 8)
429 #define RT5623_SPK_EN_IN_LO (0x1 << 7)
430 #define RT5623_AUX_R_EN_IN_LO (0x1 << 6)
431 #define RT5623_AUX_L_EN_IN_LO (0x1 << 5)
432 #define RT5623_HP_EN_IN_LO (0x1 << 4)
434 /* MISC CONTROL (0x5e) */
435 #define RT5623_DISABLE_FAST_VREG (0x1 << 15)
436 #define RT5623_SPK_CLASS_AB_OC_PD (0x1 << 13)
437 #define RT5623_SPK_CLASS_AB_OC_DET (0x1 << 12)
438 #define RT5623_HP_DEPOP_MODE3_EN (0x1 << 10)
439 #define RT5623_HP_DEPOP_MODE2_EN (0x1 << 9)
440 #define RT5623_HP_DEPOP_MODE1_EN (0x1 << 8)
441 #define RT5623_AUXOUT_DEPOP_MODE3_EN (0x1 << 6)
442 #define RT5623_AUXOUT_DEPOP_MODE2_EN (0x1 << 5)
443 #define RT5623_AUXOUT_DEPOP_MODE1_EN (0x1 << 4)
444 #define RT5623_M_DAC_L_INPUT (0x1 << 3)
445 #define RT5623_M_DAC_R_INPUT (0x1 << 2)
446 #define RT5623_IRQOUT_INV_CTRL (0x1 << 0)
448 /* Psedueo Stereo & Spatial Effect Block Control (0x60) */
449 #define RT5623_SPATIAL_CTRL_EN (0x1 << 15)
450 #define RT5623_ALL_PASS_FILTER_EN (0x1 << 14)
451 #define RT5623_PSEUDO_STEREO_EN (0x1 << 13)
452 #define RT5623_STEREO_EXPENSION_EN (0x1 << 12)
453 #define RT5623_GAIN_3D_PARA_L_MASK (0x7 << 9)
454 #define RT5623_GAIN_3D_PARA_L_1_00 (0x0 << 9)
455 #define RT5623_GAIN_3D_PARA_L_1_25 (0x1 << 9)
456 #define RT5623_GAIN_3D_PARA_L_1_50 (0x2 << 9)
457 #define RT5623_GAIN_3D_PARA_L_1_75 (0x3 << 9)
458 #define RT5623_GAIN_3D_PARA_L_2_00 (0x4 << 9)
459 #define RT5623_GAIN_3D_PARA_R_MASK (0x7 << 6)
460 #define RT5623_GAIN_3D_PARA_R_1_00 (0x0 << 6)
461 #define RT5623_GAIN_3D_PARA_R_1_25 (0x1 << 6)
462 #define RT5623_GAIN_3D_PARA_R_1_50 (0x2 << 6)
463 #define RT5623_GAIN_3D_PARA_R_1_75 (0x3 << 6)
464 #define RT5623_GAIN_3D_PARA_R_2_00 (0x4 << 6)
465 #define RT5623_RATIO_3D_L_MASK (0x3 << 4)
466 #define RT5623_RATIO_3D_L_0_0 (0x0 << 4)
467 #define RT5623_RATIO_3D_L_0_66 (0x1 << 4)
468 #define RT5623_RATIO_3D_L_1_0 (0x2 << 4)
469 #define RT5623_RATIO_3D_R_MASK (0x3 << 2)
470 #define RT5623_RATIO_3D_R_0_0 (0x0 << 2)
471 #define RT5623_RATIO_3D_R_0_66 (0x1 << 2)
472 #define RT5623_RATIO_3D_R_1_0 (0x2 << 2)
473 #define RT5623_APF_MASK (0x3)
474 #define RT5623_APF_FOR_48K (0x3)
475 #define RT5623_APF_FOR_44_1K (0x2)
476 #define RT5623_APF_FOR_32K (0x1)
478 /* EQ CONTROL (0x62) */
479 #define RT5623_EN_HW_EQ_BLK (0x1 << 15)
480 #define RT5623_EN_HW_EQ_HPF_MODE (0x1 << 14)
481 #define RT5623_EN_HW_EQ_SOUR (0x1 << 11)
482 #define RT5623_EN_HW_EQ_HPF (0x1 << 4)
483 #define RT5623_EN_HW_EQ_BP3 (0x1 << 3)
484 #define RT5623_EN_HW_EQ_BP2 (0x1 << 2)
485 #define RT5623_EN_HW_EQ_BP1 (0x1 << 1)
486 #define RT5623_EN_HW_EQ_LPF (0x1 << 0)
488 /* EQ Mode Change Enable (0x66) */
489 #define RT5623_EQ_HPF_CHANGE_EN (0x1 << 4)
490 #define RT5623_EQ_BP3_CHANGE_EN (0x1 << 3)
491 #define RT5623_EQ_BP2_CHANGE_EN (0x1 << 2)
492 #define RT5623_EQ_BP1_CHANGE_EN (0x1 << 1)
493 #define RT5623_EQ_LPF_CHANGE_EN (0x1 << 0)
495 /* AVC Control (0x68) */
496 #define RT5623_AVC_ENABLE (0x1 << 15)
497 #define RT5623_AVC_TARTGET_SEL_MASK (0x1 << 14)
498 #define RT5623_AVC_TARTGET_SEL_R (0x1 << 14)
499 #define RT5623_AVC_TARTGET_SEL_L (0x0 << 14)
502 #define RT5623_PLL_FR_MCLK 0
503 #define RT5623_PLL_FR_BCLK 1
506 #endif /* __RT5623_H__ */