sound/soc/codecs/rt5621.c

   1 /*
   2  * rt5621.c  --  RT5621 ALSA SoC audio codec driver
   3  *
   4  * Copyright 2011 Realtek Semiconductor Corp.
   5  * Author: Johnny Hsu <johnnyhsu@realtek.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/moduleparam.h>
  14 #include <linux/init.h>
  15 #include <linux/delay.h>
  16 #include <linux/pm.h>
  17 #include <linux/i2c.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/spi/spi.h>
  20 #include <sound/core.h>
  21 #include <sound/pcm.h>
  22 #include <sound/pcm_params.h>
  23 #include <sound/soc.h>
  24 #include <sound/soc-dapm.h>
  25 #include <sound/initval.h>
  26 #include <sound/tlv.h>
  27
  28 #include "rt5621.h"
  29
  30 #if REALTEK_HWDEP
  31 #include <linux/ioctl.h>
  32 #include <linux/types.h>
  33 #endif
  34
  35 #if 0
  36 #define DBG(x...)       printk(x)
  37 #else
  38 #define DBG(x...)
  39 #endif
  40
  41 #define RT5621_VERSION "0.01 alsa 1.0.24"
  42
  43 static int caps_charge = 500;
  44 module_param(caps_charge, int, 0);
  45 MODULE_PARM_DESC(caps_charge, "RT5621 cap charge time (msecs)");
  46
  47 struct snd_soc_codec *rt5621_codec;
  48
  49 static void rt5621_work(struct work_struct *work);
  50
  51 static struct workqueue_struct *rt5621_workq;
  52 static DECLARE_DELAYED_WORK(delayed_work, rt5621_work);
  53
  54 #define ENABLE_EQ_HREQ 1
  55
  56 struct rt5621_priv {
  57         unsigned int sysclk;
  58 };
  59
  60 enum {
  61         NORMAL,
  62         CLUB,
  63         DANCE,
  64         LIVE,
  65         POP,
  66         ROCK,
  67         OPPO,
  68         TREBLE,
  69         BASS,
  70         HFREQ,
  71         EQTEST,
  72         SPK_FR
  73 };
  74
  75 typedef struct  _HW_EQ_PRESET
  76 {
  77         u16     HwEqType;
  78         u16     EqValue[14];
  79         u16     HwEQCtrl;
  80
  81 }HW_EQ_PRESET;
  82
  83 HW_EQ_PRESET HwEq_Preset[]={
  84         /* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x 0x9 0xa 0x 0xc 0x62*/
  85         {NORMAL,{0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000},0x0000},
  86         {CLUB  ,{0x1C10,0x0000,0xC1CC,0x1E5D,0x0699,0xCD48,0x188D,0x0699,0xC3B6,0x1CD0,0x0699,0x0436,0x0000},0x800E},
  87         {DANCE ,{0x1F2C,0x095B,0xC071,0x1F95,0x0616,0xC96E,0x1B11,0xFC91,0xDCF2,0x1194,0xFAF2,0x0436,0x0000},0x800F},
  88         {LIVE  ,{0x1EB5,0xFCB6,0xC24A,0x1DF8,0x0E7C,0xC883,0x1C10,0x0699,0xDA41,0x1561,0x0295,0x0436,0x0000},0x800F},
  89         {POP   ,{0x1E98,0xFCB6,0xC340,0x1D60,0x095B,0xC6AC,0x1BBC,0x0556,0x0689,0x0F33,0x0000,0xEDD1,0xF805},0x801F},
  90         {ROCK  ,{0x1EB5,0xFCB6,0xC071,0x1F95,0x0424,0xC30A,0x1D27,0xF900,0x0C5D,0x0FC7,0x0E23,0x0436,0x0000},0x800F},
  91         {OPPO  ,{0x0000,0x0000,0xCA4A,0x17F8,0x0FEC,0xCA4A,0x17F8,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000},0x800F},
  92         {TREBLE,{0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x188D,0x1699},0x8010},
  93         {BASS  ,{0x1A43,0x0C00,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000},0x8001},
  94         {EQTEST,{0x1F8C,0x1830,0xC118,0x1EEF,0xFD77,0xD8CB,0x1BBC,0x0556,0x0689,0x0F33,0x0000,0xF17F,0x0FEC},0x8003},
  95 };
  96
  97 static const u16 rt5621_reg[RT5621_VENDOR_ID2 + 1] = {
  98         [RT5621_RESET] = 0x59b4,
  99         [RT5621_SPK_OUT_VOL] = 0x8080,
 100         [RT5621_HP_OUT_VOL] = 0x8080,
 101         [RT5621_MONO_AUX_OUT_VOL] = 0x8080,
 102         [RT5621_AUXIN_VOL] = 0xe808,
 103         [RT5621_LINE_IN_VOL] = 0xe808,
 104         [RT5621_STEREO_DAC_VOL] = 0xe808,
 105         [RT5621_MIC_VOL] = 0x0808,
 106         [RT5621_MIC_ROUTING_CTRL] = 0xe0e0,
 107         [RT5621_ADC_REC_GAIN] = 0xf58b,
 108         [RT5621_ADC_REC_MIXER] = 0x7f7f,
 109         [RT5621_SOFT_VOL_CTRL_TIME] = 0x000a,
 110         [RT5621_OUTPUT_MIXER_CTRL] = 0xc000,
 111         [RT5621_AUDIO_INTERFACE] = 0x8000,
 112         [RT5621_STEREO_AD_DA_CLK_CTRL] = 0x166d,
 113         [RT5621_ADD_CTRL_REG] = 0x5300,
 114         [RT5621_GPIO_PIN_CONFIG] = 0x1c0e,
 115         [RT5621_GPIO_PIN_POLARITY] = 0x1c0e,
 116         [RT5621_GPIO_PIN_STATUS] = 0x0002,
 117         [RT5621_OVER_TEMP_CURR_STATUS] = 0x003c,
 118         [RT5621_PSEDUEO_SPATIAL_CTRL] = 0x0497,
 119         [RT5621_AVC_CTRL] = 0x000b,
 120         [RT5621_VENDOR_ID1] = 0x10ec,
 121         [RT5621_VENDOR_ID2] = 0x2003,
 122 };
 123
 124 #define rt5621_write_mask(c, reg, value, mask) snd_soc_update_bits(c, reg, mask, value)
 125
 126 #define rt5621_write_index_reg(c, addr, data) \
 127 { \
 128         snd_soc_write(c, 0x6a, addr); \
 129         snd_soc_write(c, 0x6c, data); \
 130 }
 131
 132 static int rt5621_reset(struct snd_soc_codec *codec)
 133 {
 134         return snd_soc_write(codec, RT5621_RESET, 0);
 135 }
 136
 137 static int rt5621_volatile_register(
 138         struct snd_soc_codec *codec, unsigned int reg)
 139 {
 140         switch (reg) {
 141         case RT5621_RESET:
 142         case RT5621_HID_CTRL_DATA:
 143         case RT5621_GPIO_PIN_STATUS:
 144         case RT5621_OVER_TEMP_CURR_STATUS:
 145                 return 1;
 146         default:
 147                 return 0;
 148         }
 149 }
 150
 151 static int rt5621_readable_register(
 152         struct snd_soc_codec *codec, unsigned int reg)
 153 {
 154         switch (reg) {
 155         case RT5621_RESET:
 156         case RT5621_SPK_OUT_VOL:
 157         case RT5621_HP_OUT_VOL:
 158         case RT5621_MONO_AUX_OUT_VOL:
 159         case RT5621_AUXIN_VOL:
 160         case RT5621_LINE_IN_VOL:
 161         case RT5621_STEREO_DAC_VOL:
 162         case RT5621_MIC_VOL:
 163         case RT5621_MIC_ROUTING_CTRL:
 164         case RT5621_ADC_REC_GAIN:
 165         case RT5621_ADC_REC_MIXER:
 166         case RT5621_SOFT_VOL_CTRL_TIME:
 167         case RT5621_OUTPUT_MIXER_CTRL:
 168         case RT5621_MIC_CTRL:
 169         case RT5621_AUDIO_INTERFACE:
 170         case RT5621_STEREO_AD_DA_CLK_CTRL:
 171         case RT5621_COMPANDING_CTRL:
 172         case RT5621_PWR_MANAG_ADD1:
 173         case RT5621_PWR_MANAG_ADD2:
 174         case RT5621_PWR_MANAG_ADD3:
 175         case RT5621_ADD_CTRL_REG:
 176         case RT5621_GLOBAL_CLK_CTRL_REG:
 177         case RT5621_PLL_CTRL:
 178         case RT5621_GPIO_OUTPUT_PIN_CTRL:
 179         case RT5621_GPIO_PIN_CONFIG:
 180         case RT5621_GPIO_PIN_POLARITY:
 181         case RT5621_GPIO_PIN_STICKY:
 182         case RT5621_GPIO_PIN_WAKEUP:
 183         case RT5621_GPIO_PIN_STATUS:
 184         case RT5621_GPIO_PIN_SHARING:
 185         case RT5621_OVER_TEMP_CURR_STATUS:
 186         case RT5621_JACK_DET_CTRL:
 187         case RT5621_MISC_CTRL:
 188         case RT5621_PSEDUEO_SPATIAL_CTRL:
 189         case RT5621_EQ_CTRL:
 190         case RT5621_EQ_MODE_ENABLE:
 191         case RT5621_AVC_CTRL:
 192         case RT5621_HID_CTRL_INDEX:
 193         case RT5621_HID_CTRL_DATA:
 194         case RT5621_VENDOR_ID1:
 195         case RT5621_VENDOR_ID2:
 196                 return 1;
 197         default:
 198                 return 0;
 199         }
 200 }
 201
 202
 203 //static const char *rt5621_spkl_pga[] = {"Vmid","HPL mixer","SPK mixer","Mono Mixer"};
 204 static const char *rt5621_spkn_source_sel[] = {"RN", "RP", "LN"};
 205 static const char *rt5621_spk_pga[] = {"Vmid","HP mixer","SPK mixer","Mono Mixer"};
 206 static const char *rt5621_hpl_pga[]  = {"Vmid","HPL mixer"};
 207 static const char *rt5621_hpr_pga[]  = {"Vmid","HPR mixer"};
 208 static const char *rt5621_mono_pga[] = {"Vmid","HP mixer","SPK mixer","Mono Mixer"};
 209 static const char *rt5621_amp_type_sel[] = {"Class AB","Class D"};
 210 static const char *rt5621_mic_boost_sel[] = {"Bypass","20db","30db","40db"};
 211
 212 static const struct soc_enum rt5621_enum[] = {
 213 SOC_ENUM_SINGLE(RT5621_OUTPUT_MIXER_CTRL, 14, 3, rt5621_spkn_source_sel), /* spkn source from hp mixer */
 214 SOC_ENUM_SINGLE(RT5621_OUTPUT_MIXER_CTRL, 10, 4, rt5621_spk_pga), /* spk input sel 1 */
 215 SOC_ENUM_SINGLE(RT5621_OUTPUT_MIXER_CTRL, 9, 2, rt5621_hpl_pga), /* hp left input sel 2 */
 216 SOC_ENUM_SINGLE(RT5621_OUTPUT_MIXER_CTRL, 8, 2, rt5621_hpr_pga), /* hp right input sel 3 */
 217 SOC_ENUM_SINGLE(RT5621_OUTPUT_MIXER_CTRL, 6, 4, rt5621_mono_pga), /* mono input sel 4 */
 218 SOC_ENUM_SINGLE(RT5621_MIC_CTRL, 10,4, rt5621_mic_boost_sel), /*Mic1 boost sel 5 */
 219 SOC_ENUM_SINGLE(RT5621_MIC_CTRL, 8,4,rt5621_mic_boost_sel), /*Mic2 boost sel 6 */
 220 SOC_ENUM_SINGLE(RT5621_OUTPUT_MIXER_CTRL,13,2,rt5621_amp_type_sel), /*Speaker AMP sel 7 */
 221 };
 222
 223 static int rt5621_amp_sel_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
 224 {
 225         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 226         struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
 227         unsigned short val;
 228         unsigned short mask, bitmask;
 229
 230         for (bitmask = 1; bitmask < e->max; bitmask <<= 1);
 231
 232         if (ucontrol->value.enumerated.item[0] > e->max - 1)
 233                 return -EINVAL;
 234         val = ucontrol->value.enumerated.item[0] << e->shift_l;
 235         mask = (bitmask - 1) << e->shift_l;
 236         if (e->shift_l != e->shift_r) {
 237                 if (ucontrol->value.enumerated.item[1] > e->max - 1)
 238                         return -EINVAL;
 239                 val |= ucontrol->value.enumerated.item[1] << e->shift_r;
 240                 mask |= (bitmask - 1) << e->shift_r;
 241         }
 242
 243         snd_soc_update_bits(codec, e->reg, mask, val);
 244         val &= (0x1 << 13);
 245
 246         if (val == 0)
 247         {
 248                 snd_soc_update_bits(codec, 0x3c, 0x0000, 0x4000);       /*power off classd*/
 249                 snd_soc_update_bits(codec, 0x3c, 0x8000, 0x8000);       /*power on classab*/
 250         } else {
 251                 snd_soc_update_bits(codec, 0x3c, 0x0000, 0x8000);       /*power off classab*/
 252                 snd_soc_update_bits(codec, 0x3c, 0x4000, 0x4000);       /*power on classd*/
 253         }
 254
 255         return 0;
 256 }
 257
 258 //*****************************************************************************
 259 //
 260 //function:Change audio codec power status
 261 //
 262 //*****************************************************************************
 263 static int rt5621_ChangeCodecPowerStatus(struct snd_soc_codec *codec,int power_state)
 264 {
 265         unsigned short int PowerDownState=0;
 266
 267         switch(power_state) {
 268         case POWER_STATE_D0: //FULL ON-----power on all power
 269
 270                 snd_soc_write(codec,RT5621_PWR_MANAG_ADD1,~PowerDownState);
 271                 snd_soc_write(codec,RT5621_PWR_MANAG_ADD2,~PowerDownState);
 272                 snd_soc_write(codec,RT5621_PWR_MANAG_ADD3,~PowerDownState);
 273                 break;
 274         case POWER_STATE_D1: //LOW ON-----
 275                 rt5621_write_mask(codec, RT5621_PWR_MANAG_ADD2 ,PWR_VREF |
 276                         PWR_DAC_REF_CIR | PWR_L_DAC_CLK | PWR_R_DAC_CLK |
 277                         PWR_L_HP_MIXER | PWR_R_HP_MIXER | PWR_L_ADC_CLK_GAIN |
 278                         PWR_R_ADC_CLK_GAIN | PWR_L_ADC_REC_MIXER | PWR_R_ADC_REC_MIXER |
 279                         PWR_CLASS_AB, PWR_VREF | PWR_DAC_REF_CIR | PWR_L_DAC_CLK |
 280                         PWR_R_DAC_CLK | PWR_L_HP_MIXER | PWR_R_HP_MIXER |
 281                         PWR_L_ADC_CLK_GAIN | PWR_R_ADC_CLK_GAIN |
 282                         PWR_L_ADC_REC_MIXER | PWR_R_ADC_REC_MIXER | PWR_CLASS_AB);
 283
 284                 rt5621_write_mask(codec, RT5621_PWR_MANAG_ADD3 ,PWR_MAIN_BIAS |
 285                         PWR_HP_R_OUT_VOL | PWR_HP_L_OUT_VOL | PWR_SPK_OUT |
 286                         PWR_MIC1_FUN_CTRL | PWR_MIC1_BOOST_MIXER, PWR_MAIN_BIAS |
 287                         PWR_HP_R_OUT_VOL | PWR_HP_L_OUT_VOL | PWR_SPK_OUT |
 288                         PWR_MIC1_FUN_CTRL | PWR_MIC1_BOOST_MIXER);
 289
 290                 rt5621_write_mask(codec, RT5621_PWR_MANAG_ADD1 ,PWR_MAIN_I2S_EN |
 291                         PWR_HP_OUT_ENH_AMP | PWR_HP_OUT_AMP | PWR_MIC1_BIAS_EN,
 292                         PWR_MAIN_I2S_EN | PWR_HP_OUT_ENH_AMP | PWR_HP_OUT_AMP |
 293                         PWR_MIC1_BIAS_EN);
 294                 break;
 295
 296         case POWER_STATE_D1_PLAYBACK: //Low on of Playback
 297                 rt5621_write_mask(codec, RT5621_PWR_MANAG_ADD2, PWR_VREF | PWR_DAC_REF_CIR |
 298                         PWR_L_DAC_CLK | PWR_R_DAC_CLK | PWR_L_HP_MIXER | PWR_R_HP_MIXER |
 299                         PWR_CLASS_AB | PWR_CLASS_D, PWR_VREF | PWR_DAC_REF_CIR |
 300                         PWR_L_DAC_CLK | PWR_R_DAC_CLK | PWR_L_HP_MIXER | PWR_R_HP_MIXER |
 301                         PWR_CLASS_AB | PWR_CLASS_D);
 302
 303                 rt5621_write_mask(codec, RT5621_PWR_MANAG_ADD3, PWR_MAIN_BIAS |
 304                         PWR_HP_R_OUT_VOL | PWR_HP_L_OUT_VOL | PWR_SPK_OUT,
 305                         PWR_MAIN_BIAS | PWR_HP_R_OUT_VOL | PWR_HP_L_OUT_VOL | PWR_SPK_OUT);
 306
 307                 rt5621_write_mask(codec, RT5621_PWR_MANAG_ADD1, PWR_MAIN_I2S_EN |
 308                         PWR_HP_OUT_ENH_AMP | PWR_HP_OUT_AMP, PWR_MAIN_I2S_EN |
 309                         PWR_HP_OUT_ENH_AMP | PWR_HP_OUT_AMP);
 310                 break;
 311
 312         case POWER_STATE_D1_RECORD: //Low on of Record
 313                 rt5621_write_mask(codec, RT5621_PWR_MANAG_ADD1, PWR_MAIN_I2S_EN |
 314                         PWR_MIC1_BIAS_EN, PWR_MAIN_I2S_EN | PWR_MIC1_BIAS_EN);
 315                 rt5621_write_mask(codec, RT5621_PWR_MANAG_ADD2, PWR_VREF |
 316                         PWR_L_ADC_CLK_GAIN | PWR_R_ADC_CLK_GAIN | PWR_L_ADC_REC_MIXER |
 317                         PWR_R_ADC_REC_MIXER, PWR_VREF | PWR_L_ADC_CLK_GAIN |
 318                         PWR_R_ADC_CLK_GAIN | PWR_L_ADC_REC_MIXER | PWR_R_ADC_REC_MIXER);
 319                 rt5621_write_mask(codec, RT5621_PWR_MANAG_ADD3, PWR_MAIN_BIAS |
 320                         PWR_MIC2_BOOST_MIXER | PWR_MIC1_BOOST_MIXER, PWR_MAIN_BIAS |
 321                         PWR_MIC2_BOOST_MIXER | PWR_MIC1_BOOST_MIXER);
 322                 break;
 323
 324         case POWER_STATE_D2: //STANDBY----
 325                 rt5621_write_mask(codec, RT5621_PWR_MANAG_ADD1, 0, PWR_MAIN_I2S_EN |
 326                         PWR_HP_OUT_ENH_AMP | PWR_HP_OUT_AMP | PWR_MIC1_BIAS_EN);
 327                 rt5621_write_mask(codec, RT5621_PWR_MANAG_ADD3, 0, PWR_HP_R_OUT_VOL |
 328                         PWR_HP_L_OUT_VOL | PWR_SPK_OUT | PWR_MIC1_FUN_CTRL |
 329                         PWR_MIC1_BOOST_MIXER);
 330                 rt5621_write_mask(codec, RT5621_PWR_MANAG_ADD2, 0, PWR_DAC_REF_CIR |
 331                         PWR_L_DAC_CLK | PWR_R_DAC_CLK | PWR_L_HP_MIXER | PWR_R_HP_MIXER|
 332                         PWR_L_ADC_CLK_GAIN | PWR_R_ADC_CLK_GAIN | PWR_L_ADC_REC_MIXER |
 333                         PWR_R_ADC_REC_MIXER | PWR_CLASS_AB | PWR_CLASS_D);
 334                 break;
 335
 336         case POWER_STATE_D2_PLAYBACK: //STANDBY of playback
 337                 rt5621_write_mask(codec, RT5621_PWR_MANAG_ADD3, 0, /*PWR_HP_R_OUT_VOL |
 338                         PWR_HP_L_OUT_VOL |*/ PWR_SPK_OUT);
 339                 rt5621_write_mask(codec, RT5621_PWR_MANAG_ADD1, 0, PWR_HP_OUT_ENH_AMP |
 340                         PWR_HP_OUT_AMP);
 341                 rt5621_write_mask(codec, RT5621_PWR_MANAG_ADD2, 0, PWR_DAC_REF_CIR |
 342                         PWR_L_DAC_CLK | PWR_R_DAC_CLK | PWR_L_HP_MIXER | PWR_R_HP_MIXER |
 343                         PWR_CLASS_AB | PWR_CLASS_D);
 344                 break;
 345
 346         case POWER_STATE_D2_RECORD: //STANDBY of record
 347                 rt5621_write_mask(codec, RT5621_PWR_MANAG_ADD1, 0, PWR_MIC1_BIAS_EN);
 348                 rt5621_write_mask(codec, RT5621_PWR_MANAG_ADD2, 0, PWR_L_ADC_CLK_GAIN |
 349                         PWR_R_ADC_CLK_GAIN | PWR_L_ADC_REC_MIXER | PWR_R_ADC_REC_MIXER);
 350                 rt5621_write_mask(codec, RT5621_PWR_MANAG_ADD3, 0, PWR_MIC2_BOOST_MIXER |
 351                         PWR_MIC1_BOOST_MIXER);
 352                 break;
 353
 354         case POWER_STATE_D3: //SLEEP
 355         case POWER_STATE_D4: //OFF----power off all power
 356                 rt5621_write_mask(codec, RT5621_PWR_MANAG_ADD1, 0, PWR_HP_OUT_ENH_AMP |
 357                         PWR_HP_OUT_AMP);
 358                 snd_soc_write(codec, RT5621_PWR_MANAG_ADD3, 0);
 359                 snd_soc_write(codec, RT5621_PWR_MANAG_ADD1, 0);
 360                 snd_soc_write(codec, RT5621_PWR_MANAG_ADD2, 0);
 361                 break;
 362
 363         default:
 364                 break;
 365         }
 366
 367         return 0;
 368 }
 369
 370
 371 //*****************************************************************************
 372 //
 373 //function AudioOutEnable:Mute/Unmute audio out channel
 374 //WavOutPath:output channel
 375 //Mute :Mute/Unmute output channel
 376 //
 377 //*****************************************************************************
 378 static int rt5621_AudioOutEnable(struct snd_soc_codec *codec,
 379         unsigned short int WavOutPath, int Mute)
 380 {
 381         int RetVal=0;
 382
 383         if(Mute) {
 384                 switch(WavOutPath) {
 385                 case RT_WAVOUT_ALL_ON:
 386                         RetVal = rt5621_write_mask(codec, RT5621_SPK_OUT_VOL, RT_L_MUTE | RT_R_MUTE,
 387                                 RT_L_MUTE | RT_R_MUTE); //Mute Speaker right/left channel
 388                         RetVal = rt5621_write_mask(codec, RT5621_HP_OUT_VOL, RT_L_MUTE | RT_R_MUTE,
 389                                 RT_L_MUTE | RT_R_MUTE); //Mute headphone right/left channel
 390                         RetVal = rt5621_write_mask(codec, RT5621_MONO_AUX_OUT_VOL, RT_L_MUTE |
 391                                 RT_R_MUTE, RT_L_MUTE | RT_R_MUTE); //Mute Aux/Mono right/left channel
 392                         RetVal = rt5621_write_mask(codec, RT5621_STEREO_DAC_VOL, RT_M_HP_MIXER |
 393                                 RT_M_SPK_MIXER | RT_M_MONO_MIXER, RT_M_HP_MIXER |
 394                                 RT_M_SPK_MIXER | RT_M_MONO_MIXER); //Mute DAC to HP,Speaker,Mono Mixer
 395                         break;
 396
 397                 case RT_WAVOUT_HP:
 398                         RetVal = rt5621_write_mask(codec, RT5621_HP_OUT_VOL, RT_L_MUTE | RT_R_MUTE,
 399                                 RT_L_MUTE | RT_R_MUTE); //Mute headphone right/left channel
 400                         break;
 401
 402                 case RT_WAVOUT_SPK:
 403                         RetVal = rt5621_write_mask(codec, RT5621_SPK_OUT_VOL, RT_L_MUTE | RT_R_MUTE,
 404                                 RT_L_MUTE | RT_R_MUTE); //Mute Speaker right/left channel
 405                         break;
 406
 407                 case RT_WAVOUT_AUXOUT:
 408                         RetVal = rt5621_write_mask(codec, RT5621_MONO_AUX_OUT_VOL, RT_L_MUTE |
 409                                 RT_R_MUTE, RT_L_MUTE | RT_R_MUTE); //Mute AuxOut right/left channel
 410                         break;
 411
 412                 case RT_WAVOUT_MONO:
 413
 414                         RetVal = rt5621_write_mask(codec, RT5621_MONO_AUX_OUT_VOL, RT_L_MUTE,
 415                                 RT_L_MUTE); //Mute MonoOut channel
 416                         break;
 417
 418                 case RT_WAVOUT_DAC:
 419                         RetVal = rt5621_write_mask(codec, RT5621_STEREO_DAC_VOL, RT_M_HP_MIXER |
 420                                 RT_M_SPK_MIXER | RT_M_MONO_MIXER, RT_M_HP_MIXER | RT_M_SPK_MIXER |
 421                                 RT_M_MONO_MIXER); //Mute DAC to HP,Speaker,Mono Mixer
 422                         break;
 423
 424                 default:
 425                         return 0;
 426                 }
 427         } else {
 428                 switch(WavOutPath) {
 429                 case RT_WAVOUT_ALL_ON:
 430                         RetVal = rt5621_write_mask(codec, RT5621_SPK_OUT_VOL, 0, RT_L_MUTE |
 431                                 RT_R_MUTE); //Mute Speaker right/left channel
 432                         RetVal = rt5621_write_mask(codec, RT5621_HP_OUT_VOL, 0, RT_L_MUTE |
 433                                 RT_R_MUTE); //Mute headphone right/left channel
 434                         RetVal = rt5621_write_mask(codec, RT5621_MONO_AUX_OUT_VOL, 0, RT_L_MUTE |
 435                                 RT_R_MUTE); //Mute Aux/Mono right/left channel
 436                         RetVal = rt5621_write_mask(codec, RT5621_STEREO_DAC_VOL, 0, RT_M_HP_MIXER |
 437                                 RT_M_SPK_MIXER | RT_M_MONO_MIXER); //Mute DAC to HP,Speaker,Mono Mixer
 438                         break;
 439                 case RT_WAVOUT_HP:
 440                         RetVal = rt5621_write_mask(codec, RT5621_HP_OUT_VOL, 0, RT_L_MUTE |
 441                                 RT_R_MUTE); //UnMute headphone right/left channel
 442                         break;
 443
 444                 case RT_WAVOUT_SPK:
 445                         RetVal = rt5621_write_mask(codec, RT5621_SPK_OUT_VOL, 0, RT_L_MUTE |
 446                                 RT_R_MUTE); //unMute Speaker right/left channel
 447                         break;
 448                 case RT_WAVOUT_AUXOUT:
 449                         RetVal = rt5621_write_mask(codec, RT5621_MONO_AUX_OUT_VOL, 0, RT_L_MUTE |
 450                                 RT_R_MUTE); //unMute AuxOut right/left channel
 451                         break;
 452
 453                 case RT_WAVOUT_MONO:
 454                         RetVal = rt5621_write_mask(codec, RT5621_MONO_AUX_OUT_VOL, 0,
 455                                 RT_L_MUTE); //unMute MonoOut channel
 456                         break;
 457
 458                 case RT_WAVOUT_DAC:
 459                         RetVal = rt5621_write_mask(codec, RT5621_STEREO_DAC_VOL, 0, RT_M_HP_MIXER |
 460                                 RT_M_SPK_MIXER | RT_M_MONO_MIXER); //unMute DAC to HP,Speaker,Mono Mixer
 461                         break;
 462                 default:
 463                         return 0;
 464                 }
 465
 466         }
 467
 468         return RetVal;
 469 }
 470
 471
 472 //*****************************************************************************
 473 //
 474 //function:Enable/Disable ADC input source control
 475 //
 476 //*****************************************************************************
 477 static int Enable_ADC_Input_Source(struct snd_soc_codec *codec,unsigned short int ADC_Input_Sour,int Enable)
 478 {
 479         int bRetVal=0;
 480
 481         if(Enable) {
 482                 //Enable ADC source
 483                 bRetVal=rt5621_write_mask(codec,RT5621_ADC_REC_MIXER,0,ADC_Input_Sour);
 484         } else {
 485                 //Disable ADC source
 486                 bRetVal=rt5621_write_mask(codec,RT5621_ADC_REC_MIXER,ADC_Input_Sour,ADC_Input_Sour);
 487         }
 488
 489         return bRetVal;
 490 }
 491
 492 static void rt5621_update_eqmode(struct snd_soc_codec *codec, int mode)
 493 {
 494         u16 HwEqIndex=0;
 495
 496         if (mode == NORMAL) {
 497                 /*clear EQ parameter*/
 498                 for (HwEqIndex=0; HwEqIndex<=0x0C; HwEqIndex++) {
 499
 500                         rt5621_write_index_reg(codec, HwEqIndex, HwEq_Preset[mode].EqValue[HwEqIndex])
 501                 }
 502
 503                 snd_soc_write(codec, 0x62, 0x0);                /*disable EQ block*/
 504         } else {
 505                 snd_soc_write(codec, 0x62, HwEq_Preset[mode].HwEQCtrl);
 506
 507                 /*Fill EQ parameter*/
 508                 for (HwEqIndex=0; HwEqIndex<=0x0C; HwEqIndex++) {
 509
 510                         rt5621_write_index_reg(codec, HwEqIndex, HwEq_Preset[mode].EqValue[HwEqIndex])
 511                 }
 512                 //update EQ parameter
 513                 snd_soc_write(codec, 0x66, 0x1f);
 514                 schedule_timeout_uninterruptible(msecs_to_jiffies(1));
 515                 snd_soc_write(codec, 0x66, 0x0);
 516         }
 517 }
 518
 519 static const struct snd_kcontrol_new rt5621_snd_controls[] = {
 520 SOC_DOUBLE("Speaker Playback Volume",   RT5621_SPK_OUT_VOL, 8, 0, 31, 1),
 521 SOC_DOUBLE("Speaker Playback Switch",   RT5621_SPK_OUT_VOL, 15, 7, 1, 1),
 522 SOC_DOUBLE("Headphone Playback Volume", RT5621_HP_OUT_VOL, 8, 0, 31, 1),
 523 SOC_DOUBLE("Headphone Playback Switch", RT5621_HP_OUT_VOL,15, 7, 1, 1),
 524 SOC_DOUBLE("AUX Playback Volume",               RT5621_MONO_AUX_OUT_VOL, 8, 0, 31, 1),
 525 SOC_DOUBLE("AUX Playback Switch",               RT5621_MONO_AUX_OUT_VOL, 15, 7, 1, 1),
 526 SOC_DOUBLE("PCM Playback Volume",               RT5621_STEREO_DAC_VOL, 8, 0, 31, 1),
 527 SOC_DOUBLE("Line In Volume",                    RT5621_LINE_IN_VOL, 8, 0, 31, 1),
 528 SOC_SINGLE("Mic 1 Volume",                              RT5621_MIC_VOL, 8, 31, 1),
 529 SOC_SINGLE("Mic 2 Volume",                              RT5621_MIC_VOL, 0, 31, 1),
 530 SOC_ENUM("Mic 1 Boost",                                 rt5621_enum[5]),
 531 SOC_ENUM("Mic 2 Boost",                                 rt5621_enum[6]),
 532 SOC_ENUM_EXT("Speaker Amp Type",                        rt5621_enum[7], snd_soc_get_enum_double, rt5621_amp_sel_put),
 533 SOC_DOUBLE("AUX In Volume",                     RT5621_AUXIN_VOL, 8, 0, 31, 1),
 534 SOC_DOUBLE("Capture Volume",                    RT5621_ADC_REC_GAIN, 7, 0, 31, 0),
 535 };
 536
 537 void hp_depop_mode2(struct snd_soc_codec *codec)
 538 {
 539         snd_soc_update_bits(codec, 0x3e, 0x8000, 0x8000);
 540         snd_soc_update_bits(codec, 0x04, 0x8080, 0x8080);
 541         snd_soc_update_bits(codec, 0x3a, 0x0100, 0x0100);
 542         snd_soc_update_bits(codec, 0x3c, 0x2000, 0x2000);
 543         snd_soc_update_bits(codec, 0x3e, 0x0600, 0x0600);
 544         snd_soc_update_bits(codec, 0x5e, 0x0200, 0x0200);
 545         schedule_timeout_uninterruptible(msecs_to_jiffies(300));
 546 }
 547
 548 void aux_depop_mode2(struct snd_soc_codec *codec)
 549 {
 550         snd_soc_update_bits(codec, 0x3e, 0x8000, 0x8000);
 551         snd_soc_update_bits(codec, 0x06, 0x8080, 0x8080);
 552         snd_soc_update_bits(codec, 0x3a, 0x0100, 0x0100);
 553         snd_soc_update_bits(codec, 0x3c, 0x2000, 0x2000);
 554         snd_soc_update_bits(codec, 0x3e, 0x6000, 0x6000);
 555         snd_soc_update_bits(codec, 0x5e, 0x0020, 0x0200);
 556         schedule_timeout_uninterruptible(msecs_to_jiffies(300));
 557         snd_soc_update_bits(codec, 0x3a, 0x0002, 0x0002);
 558         snd_soc_update_bits(codec, 0x3a, 0x0001, 0x0001);
 559 }
 560
 561 static int rt5621_pcm_hw_prepare(struct snd_pcm_substream *substream,
 562                 struct snd_soc_dai *codec_dai)
 563 {
 564
 565         struct snd_soc_codec *codec = codec_dai->codec;
 566         int stream = substream->stream;
 567
 568         switch (stream)
 569         {
 570                 case SNDRV_PCM_STREAM_PLAYBACK:
 571
 572                         rt5621_ChangeCodecPowerStatus(codec,POWER_STATE_D1_PLAYBACK);   //power on dac to hp and speaker out
 573
 574                         rt5621_AudioOutEnable(codec,RT_WAVOUT_SPK,0);   //unmute speaker out
 575
 576                         rt5621_AudioOutEnable(codec,RT_WAVOUT_HP,0);    //unmute hp
 577
 578                         rt5621_AudioOutEnable(codec,RT_WAVOUT_AUXOUT,0);        //unmute auxout out
 579
 580                         break;
 581                 case SNDRV_PCM_STREAM_CAPTURE:
 582
 583                         rt5621_ChangeCodecPowerStatus(codec,POWER_STATE_D1_RECORD);     //power on input to adc
 584
 585                         Enable_ADC_Input_Source(codec,RT_WAVIN_L_MIC1|RT_WAVIN_R_MIC1,1);       //enable record source from mic1
 586
 587                         break;
 588         }
 589
 590         return 0;
 591 }
 592
 593 /* PLL divisors */
 594 struct _pll_div {
 595         u32 pll_in;
 596         u32 pll_out;
 597         u16 regvalue;
 598 };
 599
 600 static const struct _pll_div codec_pll_div[] = {
 601
 602         {  2048000,  8192000,   0x0ea0},
 603         {  3686400,  8192000,   0x4e27},
 604         { 12000000,  8192000,   0x456b},
 605         { 13000000,  8192000,   0x495f},
 606         { 13100000,      8192000,       0x0320},
 607         {  2048000,  11289600,  0xf637},
 608         {  3686400,  11289600,  0x2f22},
 609         { 12000000,  11289600,  0x3e2f},
 610         { 13000000,  11289600,  0x4d5b},
 611         { 13100000,      11289600,      0x363b},
 612         {  2048000,  16384000,  0x1ea0},
 613         {  3686400,  16384000,  0x9e27},
 614         { 12000000,  16384000,  0x452b},
 615         { 13000000,  16384000,  0x542f},
 616         { 13100000,      16384000,      0x03a0},
 617         {  2048000,  16934400,  0xe625},
 618         {  3686400,  16934400,  0x9126},
 619         { 12000000,  16934400,  0x4d2c},
 620         { 13000000,  16934400,  0x742f},
 621         { 13100000,      16934400,      0x3c27},
 622         {  2048000,  22579200,  0x2aa0},
 623         {  3686400,  22579200,  0x2f20},
 624         { 12000000,  22579200,  0x7e2f},
 625         { 13000000,  22579200,  0x742f},
 626         { 13100000,      22579200,      0x3c27},
 627         {  2048000,  24576000,  0x2ea0},
 628         {  3686400,  24576000,  0xee27},
 629         { 12000000,  24576000,  0x2915},
 630         { 13000000,  24576000,  0x772e},
 631         { 13100000,      24576000,      0x0d20},
 632 };
 633
 634 static const struct _pll_div codec_bclk_pll_div[] = {
 635
 636         {  1536000,      24576000,      0x3ea0},
 637         {  3072000,      24576000,      0x1ea0},
 638         {  512000,       24576000,  0x8e90},
 639         {  256000,   24576000,  0xbe80},
 640         {  2822400,      11289600,      0x1ee0},
 641         {  3072000,      12288000,      0x1ee0},
 642 };
 643
 644
 645 static int rt5621_set_dai_pll(struct snd_soc_dai *dai,
 646                 int pll_id,int source, unsigned int freq_in, unsigned int freq_out)
 647 {
 648         int i;
 649         int ret = -EINVAL;
 650         struct snd_soc_codec *codec = dai->codec;
 651
 652         if (pll_id < RT5621_PLL_FR_MCLK || pll_id > RT5621_PLL_FR_BCLK)
 653                 return -EINVAL;
 654
 655         //rt5621_write_mask(codec,RT5621_PWR_MANAG_ADD2, 0x0000,0x1000);        //disable PLL power
 656
 657         if (!freq_in || !freq_out) {
 658
 659                 return 0;
 660         }
 661
 662         if (RT5621_PLL_FR_MCLK == pll_id) {
 663         for (i = 0; i < ARRAY_SIZE(codec_pll_div); i++) {
 664
 665                 if (codec_pll_div[i].pll_in == freq_in && codec_pll_div[i].pll_out == freq_out)
 666                         {
 667                                 snd_soc_update_bits(codec, RT5621_GLOBAL_CLK_CTRL_REG, 0x0000, 0x4000);
 668                                 snd_soc_write(codec,RT5621_PLL_CTRL,codec_pll_div[i].regvalue);//set PLL parameter
 669                                 snd_soc_update_bits(codec,RT5621_PWR_MANAG_ADD2, 0x1000,0x1000);        //enable PLL power
 670                                 ret = 0;
 671                         }
 672         }
 673         }
 674         else if (RT5621_PLL_FR_BCLK == pll_id)
 675         {
 676                 for (i = 0; i < ARRAY_SIZE(codec_bclk_pll_div); i++)
 677                 {
 678                         if ((freq_in == codec_bclk_pll_div[i].pll_in) && (freq_out == codec_bclk_pll_div[i].pll_out))
 679                         {
 680                                 snd_soc_update_bits(codec, RT5621_GLOBAL_CLK_CTRL_REG, 0x4000, 0x4000);
 681                                 snd_soc_write(codec,RT5621_PLL_CTRL,codec_bclk_pll_div[i].regvalue);//set PLL parameter
 682                                 snd_soc_update_bits(codec,RT5621_PWR_MANAG_ADD2, 0x1000,0x1000);        //enable PLL power
 683                                 ret = 0;
 684                         }
 685                 }
 686         }
 687
 688         snd_soc_update_bits(codec,RT5621_GLOBAL_CLK_CTRL_REG,0x8000,0x8000);//Codec sys-clock from PLL
 689         return ret;
 690 }
 691
 692
 693 struct _coeff_div {
 694         u32 mclk;
 695         u32 rate;
 696         u16 fs;
 697         u16 regvalue;
 698 };
 699
 700 /* codec hifi mclk (after PLL) clock divider coefficients */
 701 static const struct _coeff_div coeff_div[] = {
 702         /* 8k */
 703         { 8192000,  8000, 256*4, 0x2a2d},
 704         {12288000,  8000, 384*4, 0x2c2f},
 705
 706         /* 11.025k */
 707         {11289600, 11025, 256*4, 0x2a2d},
 708         {16934400, 11025, 384*4, 0x2c2f},
 709
 710         /* 16k */
 711         {12288000, 16000, 384*2, 0x1c2f},
 712         {16384000, 16000, 256*4, 0x2a2d},
 713         {24576000, 16000, 384*4, 0x2c2f},
 714
 715         /* 22.05k */
 716         {11289600, 22050, 256*2, 0x1a2d},
 717         {16934400, 22050, 384*2, 0x1c2f},
 718
 719         /* 32k */
 720         {12288000, 32000, 384  , 0x0c2f},
 721         {16384000, 32000, 256*2, 0x1a2d},
 722         {24576000, 32000, 384*2, 0x1c2f},
 723
 724         /* 44.1k */
 725         {11289600, 44100, 256*1, 0x0a2d},
 726         {22579200, 44100, 256*2, 0x1a2d},
 727         {45158400, 44100, 256*4, 0x2a2d},
 728
 729         /* 48k */
 730         {12288000, 48000, 256*1, 0x0a2d},
 731         {24576000, 48000, 256*2, 0x1a2d},
 732         {49152000, 48000, 256*4, 0x2a2d},
 733
 734         //MCLK is 24.576Mhz(for 8k,16k,32k)
 735         {24576000,  8000, 384*8, 0x3c6b},
 736         {24576000, 16000, 384*4, 0x2c6b},
 737         {24576000, 32000, 384*2, 0x1c6b},
 738
 739         //MCLK is 22.5792mHz(for 11k,22k)
 740         {22579200, 11025, 256*8, 0x3a2d},
 741         {22579200, 22050, 256*4, 0x2a2d},
 742 };
 743
 744
 745
 746 static int get_coeff(int mclk, int rate)
 747 {
 748         int i;
 749
 750         DBG("get_coeff mclk=%d,rate=%d\n",mclk,rate);
 751
 752         for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
 753                 if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
 754                         return i;
 755         }
 756         return -EINVAL;
 757 }
 758
 759
 760 /*
 761  * Clock after PLL and dividers
 762  */
 763  /*in this driver, you have to set sysclk to be 24576000,
 764  * but you don't need to give a clk to be 24576000, our
 765  * internal pll will generate this clock! so it won't make
 766  * you any difficult.
 767  */
 768 static int rt5621_set_dai_sysclk(struct snd_soc_dai *dai,
 769                 int clk_id, unsigned int freq, int dir)
 770 {
 771         struct snd_soc_codec *codec = dai->codec;
 772         struct rt5621_priv *rt5621 = snd_soc_codec_get_drvdata(codec);
 773
 774         if ((freq >= (256 * 8000)) && (freq <= (512 * 48000))) {
 775                 rt5621->sysclk = freq;
 776                 return 0;
 777         }
 778
 779         printk("unsupported sysclk freq %u for audio i2s\n", freq);
 780
 781         return -EINVAL;
 782 }
 783
 784
 785 static int rt5621_set_dai_fmt(struct snd_soc_dai *dai,
 786                 unsigned int fmt)
 787 {
 788         struct snd_soc_codec *codec = dai->codec;
 789         u16 iface = 0;
 790
 791         /* set master/slave audio interface */
 792         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 793         case SND_SOC_DAIFMT_CBM_CFM:
 794                 iface = 0x0000;
 795                 break;
 796         case SND_SOC_DAIFMT_CBS_CFS:
 797                 iface = 0x8000;
 798                 break;
 799         default:
 800                 return -EINVAL;
 801         }
 802
 803         /* interface format */
 804         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 805         case SND_SOC_DAIFMT_I2S:
 806                 iface |= 0x0000;
 807                 break;
 808         case SND_SOC_DAIFMT_RIGHT_J:
 809                 iface |= 0x0001;
 810                 break;
 811         case SND_SOC_DAIFMT_LEFT_J:
 812                 iface |= 0x0002;
 813                 break;
 814         case SND_SOC_DAIFMT_DSP_A:
 815                 iface |= 0x0003;
 816                 break;
 817         case SND_SOC_DAIFMT_DSP_B:
 818                 iface |= 0x4003;
 819                 break;
 820         default:
 821                 return -EINVAL;
 822         }
 823
 824         /* clock inversion */
 825         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 826         case SND_SOC_DAIFMT_NB_NF:
 827                 iface |= 0x0000;
 828                 break;
 829         case SND_SOC_DAIFMT_IB_NF:
 830                 iface |= 0x0100;
 831                 break;
 832         default:
 833                 return -EINVAL;
 834         }
 835
 836         snd_soc_write(codec,RT5621_AUDIO_INTERFACE,iface);
 837         return 0;
 838 }
 839
 840
 841 static int rt5621_pcm_hw_params(struct snd_pcm_substream *substream,
 842         struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
 843 {
 844         struct snd_soc_codec *codec = dai->codec;
 845         struct rt5621_priv *rt5621 = snd_soc_codec_get_drvdata(codec);
 846         u16 iface = snd_soc_read(codec,RT5621_AUDIO_INTERFACE)&0xfff3;
 847         int coeff = get_coeff(rt5621->sysclk, params_rate(params));
 848
 849         DBG("rt5621_pcm_hw_params\n");
 850         if (coeff < 0)
 851                 coeff = get_coeff(24576000, params_rate(params));         /*if not set sysclk, default to be 24.576MHz*/
 852
 853         /* bit size */
 854         switch (params_format(params)) {
 855         case SNDRV_PCM_FORMAT_S16_LE:
 856                 iface |= 0x0000;
 857                 break;
 858         case SNDRV_PCM_FORMAT_S20_3LE:
 859                 iface |= 0x0004;
 860                 break;
 861         case SNDRV_PCM_FORMAT_S24_LE:
 862                 iface |= 0x0008;
 863                 break;
 864         case SNDRV_PCM_FORMAT_S32_LE:
 865                 iface |= 0x000c;
 866                 break;
 867         }
 868
 869         /* set iface & srate */
 870         snd_soc_write(codec, RT5621_AUDIO_INTERFACE, iface);
 871
 872         if (coeff >= 0)
 873                 snd_soc_write(codec, RT5621_STEREO_AD_DA_CLK_CTRL, coeff_div[coeff].regvalue);
 874         else
 875         {
 876                 printk(KERN_ERR "cant find matched sysclk and rate config\n");
 877                 return -EINVAL;
 878
 879         }
 880         return 0;
 881 }
 882
 883 static int rt5621_set_bias_level(struct snd_soc_codec *codec,
 884                         enum snd_soc_bias_level level)
 885 {
 886         switch (level) {
 887         case SND_SOC_BIAS_ON:
 888                 snd_soc_update_bits(codec, RT5621_SPK_OUT_VOL, RT_L_MUTE | RT_R_MUTE, 0);
 889                 snd_soc_update_bits(codec, RT5621_HP_OUT_VOL, RT_L_MUTE | RT_R_MUTE, 0);
 890                 break;
 891
 892         case SND_SOC_BIAS_PREPARE:
 893                 break;
 894
 895         case SND_SOC_BIAS_STANDBY:
 896                 snd_soc_update_bits(codec, RT5621_SPK_OUT_VOL, RT_L_MUTE | RT_R_MUTE, RT_L_MUTE | RT_R_MUTE);
 897                 snd_soc_update_bits(codec, RT5621_HP_OUT_VOL, RT_L_MUTE | RT_R_MUTE, RT_L_MUTE | RT_R_MUTE);
 898                 if (SND_SOC_BIAS_OFF == codec->dapm.bias_level) {
 899                         snd_soc_write(codec, RT5621_PWR_MANAG_ADD3, 0x8000);//enable Main bias
 900                         snd_soc_write(codec, RT5621_PWR_MANAG_ADD2, 0x2000);//enable Vref
 901                         codec->cache_only = false;
 902                         snd_soc_cache_sync(codec);
 903                 }
 904                 break;
 905
 906         case SND_SOC_BIAS_OFF:
 907                 snd_soc_update_bits(codec, RT5621_SPK_OUT_VOL, RT_L_MUTE | RT_R_MUTE, RT_L_MUTE | RT_R_MUTE);
 908                 snd_soc_update_bits(codec, RT5621_HP_OUT_VOL, RT_L_MUTE | RT_R_MUTE, RT_L_MUTE | RT_R_MUTE);
 909                 snd_soc_write(codec, RT5621_PWR_MANAG_ADD3, 0x0000);
 910                 snd_soc_write(codec, RT5621_PWR_MANAG_ADD2, 0x0000);
 911                 snd_soc_write(codec, RT5621_PWR_MANAG_ADD1, 0x0000);
 912                 break;
 913
 914         default:
 915                 break;
 916         }
 917         codec->dapm.bias_level = level;
 918
 919         return 0;
 920 }
 921
 922
 923
 924 struct rt5621_init_reg{
 925
 926         u8 reg_index;
 927         u16 reg_value;
 928 };
 929
 930 static struct rt5621_init_reg init_data[] = {
 931         {RT5621_AUDIO_INTERFACE,        0x8000},    //set I2S codec to slave mode
 932         {RT5621_STEREO_DAC_VOL,         0x0505},    //default stereo DAC volume to 0db
 933         {RT5621_OUTPUT_MIXER_CTRL,      0x2b40},    //default output mixer control
 934         {RT5621_ADC_REC_MIXER,          0x3f3f},    //set record source is Mic1 by default
 935         {RT5621_MIC_CTRL,               0x0a00},    //set Mic1,Mic2 boost 20db
 936         {RT5621_SPK_OUT_VOL,            0x8080},    //default speaker volume to 0db
 937         {RT5621_HP_OUT_VOL,             0x8080},    //default HP volume to -12db
 938         {RT5621_ADD_CTRL_REG,           0x4b00},    //Class AB/D speaker ratio is 1.25VDD
 939         {RT5621_STEREO_AD_DA_CLK_CTRL,  0x066d},    //set Dac filter to 256fs
 940         {RT5621_ADC_REC_GAIN,               0xfa95},    //set ADC boost to 15db
 941         {RT5621_HID_CTRL_INDEX,         0x46},      //Class D setting
 942         {RT5621_MIC_VOL,              0x1f08},
 943         {RT5621_HID_CTRL_DATA,          0xFFFF},    //power on Class D Internal register
 944         {RT5621_JACK_DET_CTRL,          0x4810},    //power on Class D Internal register
 945 };
 946 #define RT5621_INIT_REG_NUM ARRAY_SIZE(init_data)
 947
 948 static int rt5621_reg_init(struct snd_soc_codec *codec)
 949 {
 950         int i;
 951
 952         for (i = 0; i < RT5621_INIT_REG_NUM; i++)
 953                 snd_soc_write(codec, init_data[i].reg_index, init_data[i].reg_value);
 954
 955         return 0;
 956 }
 957
 958 void codec_set_spk(bool on)
 959 {
 960         struct snd_soc_codec *codec = rt5621_codec;
 961
 962         DBG("%s: %d\n", __func__, on);
 963
 964         if(!codec)
 965                 return;
 966
 967         if(on){
 968                 DBG("snd_soc_dapm_enable_pin\n");
 969                 snd_soc_dapm_enable_pin(&codec->dapm, "Headphone Jack");
 970                 snd_soc_dapm_enable_pin(&codec->dapm, "Ext Spk");
 971         }
 972         else{
 973
 974                 DBG("snd_soc_dapm_disable_pin\n");
 975                 snd_soc_dapm_disable_pin(&codec->dapm, "Headphone Jack");
 976                 snd_soc_dapm_disable_pin(&codec->dapm, "Ext Spk");
 977         }
 978
 979         snd_soc_dapm_sync(&codec->dapm);
 980
 981         return;
 982 }
 983
 984 static void rt5621_work(struct work_struct *work)
 985 {
 986         struct snd_soc_codec *codec = rt5621_codec;
 987
 988         rt5621_set_bias_level(codec, codec->dapm.bias_level);
 989 }
 990
 991 static int rt5621_probe(struct snd_soc_codec *codec)
 992 {
 993         int ret;
 994
 995         ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
 996         if (ret != 0) {
 997                 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
 998                 return ret;
 999         }
1000         codec->cache_bypass = 1;
1001
1002         rt5621_reset(codec);
1003         snd_soc_write(codec, RT5621_PWR_MANAG_ADD3, 0x8000);//enable Main bias
1004         snd_soc_write(codec, RT5621_PWR_MANAG_ADD2, 0x2000);//enable Vref
1005         hp_depop_mode2(codec);
1006         rt5621_reg_init(codec);
1007
1008 #if ENABLE_EQ_HREQ
1009
1010         rt5621_write_index_reg(codec, 0x11,0x1);
1011         rt5621_write_index_reg(codec, 0x12,0x1);
1012         rt5621_update_eqmode(codec, HFREQ);
1013
1014 #endif
1015         rt5621_workq = create_freezable_workqueue("rt5621");
1016         if (rt5621_workq == NULL) {
1017                 printk("wm8900_probe::create_freezeable_workqueue ERROR !");
1018                 kfree(codec);
1019                 return -ENOMEM;
1020         }
1021
1022         rt5621_set_bias_level(codec, SND_SOC_BIAS_PREPARE);
1023         codec->dapm.bias_level = SND_SOC_BIAS_STANDBY;
1024
1025         queue_delayed_work(rt5621_workq, &delayed_work,
1026                 msecs_to_jiffies(caps_charge));
1027
1028         codec->dapm.bias_level = SND_SOC_BIAS_STANDBY;
1029
1030         rt5621_codec = codec;
1031
1032         return 0;
1033 }
1034
1035 static int rt5621_remove(struct snd_soc_codec *codec)
1036 {
1037         rt5621_set_bias_level(codec, SND_SOC_BIAS_OFF);
1038
1039         cancel_delayed_work_sync(&delayed_work);
1040         return 0;
1041 }
1042
1043 #ifdef CONFIG_PM
1044 static int rt5621_suspend(struct snd_soc_codec *codec, pm_message_t state)
1045 {
1046         rt5621_set_bias_level(codec, SND_SOC_BIAS_OFF);
1047         return 0;
1048 }
1049
1050 static int rt5621_resume(struct snd_soc_codec *codec)
1051 {
1052
1053         rt5621_reset(codec);
1054         snd_soc_write(codec, RT5621_PWR_MANAG_ADD3, 0x8000);//enable Main bias
1055         snd_soc_write(codec, RT5621_PWR_MANAG_ADD2, 0x2000);//enable Vref
1056
1057         hp_depop_mode2(codec);
1058
1059         rt5621_reg_init(codec);
1060
1061 #if ENABLE_EQ_HREQ
1062
1063         rt5621_write_index_reg(codec, 0x11,0x1);
1064         rt5621_write_index_reg(codec, 0x12,0x1);
1065         rt5621_update_eqmode(codec, HFREQ);
1066 #endif
1067
1068         rt5621_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1069         if (codec->dapm.suspend_bias_level == SND_SOC_BIAS_ON) {
1070                 rt5621_set_bias_level(codec, SND_SOC_BIAS_PREPARE);
1071                 codec->dapm.bias_level = SND_SOC_BIAS_ON;
1072                 queue_delayed_work(rt5621_workq, &delayed_work,
1073                         msecs_to_jiffies(caps_charge));
1074         }
1075         return 0;
1076 }
1077 #else
1078 #define rt5621_suspend NULL
1079 #define rt5621_resume NULL
1080 #endif
1081
1082 static void rt5621_shutdown(struct snd_pcm_substream *substream,
1083                 struct snd_soc_dai *codec_dai)
1084 {
1085         struct snd_soc_codec *codec = codec_dai->codec;
1086         int stream = substream->stream;
1087
1088         switch (stream)
1089         {
1090                 case SNDRV_PCM_STREAM_PLAYBACK:
1091
1092                         rt5621_AudioOutEnable(codec,RT_WAVOUT_SPK,1);   //mute speaker out
1093
1094                         rt5621_AudioOutEnable(codec,RT_WAVOUT_HP,1);    //mute hp out
1095
1096                         rt5621_AudioOutEnable(codec,RT_WAVOUT_AUXOUT,1);        //mute auxout
1097
1098                         rt5621_ChangeCodecPowerStatus(codec,POWER_STATE_D2_PLAYBACK);   //power off dac to hp and speaker out and auxout
1099
1100
1101
1102                         break;
1103                 case SNDRV_PCM_STREAM_CAPTURE:
1104
1105                         Enable_ADC_Input_Source(codec,RT_WAVIN_L_MIC1|RT_WAVIN_R_MIC1,0);       //disable record source from mic1
1106
1107                         rt5621_ChangeCodecPowerStatus(codec,POWER_STATE_D2_RECORD);
1108
1109
1110                         break;
1111         }
1112 }
1113
1114 //#define RT5621_HIFI_RATES SNDRV_PCM_RATE_8000_48000
1115 #define RT5621_HIFI_RATES (SNDRV_PCM_RATE_44100) // zyy 20110704, playback and record use same sample rate
1116
1117 #define RT5621_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1118                 SNDRV_PCM_FMTBIT_S24_LE)
1119
1120 struct snd_soc_dai_ops rt5621_hifi_ops = {
1121         .hw_params = rt5621_pcm_hw_params,
1122         .set_fmt = rt5621_set_dai_fmt,
1123         .set_sysclk = rt5621_set_dai_sysclk,
1124         .set_pll = rt5621_set_dai_pll,
1125         .prepare = rt5621_pcm_hw_prepare,
1126         .shutdown = rt5621_shutdown,
1127 };
1128
1129 struct snd_soc_dai_driver rt5621_dai = {
1130         .name = "RT5621 HiFi",
1131         .playback = {
1132                 .stream_name = "HiFi Playback",
1133                 .channels_min = 1,
1134                 .channels_max = 2,
1135                 .rates = RT5621_HIFI_RATES,
1136                 .formats = RT5621_FORMATS,
1137         },
1138         .capture = {
1139                 .stream_name = "HiFi Capture",
1140                 .channels_min = 1,
1141                 .channels_max = 2,
1142                 .rates = RT5621_HIFI_RATES,
1143                 .formats = RT5621_FORMATS,
1144         },
1145         .ops = &rt5621_hifi_ops,
1146 };
1147
1148 static struct snd_soc_codec_driver soc_codec_dev_rt5621 = {
1149         .probe =        rt5621_probe,
1150         .remove = rt5621_remove,
1151         .suspend = rt5621_suspend,
1152         .resume = rt5621_resume,
1153         .set_bias_level = rt5621_set_bias_level,
1154         .reg_cache_size = RT5621_VENDOR_ID2 + 1,
1155         .reg_word_size = sizeof(u16),
1156         .reg_cache_default = rt5621_reg,
1157         .volatile_register = rt5621_volatile_register,
1158         .readable_register = rt5621_readable_register,
1159         .reg_cache_step = 1,
1160         .controls = rt5621_snd_controls,
1161         .num_controls = ARRAY_SIZE(rt5621_snd_controls),
1162 };
1163
1164 static const struct i2c_device_id rt5621_i2c_id[] = {
1165         { "rt5621", 0 },
1166         { }
1167 };
1168 MODULE_DEVICE_TABLE(i2c, rt5621_i2c_id);
1169
1170 static int rt5621_i2c_probe(struct i2c_client *i2c,
1171                     const struct i2c_device_id *id)
1172 {
1173         struct rt5621_priv *rt5621;
1174         int ret;
1175
1176         rt5621 = kzalloc(sizeof(struct rt5621_priv), GFP_KERNEL);
1177         if (NULL == rt5621)
1178                 return -ENOMEM;
1179
1180         i2c_set_clientdata(i2c, rt5621);
1181
1182         ret = snd_soc_register_codec(&i2c->dev,
1183                 &soc_codec_dev_rt5621, &rt5621_dai, 1);
1184         if (ret < 0)
1185                 kfree(rt5621);
1186
1187         return ret;
1188 }
1189
1190 static __devexit int rt5621_i2c_remove(struct i2c_client *i2c)
1191 {
1192         snd_soc_unregister_codec(&i2c->dev);
1193         kfree(i2c_get_clientdata(i2c));
1194         return 0;
1195 }
1196
1197 struct i2c_driver rt5621_i2c_driver = {
1198         .driver = {
1199                 .name = "RT5621",
1200                 .owner = THIS_MODULE,
1201         },
1202         .probe = rt5621_i2c_probe,
1203         .remove   = __devexit_p(rt5621_i2c_remove),
1204         .id_table = rt5621_i2c_id,
1205 };
1206
1207 static int __init rt5621_modinit(void)
1208 {
1209         return i2c_add_driver(&rt5621_i2c_driver);
1210 }
1211 module_init(rt5621_modinit);
1212
1213 static void __exit rt5621_modexit(void)
1214 {
1215         i2c_del_driver(&rt5621_i2c_driver);
1216 }
1217 module_exit(rt5621_modexit);
1218
1219 MODULE_DESCRIPTION("ASoC RT5621 driver");
1220 MODULE_AUTHOR("Johnny Hsu <johnnyhsu@realtek.com>");
1221 MODULE_LICENSE("GPL");