2 * rk3036.h -- RK312x CODEC ALSA SoC audio driver
4 * Copyright 2013 Rockship
5 * Author: chenjq <chenjq@rock-chips.com>
9 #ifndef __RK312x_CODEC_H__
10 #define __RK312x_CODEC_H__
15 #define RK312x_CODEC_BASE (0x0)
17 #define RK312x_RESET (RK312x_CODEC_BASE + 0x00)
18 #define RK312x_ADC_INT_CTL1 (RK312x_CODEC_BASE + 0x08)
19 #define RK312x_ADC_INT_CTL2 (RK312x_CODEC_BASE + 0x0c)
20 #define RK312x_DAC_INT_CTL1 (RK312x_CODEC_BASE + 0x10)
21 #define RK312x_DAC_INT_CTL2 (RK312x_CODEC_BASE + 0x14)
22 #define RK312x_DAC_INT_CTL3 (RK312x_CODEC_BASE + 0x18)
23 #define RK312x_ALC_CTL (RK312x_CODEC_BASE + 0x28)
24 #define RK312x_ADC_MIC_CTL (RK312x_CODEC_BASE + 0x88)
25 #define RK312x_BST_CTL (RK312x_CODEC_BASE + 0x8c)
26 #define RK312x_ALC_MUNIN_CTL (RK312x_CODEC_BASE + 0x90)
27 #define RK312x_BSTL_ALCL_CTL (RK312x_CODEC_BASE + 0x94)
28 #define RK312x_ALCR_GAIN_CTL (RK312x_CODEC_BASE + 0x98)
29 #define RK312x_ADC_ENABLE (RK312x_CODEC_BASE + 0x9c)
30 #define RK312x_DAC_CTL (RK312x_CODEC_BASE + 0xa0)
31 #define RK312x_DAC_ENABLE (RK312x_CODEC_BASE + 0xa4)
32 #define RK312x_HPMIX_CTL (RK312x_CODEC_BASE + 0xa8)
33 #define RK312x_HPMIX_S_SELECT (RK312x_CODEC_BASE + 0xac)
34 #define RK312x_HPOUT_CTL (RK312x_CODEC_BASE + 0xB0)
35 #define RK312x_HPOUTL_GAIN (RK312x_CODEC_BASE + 0xB4)
36 #define RK312x_HPOUTR_GAIN (RK312x_CODEC_BASE + 0xB8)
37 #define RK312x_SELECT_CURRENT (RK312x_CODEC_BASE + 0xBC)
38 #define RK312x_PGAL_AGC_CTL1 (RK312x_CODEC_BASE + 0x100)
39 #define RK312x_PGAL_AGC_CTL2 (RK312x_CODEC_BASE + 0x104)
40 #define RK312x_PGAL_AGC_CTL3 (RK312x_CODEC_BASE + 0x108)
41 #define RK312x_PGAL_AGC_CTL4 (RK312x_CODEC_BASE + 0x10c)
42 #define RK312x_PGAL_ASR_CTL (RK312x_CODEC_BASE + 0x110)
43 #define RK312x_PGAL_AGC_MAX_H (RK312x_CODEC_BASE + 0x114)
44 #define RK312x_PGAL_AGC_MAX_L (RK312x_CODEC_BASE + 0x118)
45 #define RK312x_PGAL_AGC_MIN_H (RK312x_CODEC_BASE + 0x11c)
46 #define RK312x_PGAL_AGC_MIN_L (RK312x_CODEC_BASE + 0x120)
47 #define RK312x_PGAL_AGC_CTL5 (RK312x_CODEC_BASE + 0x124)
48 #define RK312x_PGAR_AGC_CTL1 (RK312x_CODEC_BASE + 0x140)
49 #define RK312x_PGAR_AGC_CTL2 (RK312x_CODEC_BASE + 0x144)
50 #define RK312x_PGAR_AGC_CTL3 (RK312x_CODEC_BASE + 0x148)
51 #define RK312x_PGAR_AGC_CTL4 (RK312x_CODEC_BASE + 0x14c)
52 #define RK312x_PGAR_ASR_CTL (RK312x_CODEC_BASE + 0x150)
53 #define RK312x_PGAR_AGC_MAX_H (RK312x_CODEC_BASE + 0x154)
54 #define RK312x_PGAR_AGC_MAX_L (RK312x_CODEC_BASE + 0x158)
55 #define RK312x_PGAR_AGC_MIN_H (RK312x_CODEC_BASE + 0x15c)
56 #define RK312x_PGAR_AGC_MIN_L (RK312x_CODEC_BASE + 0x160)
57 #define RK312x_PGAR_AGC_CTL5 (RK312x_CODEC_BASE + 0x164)
59 /* ADC Interface Control 1 (0x08) */
60 #define RK312x_ALRCK_POL_MASK (0x1 << 7)
61 #define RK312x_ALRCK_POL_SFT 7
62 #define RK312x_ALRCK_POL_EN (0x1 << 7)
63 #define RK312x_ALRCK_POL_DIS (0x0 << 7)
65 #define RK312x_ADC_VWL_MASK (0x3 << 5)
66 #define RK312x_ADC_VWL_SFT 5
67 #define RK312x_ADC_VWL_32 (0x3 << 5)
68 #define RK312x_ADC_VWL_24 (0x2 << 5)
69 #define RK312x_ADC_VWL_20 (0x1 << 5)
70 #define RK312x_ADC_VWL_16 (0x0 << 5)
72 #define RK312x_ADC_DF_MASK (0x3 << 3)
73 #define RK312x_ADC_DF_SFT 3
74 #define RK312x_ADC_DF_PCM (0x3 << 3)
75 #define RK312x_ADC_DF_I2S (0x2 << 3)
76 #define RK312x_ADC_DF_LJ (0x1 << 3)
77 #define RK312x_ADC_DF_RJ (0x0 << 3)
79 #define RK312x_ADC_SWAP_MASK (0x1 << 1)
80 #define RK312x_ADC_SWAP_SFT 1
81 #define RK312x_ADC_SWAP_EN (0x1 << 1)
82 #define RK312x_ADC_SWAP_DIS (0x0 << 1)
84 #define RK312x_ADC_TYPE_MASK 0x1
85 #define RK312x_ADC_TYPE_SFT 0
86 #define RK312x_ADC_TYPE_MONO 0x1
87 #define RK312x_ADC_TYPE_STEREO 0x0
89 /* ADC Interface Control 2 (0x0c) */
90 #define RK312x_I2S_MODE_MASK (0x1 << 4)
91 #define RK312x_I2S_MODE_SFT (4)
92 #define RK312x_I2S_MODE_MST (0x1 << 4)
93 #define RK312x_I2S_MODE_SLV (0x0 << 4)
95 #define RK312x_ADC_WL_MASK (0x3 << 2)
96 #define RK312x_ADC_WL_SFT (2)
97 #define RK312x_ADC_WL_32 (0x3 << 2)
98 #define RK312x_ADC_WL_24 (0x2 << 2)
99 #define RK312x_ADC_WL_20 (0x1 << 2)
100 #define RK312x_ADC_WL_16 (0x0 << 2)
102 #define RK312x_ADC_RST_MASK (0x1 << 1)
103 #define RK312x_ADC_RST_SFT (1)
104 #define RK312x_ADC_RST_DIS (0x1 << 1)
105 #define RK312x_ADC_RST_EN (0x0 << 1)
107 #define RK312x_ABCLK_POL_MASK 0x1
108 #define RK312x_ABCLK_POL_SFT 0
109 #define RK312x_ABCLK_POL_EN 0x1
110 #define RK312x_ABCLK_POL_DIS 0x0
112 /* DAC Interface Control 1 (0x10) */
113 #define RK312x_DLRCK_POL_MASK (0x1 << 7)
114 #define RK312x_DLRCK_POL_SFT 7
115 #define RK312x_DLRCK_POL_EN (0x1 << 7)
116 #define RK312x_DLRCK_POL_DIS (0x0 << 7)
118 #define RK312x_DAC_VWL_MASK (0x3 << 5)
119 #define RK312x_DAC_VWL_SFT 5
120 #define RK312x_DAC_VWL_32 (0x3 << 5)
121 #define RK312x_DAC_VWL_24 (0x2 << 5)
122 #define RK312x_DAC_VWL_20 (0x1 << 5)
123 #define RK312x_DAC_VWL_16 (0x0 << 5)
125 #define RK312x_DAC_DF_MASK (0x3 << 3)
126 #define RK312x_DAC_DF_SFT 3
127 #define RK312x_DAC_DF_PCM (0x3 << 3)
128 #define RK312x_DAC_DF_I2S (0x2 << 3)
129 #define RK312x_DAC_DF_LJ (0x1 << 3)
130 #define RK312x_DAC_DF_RJ (0x0 << 3)
132 #define RK312x_DAC_SWAP_MASK (0x1 << 2)
133 #define RK312x_DAC_SWAP_SFT 2
134 #define RK312x_DAC_SWAP_EN (0x1 << 2)
135 #define RK312x_DAC_SWAP_DIS (0x0 << 2)
137 /* DAC Interface Control 2 (0x14) */
138 #define RK312x_DAC_WL_MASK (0x3 << 2)
139 #define RK312x_DAC_WL_SFT 2
140 #define RK312x_DAC_WL_32 (0x3 << 2)
141 #define RK312x_DAC_WL_24 (0x2 << 2)
142 #define RK312x_DAC_WL_20 (0x1 << 2)
143 #define RK312x_DAC_WL_16 (0x0 << 2)
145 #define RK312x_DAC_RST_MASK (0x1 << 1)
146 #define RK312x_DAC_RST_SFT 1
147 #define RK312x_DAC_RST_DIS (0x1 << 1)
148 #define RK312x_DAC_RST_EN (0x0 << 1)
150 #define RK312x_DBCLK_POL_MASK 0x1
151 #define RK312x_DBCLK_POL_SFT 0
152 #define RK312x_DBCLK_POL_EN 0x1
153 #define RK312x_DBCLK_POL_DIS 0x0
155 /* ADC & MICBIAS (0x88) */
156 #define RK312x_ADC_CURRENT_ENABLE (0x1 << 7)
157 #define RK312x_ADC_CURRENT_DISABLE (0x0 << 7)
159 #define RK312x_MICBIAS_VOL_ENABLE (6)
161 #define RK312x_ADCL_ZERO_DET_EN_SFT (5)
162 #define RK312x_ADCL_ZERO_DET_EN (0x1 << 5)
163 #define RK312x_ADCL_ZERO_DET_DIS (0x0 << 5)
165 #define RK312x_ADCR_ZERO_DET_EN_SFT (4)
166 #define RK312x_ADCR_ZERO_DET_EN (0x1 << 4)
167 #define RK312x_ADCR_ZERO_DET_DIS (0x0 << 4)
169 #define RK312x_MICBIAS_VOL_SHT 0
170 #define RK312x_MICBIAS_VOL_MSK 7
171 #define RK312x_MICBIAS_VOL_MIN (0x0 << 0)
172 #define RK312x_MICBIAS_VOL_MAX (0x7 << 0)
174 /* BST_L BST_R CONTROL (0x8C) */
175 #define RK312x_BSTL_PWRD_SFT (6)
176 #define RK312x_BSTL_EN (0x1 << 6)
177 #define RK312x_BSTL_DIS (0x0 << 6)
178 #define RK312x_BSTL_GAIN_SHT (5)
179 #define RK312x_BSTL_GAIN_20 (0x1 << 5)
180 #define RK312x_BSTL_GAIN_0 (0x0 << 5)
181 #define RK312x_BSTL_MUTE_SHT (4)
183 #define RK312x_BSTR_PWRD_SFT (2)
184 #define RK312x_BSTR_EN (0x1 << 2)
185 #define RK312x_BSTR_DIS (0x0 << 2)
186 #define RK312x_BSTR_GAIN_SHT (1)
187 #define RK312x_BSTR_GAIN_20 (0x1 << 1)
188 #define RK312x_BSTR_GAIN_0 (0x0 << 1)
189 #define RK312x_BSTR_MUTE_SHT (0)
192 /* MUXINL ALCL MUXINR ALCR (0x90) */
193 #define RK312x_MUXINL_F_SHT (6)
194 #define RK312x_MUXINL_F_MSK (0x03 << 6)
195 #define RK312x_MUXINL_F_INL (0x02 << 6)
196 #define RK312x_MUXINL_F_BSTL (0x01 << 6)
197 #define RK312x_ALCL_PWR_SHT (5)
198 #define RK312x_ALCL_EN (0x1 << 5)
199 #define RK312x_ALCL_DIS (0x0 << 5)
200 #define RK312x_ALCL_MUTE_SHT (4)
201 #define RK312x_MUXINR_F_SHT (2)
202 #define RK312x_MUXINR_F_MSK (0x03 << 2)
203 #define RK312x_MUXINR_F_INR (0x02 << 2)
204 #define RK312x_MUXINR_F_BSTR (0x01 << 2)
205 #define RK312x_ALCR_PWR_SHT (1)
206 #define RK312x_ALCR_EN (0x1 << 1)
207 #define RK312x_ALCR_DIS (0x0 << 1)
208 #define RK312x_ALCR_MUTE_SHT (0)
210 /* BST_L MODE & ALC_L GAIN (0x94) */
211 #define RK312x_BSTL_MODE_SFT (5)
212 #define RK312x_BSTL_MODE_SINGLE (0x1 << 5)
213 #define RK312x_BSTL_MODE_DIFF (0x0 << 5)
215 #define RK312x_ALCL_GAIN_SHT (0)
216 #define RK312x_ALCL_GAIN_MSK (0x1f)
218 /* ALC_R GAIN (0x98) */
219 #define RK312x_ALCR_GAIN_SHT (0)
220 #define RK312x_ALCR_GAIN_MSK (0x1f)
222 /* ADC control (0x9C) */
223 #define RK312x_ADCL_REF_VOL_EN_SFT (3)
224 #define RK312x_ADCL_REF_VOL_EN (0x1 << 7)
225 #define RK312x_ADCL_REF_VOL_DIS (0x0 << 7)
227 #define RK312x_ADCL_CLK_EN_SFT (6)
228 #define RK312x_ADCL_CLK_EN (0x1 << 6)
229 #define RK312x_ADCL_CLK_DIS (0x0 << 6)
231 #define RK312x_ADCL_AMP_EN_SFT (5)
232 #define RK312x_ADCL_AMP_EN (0x1 << 5)
233 #define RK312x_ADCL_AMP_DIS (0x0 << 5)
235 #define RK312x_ADCL_RST_EN (0x1 << 4)
236 #define RK312x_ADCL_RST_DIS (0x0 << 4)
238 #define RK312x_ADCR_REF_VOL_EN_SFT (3)
239 #define RK312x_ADCR_REF_VOL_EN (0x1 << 3)
240 #define RK312x_ADCR_REF_VOL_DIS (0x0 << 3)
242 #define RK312x_ADCR_CLK_EN_SFT (2)
243 #define RK312x_ADCR_CLK_EN (0x1 << 2)
244 #define RK312x_ADCR_CLK_DIS (0x0 << 2)
246 #define RK312x_ADCR_AMP_EN_SFT (1)
247 #define RK312x_ADCR_AMP_EN (0x1 << 1)
248 #define RK312x_ADCR_AMP_DIS (0x0 << 1)
250 #define RK312x_ADCR_RST_EN (0x1 << 0)
251 #define RK312x_ADCR_RST_DIS (0x0 << 0)
253 /* DAC & VOUT Control (0xa0) */
254 #define RK312x_CURRENT_EN (0x1 << 6)
255 #define RK312x_CURRENT_DIS (0x0 << 6)
256 #define RK312x_REF_VOL_DACL_EN_SFT (5)
257 #define RK312x_REF_VOL_DACL_EN (0x1 << 5)
258 #define RK312x_REF_VOL_DACL_DIS (0x0 << 5)
259 #define RK312x_ZO_DET_VOUTL_SFT (4)
260 #define RK312x_ZO_DET_VOUTL_EN (0x1 << 4)
261 #define RK312x_ZO_DET_VOUTL_DIS (0x0 << 4)
262 #define RK312x_DET_ERAPHONE_DIS (0x0 << 3)
263 #define RK312x_DET_ERAPHONE_EN (0x1 << 3)
264 #define RK312x_REF_VOL_DACR_EN_SFT (1)
265 #define RK312x_REF_VOL_DACR_EN (0x1 << 1)
266 #define RK312x_REF_VOL_DACR_DIS (0x0 << 1)
267 #define RK312x_ZO_DET_VOUTR_SFT (0)
268 #define RK312x_ZO_DET_VOUTR_EN (0x1 << 0)
269 #define RK312x_ZO_DET_VOUTR_DIS (0x0 << 0)
271 /* DAC control (0xa4) */
272 #define RK312x_DACL_REF_VOL_EN_SFT (7)
273 #define RK312x_DACL_REF_VOL_EN (0x1 << 7)
274 #define RK312x_DACL_REF_VOL_DIS (0x0 << 7)
276 #define RK312x_DACL_CLK_EN (0x1 << 6)
277 #define RK312x_DACL_CLK_DIS (0x0 << 6)
279 #define RK312x_DACL_EN (0x1 << 5)
280 #define RK312x_DACL_DIS (0x0 << 5)
282 #define RK312x_DACL_INIT (0x0 << 4)
283 #define RK312x_DACL_WORK (0x1 << 4)
285 #define RK312x_DACR_REF_VOL_EN_SFT (3)
286 #define RK312x_DACR_REF_VOL_EN (0x1 << 3)
287 #define RK312x_DACR_REF_VOL_DIS (0x0 << 3)
289 #define RK312x_DACR_CLK_EN (0x1 << 2)
290 #define RK312x_DACR_CLK_DIS (0x0 << 2)
292 #define RK312x_DACR_EN (0x1 << 1)
293 #define RK312x_DACR_DIS (0x0 << 1)
295 #define RK312x_DACR_INIT (0x0 << 0)
296 #define RK312x_DACR_WORK (0x1 << 0)
298 /* HPMIXL HPMIXR Control (0xa8) */
299 #define RK312x_HPMIXL_SFT (6)
300 #define RK312x_HPMIXL_EN (0x1 << 6)
301 #define RK312x_HPMIXL_DIS (0x0 << 6)
302 #define RK312x_HPMIXL_INIT1 (0x0 << 5)
303 #define RK312x_HPMIXL_WORK1 (0x1 << 5)
304 #define RK312x_HPMIXL_INIT2 (0x0 << 4)
305 #define RK312x_HPMIXL_WORK2 (0x1 << 4)
306 #define RK312x_HPMIXR_SFT (2)
307 #define RK312x_HPMIXR_EN (0x1 << 2)
308 #define RK312x_HPMIXR_DIS (0x0 << 2)
309 #define RK312x_HPMIXR_INIT1 (0x0 << 1)
310 #define RK312x_HPMIXR_WORK1 (0x1 << 1)
311 #define RK312x_HPMIXR_INIT2 (0x0 << 0)
312 #define RK312x_HPMIXR_WORK2 (0x1 << 0)
314 /* HPMIXL Control (0xac) */
315 #define RK312x_HPMIXL_BYPASS_SFT (7)
316 #define RK312x_HPMIXL_SEL_ALCL_SFT (6)
317 #define RK312x_HPMIXL_SEL_ALCR_SFT (5)
318 #define RK312x_HPMIXL_SEL_DACL_SFT (4)
319 #define RK312x_HPMIXR_BYPASS_SFT (3)
320 #define RK312x_HPMIXR_SEL_ALCL_SFT (2)
321 #define RK312x_HPMIXR_SEL_ALCR_SFT (1)
322 #define RK312x_HPMIXR_SEL_DACR_SFT (0)
324 /* HPOUT Control (0xb0) */
325 #define RK312x_HPOUTL_PWR_SHT (7)
326 #define RK312x_HPOUTL_MSK (0x1 << 7)
327 #define RK312x_HPOUTL_EN (0x1 << 7)
328 #define RK312x_HPOUTL_DIS (0x0 << 7)
329 #define RK312x_HPOUTL_INIT_MSK (0x1 << 6)
330 #define RK312x_HPOUTL_INIT (0x0 << 6)
331 #define RK312x_HPOUTL_WORK (0x1 << 6)
332 #define RK312x_HPOUTL_MUTE_SHT (5)
333 #define RK312x_HPOUTL_MUTE_MSK (0x1 << 5)
334 #define RK312x_HPOUTL_MUTE_EN (0x0 << 5)
335 #define RK312x_HPOUTL_MUTE_DIS (0x1 << 5)
336 #define RK312x_HPOUTR_PWR_SHT (4)
337 #define RK312x_HPOUTR_MSK (0x1 << 4)
338 #define RK312x_HPOUTR_EN (0x1 << 4)
339 #define RK312x_HPOUTR_DIS (0x0 << 4)
340 #define RK312x_HPOUTR_INIT_MSK (0x1 << 3)
341 #define RK312x_HPOUTR_WORK (0x1 << 3)
342 #define RK312x_HPOUTR_INIT (0x0 << 3)
343 #define RK312x_HPOUTR_MUTE_SHT (2)
344 #define RK312x_HPOUTR_MUTE_MSK (0x1 << 2)
345 #define RK312x_HPOUTR_MUTE_EN (0x0 << 2)
346 #define RK312x_HPOUTR_MUTE_DIS (0x1 << 2)
348 #define RK312x_HPVREF_PWR_SHT (1)
349 #define RK312x_HPVREF_EN (0x1 << 1)
350 #define RK312x_HPVREF_DIS (0x0 << 1)
351 #define RK312x_HPVREF_WORK (0x1 << 0)
352 #define RK312x_HPVREF_INIT (0x0 << 0)
354 /* HPOUT GAIN (0xb4 0xb8) */
355 #define RK312x_HPOUT_GAIN_SFT (0)
357 /* SELECT CURR prechagrge/discharge (0xbc) */
358 #define RK312x_PRE_HPOUT (0x1 << 5)
359 #define RK312x_DIS_HPOUT (0x0 << 5)
360 #define RK312x_CUR_10UA_EN (0x0 << 4)
361 #define RK312x_CUR_10UA_DIS (0x1 << 4)
362 #define RK312x_CUR_I_EN (0x0 << 3)
363 #define RK312x_CUR_I_DIS (0x1 << 3)
364 #define RK312x_CUR_2I_EN (0x0 << 2)
365 #define RK312x_CUR_2I_DIS (0x1 << 2)
366 #define RK312x_CUR_4I_EN (0x0 << 0)
367 #define RK312x_CUR_4I_DIS (0x3 << 0)
369 /* PGA AGC control 1 (0xc0 0x100) */
370 #define RK312x_PGA_AGC_WAY_MASK (0x1 << 6)
371 #define RK312x_PGA_AGC_WAY_SFT 6
372 #define RK312x_PGA_AGC_WAY_JACK (0x1 << 6)
373 #define RK312x_PGA_AGC_WAY_NOR (0x0 << 6)
375 #define RK312x_PGA_AGC_BK_WAY_SFT 4
376 #define RK312x_PGA_AGC_BK_WAY_JACK1 (0x1 << 4)
377 #define RK312x_PGA_AGC_BK_WAY_NOR (0x0 << 4)
378 #define RK312x_PGA_AGC_BK_WAY_JACK2 (0x2 << 4)
379 #define RK312x_PGA_AGC_BK_WAY_JACK3 (0x3 << 4)
381 #define RK312x_PGA_AGC_HOLD_T_MASK 0xf
382 #define RK312x_PGA_AGC_HOLD_T_SFT 0
383 #define RK312x_PGA_AGC_HOLD_T_1024 0xa
384 #define RK312x_PGA_AGC_HOLD_T_512 0x9
385 #define RK312x_PGA_AGC_HOLD_T_256 0x8
386 #define RK312x_PGA_AGC_HOLD_T_128 0x7
387 #define RK312x_PGA_AGC_HOLD_T_64 0x6
388 #define RK312x_PGA_AGC_HOLD_T_32 0x5
389 #define RK312x_PGA_AGC_HOLD_T_16 0x4
390 #define RK312x_PGA_AGC_HOLD_T_8 0x3
391 #define RK312x_PGA_AGC_HOLD_T_4 0x2
392 #define RK312x_PGA_AGC_HOLD_T_2 0x1
393 #define RK312x_PGA_AGC_HOLD_T_0 0x0
395 /* PGA AGC control 2 (0xc4 0x104) */
396 #define RK312x_PGA_AGC_GRU_T_MASK (0xf << 4)
397 #define RK312x_PGA_AGC_GRU_T_SFT 4
398 #define RK312x_PGA_AGC_GRU_T_512 (0xa << 4)
399 #define RK312x_PGA_AGC_GRU_T_256 (0x9 << 4)
400 #define RK312x_PGA_AGC_GRU_T_128 (0x8 << 4)
401 #define RK312x_PGA_AGC_GRU_T_64 (0x7 << 4)
402 #define RK312x_PGA_AGC_GRU_T_32 (0x6 << 4)
403 #define RK312x_PGA_AGC_GRU_T_16 (0x5 << 4)
404 #define RK312x_PGA_AGC_GRU_T_8 (0x4 << 4)
405 #define RK312x_PGA_AGC_GRU_T_4 (0x3 << 4)
406 #define RK312x_PGA_AGC_GRU_T_2 (0x2 << 4)
407 #define RK312x_PGA_AGC_GRU_T_1 (0x1 << 4)
408 #define RK312x_PGA_AGC_GRU_T_0_5 (0x0 << 4)
410 #define RK312x_PGA_AGC_GRD_T_MASK 0xf
411 #define RK312x_PGA_AGC_GRD_T_SFT 0
412 #define RK312x_PGA_AGC_GRD_T_128_32 0xa
413 #define RK312x_PGA_AGC_GRD_T_64_16 0x9
414 #define RK312x_PGA_AGC_GRD_T_32_8 0x8
415 #define RK312x_PGA_AGC_GRD_T_16_4 0x7
416 #define RK312x_PGA_AGC_GRD_T_8_2 0x6
417 #define RK312x_PGA_AGC_GRD_T_4_1 0x5
418 #define RK312x_PGA_AGC_GRD_T_2_0_512 0x4
419 #define RK312x_PGA_AGC_GRD_T_1_0_256 0x3
420 #define RK312x_PGA_AGC_GRD_T_0_500_128 0x2
421 #define RK312x_PGA_AGC_GRD_T_0_250_64 0x1
422 #define RK312x_PGA_AGC_GRD_T_0_125_32 0x0
424 /* PGA AGC control 3 (0xc8 0x108) */
425 #define RK312x_PGA_AGC_MODE_MASK (0x1 << 7)
426 #define RK312x_PGA_AGC_MODE_SFT 7
427 #define RK312x_PGA_AGC_MODE_LIMIT (0x1 << 7)
428 #define RK312x_PGA_AGC_MODE_NOR (0x0 << 7)
430 #define RK312x_PGA_AGC_ZO_MASK (0x1 << 6)
431 #define RK312x_PGA_AGC_ZO_SFT 6
432 #define RK312x_PGA_AGC_ZO_EN (0x1 << 6)
433 #define RK312x_PGA_AGC_ZO_DIS (0x0 << 6)
435 #define RK312x_PGA_AGC_REC_MODE_MASK (0x1 << 5)
436 #define RK312x_PGA_AGC_REC_MODE_SFT 5
437 #define RK312x_PGA_AGC_REC_MODE_AC (0x1 << 5)
438 #define RK312x_PGA_AGC_REC_MODE_RN (0x0 << 5)
440 #define RK312x_PGA_AGC_FAST_D_MASK (0x1 << 4)
441 #define RK312x_PGA_AGC_FAST_D_SFT 4
442 #define RK312x_PGA_AGC_FAST_D_EN (0x1 << 4)
443 #define RK312x_PGA_AGC_FAST_D_DIS (0x0 << 4)
445 #define RK312x_PGA_AGC_NG_MASK (0x1 << 3)
446 #define RK312x_PGA_AGC_NG_SFT 3
447 #define RK312x_PGA_AGC_NG_EN (0x1 << 3)
448 #define RK312x_PGA_AGC_NG_DIS (0x0 << 3)
450 #define RK312x_PGA_AGC_NG_THR_MASK 0x7
451 #define RK312x_PGA_AGC_NG_THR_SFT 0
452 #define RK312x_PGA_AGC_NG_THR_N81DB 0x7
453 #define RK312x_PGA_AGC_NG_THR_N75DB 0x6
454 #define RK312x_PGA_AGC_NG_THR_N69DB 0x5
455 #define RK312x_PGA_AGC_NG_THR_N63DB 0x4
456 #define RK312x_PGA_AGC_NG_THR_N57DB 0x3
457 #define RK312x_PGA_AGC_NG_THR_N51DB 0x2
458 #define RK312x_PGA_AGC_NG_THR_N45DB 0x1
459 #define RK312x_PGA_AGC_NG_THR_N39DB 0x0
461 /* PGA AGC Control 4 (0xcc 0x10c) */
462 #define RK312x_PGA_AGC_ZO_MODE_MASK (0x1 << 5)
463 #define RK312x_PGA_AGC_ZO_MODE_SFT 5
464 #define RK312x_PGA_AGC_ZO_MODE_UWRC (0x1 << 5)
465 #define RK312x_PGA_AGC_ZO_MODE_UARC (0x0 << 5)
467 #define RK312x_PGA_AGC_VOL_MASK 0x1f
468 #define RK312x_PGA_AGC_VOL_SFT 0
470 /* PGA ASR Control (0xd0 0x110) */
471 #define RK312x_PGA_SLOW_CLK_MASK (0x1 << 3)
472 #define RK312x_PGA_SLOW_CLK_SFT 3
473 #define RK312x_PGA_SLOW_CLK_EN (0x1 << 3)
474 #define RK312x_PGA_SLOW_CLK_DIS (0x0 << 3)
476 #define RK312x_PGA_ASR_MASK 0x7
477 #define RK312x_PGA_ASR_SFT 0
478 #define RK312x_PGA_ASR_8KHz 0x7
479 #define RK312x_PGA_ASR_12KHz 0x6
480 #define RK312x_PGA_ASR_16KHz 0x5
481 #define RK312x_PGA_ASR_24KHz 0x4
482 #define RK312x_PGA_ASR_32KHz 0x3
483 #define RK312x_PGA_ASR_441KHz 0x2
484 #define RK312x_PGA_ASR_48KHz 0x1
485 #define RK312x_PGA_ASR_96KHz 0x0
487 /* PGA AGC Control 5 (0xe4 0x124) */
488 #define RK312x_PGA_AGC_MASK (0x1 << 6)
489 #define RK312x_PGA_AGC_SFT 6
490 #define RK312x_PGA_AGC_EN (0x1 << 6)
491 #define RK312x_PGA_AGC_DIS (0x0 << 6)
493 #define RK312x_PGA_AGC_MAX_G_MASK (0x7 << 3)
494 #define RK312x_PGA_AGC_MAX_G_SFT 3
495 #define RK312x_PGA_AGC_MAX_G_28_5DB (0x7 << 3)
496 #define RK312x_PGA_AGC_MAX_G_22_5DB (0x6 << 3)
497 #define RK312x_PGA_AGC_MAX_G_16_5DB (0x5 << 3)
498 #define RK312x_PGA_AGC_MAX_G_10_5DB (0x4 << 3)
499 #define RK312x_PGA_AGC_MAX_G_4_5DB (0x3 << 3)
500 #define RK312x_PGA_AGC_MAX_G_N1_5DB (0x2 << 3)
501 #define RK312x_PGA_AGC_MAX_G_N7_5DB (0x1 << 3)
502 #define RK312x_PGA_AGC_MAX_G_N13_5DB (0x0 << 3)
504 #define RK312x_PGA_AGC_MIN_G_MASK 0x7
505 #define RK312x_PGA_AGC_MIN_G_SFT 0
506 #define RK312x_PGA_AGC_MIN_G_24DB 0x7
507 #define RK312x_PGA_AGC_MIN_G_18DB 0x6
508 #define RK312x_PGA_AGC_MIN_G_12DB 0x5
509 #define RK312x_PGA_AGC_MIN_G_6DB 0x4
510 #define RK312x_PGA_AGC_MIN_G_0DB 0x3
511 #define RK312x_PGA_AGC_MIN_G_N6DB 0x2
512 #define RK312x_PGA_AGC_MIN_G_N12DB 0x1
513 #define RK312x_PGA_AGC_MIN_G_N18DB 0x0
546 struct rk312x_reg_val_typ {
551 struct rk312x_init_bit_typ {
553 unsigned int power_bit;
554 unsigned int init2_bit;
555 unsigned int init1_bit;
556 unsigned int init0_bit;
559 struct rk312x_codec_pdata {
565 #endif /* __RK312x_CODEC_H__ */