sound/soc/codecs/rk312x_codec.c

   1 /*
   2  * rk312x_codec.c
   3  *
   4  * Driver for rockchip rk3036 codec
   5  * Copyright (C) 2014
   6  *
   7  * This program is free software; you can redistribute  it and/or modify it
   8  * under  the terms of  the GNU General  Public License as published by the
   9  * Free Software Foundation;  either version 2 of the  License, or (at your
  10  * option) any later version.
  11  *
  12  *
  13  */
  14 #include <linux/init.h>
  15 #include <linux/module.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/device.h>
  18 #include <linux/delay.h>
  19 #include <linux/clk.h>
  20 #include <linux/version.h>
  21 #include <linux/of.h>
  22 #include <linux/of_gpio.h>
  23 #include <linux/clk.h>
  24 #include <linux/io.h>
  25 #include <linux/rockchip/iomap.h>
  26 #include <linux/rockchip/grf.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/regmap.h>
  30 #include <linux/slab.h>
  31 #include <asm/dma.h>
  32 #include <sound/core.h>
  33 #include <sound/pcm.h>
  34 #include <sound/pcm_params.h>
  35 #include <sound/initval.h>
  36 #include <sound/soc.h>
  37 #include <sound/soc-dapm.h>
  38 #include <sound/dmaengine_pcm.h>
  39 #include <linux/io.h>
  40 #include <linux/spinlock.h>
  41 #include <sound/tlv.h>
  42 #include <linux/switch.h>
  43 #include "rk312x_codec.h"
  44
  45 static int debug = -1;
  46 module_param(debug, int, S_IRUGO|S_IWUSR);
  47
  48 #define dbg_codec(level, fmt, arg...)           \
  49         do {                                    \
  50                 if (debug >= level)             \
  51                         printk(fmt , ## arg);   \
  52          } while (0)
  53
  54 #define DBG(fmt, ...)   dbg_codec(0, fmt, ## __VA_ARGS__)
  55
  56 #define INVALID_GPIO   -1
  57 #define CODEC_SET_SPK 1
  58 #define CODEC_SET_HP 2
  59 #define SWITCH_SPK 1
  60 #define BIT_HEADSET             (1 << 0)
  61 #define BIT_HEADSET_NO_MIC      (1 << 1)
  62 #define GRF_ACODEC_CON  0x013c
  63 #define GRF_SOC_STATUS0 0x014c
  64 /* volume setting
  65  *  0: -39dB
  66  *  26: 0dB
  67  *  31: 6dB
  68  *  Step: 1.5dB
  69 */
  70 #define  OUT_VOLUME    25
  71
  72 /* capture vol set
  73  * 0: -18db
  74  * 12: 0db
  75  * 31: 28.5db
  76  * step: 1.5db
  77 */
  78 #define CAP_VOL         26      /*0-31 */
  79 /*with capacity or not*/
  80 #define WITH_CAP
  81
  82 struct rk312x_codec_priv {
  83         void __iomem    *regbase;
  84         struct snd_soc_codec *codec;
  85
  86         unsigned int stereo_sysclk;
  87         unsigned int rate;
  88
  89         int playback_active;
  90         int capture_active;
  91         int spk_ctl_gpio;
  92         int hp_ctl_gpio;
  93         int spk_mute_delay;
  94         int hp_mute_delay;
  95         int spk_hp_switch_gpio;
  96         /* 1 spk; */
  97         /* 0 hp; */
  98         enum of_gpio_flags spk_io;
  99
 100         /* 0 for box; */
 101         /* 1 default for mid; */
 102         int rk312x_for_mid;
 103         /* 1: for rk3128 */
 104         /* 0: for rk3126 */
 105         int is_rk3128;
 106         int gpio_debug;
 107         int codec_hp_det;
 108         enum of_gpio_flags hp_active_level;
 109         enum of_gpio_flags spk_active_level;
 110         unsigned int spk_volume;
 111         unsigned int hp_volume;
 112         unsigned int capture_volume;
 113
 114         long int playback_path;
 115         long int capture_path;
 116         long int voice_call_path;
 117         struct clk      *pclk;
 118         struct switch_dev sdev;
 119         struct timer_list timer;
 120         struct work_struct work;
 121 };
 122 static struct rk312x_codec_priv *rk312x_priv;
 123
 124 #define RK312x_CODEC_ALL        0
 125 #define RK312x_CODEC_PLAYBACK   1
 126 #define RK312x_CODEC_CAPTURE    2
 127 #define RK312x_CODEC_INCALL     3
 128
 129 #define RK312x_CODEC_WORK_NULL  0
 130 #define RK312x_CODEC_WORK_POWER_DOWN    1
 131 #define RK312x_CODEC_WORK_POWER_UP      2
 132 static struct workqueue_struct *rk312x_codec_workq;
 133
 134 static void rk312x_codec_capture_work(struct work_struct *work);
 135 static DECLARE_DELAYED_WORK(capture_delayed_work, rk312x_codec_capture_work);
 136 static int rk312x_codec_work_capture_type = RK312x_CODEC_WORK_NULL;
 137 /* static bool rk312x_for_mid = 1; */
 138 static int rk312x_codec_power_up(int type);
 139 static const unsigned int rk312x_reg_defaults[RK312x_PGAR_AGC_CTL5+1] = {
 140         [RK312x_RESET] = 0x0003,
 141         [RK312x_ADC_INT_CTL1] = 0x0050,
 142         [RK312x_ADC_INT_CTL2] = 0x000e,
 143         [RK312x_DAC_INT_CTL1] = 0x0050,
 144         [RK312x_DAC_INT_CTL2] = 0x000e,
 145         [RK312x_DAC_INT_CTL3] = 0x22,
 146         [RK312x_ADC_MIC_CTL] = 0x0000,
 147         [RK312x_BST_CTL] = 0x000,
 148         [RK312x_ALC_MUNIN_CTL] = 0x0044,
 149         [RK312x_BSTL_ALCL_CTL] = 0x000c,
 150         [RK312x_ALCR_GAIN_CTL] = 0x000C,
 151         [RK312x_ADC_ENABLE] = 0x0000,
 152         [RK312x_DAC_CTL] = 0x0000,
 153         [RK312x_DAC_ENABLE] = 0x0000,
 154         [RK312x_HPMIX_CTL] = 0x0000,
 155         [RK312x_HPMIX_S_SELECT] = 0x0000,
 156         [RK312x_HPOUT_CTL] = 0x0000,
 157         [RK312x_HPOUTL_GAIN] = 0x0000,
 158         [RK312x_HPOUTR_GAIN] = 0x0000,
 159         [RK312x_SELECT_CURRENT] = 0x003e,
 160         [RK312x_PGAL_AGC_CTL1] = 0x0000,
 161         [RK312x_PGAL_AGC_CTL2] = 0x0046,
 162         [RK312x_PGAL_AGC_CTL3] = 0x0041,
 163         [RK312x_PGAL_AGC_CTL4] = 0x002c,
 164         [RK312x_PGAL_ASR_CTL] = 0x0000,
 165         [RK312x_PGAL_AGC_MAX_H] = 0x0026,
 166         [RK312x_PGAL_AGC_MAX_L] = 0x0040,
 167         [RK312x_PGAL_AGC_MIN_H] = 0x0036,
 168         [RK312x_PGAL_AGC_MIN_L] = 0x0020,
 169         [RK312x_PGAL_AGC_CTL5] = 0x0038,
 170         [RK312x_PGAR_AGC_CTL1] = 0x0000,
 171         [RK312x_PGAR_AGC_CTL2] = 0x0046,
 172         [RK312x_PGAR_AGC_CTL3] = 0x0041,
 173         [RK312x_PGAR_AGC_CTL4] = 0x002c,
 174         [RK312x_PGAR_ASR_CTL] = 0x0000,
 175         [RK312x_PGAR_AGC_MAX_H] = 0x0026,
 176         [RK312x_PGAR_AGC_MAX_L] = 0x0040,
 177         [RK312x_PGAR_AGC_MIN_H] = 0x0036,
 178         [RK312x_PGAR_AGC_MIN_L] = 0x0020,
 179         [RK312x_PGAR_AGC_CTL5] = 0x0038,
 180 };
 181
 182 static struct rk312x_init_bit_typ rk312x_init_bit_list[] = {
 183         {RK312x_HPOUT_CTL, RK312x_HPOUTL_EN,
 184          RK312x_HPOUTL_WORK, RK312x_HPVREF_EN},
 185         {RK312x_HPOUT_CTL, RK312x_HPOUTR_EN,
 186          RK312x_HPOUTR_WORK, RK312x_HPVREF_WORK},
 187         {RK312x_HPMIX_CTL, RK312x_HPMIXR_EN,
 188          RK312x_HPMIXR_WORK2, RK312x_HPMIXR_WORK1},
 189         {RK312x_HPMIX_CTL, RK312x_HPMIXL_EN,
 190          RK312x_HPMIXL_WORK2, RK312x_HPMIXL_WORK1},
 191 };
 192 #define RK312x_INIT_BIT_LIST_LEN ARRAY_SIZE(rk312x_init_bit_list)
 193
 194 static int rk312x_init_bit_register(unsigned int reg, int i)
 195 {
 196         for (; i < RK312x_INIT_BIT_LIST_LEN; i++) {
 197                 if (rk312x_init_bit_list[i].reg == reg)
 198                         return i;
 199         }
 200
 201         return -1;
 202 }
 203
 204 static unsigned int
 205 rk312x_codec_read(struct snd_soc_codec *codec,
 206                   unsigned int reg);
 207 static inline void
 208 rk312x_write_reg_cache(struct snd_soc_codec *codec,
 209                        unsigned int reg,
 210                        unsigned int value);
 211
 212 static unsigned int
 213 rk312x_set_init_value(struct snd_soc_codec *codec,
 214                       unsigned int reg, unsigned int value)
 215 {
 216         unsigned int read_value, power_bit, set_bit2, set_bit1;
 217         int i;
 218         int tmp = 0;
 219
 220         /* read codec init register */
 221         i = rk312x_init_bit_register(reg, 0);
 222
 223         /* set codec init bit
 224         widget init bit should be setted 0 after widget power up or unmute,
 225         and should be setted 1 after widget power down or mute.
 226         */
 227         if (i >= 0) {
 228                 read_value = rk312x_codec_read(codec, reg);
 229                 while (i >= 0) {
 230                         power_bit = rk312x_init_bit_list[i].power_bit;
 231                         set_bit2 = rk312x_init_bit_list[i].init2_bit;
 232                         set_bit1 = rk312x_init_bit_list[i].init1_bit;
 233
 234                         if ((read_value & power_bit) != (value & power_bit)) {
 235                                 if (value & power_bit) {
 236                                         tmp = value | set_bit2 | set_bit1;
 237                                         writel(value, rk312x_priv->regbase+reg);
 238                                         writel(tmp, rk312x_priv->regbase+reg);
 239
 240                                 } else {
 241                                         tmp = value & (~set_bit2) & (~set_bit1);
 242                                         writel(tmp, rk312x_priv->regbase+reg);
 243                                         writel(value, rk312x_priv->regbase+reg);
 244                                 }
 245                                 value = tmp;
 246                         } else {
 247                                 if (read_value != value)
 248                                         writel(value, rk312x_priv->regbase+reg);
 249                         }
 250
 251                         i = rk312x_init_bit_register(reg, ++i);
 252
 253                         rk312x_write_reg_cache(codec, reg, value);
 254                 }
 255         } else {
 256                 return i;
 257         }
 258
 259         return value;
 260 }
 261
 262 static int rk312x_volatile_register(struct snd_soc_codec *codec,
 263                                     unsigned int reg)
 264 {
 265         switch (reg) {
 266         case RK312x_RESET:
 267                 return 1;
 268         default:
 269                 return 0;
 270         }
 271 }
 272
 273 static int rk312x_codec_register(struct snd_soc_codec *codec, unsigned int reg)
 274 {
 275         switch (reg) {
 276         case RK312x_RESET:
 277         case RK312x_ADC_INT_CTL1:
 278         case RK312x_ADC_INT_CTL2:
 279         case RK312x_DAC_INT_CTL1:
 280         case RK312x_DAC_INT_CTL2:
 281         case RK312x_DAC_INT_CTL3:
 282         case RK312x_ADC_MIC_CTL:
 283         case RK312x_BST_CTL:
 284         case RK312x_ALC_MUNIN_CTL:
 285         case RK312x_BSTL_ALCL_CTL:
 286         case RK312x_ALCR_GAIN_CTL:
 287         case RK312x_ADC_ENABLE:
 288         case RK312x_DAC_CTL:
 289         case RK312x_DAC_ENABLE:
 290         case RK312x_HPMIX_CTL:
 291         case RK312x_HPMIX_S_SELECT:
 292         case RK312x_HPOUT_CTL:
 293         case RK312x_HPOUTL_GAIN:
 294         case RK312x_HPOUTR_GAIN:
 295         case RK312x_SELECT_CURRENT:
 296         case RK312x_PGAL_AGC_CTL1:
 297         case RK312x_PGAL_AGC_CTL2:
 298         case RK312x_PGAL_AGC_CTL3:
 299         case RK312x_PGAL_AGC_CTL4:
 300         case RK312x_PGAL_ASR_CTL:
 301         case RK312x_PGAL_AGC_MAX_H:
 302         case RK312x_PGAL_AGC_MAX_L:
 303         case RK312x_PGAL_AGC_MIN_H:
 304         case RK312x_PGAL_AGC_MIN_L:
 305         case RK312x_PGAL_AGC_CTL5:
 306         case RK312x_PGAR_AGC_CTL1:
 307         case RK312x_PGAR_AGC_CTL2:
 308         case RK312x_PGAR_AGC_CTL3:
 309         case RK312x_PGAR_AGC_CTL4:
 310         case RK312x_PGAR_ASR_CTL:
 311         case RK312x_PGAR_AGC_MAX_H:
 312         case RK312x_PGAR_AGC_MAX_L:
 313         case RK312x_PGAR_AGC_MIN_H:
 314         case RK312x_PGAR_AGC_MIN_L:
 315         case RK312x_PGAR_AGC_CTL5:
 316         case RK312x_ALC_CTL:
 317                 return 1;
 318         default:
 319                 return 0;
 320         }
 321 }
 322
 323 static inline unsigned int rk312x_read_reg_cache(struct snd_soc_codec *codec,
 324                                                  unsigned int reg)
 325 {
 326         unsigned int *cache = codec->reg_cache;
 327
 328         if (rk312x_codec_register(codec, reg))
 329                 return  cache[reg];
 330
 331         DBG("%s : reg error!\n", __func__);
 332
 333         return -EINVAL;
 334 }
 335
 336 static inline void rk312x_write_reg_cache(struct snd_soc_codec *codec,
 337                                           unsigned int reg,
 338                                           unsigned int value)
 339 {
 340         unsigned int *cache = codec->reg_cache;
 341
 342         if (rk312x_codec_register(codec, reg)) {
 343                 cache[reg] = value;
 344                 return;
 345         }
 346
 347         DBG("%s : reg error!\n", __func__);
 348 }
 349
 350 static unsigned int rk312x_codec_read(struct snd_soc_codec *codec,
 351                                       unsigned int reg)
 352 {
 353         unsigned int value;
 354
 355         if (!rk312x_priv) {
 356                 DBG("%s : rk312x is NULL\n", __func__);
 357                 return -EINVAL;
 358         }
 359
 360         if (!rk312x_codec_register(codec, reg)) {
 361                 DBG("%s : reg error!\n", __func__);
 362                 return -EINVAL;
 363         }
 364
 365         if (rk312x_volatile_register(codec, reg) == 0)
 366                 value = rk312x_read_reg_cache(codec, reg);
 367         else
 368                 value = readl_relaxed(rk312x_priv->regbase+reg);
 369
 370         value = readl_relaxed(rk312x_priv->regbase+reg);
 371         dbg_codec(2, "%s : reg = 0x%x, val= 0x%x\n", __func__,
 372                   reg, value);
 373
 374         return value;
 375 }
 376
 377 static int rk312x_codec_write(struct snd_soc_codec *codec,
 378                               unsigned int reg, unsigned int value)
 379 {
 380         int new_value;
 381
 382         if (!rk312x_priv) {
 383                 DBG("%s : rk312x is NULL\n", __func__);
 384                 return -EINVAL;
 385         } else if (!rk312x_codec_register(codec, reg)) {
 386                 DBG("%s : reg error!\n", __func__);
 387                 return -EINVAL;
 388         }
 389         new_value = rk312x_set_init_value(codec, reg, value);
 390
 391         if (new_value == -1) {
 392                 writel(value, rk312x_priv->regbase+reg);
 393                 rk312x_write_reg_cache(codec, reg, value);
 394         }
 395         rk312x_codec_read(codec, reg);
 396         return 0;
 397 }
 398
 399 static int rk312x_codec_ctl_gpio(int gpio, int level)
 400 {
 401
 402         if (!rk312x_priv) {
 403                 DBG("%s : rk312x is NULL\n", __func__);
 404                 return -EINVAL;
 405         }
 406
 407         if ((gpio & CODEC_SET_SPK) && rk312x_priv
 408             && rk312x_priv->spk_ctl_gpio != INVALID_GPIO) {
 409                 gpio_set_value(rk312x_priv->spk_ctl_gpio, level);
 410                 DBG(KERN_INFO"%s set spk clt %d\n", __func__, level);
 411                 msleep(rk312x_priv->spk_mute_delay);
 412         }
 413
 414         if ((gpio & CODEC_SET_HP) && rk312x_priv
 415             && rk312x_priv->hp_ctl_gpio != INVALID_GPIO) {
 416                 gpio_set_value(rk312x_priv->hp_ctl_gpio, level);
 417                 DBG(KERN_INFO"%s set hp clt %d\n", __func__, level);
 418                 msleep(rk312x_priv->hp_mute_delay);
 419         }
 420
 421         return 0;
 422 }
 423
 424 #if 0
 425 static int switch_to_spk(int enable)
 426 {
 427         if (!rk312x_priv) {
 428                 DBG(KERN_ERR"%s : rk312x is NULL\n", __func__);
 429                 return -EINVAL;
 430         }
 431         if (enable) {
 432                 if (rk312x_priv->spk_hp_switch_gpio != INVALID_GPIO) {
 433                         gpio_set_value(rk312x_priv->spk_hp_switch_gpio, rk312x_priv->spk_io);
 434                         DBG(KERN_INFO"%s switch to spk\n", __func__);
 435                         msleep(rk312x_priv->spk_mute_delay);
 436                 }
 437         } else {
 438                 if (rk312x_priv->spk_hp_switch_gpio != INVALID_GPIO) {
 439                         gpio_set_value(rk312x_priv->spk_hp_switch_gpio, !rk312x_priv->spk_io);
 440                         DBG(KERN_INFO"%s switch to hp\n", __func__);
 441                         msleep(rk312x_priv->hp_mute_delay);
 442                 }
 443         }
 444         return 0;
 445 }
 446 #endif
 447 static int rk312x_hw_write(const struct i2c_client *client,
 448                            const char *buf, int count)
 449 {
 450         unsigned int reg, value;
 451
 452         if (!rk312x_priv || !rk312x_priv->codec) {
 453                 DBG("%s : rk312x_priv or rk312x_priv->codec is NULL\n",
 454                     __func__);
 455                 return -EINVAL;
 456         }
 457         if (count == 3) {
 458                 reg = (unsigned int)buf[0];
 459                 value = (buf[1] & 0xff00) | (0x00ff & buf[2]);
 460                 writel(value, rk312x_priv->regbase+reg);
 461         } else {
 462                 DBG("%s : i2c len error\n", __func__);
 463         }
 464
 465         return  count;
 466 }
 467
 468 static int rk312x_reset(struct snd_soc_codec *codec)
 469 {
 470         writel(0x00, rk312x_priv->regbase+RK312x_RESET);
 471         mdelay(10);
 472         writel(0x43, rk312x_priv->regbase+RK312x_RESET);
 473         mdelay(10);
 474
 475         memcpy(codec->reg_cache, rk312x_reg_defaults,
 476                sizeof(rk312x_reg_defaults));
 477
 478         return 0;
 479 }
 480
 481 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -3900, 150, 0);
 482 static const DECLARE_TLV_DB_SCALE(pga_vol_tlv, -1800, 150, 0);
 483 static const DECLARE_TLV_DB_SCALE(bst_vol_tlv, 0, 2000, 0);
 484 static const DECLARE_TLV_DB_SCALE(pga_agc_max_vol_tlv, -1350, 600, 0);
 485 static const DECLARE_TLV_DB_SCALE(pga_agc_min_vol_tlv, -1800, 600, 0);
 486
 487 static const char *const rk312x_input_mode[] = {
 488                         "Differential", "Single-Ended"};
 489
 490 static const char *const rk312x_micbias_ratio[] = {
 491                         "1.0 Vref", "1.1 Vref",
 492                         "1.2 Vref", "1.3 Vref",
 493                         "1.4 Vref", "1.5 Vref",
 494                         "1.6 Vref", "1.7 Vref",};
 495
 496 static const char *const rk312x_dis_en_sel[] = {"Disable", "Enable"};
 497
 498 static const char *const rk312x_pga_agc_way[] = {"Normal", "Jack"};
 499
 500 static const char *const rk312x_agc_backup_way[] = {
 501                         "Normal", "Jack1", "Jack2", "Jack3"};
 502
 503 static const char *const rk312x_pga_agc_hold_time[] = {
 504                         "0ms", "2ms", "4ms", "8ms",
 505                         "16ms", "32ms", "64ms",
 506                         "128ms", "256ms", "512ms", "1s"};
 507
 508 static const char *const rk312x_pga_agc_ramp_up_time[] = {
 509                 "Normal:500us Jack:125us",
 510                 "Normal:1ms Jack:250us",
 511                 "Normal:2ms Jack:500us",
 512                 "Normal:4ms Jack:1ms",
 513                 "Normal:8ms Jack:2ms",
 514                 "Normal:16ms Jack:4ms",
 515                 "Normal:32ms Jack:8ms",
 516                 "Normal:64ms Jack:16ms",
 517                 "Normal:128ms Jack:32ms",
 518                 "Normal:256ms Jack:64ms",
 519                 "Normal:512ms Jack:128ms"};
 520
 521 static const char *const rk312x_pga_agc_ramp_down_time[] = {
 522                 "Normal:125us Jack:32us",
 523                 "Normal:250us Jack:64us",
 524                 "Normal:500us Jack:125us",
 525                 "Normal:1ms Jack:250us",
 526                 "Normal:2ms Jack:500us",
 527                 "Normal:4ms Jack:1ms",
 528                 "Normal:8ms Jack:2ms",
 529                 "Normal:16ms Jack:4ms",
 530                 "Normal:32ms Jack:8ms",
 531                 "Normal:64ms Jack:16ms",
 532                 "Normal:128ms Jack:32ms"};
 533
 534 static const char *const rk312x_pga_agc_mode[] = {"Normal", "Limiter"};
 535
 536 static const char *const rk312x_pga_agc_recovery_mode[] = {
 537                 "Right Now", "After AGC to Limiter"};
 538
 539 static const char *const rk312x_pga_agc_noise_gate_threhold[] = {
 540                 "-39dB", "-45dB", "-51dB",
 541                 "-57dB", "-63dB", "-69dB", "-75dB", "-81dB"};
 542
 543 static const char *const rk312x_pga_agc_update_gain[] = {
 544                 "Right Now", "After 1st Zero Cross"};
 545
 546 static const char *const rk312x_pga_agc_approximate_sample_rate[] = {
 547                 "96KHZ", "48KHz", "441KHZ", "32KHz",
 548                 "24KHz", "16KHz", "12KHz", "8KHz"};
 549
 550 static const struct soc_enum rk312x_bst_enum[] = {
 551                 SOC_ENUM_SINGLE(RK312x_BSTL_ALCL_CTL,
 552                                 RK312x_BSTL_MODE_SFT, 2,
 553                                 rk312x_input_mode),
 554 };
 555
 556
 557 static const struct soc_enum rk312x_micbias_enum[] = {
 558         SOC_ENUM_SINGLE(RK312x_ADC_MIC_CTL,
 559                         RK312x_MICBIAS_VOL_SHT, 8,
 560                         rk312x_micbias_ratio),
 561 };
 562
 563 static const struct soc_enum rk312x_agcl_enum[] = {
 564         SOC_ENUM_SINGLE(RK312x_PGAL_AGC_CTL1,
 565                         RK312x_PGA_AGC_BK_WAY_SFT, 4,
 566                         rk312x_agc_backup_way),/*0*/
 567         SOC_ENUM_SINGLE(RK312x_PGAL_AGC_CTL1,
 568                         RK312x_PGA_AGC_WAY_SFT, 2,
 569                         rk312x_pga_agc_way),/*1*/
 570         SOC_ENUM_SINGLE(RK312x_PGAL_AGC_CTL1,
 571                         RK312x_PGA_AGC_HOLD_T_SFT, 11,
 572                         rk312x_pga_agc_hold_time),/*2*/
 573         SOC_ENUM_SINGLE(RK312x_PGAL_AGC_CTL2,
 574                         RK312x_PGA_AGC_GRU_T_SFT, 11,
 575                         rk312x_pga_agc_ramp_up_time),/*3*/
 576         SOC_ENUM_SINGLE(RK312x_PGAL_AGC_CTL2,
 577                         RK312x_PGA_AGC_GRD_T_SFT, 11,
 578                         rk312x_pga_agc_ramp_down_time),/*4*/
 579         SOC_ENUM_SINGLE(RK312x_PGAL_AGC_CTL3,
 580                         RK312x_PGA_AGC_MODE_SFT, 2,
 581                         rk312x_pga_agc_mode),/*5*/
 582         SOC_ENUM_SINGLE(RK312x_PGAL_AGC_CTL3,
 583                         RK312x_PGA_AGC_ZO_SFT, 2,
 584                         rk312x_dis_en_sel),/*6*/
 585         SOC_ENUM_SINGLE(RK312x_PGAL_AGC_CTL3,
 586                         RK312x_PGA_AGC_REC_MODE_SFT, 2,
 587                         rk312x_pga_agc_recovery_mode),/*7*/
 588         SOC_ENUM_SINGLE(RK312x_PGAL_AGC_CTL3,
 589                         RK312x_PGA_AGC_FAST_D_SFT, 2,
 590                         rk312x_dis_en_sel),/*8*/
 591         SOC_ENUM_SINGLE(RK312x_PGAL_AGC_CTL3,
 592                         RK312x_PGA_AGC_NG_SFT, 2,
 593                         rk312x_dis_en_sel),/*9*/
 594         SOC_ENUM_SINGLE(RK312x_PGAL_AGC_CTL3,
 595                         RK312x_PGA_AGC_NG_THR_SFT, 8,
 596                         rk312x_pga_agc_noise_gate_threhold),/*10*/
 597         SOC_ENUM_SINGLE(RK312x_PGAL_AGC_CTL4,
 598                         RK312x_PGA_AGC_ZO_MODE_SFT, 2,
 599                         rk312x_pga_agc_update_gain),/*11*/
 600         SOC_ENUM_SINGLE(RK312x_PGAL_ASR_CTL,
 601                         RK312x_PGA_SLOW_CLK_SFT, 2,
 602                         rk312x_dis_en_sel),/*12*/
 603         SOC_ENUM_SINGLE(RK312x_PGAL_ASR_CTL,
 604                         RK312x_PGA_ASR_SFT, 8,
 605                         rk312x_pga_agc_approximate_sample_rate),/*13*/
 606         SOC_ENUM_SINGLE(RK312x_PGAL_AGC_CTL5,
 607                         RK312x_PGA_AGC_SFT, 2,
 608                         rk312x_dis_en_sel),/*14*/
 609 };
 610
 611 static const struct soc_enum rk312x_agcr_enum[] = {
 612         SOC_ENUM_SINGLE(RK312x_PGAR_AGC_CTL1,
 613                         RK312x_PGA_AGC_BK_WAY_SFT, 4,
 614                         rk312x_agc_backup_way),/*0*/
 615         SOC_ENUM_SINGLE(RK312x_PGAR_AGC_CTL1,
 616                         RK312x_PGA_AGC_WAY_SFT, 2,
 617                         rk312x_pga_agc_way),/*1*/
 618         SOC_ENUM_SINGLE(RK312x_PGAR_AGC_CTL1,
 619                         RK312x_PGA_AGC_HOLD_T_SFT, 11,
 620                         rk312x_pga_agc_hold_time),/*2*/
 621         SOC_ENUM_SINGLE(RK312x_PGAR_AGC_CTL2,
 622                         RK312x_PGA_AGC_GRU_T_SFT, 11,
 623                         rk312x_pga_agc_ramp_up_time),/*3*/
 624         SOC_ENUM_SINGLE(RK312x_PGAR_AGC_CTL2,
 625                         RK312x_PGA_AGC_GRD_T_SFT, 11,
 626                         rk312x_pga_agc_ramp_down_time),/*4*/
 627         SOC_ENUM_SINGLE(RK312x_PGAR_AGC_CTL3,
 628                         RK312x_PGA_AGC_MODE_SFT, 2,
 629                         rk312x_pga_agc_mode),/*5*/
 630         SOC_ENUM_SINGLE(RK312x_PGAR_AGC_CTL3,
 631                         RK312x_PGA_AGC_ZO_SFT, 2,
 632                         rk312x_dis_en_sel),/*6*/
 633         SOC_ENUM_SINGLE(RK312x_PGAR_AGC_CTL3,
 634                         RK312x_PGA_AGC_REC_MODE_SFT, 2,
 635                         rk312x_pga_agc_recovery_mode),/*7*/
 636         SOC_ENUM_SINGLE(RK312x_PGAR_AGC_CTL3,
 637                         RK312x_PGA_AGC_FAST_D_SFT, 2,
 638                         rk312x_dis_en_sel),/*8*/
 639         SOC_ENUM_SINGLE(RK312x_PGAR_AGC_CTL3,
 640                         RK312x_PGA_AGC_NG_SFT, 2, rk312x_dis_en_sel),/*9*/
 641         SOC_ENUM_SINGLE(RK312x_PGAR_AGC_CTL3,
 642                         RK312x_PGA_AGC_NG_THR_SFT, 8,
 643                         rk312x_pga_agc_noise_gate_threhold),/*10*/
 644         SOC_ENUM_SINGLE(RK312x_PGAR_AGC_CTL4,
 645                         RK312x_PGA_AGC_ZO_MODE_SFT, 2,
 646                         rk312x_pga_agc_update_gain),/*11*/
 647         SOC_ENUM_SINGLE(RK312x_PGAR_ASR_CTL,
 648                         RK312x_PGA_SLOW_CLK_SFT, 2,
 649                         rk312x_dis_en_sel),/*12*/
 650         SOC_ENUM_SINGLE(RK312x_PGAR_ASR_CTL,
 651                         RK312x_PGA_ASR_SFT, 8,
 652                         rk312x_pga_agc_approximate_sample_rate),/*13*/
 653         SOC_ENUM_SINGLE(RK312x_PGAR_AGC_CTL5,
 654                         RK312x_PGA_AGC_SFT, 2,
 655                         rk312x_dis_en_sel),/*14*/
 656 };
 657
 658 static const struct snd_kcontrol_new rk312x_snd_controls[] = {
 659         /* Add for set voice volume */
 660         SOC_DOUBLE_R_TLV("Speaker Playback Volume", RK312x_HPOUTL_GAIN,
 661                          RK312x_HPOUTR_GAIN, RK312x_HPOUT_GAIN_SFT,
 662                          31, 0, out_vol_tlv),
 663         SOC_DOUBLE("Speaker Playback Switch", RK312x_HPOUT_CTL,
 664                    RK312x_HPOUTL_MUTE_SHT, RK312x_HPOUTR_MUTE_SHT, 1, 0),
 665         SOC_DOUBLE_R_TLV("Headphone Playback Volume", RK312x_HPOUTL_GAIN,
 666                          RK312x_HPOUTR_GAIN, RK312x_HPOUT_GAIN_SFT,
 667                          31, 0, out_vol_tlv),
 668         SOC_DOUBLE("Headphone Playback Switch", RK312x_HPOUT_CTL,
 669                    RK312x_HPOUTL_MUTE_SHT, RK312x_HPOUTR_MUTE_SHT, 1, 0),
 670         SOC_DOUBLE_R_TLV("Earpiece Playback Volume", RK312x_HPOUTL_GAIN,
 671                          RK312x_HPOUTR_GAIN, RK312x_HPOUT_GAIN_SFT,
 672                          31, 0, out_vol_tlv),
 673         SOC_DOUBLE("Earpiece Playback Switch", RK312x_HPOUT_CTL,
 674                    RK312x_HPOUTL_MUTE_SHT, RK312x_HPOUTR_MUTE_SHT, 1, 0),
 675
 676
 677         /* Add for set capture mute */
 678         SOC_SINGLE_TLV("Main Mic Capture Volume", RK312x_BST_CTL,
 679                        RK312x_BSTL_GAIN_SHT, 1, 0, bst_vol_tlv),
 680         SOC_SINGLE("Main Mic Capture Switch", RK312x_BST_CTL,
 681                    RK312x_BSTL_MUTE_SHT, 1, 0),
 682         SOC_SINGLE_TLV("Headset Mic Capture Volume", RK312x_BST_CTL,
 683                        RK312x_BSTR_GAIN_SHT, 1, 0, bst_vol_tlv),
 684         SOC_SINGLE("Headset Mic Capture Switch", RK312x_BST_CTL,
 685                    RK312x_BSTR_MUTE_SHT, 1, 0),
 686
 687         SOC_SINGLE("ALCL Switch", RK312x_ALC_MUNIN_CTL,
 688                    RK312x_ALCL_MUTE_SHT, 1, 0),
 689         SOC_SINGLE_TLV("ALCL Capture Volume", RK312x_BSTL_ALCL_CTL,
 690                        RK312x_ALCL_GAIN_SHT, 31, 0, pga_vol_tlv),
 691         SOC_SINGLE("ALCR Switch", RK312x_ALC_MUNIN_CTL,
 692                    RK312x_ALCR_MUTE_SHT, 1, 0),
 693         SOC_SINGLE_TLV("ALCR Capture Volume", RK312x_ALCR_GAIN_CTL,
 694                        RK312x_ALCL_GAIN_SHT, 31, 0, pga_vol_tlv),
 695
 696         SOC_ENUM("BST_L Mode",  rk312x_bst_enum[0]),
 697
 698         SOC_ENUM("Micbias Voltage",  rk312x_micbias_enum[0]),
 699         SOC_ENUM("PGAL AGC Back Way",  rk312x_agcl_enum[0]),
 700         SOC_ENUM("PGAL AGC Way",  rk312x_agcl_enum[1]),
 701         SOC_ENUM("PGAL AGC Hold Time",  rk312x_agcl_enum[2]),
 702         SOC_ENUM("PGAL AGC Ramp Up Time",  rk312x_agcl_enum[3]),
 703         SOC_ENUM("PGAL AGC Ramp Down Time",  rk312x_agcl_enum[4]),
 704         SOC_ENUM("PGAL AGC Mode",  rk312x_agcl_enum[5]),
 705         SOC_ENUM("PGAL AGC Gain Update Zero Enable",  rk312x_agcl_enum[6]),
 706         SOC_ENUM("PGAL AGC Gain Recovery LPGA VOL",  rk312x_agcl_enum[7]),
 707         SOC_ENUM("PGAL AGC Fast Decrement Enable",  rk312x_agcl_enum[8]),
 708         SOC_ENUM("PGAL AGC Noise Gate Enable",  rk312x_agcl_enum[9]),
 709         SOC_ENUM("PGAL AGC Noise Gate Threhold",  rk312x_agcl_enum[10]),
 710         SOC_ENUM("PGAL AGC Upate Gain",  rk312x_agcl_enum[11]),
 711         SOC_ENUM("PGAL AGC Slow Clock Enable",  rk312x_agcl_enum[12]),
 712         SOC_ENUM("PGAL AGC Approximate Sample Rate",  rk312x_agcl_enum[13]),
 713         SOC_ENUM("PGAL AGC Enable",  rk312x_agcl_enum[14]),
 714
 715         SOC_SINGLE_TLV("PGAL AGC Volume", RK312x_PGAL_AGC_CTL4,
 716                        RK312x_PGA_AGC_VOL_SFT, 31, 0, pga_vol_tlv),
 717
 718         SOC_SINGLE("PGAL AGC Max Level High 8 Bits",
 719                    RK312x_PGAL_AGC_MAX_H,
 720                    0, 255, 0),
 721         SOC_SINGLE("PGAL AGC Max Level Low 8 Bits",
 722                    RK312x_PGAL_AGC_MAX_L,
 723                    0, 255, 0),
 724         SOC_SINGLE("PGAL AGC Min Level High 8 Bits",
 725                    RK312x_PGAL_AGC_MIN_H,
 726                    0, 255, 0),
 727         SOC_SINGLE("PGAL AGC Min Level Low 8 Bits",
 728                    RK312x_PGAL_AGC_MIN_L,
 729                    0, 255, 0),
 730
 731         SOC_SINGLE_TLV("PGAL AGC Max Gain",
 732                        RK312x_PGAL_AGC_CTL5,
 733                        RK312x_PGA_AGC_MAX_G_SFT, 7, 0,
 734                        pga_agc_max_vol_tlv),
 735         /* AGC enable and 0x0a bit 5 is 1 */
 736         SOC_SINGLE_TLV("PGAL AGC Min Gain", RK312x_PGAL_AGC_CTL5,
 737                        RK312x_PGA_AGC_MIN_G_SFT, 7, 0, pga_agc_min_vol_tlv),
 738         /* AGC enable and 0x0a bit 5 is 1 */
 739
 740         SOC_ENUM("PGAR AGC Back Way",  rk312x_agcr_enum[0]),
 741         SOC_ENUM("PGAR AGC Way",  rk312x_agcr_enum[1]),
 742         SOC_ENUM("PGAR AGC Hold Time",  rk312x_agcr_enum[2]),
 743         SOC_ENUM("PGAR AGC Ramp Up Time",  rk312x_agcr_enum[3]),
 744         SOC_ENUM("PGAR AGC Ramp Down Time",  rk312x_agcr_enum[4]),
 745         SOC_ENUM("PGAR AGC Mode",  rk312x_agcr_enum[5]),
 746         SOC_ENUM("PGAR AGC Gain Update Zero Enable",  rk312x_agcr_enum[6]),
 747         SOC_ENUM("PGAR AGC Gain Recovery LPGA VOL",  rk312x_agcr_enum[7]),
 748         SOC_ENUM("PGAR AGC Fast Decrement Enable",  rk312x_agcr_enum[8]),
 749         SOC_ENUM("PGAR AGC Noise Gate Enable",  rk312x_agcr_enum[9]),
 750         SOC_ENUM("PGAR AGC Noise Gate Threhold",  rk312x_agcr_enum[10]),
 751         SOC_ENUM("PGAR AGC Upate Gain",  rk312x_agcr_enum[11]),
 752         SOC_ENUM("PGAR AGC Slow Clock Enable",  rk312x_agcr_enum[12]),
 753         SOC_ENUM("PGAR AGC Approximate Sample Rate",  rk312x_agcr_enum[13]),
 754         SOC_ENUM("PGAR AGC Enable",  rk312x_agcr_enum[14]),
 755         /* AGC disable and 0x0a bit 4 is 1 */
 756         SOC_SINGLE_TLV("PGAR AGC Volume", RK312x_PGAR_AGC_CTL4,
 757                        RK312x_PGA_AGC_VOL_SFT, 31, 0, pga_vol_tlv),
 758
 759         SOC_SINGLE("PGAR AGC Max Level High 8 Bits", RK312x_PGAR_AGC_MAX_H,
 760                    0, 255, 0),
 761         SOC_SINGLE("PGAR AGC Max Level Low 8 Bits", RK312x_PGAR_AGC_MAX_L,
 762                    0, 255, 0),
 763         SOC_SINGLE("PGAR AGC Min Level High 8 Bits", RK312x_PGAR_AGC_MIN_H,
 764                    0, 255, 0),
 765         SOC_SINGLE("PGAR AGC Min Level Low 8 Bits", RK312x_PGAR_AGC_MIN_L,
 766                    0, 255, 0),
 767         /* AGC enable and 0x06 bit 4 is 1 */
 768         SOC_SINGLE_TLV("PGAR AGC Max Gain", RK312x_PGAR_AGC_CTL5,
 769                        RK312x_PGA_AGC_MAX_G_SFT, 7, 0, pga_agc_max_vol_tlv),
 770         /*  AGC enable and 0x06 bit 4 is 1 */
 771         SOC_SINGLE_TLV("PGAR AGC Min Gain", RK312x_PGAR_AGC_CTL5,
 772                        RK312x_PGA_AGC_MIN_G_SFT, 7, 0, pga_agc_min_vol_tlv),
 773
 774 };
 775
 776 /* For tiny alsa playback/capture/voice call path */
 777 static const char *const rk312x_playback_path_mode[] = {
 778                 "OFF", "RCV", "SPK", "HP", "HP_NO_MIC",
 779                 "BT", "SPK_HP", "RING_SPK", "RING_HP",
 780                 "RING_HP_NO_MIC", "RING_SPK_HP"};
 781
 782 static const char *const rk312x_capture_path_mode[] = {
 783                 "MIC OFF", "Main Mic", "Hands Free Mic", "BT Sco Mic"};
 784
 785 static const char *const rk312x_voice_call_path_mode[] = {
 786                 "OFF", "RCV", "SPK", "HP", "HP_NO_MIC", "BT"};
 787
 788
 789 static const SOC_ENUM_SINGLE_DECL(rk312x_playback_path_type, 0, 0,
 790                                   rk312x_playback_path_mode);
 791 static const SOC_ENUM_SINGLE_DECL(rk312x_capture_path_type, 0, 0,
 792                                   rk312x_capture_path_mode);
 793 static const SOC_ENUM_SINGLE_DECL(rk312x_voice_call_path_type, 0, 0,
 794                                   rk312x_voice_call_path_mode);
 795
 796
 797 /* static int rk312x_codec_power_up(int type); */
 798 static int rk312x_codec_power_down(int type);
 799
 800 static int rk312x_playback_path_get(struct snd_kcontrol *kcontrol,
 801                                     struct snd_ctl_elem_value *ucontrol)
 802 {
 803         if (!rk312x_priv) {
 804                 DBG("%s : rk312x_priv is NULL\n", __func__);
 805                 return -EINVAL;
 806         }
 807
 808         DBG("%s : playback_path = %ld\n",
 809             __func__, ucontrol->value.integer.value[0]);
 810
 811         ucontrol->value.integer.value[0] = rk312x_priv->playback_path;
 812
 813         return 0;
 814 }
 815
 816 static int rk312x_playback_path_put(struct snd_kcontrol *kcontrol,
 817                                     struct snd_ctl_elem_value *ucontrol)
 818 {
 819         /* struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); */
 820         long int pre_path;
 821
 822         if (!rk312x_priv) {
 823                 DBG("%s : rk312x_priv is NULL\n", __func__);
 824                 return -EINVAL;
 825         }
 826
 827         if (rk312x_priv->playback_path ==
 828             ucontrol->value.integer.value[0]) {
 829                 DBG("%s : playback_path is not changed!\n", __func__);
 830                 return 0;
 831         }
 832
 833         pre_path = rk312x_priv->playback_path;
 834         rk312x_priv->playback_path = ucontrol->value.integer.value[0];
 835
 836         DBG("%s : set playback_path = %ld\n", __func__,
 837             rk312x_priv->playback_path);
 838
 839         switch (rk312x_priv->playback_path) {
 840         case OFF:
 841                 if (pre_path != OFF)
 842                         rk312x_codec_power_down(RK312x_CODEC_PLAYBACK);
 843                 break;
 844         case RCV:
 845                 break;
 846         case SPK_PATH:
 847         case RING_SPK:
 848                 if (pre_path == OFF) {
 849                         rk312x_codec_power_up(RK312x_CODEC_PLAYBACK);
 850                         snd_soc_write(rk312x_priv->codec, 0xb4, rk312x_priv->spk_volume);
 851                         snd_soc_write(rk312x_priv->codec, 0xb8, rk312x_priv->spk_volume);
 852                 }
 853                 break;
 854         case HP_PATH:
 855         case HP_NO_MIC:
 856         case RING_HP:
 857         case RING_HP_NO_MIC:
 858                 if (pre_path == OFF) {
 859                         rk312x_codec_power_up(RK312x_CODEC_PLAYBACK);
 860                         snd_soc_write(rk312x_priv->codec, 0xb4, rk312x_priv->hp_volume);
 861                         snd_soc_write(rk312x_priv->codec, 0xb8, rk312x_priv->hp_volume);
 862                 }
 863                 break;
 864         case BT:
 865                 break;
 866         case SPK_HP:
 867         case RING_SPK_HP:
 868                 if (pre_path == OFF) {
 869                         rk312x_codec_power_up(RK312x_CODEC_PLAYBACK);
 870                         snd_soc_write(rk312x_priv->codec, 0xb4, rk312x_priv->spk_volume);
 871                         snd_soc_write(rk312x_priv->codec, 0xb8, rk312x_priv->spk_volume);
 872                 }
 873                 break;
 874         default:
 875                 return -EINVAL;
 876         }
 877
 878         return 0;
 879 }
 880
 881 static int rk312x_capture_path_get(struct snd_kcontrol *kcontrol,
 882                                    struct snd_ctl_elem_value *ucontrol)
 883 {
 884         if (!rk312x_priv) {
 885                 DBG("%s : rk312x_priv is NULL\n", __func__);
 886                 return -EINVAL;
 887         }
 888
 889         DBG("%s : capture_path = %ld\n", __func__,
 890             ucontrol->value.integer.value[0]);
 891
 892         ucontrol->value.integer.value[0] = rk312x_priv->capture_path;
 893
 894         return 0;
 895 }
 896
 897 static int rk312x_capture_path_put(struct snd_kcontrol *kcontrol,
 898                                    struct snd_ctl_elem_value *ucontrol)
 899 {
 900         /* struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); */
 901         long int pre_path;
 902
 903         if (!rk312x_priv) {
 904                 DBG("%s : rk312x_priv is NULL\n", __func__);
 905                 return -EINVAL;
 906         }
 907
 908         if (rk312x_priv->capture_path == ucontrol->value.integer.value[0])
 909                 DBG("%s : capture_path is not changed!\n", __func__);
 910
 911         pre_path = rk312x_priv->capture_path;
 912         rk312x_priv->capture_path = ucontrol->value.integer.value[0];
 913
 914         DBG("%s : set capture_path = %ld\n", __func__,
 915             rk312x_priv->capture_path);
 916
 917         switch (rk312x_priv->capture_path) {
 918         case MIC_OFF:
 919                 if (pre_path != MIC_OFF)
 920                         rk312x_codec_power_down(RK312x_CODEC_CAPTURE);
 921                 break;
 922         case Main_Mic:
 923                 if (pre_path == MIC_OFF) {
 924                         rk312x_codec_power_up(RK312x_CODEC_CAPTURE);
 925                         snd_soc_write(rk312x_priv->codec, 0x94, 0x20|rk312x_priv->capture_volume);
 926                         snd_soc_write(rk312x_priv->codec, 0x98, rk312x_priv->capture_volume);
 927                 }
 928                 break;
 929         case Hands_Free_Mic:
 930                 if (pre_path == MIC_OFF) {
 931                         rk312x_codec_power_up(RK312x_CODEC_CAPTURE);
 932                         snd_soc_write(rk312x_priv->codec, 0x94, 0x20|rk312x_priv->capture_volume);
 933                         snd_soc_write(rk312x_priv->codec, 0x98, rk312x_priv->capture_volume);
 934                 }
 935                 break;
 936         case BT_Sco_Mic:
 937                 break;
 938
 939         default:
 940                 return -EINVAL;
 941         }
 942
 943         return 0;
 944 }
 945
 946 static int rk312x_voice_call_path_get(struct snd_kcontrol *kcontrol,
 947                                       struct snd_ctl_elem_value *ucontrol)
 948 {
 949         if (!rk312x_priv) {
 950                 DBG("%s : rk312x_priv is NULL\n", __func__);
 951                 return -EINVAL;
 952         }
 953
 954         DBG("%s : playback_path = %ld\n", __func__,
 955             ucontrol->value.integer.value[0]);
 956
 957         ucontrol->value.integer.value[0] = rk312x_priv->voice_call_path;
 958
 959         return 0;
 960 }
 961
 962 static int rk312x_voice_call_path_put(struct snd_kcontrol *kcontrol,
 963                                       struct snd_ctl_elem_value *ucontrol)
 964 {
 965         /* struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); */
 966         long int pre_path;
 967
 968         if (!rk312x_priv) {
 969                 DBG("%s : rk312x_priv is NULL\n", __func__);
 970                 return -EINVAL;
 971         }
 972
 973         if (rk312x_priv->voice_call_path == ucontrol->value.integer.value[0])
 974                 DBG("%s : playback_path is not changed!\n", __func__);
 975
 976         pre_path = rk312x_priv->voice_call_path;
 977         rk312x_priv->voice_call_path = ucontrol->value.integer.value[0];
 978
 979         DBG("%s : set playback_path = %ld\n", __func__,
 980             rk312x_priv->voice_call_path);
 981
 982         /* open playback route for incall route and keytone */
 983         if (pre_path == OFF) {
 984                 if (rk312x_priv->playback_path != OFF) {
 985                         /* mute output for incall route pop nosie */
 986                                 mdelay(100);
 987                 } else {
 988                         rk312x_codec_power_up(RK312x_CODEC_PLAYBACK);
 989                         snd_soc_write(rk312x_priv->codec, 0xb4, rk312x_priv->spk_volume);
 990                         snd_soc_write(rk312x_priv->codec, 0xb8, rk312x_priv->spk_volume);
 991                 }
 992         }
 993
 994         switch (rk312x_priv->voice_call_path) {
 995         case OFF:
 996                 if (pre_path != MIC_OFF)
 997                         rk312x_codec_power_down(RK312x_CODEC_CAPTURE);
 998                 break;
 999         case RCV:
1000                 break;
1001         case SPK_PATH:
1002                 /* open incall route */
1003                 if (pre_path == OFF ||  pre_path == RCV || pre_path == BT)
1004                         rk312x_codec_power_up(RK312x_CODEC_INCALL);
1005
1006                 break;
1007         case HP_PATH:
1008         case HP_NO_MIC:
1009                 /* open incall route */
1010                 if (pre_path == OFF ||  pre_path == RCV || pre_path == BT)
1011                         rk312x_codec_power_up(RK312x_CODEC_INCALL);
1012                 break;
1013         case BT:
1014                 break;
1015         default:
1016                 return -EINVAL;
1017         }
1018
1019         return 0;
1020 }
1021
1022 static const struct snd_kcontrol_new rk312x_snd_path_controls[] = {
1023         SOC_ENUM_EXT("Playback Path", rk312x_playback_path_type,
1024                      rk312x_playback_path_get, rk312x_playback_path_put),
1025         SOC_ENUM_EXT("Capture MIC Path", rk312x_capture_path_type,
1026                      rk312x_capture_path_get, rk312x_capture_path_put),
1027         SOC_ENUM_EXT("Voice Call Path", rk312x_voice_call_path_type,
1028                      rk312x_voice_call_path_get, rk312x_voice_call_path_put),
1029 };
1030
1031 static int rk312x_dacl_event(struct snd_soc_dapm_widget *w,
1032                              struct snd_kcontrol *kcontrol,
1033                              int event)
1034 {
1035         struct snd_soc_codec *codec = w->codec;
1036
1037         switch (event) {
1038         case SND_SOC_DAPM_POST_PMU:
1039                 snd_soc_update_bits(codec, RK312x_DAC_ENABLE,
1040                                     RK312x_DACL_WORK, 0);
1041                 snd_soc_update_bits(codec, RK312x_DAC_ENABLE,
1042                                     RK312x_DACL_EN | RK312x_DACL_CLK_EN,
1043                                     RK312x_DACL_EN | RK312x_DACL_CLK_EN);
1044                 snd_soc_update_bits(codec, RK312x_DAC_ENABLE,
1045                                     RK312x_DACL_WORK, RK312x_DACL_WORK);
1046                 break;
1047
1048         case SND_SOC_DAPM_POST_PMD:
1049                 snd_soc_update_bits(codec, RK312x_DAC_ENABLE,
1050                                     RK312x_DACL_EN
1051                                     | RK312x_DACL_CLK_EN, 0);
1052                 snd_soc_update_bits(codec, RK312x_DAC_ENABLE,
1053                                     RK312x_DACL_WORK, 0);
1054                 break;
1055
1056         default:
1057                 return 0;
1058         }
1059
1060         return 0;
1061 }
1062
1063 static int rk312x_dacr_event(struct snd_soc_dapm_widget *w,
1064                              struct snd_kcontrol *kcontrol,
1065                              int event)
1066 {
1067         struct snd_soc_codec *codec = w->codec;
1068
1069         switch (event) {
1070         case SND_SOC_DAPM_POST_PMU:
1071                 snd_soc_update_bits(codec, RK312x_DAC_ENABLE,
1072                                     RK312x_DACR_WORK, 0);
1073                 snd_soc_update_bits(codec, RK312x_DAC_ENABLE,
1074                                     RK312x_DACR_EN
1075                                     | RK312x_DACR_CLK_EN,
1076                                     RK312x_DACR_EN
1077                                     | RK312x_DACR_CLK_EN);
1078                 snd_soc_update_bits(codec, RK312x_DAC_ENABLE,
1079                                     RK312x_DACR_WORK,
1080                                     RK312x_DACR_WORK);
1081                 break;
1082
1083         case SND_SOC_DAPM_POST_PMD:
1084                 snd_soc_update_bits(codec, RK312x_DAC_ENABLE,
1085                                     RK312x_DACR_EN
1086                                     | RK312x_DACR_CLK_EN, 0);
1087                 snd_soc_update_bits(codec, RK312x_DAC_ENABLE,
1088                                     RK312x_DACR_WORK, 0);
1089                 break;
1090
1091         default:
1092                 return 0;
1093         }
1094
1095         return 0;
1096 }
1097
1098 static int rk312x_adcl_event(struct snd_soc_dapm_widget *w,
1099                              struct snd_kcontrol *kcontrol, int event)
1100 {
1101         struct snd_soc_codec *codec = w->codec;
1102
1103         switch (event) {
1104         case SND_SOC_DAPM_POST_PMU:
1105                 snd_soc_update_bits(codec, RK312x_ADC_ENABLE,
1106                                     RK312x_ADCL_CLK_EN_SFT
1107                                     | RK312x_ADCL_AMP_EN_SFT,
1108                                     RK312x_ADCL_CLK_EN
1109                                     | RK312x_ADCL_AMP_EN);
1110                 break;
1111
1112         case SND_SOC_DAPM_POST_PMD:
1113                 snd_soc_update_bits(codec, RK312x_ADC_ENABLE,
1114                                     RK312x_ADCL_CLK_EN_SFT
1115                                     | RK312x_ADCL_AMP_EN_SFT, 0);
1116                 break;
1117
1118         default:
1119                 return 0;
1120         }
1121
1122         return 0;
1123 }
1124
1125 static int rk312x_adcr_event(struct snd_soc_dapm_widget *w,
1126                              struct snd_kcontrol *kcontrol, int event)
1127 {
1128         struct snd_soc_codec *codec = w->codec;
1129
1130         switch (event) {
1131         case SND_SOC_DAPM_POST_PMU:
1132                 snd_soc_update_bits(codec, RK312x_ADC_ENABLE,
1133                                     RK312x_ADCR_CLK_EN_SFT
1134                                     | RK312x_ADCR_AMP_EN_SFT,
1135                                     RK312x_ADCR_CLK_EN
1136                                     | RK312x_ADCR_AMP_EN);
1137                 break;
1138
1139         case SND_SOC_DAPM_POST_PMD:
1140                 snd_soc_update_bits(codec, RK312x_ADC_ENABLE,
1141                                     RK312x_ADCR_CLK_EN_SFT
1142                                     | RK312x_ADCR_AMP_EN_SFT, 0);
1143                 break;
1144
1145         default:
1146                 return 0;
1147         }
1148
1149         return 0;
1150 }
1151
1152 /* HPmix */
1153 static const struct snd_kcontrol_new rk312x_hpmixl[] = {
1154         SOC_DAPM_SINGLE("ALCR Switch", RK312x_HPMIX_S_SELECT,
1155                         RK312x_HPMIXL_SEL_ALCR_SFT, 1, 0),
1156         SOC_DAPM_SINGLE("ALCL Switch", RK312x_HPMIX_S_SELECT,
1157                         RK312x_HPMIXL_SEL_ALCL_SFT, 1, 0),
1158         SOC_DAPM_SINGLE("DACL Switch", RK312x_HPMIX_S_SELECT,
1159                         RK312x_HPMIXL_SEL_DACL_SFT, 1, 0),
1160 };
1161
1162 static const struct snd_kcontrol_new rk312x_hpmixr[] = {
1163         SOC_DAPM_SINGLE("ALCR Switch", RK312x_HPMIX_S_SELECT,
1164                         RK312x_HPMIXR_SEL_ALCR_SFT, 1, 0),
1165         SOC_DAPM_SINGLE("ALCL Switch", RK312x_HPMIX_S_SELECT,
1166                         RK312x_HPMIXR_SEL_ALCL_SFT, 1, 0),
1167         SOC_DAPM_SINGLE("DACR Switch", RK312x_HPMIX_S_SELECT,
1168                         RK312x_HPMIXR_SEL_DACR_SFT, 1, 0),
1169 };
1170
1171 static int rk312x_hpmixl_event(struct snd_soc_dapm_widget *w,
1172                                struct snd_kcontrol *kcontrol, int event)
1173 {
1174         struct snd_soc_codec *codec = w->codec;
1175
1176         switch (event) {
1177         case SND_SOC_DAPM_POST_PMU:
1178                 snd_soc_update_bits(codec, RK312x_DAC_CTL,
1179                                     RK312x_ZO_DET_VOUTR_SFT,
1180                                     RK312x_ZO_DET_VOUTR_EN);
1181                 snd_soc_update_bits(codec, RK312x_DAC_CTL,
1182                                     RK312x_ZO_DET_VOUTL_SFT,
1183                                     RK312x_ZO_DET_VOUTL_EN);
1184                 break;
1185
1186         case SND_SOC_DAPM_PRE_PMD:
1187                 snd_soc_update_bits(codec, RK312x_DAC_CTL,
1188                                     RK312x_ZO_DET_VOUTR_SFT,
1189                                     RK312x_ZO_DET_VOUTR_DIS);
1190                 snd_soc_update_bits(codec, RK312x_DAC_CTL,
1191                                     RK312x_ZO_DET_VOUTL_SFT,
1192                                     RK312x_ZO_DET_VOUTL_DIS);
1193                 break;
1194
1195         default:
1196                 return 0;
1197         }
1198
1199         return 0;
1200 }
1201
1202 static int rk312x_hpmixr_event(struct snd_soc_dapm_widget *w,
1203                                struct snd_kcontrol *kcontrol, int event)
1204 {
1205         /* struct snd_soc_codec *codec = w->codec; */
1206 #if 0
1207         switch (event) {
1208         case SND_SOC_DAPM_POST_PMU:
1209                 snd_soc_update_bits(codec, RK312x_HPMIX_CTL,
1210                                     RK312x_HPMIXR_WORK2, RK312x_HPMIXR_WORK2);
1211                 break;
1212
1213         case SND_SOC_DAPM_PRE_PMD:
1214                 snd_soc_update_bits(codec, RK312x_HPMIX_CTL,
1215                                     RK312x_HPMIXR_WORK2, 0);
1216                 break;
1217
1218         default:
1219                 return 0;
1220         }
1221 #endif
1222         return 0;
1223 }
1224
1225 /* HP MUX */
1226
1227 static const char *const hpl_sel[] = {"HPMIXL", "DACL"};
1228
1229 static const struct soc_enum hpl_sel_enum =
1230         SOC_ENUM_SINGLE(RK312x_HPMIX_S_SELECT, RK312x_HPMIXL_BYPASS_SFT,
1231                         ARRAY_SIZE(hpl_sel), hpl_sel);
1232
1233 static const struct snd_kcontrol_new hpl_sel_mux =
1234         SOC_DAPM_ENUM("HPL select Mux", hpl_sel_enum);
1235
1236 static const char *const hpr_sel[] = {"HPMIXR", "DACR"};
1237
1238 static const struct soc_enum hpr_sel_enum =
1239         SOC_ENUM_SINGLE(RK312x_HPMIX_S_SELECT, RK312x_HPMIXR_BYPASS_SFT,
1240                         ARRAY_SIZE(hpr_sel), hpr_sel);
1241
1242 static const struct snd_kcontrol_new hpr_sel_mux =
1243         SOC_DAPM_ENUM("HPR select Mux", hpr_sel_enum);
1244
1245 /* IN_L MUX */
1246 static const char *const lnl_sel[] = {"NO", "BSTL", "LINEL", "NOUSE"};
1247
1248 static const struct soc_enum lnl_sel_enum =
1249         SOC_ENUM_SINGLE(RK312x_ALC_MUNIN_CTL, RK312x_MUXINL_F_SHT,
1250                         ARRAY_SIZE(lnl_sel), lnl_sel);
1251
1252 static const struct snd_kcontrol_new lnl_sel_mux =
1253         SOC_DAPM_ENUM("MUXIN_L select", lnl_sel_enum);
1254
1255 /* IN_R MUX */
1256 static const char *const lnr_sel[] = {"NO", "BSTR", "LINER", "NOUSE"};
1257
1258 static const struct soc_enum lnr_sel_enum =
1259         SOC_ENUM_SINGLE(RK312x_ALC_MUNIN_CTL, RK312x_MUXINR_F_SHT,
1260                         ARRAY_SIZE(lnr_sel), lnr_sel);
1261
1262 static const struct snd_kcontrol_new lnr_sel_mux =
1263         SOC_DAPM_ENUM("MUXIN_R select", lnr_sel_enum);
1264
1265
1266 static const struct snd_soc_dapm_widget rk312x_dapm_widgets[] = {
1267         /* microphone bias */
1268         SND_SOC_DAPM_MICBIAS("Mic Bias", RK312x_ADC_MIC_CTL,
1269                              RK312x_MICBIAS_VOL_ENABLE, 0),
1270
1271         /* DACs */
1272         SND_SOC_DAPM_DAC_E("DACL", NULL, SND_SOC_NOPM,
1273                            0, 0, rk312x_dacl_event,
1274                            SND_SOC_DAPM_POST_PMD
1275                            | SND_SOC_DAPM_POST_PMU),
1276         SND_SOC_DAPM_DAC_E("DACR", NULL, SND_SOC_NOPM,
1277                            0, 0, rk312x_dacr_event,
1278                            SND_SOC_DAPM_POST_PMD
1279                            | SND_SOC_DAPM_POST_PMU),
1280
1281         /* ADCs */
1282         SND_SOC_DAPM_ADC_E("ADCL", NULL, SND_SOC_NOPM,
1283                            0, 0, rk312x_adcl_event,
1284                            SND_SOC_DAPM_POST_PMD
1285                            | SND_SOC_DAPM_POST_PMU),
1286         SND_SOC_DAPM_ADC_E("ADCR", NULL, SND_SOC_NOPM,
1287                            0, 0, rk312x_adcr_event,
1288                            SND_SOC_DAPM_POST_PMD
1289                            | SND_SOC_DAPM_POST_PMU),
1290
1291         /* PGA */
1292         SND_SOC_DAPM_PGA("BSTL", RK312x_BST_CTL,
1293                          RK312x_BSTL_PWRD_SFT, 0, NULL, 0),
1294         SND_SOC_DAPM_PGA("BSTR", RK312x_BST_CTL,
1295                          RK312x_BSTR_PWRD_SFT, 0, NULL, 0),
1296         SND_SOC_DAPM_PGA("ALCL", RK312x_ALC_MUNIN_CTL,
1297                          RK312x_ALCL_PWR_SHT , 0, NULL, 0),
1298         SND_SOC_DAPM_PGA("ALCR", RK312x_ALC_MUNIN_CTL,
1299                          RK312x_ALCR_PWR_SHT , 0, NULL, 0),
1300         SND_SOC_DAPM_PGA("HPL", RK312x_HPOUT_CTL,
1301                          RK312x_HPOUTL_PWR_SHT, 0, NULL, 0),
1302         SND_SOC_DAPM_PGA("HPR", RK312x_HPOUT_CTL,
1303                          RK312x_HPOUTR_PWR_SHT, 0, NULL, 0),
1304
1305         /* MIXER */
1306         SND_SOC_DAPM_MIXER_E("HPMIXL", RK312x_HPMIX_CTL,
1307                              RK312x_HPMIXL_SFT, 0,
1308                              rk312x_hpmixl,
1309                              ARRAY_SIZE(rk312x_hpmixl),
1310                              rk312x_hpmixl_event,
1311                              SND_SOC_DAPM_PRE_PMD
1312                              | SND_SOC_DAPM_POST_PMU),
1313         SND_SOC_DAPM_MIXER_E("HPMIXR", RK312x_HPMIX_CTL,
1314                              RK312x_HPMIXR_SFT, 0,
1315                              rk312x_hpmixr,
1316                              ARRAY_SIZE(rk312x_hpmixr),
1317                              rk312x_hpmixr_event,
1318                              SND_SOC_DAPM_PRE_PMD
1319                              | SND_SOC_DAPM_POST_PMU),
1320
1321         /* MUX */
1322         SND_SOC_DAPM_MUX("IN_R Mux", SND_SOC_NOPM, 0, 0,
1323                          &lnr_sel_mux),
1324         SND_SOC_DAPM_MUX("IN_L Mux", SND_SOC_NOPM, 0, 0,
1325                          &lnl_sel_mux),
1326         SND_SOC_DAPM_MUX("HPL Mux", SND_SOC_NOPM, 0, 0,
1327                          &hpl_sel_mux),
1328         SND_SOC_DAPM_MUX("HPR Mux", SND_SOC_NOPM, 0, 0,
1329                          &hpr_sel_mux),
1330
1331         /* Audio Interface */
1332         SND_SOC_DAPM_AIF_IN("I2S DAC", "HiFi Playback", 0,
1333                             SND_SOC_NOPM, 0, 0),
1334         SND_SOC_DAPM_AIF_OUT("I2S ADC", "HiFi Capture", 0,
1335                              SND_SOC_NOPM, 0, 0),
1336
1337         /* Input */
1338         SND_SOC_DAPM_INPUT("LINEL"),
1339         SND_SOC_DAPM_INPUT("LINER"),
1340         SND_SOC_DAPM_INPUT("MICP"),
1341         SND_SOC_DAPM_INPUT("MICN"),
1342
1343         /* Output */
1344         SND_SOC_DAPM_OUTPUT("HPOUTL"),
1345         SND_SOC_DAPM_OUTPUT("HPOUTR"),
1346
1347 };
1348
1349 static const struct snd_soc_dapm_route rk312x_dapm_routes[] = {
1350         /* Input */
1351         {"BSTR", NULL, "MICP"},
1352         {"BSTL", NULL, "MICP"},
1353         {"BSTL", NULL, "MICN"},
1354
1355         {"IN_R Mux", "LINER", "LINER"},
1356         {"IN_R Mux", "BSTR", "BSTR"},
1357         {"IN_L Mux", "LINEL", "LINEL"},
1358         {"IN_L Mux", "BSTL", "BSTL"},
1359
1360         {"ALCL", NULL, "IN_L Mux"},
1361         {"ALCR", NULL, "IN_R Mux"},
1362
1363
1364         {"ADCR", NULL, "ALCR"},
1365         {"ADCL", NULL, "ALCL"},
1366
1367         {"I2S ADC", NULL, "ADCR"},
1368         {"I2S ADC", NULL, "ADCL"},
1369
1370         /* Output */
1371
1372         {"DACR", NULL, "I2S DAC"},
1373         {"DACL", NULL, "I2S DAC"},
1374
1375         {"HPMIXR", "ALCR Switch", "ALCR"},
1376         {"HPMIXR", "ALCL Switch", "ALCL"},
1377         {"HPMIXR", "DACR Switch", "DACR"},
1378
1379         {"HPMIXL", "ALCR Switch", "ALCR"},
1380         {"HPMIXL", "ALCL Switch", "ALCL"},
1381         {"HPMIXL", "DACL Switch", "DACL"},
1382
1383
1384         {"HPR Mux", "DACR", "DACR"},
1385         {"HPR Mux", "HPMIXR", "HPMIXR"},
1386         {"HPL Mux", "DACL", "DACL"},
1387         {"HPL Mux", "HPMIXL", "HPMIXL"},
1388
1389         {"HPR", NULL, "HPR Mux"},
1390         {"HPL", NULL, "HPL Mux"},
1391
1392         {"HPOUTR", NULL, "HPR"},
1393         {"HPOUTL", NULL, "HPL"},
1394 };
1395
1396 static int rk312x_set_bias_level(struct snd_soc_codec *codec,
1397                                  enum snd_soc_bias_level level)
1398 {
1399         DBG("%s  level=%d\n", __func__, level);
1400
1401         switch (level) {
1402         case SND_SOC_BIAS_ON:
1403                 break;
1404
1405         case SND_SOC_BIAS_PREPARE:
1406                 break;
1407
1408         case SND_SOC_BIAS_STANDBY:
1409                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1410                         writel(0x32, rk312x_priv->regbase+RK312x_DAC_INT_CTL3);
1411                         snd_soc_update_bits(codec, RK312x_ADC_MIC_CTL,
1412                                             RK312x_ADC_CURRENT_ENABLE,
1413                                             RK312x_ADC_CURRENT_ENABLE);
1414                         snd_soc_update_bits(codec, RK312x_DAC_CTL,
1415                                             RK312x_CURRENT_EN,
1416                                             RK312x_CURRENT_EN);
1417                         /* set power */
1418                         snd_soc_update_bits(codec, RK312x_ADC_ENABLE,
1419                                             RK312x_ADCL_REF_VOL_EN_SFT
1420                                             | RK312x_ADCR_REF_VOL_EN_SFT,
1421                                             RK312x_ADCL_REF_VOL_EN
1422                                             | RK312x_ADCR_REF_VOL_EN);
1423
1424                         snd_soc_update_bits(codec, RK312x_ADC_MIC_CTL,
1425                                             RK312x_ADCL_ZERO_DET_EN_SFT
1426                                             | RK312x_ADCR_ZERO_DET_EN_SFT,
1427                                             RK312x_ADCL_ZERO_DET_EN
1428                                             | RK312x_ADCR_ZERO_DET_EN);
1429
1430                         snd_soc_update_bits(codec, RK312x_DAC_CTL,
1431                                             RK312x_REF_VOL_DACL_EN_SFT
1432                                             | RK312x_REF_VOL_DACR_EN_SFT,
1433                                             RK312x_REF_VOL_DACL_EN
1434                                             | RK312x_REF_VOL_DACR_EN);
1435
1436                         snd_soc_update_bits(codec, RK312x_DAC_ENABLE,
1437                                             RK312x_DACL_REF_VOL_EN_SFT
1438                                             | RK312x_DACR_REF_VOL_EN_SFT,
1439                                             RK312x_DACL_REF_VOL_EN
1440                                             | RK312x_DACR_REF_VOL_EN);
1441                 }
1442                 break;
1443
1444         case SND_SOC_BIAS_OFF:
1445                         snd_soc_update_bits(codec, RK312x_DAC_ENABLE,
1446                                             RK312x_DACL_REF_VOL_EN_SFT
1447                                             | RK312x_DACR_REF_VOL_EN_SFT, 0);
1448                         snd_soc_update_bits(codec, RK312x_DAC_CTL,
1449                                             RK312x_REF_VOL_DACL_EN_SFT
1450                                             | RK312x_REF_VOL_DACR_EN_SFT, 0);
1451                         snd_soc_update_bits(codec, RK312x_ADC_MIC_CTL,
1452                                             RK312x_ADCL_ZERO_DET_EN_SFT
1453                                             | RK312x_ADCR_ZERO_DET_EN_SFT, 0);
1454                         snd_soc_update_bits(codec, RK312x_ADC_ENABLE,
1455                                             RK312x_ADCL_REF_VOL_EN_SFT
1456                                             | RK312x_ADCR_REF_VOL_EN_SFT, 0);
1457                         snd_soc_update_bits(codec, RK312x_ADC_MIC_CTL,
1458                                             RK312x_ADC_CURRENT_ENABLE, 0);
1459                         snd_soc_update_bits(codec, RK312x_DAC_CTL,
1460                                             RK312x_CURRENT_EN, 0);
1461                         writel(0x22, rk312x_priv->regbase+RK312x_DAC_INT_CTL3);
1462                 break;
1463         }
1464         codec->dapm.bias_level = level;
1465
1466         return 0;
1467 }
1468
1469 static int rk312x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1470                                  int clk_id, unsigned int freq, int dir)
1471 {
1472         struct rk312x_codec_priv *rk312x = rk312x_priv;
1473
1474         if (!rk312x) {
1475                 DBG("%s : rk312x is NULL\n", __func__);
1476                 return -EINVAL;
1477         }
1478
1479         rk312x->stereo_sysclk = freq;
1480
1481         return 0;
1482 }
1483
1484 static int rk312x_set_dai_fmt(struct snd_soc_dai *codec_dai,
1485                               unsigned int fmt)
1486 {
1487         struct snd_soc_codec *codec = codec_dai->codec;
1488         unsigned int adc_aif1 = 0, adc_aif2 = 0, dac_aif1 = 0, dac_aif2 = 0;
1489
1490         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1491         case SND_SOC_DAIFMT_CBS_CFS:
1492                 adc_aif2 |= RK312x_I2S_MODE_SLV;
1493                 break;
1494         case SND_SOC_DAIFMT_CBM_CFM:
1495                 adc_aif2 |= RK312x_I2S_MODE_MST;
1496                 break;
1497         default:
1498                 DBG("%s : set master mask failed!\n", __func__);
1499                 return -EINVAL;
1500         }
1501
1502         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1503         case SND_SOC_DAIFMT_DSP_A:
1504                 adc_aif1 |= RK312x_ADC_DF_PCM;
1505                 dac_aif1 |= RK312x_DAC_DF_PCM;
1506                 break;
1507         case SND_SOC_DAIFMT_DSP_B:
1508                 break;
1509         case SND_SOC_DAIFMT_I2S:
1510                 adc_aif1 |= RK312x_ADC_DF_I2S;
1511                 dac_aif1 |= RK312x_DAC_DF_I2S;
1512                 break;
1513         case SND_SOC_DAIFMT_RIGHT_J:
1514                 adc_aif1 |= RK312x_ADC_DF_RJ;
1515                 dac_aif1 |= RK312x_DAC_DF_RJ;
1516                 break;
1517         case SND_SOC_DAIFMT_LEFT_J:
1518                 adc_aif1 |= RK312x_ADC_DF_LJ;
1519                 dac_aif1 |= RK312x_DAC_DF_LJ;
1520                 break;
1521         default:
1522                 DBG("%s : set format failed!\n", __func__);
1523                 return -EINVAL;
1524         }
1525
1526         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1527         case SND_SOC_DAIFMT_NB_NF:
1528                 adc_aif1 |= RK312x_ALRCK_POL_DIS;
1529                 adc_aif2 |= RK312x_ABCLK_POL_DIS;
1530                 dac_aif1 |= RK312x_DLRCK_POL_DIS;
1531                 dac_aif2 |= RK312x_DBCLK_POL_DIS;
1532                 break;
1533         case SND_SOC_DAIFMT_IB_IF:
1534                 adc_aif1 |= RK312x_ALRCK_POL_EN;
1535                 adc_aif2 |= RK312x_ABCLK_POL_EN;
1536                 dac_aif1 |= RK312x_DLRCK_POL_EN;
1537                 dac_aif2 |= RK312x_DBCLK_POL_EN;
1538                 break;
1539         case SND_SOC_DAIFMT_IB_NF:
1540                 adc_aif1 |= RK312x_ALRCK_POL_DIS;
1541                 adc_aif2 |= RK312x_ABCLK_POL_EN;
1542                 dac_aif1 |= RK312x_DLRCK_POL_DIS;
1543                 dac_aif2 |= RK312x_DBCLK_POL_EN;
1544                 break;
1545         case SND_SOC_DAIFMT_NB_IF:
1546                 adc_aif1 |= RK312x_ALRCK_POL_EN;
1547                 adc_aif2 |= RK312x_ABCLK_POL_DIS;
1548                 dac_aif1 |= RK312x_DLRCK_POL_EN;
1549                 dac_aif2 |= RK312x_DBCLK_POL_DIS;
1550                 break;
1551         default:
1552                 DBG("%s : set dai format failed!\n", __func__);
1553                 return -EINVAL;
1554         }
1555
1556         snd_soc_update_bits(codec, RK312x_ADC_INT_CTL1,
1557                             RK312x_ALRCK_POL_MASK
1558                             | RK312x_ADC_DF_MASK, adc_aif1);
1559         snd_soc_update_bits(codec, RK312x_ADC_INT_CTL2,
1560                             RK312x_ABCLK_POL_MASK
1561                             | RK312x_I2S_MODE_MASK, adc_aif2);
1562         snd_soc_update_bits(codec, RK312x_DAC_INT_CTL1,
1563                             RK312x_DLRCK_POL_MASK
1564                             | RK312x_DAC_DF_MASK, dac_aif1);
1565         snd_soc_update_bits(codec, RK312x_DAC_INT_CTL2,
1566                             RK312x_DBCLK_POL_MASK, dac_aif2);
1567
1568         return 0;
1569 }
1570
1571 static int rk312x_hw_params(struct snd_pcm_substream *substream,
1572                             struct snd_pcm_hw_params *params,
1573                             struct snd_soc_dai *dai)
1574 {
1575         struct snd_soc_pcm_runtime *rtd = substream->private_data;
1576         struct snd_soc_codec *codec = rtd->codec;
1577         struct rk312x_codec_priv *rk312x = rk312x_priv;
1578         unsigned int rate = params_rate(params);
1579         unsigned int div;
1580         unsigned int adc_aif1 = 0, adc_aif2  = 0, dac_aif1 = 0, dac_aif2  = 0;
1581
1582         if (!rk312x) {
1583                 DBG("%s : rk312x is NULL\n", __func__);
1584                 return -EINVAL;
1585         }
1586
1587         /* bclk = codec_clk / 4 */
1588         /* lrck = bclk / (wl * 2) */
1589         div = (((rk312x->stereo_sysclk / 4) / rate) / 2);
1590
1591         if ((rk312x->stereo_sysclk % (4 * rate * 2) > 0) ||
1592             (div != 16 && div != 20 && div != 24 && div != 32)) {
1593                 DBG("%s : need PLL\n", __func__);
1594                 return -EINVAL;
1595         }
1596
1597         switch (div) {
1598         case 16:
1599                 adc_aif2 |= RK312x_ADC_WL_16;
1600                 dac_aif2 |= RK312x_DAC_WL_16;
1601                 break;
1602         case 20:
1603                 adc_aif2 |= RK312x_ADC_WL_20;
1604                 dac_aif2 |= RK312x_DAC_WL_20;
1605                 break;
1606         case 24:
1607                 adc_aif2 |= RK312x_ADC_WL_24;
1608                 dac_aif2 |= RK312x_DAC_WL_24;
1609                 break;
1610         case 32:
1611                 adc_aif2 |= RK312x_ADC_WL_32;
1612                 dac_aif2 |= RK312x_DAC_WL_32;
1613                 break;
1614         default:
1615                 return -EINVAL;
1616         }
1617
1618
1619         DBG("%s : MCLK = %dHz, sample rate = %dHz, div = %d\n",
1620             __func__, rk312x->stereo_sysclk, rate, div);
1621
1622         switch (params_format(params)) {
1623         case SNDRV_PCM_FORMAT_S16_LE:
1624                 adc_aif1 |= RK312x_ADC_VWL_16;
1625                 dac_aif1 |= RK312x_DAC_VWL_16;
1626                 break;
1627         case SNDRV_PCM_FORMAT_S20_3LE:
1628                 adc_aif1 |= RK312x_ADC_VWL_20;
1629                 dac_aif1 |= RK312x_DAC_VWL_20;
1630                 break;
1631         case SNDRV_PCM_FORMAT_S24_LE:
1632                 adc_aif1 |= RK312x_ADC_VWL_24;
1633                 dac_aif1 |= RK312x_DAC_VWL_24;
1634                 break;
1635         case SNDRV_PCM_FORMAT_S32_LE:
1636                 adc_aif1 |= RK312x_ADC_VWL_32;
1637                 dac_aif1 |= RK312x_DAC_VWL_32;
1638                 break;
1639         default:
1640                 return -EINVAL;
1641         }
1642
1643         switch (params_channels(params)) {
1644         case RK312x_MONO:
1645                 adc_aif1 |= RK312x_ADC_TYPE_MONO;
1646                 DBG("mono\n");
1647                 break;
1648         case RK312x_STEREO:
1649                 adc_aif1 |= RK312x_ADC_TYPE_STEREO;
1650                 DBG("stero\n");
1651                 break;
1652         default:
1653                 return -EINVAL;
1654         }
1655
1656         adc_aif1 |= RK312x_ADC_SWAP_DIS;
1657         adc_aif2 |= RK312x_ADC_RST_DIS;
1658         dac_aif1 |= RK312x_DAC_SWAP_DIS;
1659         dac_aif2 |= RK312x_DAC_RST_DIS;
1660
1661         rk312x->rate = rate;
1662
1663         snd_soc_update_bits(codec, RK312x_ADC_INT_CTL1,
1664                             RK312x_ADC_VWL_MASK
1665                             | RK312x_ADC_SWAP_MASK
1666                             | RK312x_ADC_TYPE_MASK, adc_aif1);
1667         snd_soc_update_bits(codec, RK312x_ADC_INT_CTL2,
1668                             RK312x_ADC_WL_MASK
1669                             | RK312x_ADC_RST_MASK, adc_aif2);
1670         snd_soc_update_bits(codec, RK312x_DAC_INT_CTL1,
1671                             RK312x_DAC_VWL_MASK
1672                             | RK312x_DAC_SWAP_MASK, dac_aif1);
1673         snd_soc_update_bits(codec, RK312x_DAC_INT_CTL2,
1674                             RK312x_DAC_WL_MASK
1675                             | RK312x_DAC_RST_MASK, dac_aif2);
1676
1677         return 0;
1678 }
1679
1680 static int rk312x_digital_mute(struct snd_soc_dai *dai, int mute)
1681 {
1682
1683         if (mute) {
1684                 rk312x_codec_ctl_gpio(CODEC_SET_SPK, !rk312x_priv->spk_active_level);
1685                 rk312x_codec_ctl_gpio(CODEC_SET_HP, !rk312x_priv->hp_active_level);
1686         } else {
1687                 switch (rk312x_priv->playback_path) {
1688                 case SPK_PATH:
1689                 case RING_SPK:
1690                         /* rk312x_codec_ctl_gpio(CODEC_SET_SPK, rk312x_priv->spk_active_level); */
1691                         /* rk312x_codec_ctl_gpio(CODEC_SET_HP, rk312x_priv->hp_active_level); */
1692                         /* break; */
1693                 case HP_PATH:
1694                 case HP_NO_MIC:
1695                 case RING_HP:
1696                 case RING_HP_NO_MIC:
1697                         /* rk312x_codec_ctl_gpio(CODEC_SET_HP, rk312x_priv->hp_active_level); */
1698                         /* rk312x_codec_ctl_gpio(CODEC_SET_SPK, rk312x_priv->spk_active_level); */
1699                         /* break; */
1700                 case SPK_HP:
1701                 case RING_SPK_HP:
1702                         rk312x_codec_ctl_gpio(CODEC_SET_SPK, rk312x_priv->spk_active_level);
1703                         rk312x_codec_ctl_gpio(CODEC_SET_HP, rk312x_priv->hp_active_level);
1704                         break;
1705                 default:
1706                         break;
1707                 }
1708         }
1709         return 0;
1710 }
1711
1712 static struct rk312x_reg_val_typ playback_power_up_list[] = {
1713         {0x18, 0x32},
1714         {0xa0, 0x40|0x08},
1715         {0xa0, 0x62|0x08},
1716         {0xa4, 0x88},
1717         {0xa4, 0xcc},
1718         {0xa4, 0xee},
1719         {0xa8, 0x44},
1720         {0xb0, 0x92},
1721         {0xb0, 0xdb},
1722         {0xac, 0x11}, /*DAC*/
1723         {0xa8, 0x55},
1724         {0xa8, 0x77},
1725         {0xa4, 0xff},
1726         {0xb0, 0xff},
1727         {0xa0, 0x73|0x08},
1728         {0xb4, OUT_VOLUME},
1729         {0xb8, OUT_VOLUME},
1730 };
1731 #define RK312x_CODEC_PLAYBACK_POWER_UP_LIST_LEN ARRAY_SIZE( \
1732                                         playback_power_up_list)
1733
1734 static struct rk312x_reg_val_typ playback_power_down_list[] = {
1735         {0xb0, 0xdb},
1736         {0xa8, 0x44},
1737         {0xac, 0x00},
1738         {0xb0, 0x92},
1739         {0xa0, 0x22|0x08},
1740         {0xb0, 0x00},
1741         {0xa8, 0x00},
1742         {0xa4, 0x00},
1743         {0xa0, 0x00|0x08},
1744         {0x18, 0x22},
1745 #ifdef WITH_CAP
1746         /* {0xbc, 0x08},*/
1747 #endif
1748         {0xb4, 0x0},
1749         {0xb8, 0x0},
1750         {0x18, 0x22},
1751 };
1752 #define RK312x_CODEC_PLAYBACK_POWER_DOWN_LIST_LEN ARRAY_SIZE( \
1753                                 playback_power_down_list)
1754
1755 static struct rk312x_reg_val_typ capture_power_up_list[] = {
1756         {0x88, 0x80},
1757         {0x88, 0xc0},
1758         {0x88, 0xc7},
1759         {0x9c, 0x88},
1760         {0x8c, 0x04},
1761         {0x90, 0x66},
1762         {0x9c, 0xcc},
1763         {0x9c, 0xee},
1764         {0x8c, 0x07},
1765         {0x90, 0x77},
1766         {0x94, 0x20 | CAP_VOL},
1767         {0x98, CAP_VOL},
1768         {0x88, 0xf7},
1769         {0x28, 0x3c},
1770         {0x124, 0x78},
1771         {0x164, 0x78},
1772
1773 };
1774 #define RK312x_CODEC_CAPTURE_POWER_UP_LIST_LEN ARRAY_SIZE(capture_power_up_list)
1775
1776 static struct rk312x_reg_val_typ capture_power_down_list[] = {
1777         {0x9c, 0xcc},
1778         {0x90, 0x66},
1779         {0x8c, 0x44},
1780         {0x9c, 0x88},
1781         {0x88, 0xc7},
1782         {0x88, 0xc0},
1783         {0x88, 0x80},
1784         {0x8c, 0x00},
1785         {0X94, 0x0c},
1786         {0X98, 0x0c},
1787         {0x9c, 0x00},
1788         {0x88, 0x00},
1789         {0x90, 0x44},
1790         {0x28, 0x0c},
1791         {0x124, 0x38},
1792         {0x164, 0x38},
1793 };
1794 #define RK312x_CODEC_CAPTURE_POWER_DOWN_LIST_LEN ARRAY_SIZE(\
1795                                 capture_power_down_list)
1796
1797 static int rk312x_codec_power_up(int type)
1798 {
1799         struct snd_soc_codec *codec = rk312x_priv->codec;
1800         int i;
1801
1802         if (!rk312x_priv || !rk312x_priv->codec) {
1803                 DBG("%s : rk312x_priv or rk312x_priv->codec is NULL\n",
1804                     __func__);
1805                 return -EINVAL;
1806         }
1807         DBG("%s : power up %s%s\n", __func__,
1808             type == RK312x_CODEC_PLAYBACK ? "playback" : "",
1809             type == RK312x_CODEC_CAPTURE ? "capture" : "");
1810
1811         if (type == RK312x_CODEC_PLAYBACK) {
1812                 for (i = 0; i < RK312x_CODEC_PLAYBACK_POWER_UP_LIST_LEN; i++) {
1813                         snd_soc_write(codec, playback_power_up_list[i].reg,
1814                                       playback_power_up_list[i].value);
1815                 }
1816         } else if (type == RK312x_CODEC_CAPTURE) {
1817                 for (i = 0; i < RK312x_CODEC_CAPTURE_POWER_UP_LIST_LEN; i++) {
1818                         snd_soc_write(codec, capture_power_up_list[i].reg,
1819                                       capture_power_up_list[i].value);
1820                 }
1821         } else if (type == RK312x_CODEC_INCALL) {
1822                 snd_soc_update_bits(codec, RK312x_ALC_MUNIN_CTL,
1823                                     RK312x_MUXINL_F_MSK | RK312x_MUXINR_F_MSK,
1824                                     RK312x_MUXINR_F_INR | RK312x_MUXINL_F_INL);
1825         }
1826
1827         return 0;
1828 }
1829
1830 static int rk312x_codec_power_down(int type)
1831 {
1832         struct snd_soc_codec *codec = rk312x_priv->codec;
1833         int i;
1834
1835         if (!rk312x_priv || !rk312x_priv->codec) {
1836                 DBG("%s : rk312x_priv or rk312x_priv->codec is NULL\n",
1837                     __func__);
1838                 return -EINVAL;
1839         }
1840
1841         DBG("%s : power down %s%s%s\n", __func__,
1842             type == RK312x_CODEC_PLAYBACK ? "playback" : "",
1843             type == RK312x_CODEC_CAPTURE ? "capture" : "",
1844             type == RK312x_CODEC_ALL ? "all" : "");
1845
1846         if ((type == RK312x_CODEC_CAPTURE) || (type == RK312x_CODEC_INCALL)) {
1847                 for (i = 0; i < RK312x_CODEC_CAPTURE_POWER_DOWN_LIST_LEN; i++) {
1848                         snd_soc_write(codec, capture_power_down_list[i].reg,
1849                                       capture_power_down_list[i].value);
1850                 }
1851         } else if (type == RK312x_CODEC_PLAYBACK) {
1852                 for (i = 0;
1853                      i < RK312x_CODEC_PLAYBACK_POWER_DOWN_LIST_LEN;
1854                      i++) {
1855                         snd_soc_write(codec, playback_power_down_list[i].reg,
1856                                       playback_power_down_list[i].value);
1857                 }
1858
1859         } else if (type == RK312x_CODEC_ALL) {
1860                 rk312x_reset(codec);
1861         }
1862
1863         return 0;
1864 }
1865
1866 static void  rk312x_codec_capture_work(struct work_struct *work)
1867 {
1868         DBG("%s : rk312x_codec_work_capture_type = %d\n", __func__,
1869             rk312x_codec_work_capture_type);
1870
1871         switch (rk312x_codec_work_capture_type) {
1872         case RK312x_CODEC_WORK_POWER_DOWN:
1873                 rk312x_codec_power_down(RK312x_CODEC_CAPTURE);
1874                 break;
1875         case RK312x_CODEC_WORK_POWER_UP:
1876                 rk312x_codec_power_up(RK312x_CODEC_CAPTURE);
1877                 snd_soc_write(rk312x_priv->codec, 0x94, 0x20|rk312x_priv->capture_volume);
1878                 snd_soc_write(rk312x_priv->codec, 0x98, rk312x_priv->capture_volume);
1879                 break;
1880         default:
1881                 break;
1882         }
1883
1884         rk312x_codec_work_capture_type = RK312x_CODEC_WORK_NULL;
1885 }
1886
1887 static int rk312x_startup(struct snd_pcm_substream *substream,
1888                           struct snd_soc_dai *dai)
1889 {
1890         struct rk312x_codec_priv *rk312x = rk312x_priv;
1891         bool playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
1892         bool is_codec_playback_running = rk312x->playback_active > 0;
1893         bool is_codec_capture_running = rk312x->capture_active > 0;
1894
1895         if (rk312x_priv->rk312x_for_mid) {
1896                 return 0;
1897         }
1898         if (!rk312x) {
1899                 DBG("%s : rk312x is NULL\n", __func__);
1900                 return -EINVAL;
1901         }
1902         if (playback)
1903                 rk312x->playback_active++;
1904         else
1905                 rk312x->capture_active++;
1906
1907         if (playback) {
1908                 if (rk312x->playback_active > 0)
1909                         if (!is_codec_playback_running) {
1910                                 rk312x_codec_power_up(RK312x_CODEC_PLAYBACK);
1911                                 snd_soc_write(rk312x_priv->codec, 0xb4, rk312x_priv->spk_volume);
1912                                 snd_soc_write(rk312x_priv->codec, 0xb8, rk312x_priv->spk_volume);
1913                                 rk312x_codec_ctl_gpio(CODEC_SET_SPK, rk312x_priv->spk_active_level);
1914                         }
1915         } else {
1916                 if (rk312x->capture_active > 0 && !is_codec_capture_running) {
1917                         if (rk312x_codec_work_capture_type != RK312x_CODEC_WORK_POWER_UP) {
1918                                 //cancel_delayed_work_sync(&capture_delayed_work);
1919                                 if (rk312x_codec_work_capture_type == RK312x_CODEC_WORK_NULL)
1920                                         rk312x_codec_power_up(RK312x_CODEC_CAPTURE);
1921                                 else
1922                                         rk312x_codec_work_capture_type = RK312x_CODEC_WORK_NULL;
1923                         }
1924                 }
1925         }
1926
1927         return 0;
1928 }
1929
1930 static void rk312x_shutdown(struct snd_pcm_substream *substream,
1931                             struct snd_soc_dai *dai)
1932 {
1933         struct rk312x_codec_priv *rk312x = rk312x_priv;
1934         bool playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
1935         bool is_codec_playback_running = rk312x->playback_active > 0;
1936         bool is_codec_capture_running = rk312x->capture_active > 0;
1937
1938         if (rk312x_priv->rk312x_for_mid) {
1939                 return;
1940         }
1941
1942         if (!rk312x) {
1943                 DBG("%s : rk312x is NULL\n", __func__);
1944                 return;
1945         }
1946         if (playback)
1947                 rk312x->playback_active--;
1948         else
1949                 rk312x->capture_active--;
1950
1951         if (playback) {
1952                 if (rk312x->playback_active <= 0) {
1953                         if (is_codec_playback_running == true)
1954                                 rk312x_codec_power_down(
1955                                         RK312x_CODEC_PLAYBACK);
1956                         else
1957                                 DBG(" Warning:playback closed! return !\n");
1958                 }
1959         } else {
1960                 if (rk312x->capture_active <= 0) {
1961                         if ((rk312x_codec_work_capture_type !=
1962                              RK312x_CODEC_WORK_POWER_DOWN) &&
1963                             (is_codec_capture_running == true)) {
1964                                 cancel_delayed_work_sync(&capture_delayed_work);
1965                         /*
1966                          * If rk312x_codec_work_capture_type is NULL
1967                          * means codec already power down,
1968                          * so power up codec.
1969                          * If rk312x_codec_work_capture_type is
1970                          * RK312x_CODEC_WORK_POWER_UP it means
1971                          * codec haven't be powered up, so we don't
1972                          * need to power down codec.
1973                          * If is playback call power down,
1974                          * power down immediatly, because audioflinger
1975                          * already has delay 3s.
1976                          */
1977                                 if (rk312x_codec_work_capture_type ==
1978                                     RK312x_CODEC_WORK_NULL) {
1979                                         rk312x_codec_work_capture_type =
1980                                                 RK312x_CODEC_WORK_POWER_DOWN;
1981                                         queue_delayed_work(rk312x_codec_workq,
1982                                                         &capture_delayed_work,
1983                                                         msecs_to_jiffies(3000));
1984                                 } else {
1985                                         rk312x_codec_work_capture_type =
1986                                                         RK312x_CODEC_WORK_NULL;
1987                                 }
1988                         }
1989                 }
1990         }
1991 }
1992
1993 #define RK312x_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
1994                               SNDRV_PCM_RATE_16000 |    \
1995                               SNDRV_PCM_RATE_32000 |    \
1996                               SNDRV_PCM_RATE_44100 |    \
1997                               SNDRV_PCM_RATE_48000 |    \
1998                               SNDRV_PCM_RATE_96000 |    \
1999                               SNDRV_PCM_RATE_192000)
2000
2001 #define RK312x_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
2002                               SNDRV_PCM_RATE_16000 |    \
2003                               SNDRV_PCM_RATE_32000 |    \
2004                               SNDRV_PCM_RATE_44100 |    \
2005                               SNDRV_PCM_RATE_48000 |    \
2006                               SNDRV_PCM_RATE_96000)
2007
2008 #define RK312x_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
2009                         SNDRV_PCM_FMTBIT_S20_3LE |\
2010                         SNDRV_PCM_FMTBIT_S24_LE |\
2011                         SNDRV_PCM_FMTBIT_S32_LE)
2012
2013 static struct snd_soc_dai_ops rk312x_dai_ops = {
2014         .hw_params      = rk312x_hw_params,
2015         .set_fmt        = rk312x_set_dai_fmt,
2016         .set_sysclk     = rk312x_set_dai_sysclk,
2017         .digital_mute   = rk312x_digital_mute,
2018         .startup        = rk312x_startup,
2019         .shutdown       = rk312x_shutdown,
2020 };
2021
2022 static struct snd_soc_dai_driver rk312x_dai[] = {
2023         {
2024                 .name = "rk312x-hifi",
2025                 .id = RK312x_HIFI,
2026                 .playback = {
2027                         .stream_name = "HiFi Playback",
2028                         .channels_min = 2,
2029                         .channels_max = 2,
2030                         .rates = RK312x_PLAYBACK_RATES,
2031                         .formats = RK312x_FORMATS,
2032                 },
2033                 .capture = {
2034                         .stream_name = "HiFi Capture",
2035                         .channels_min = 2,
2036                         .channels_max = 2,
2037                         .rates = RK312x_CAPTURE_RATES,
2038                         .formats = RK312x_FORMATS,
2039                 },
2040                 .ops = &rk312x_dai_ops,
2041         },
2042         {
2043                 .name = "rk312x-voice",
2044                 .id = RK312x_VOICE,
2045                 .playback = {
2046                         .stream_name = "Voice Playback",
2047                         .channels_min = 1,
2048                         .channels_max = 2,
2049                         .rates = RK312x_PLAYBACK_RATES,
2050                         .formats = RK312x_FORMATS,
2051                 },
2052                 .capture = {
2053                         .stream_name = "Voice Capture",
2054                         .channels_min = 1,
2055                         .channels_max = 2,
2056                         .rates = RK312x_CAPTURE_RATES,
2057                         .formats = RK312x_FORMATS,
2058                 },
2059                 .ops = &rk312x_dai_ops,
2060         },
2061
2062 };
2063
2064 static int rk312x_suspend(struct snd_soc_codec *codec)
2065 {
2066         unsigned int val=0;
2067         DBG("%s\n", __func__);
2068         if (rk312x_priv->codec_hp_det) {
2069         /* disable hp det interrupt */
2070                 val = readl_relaxed(RK_GRF_VIRT + GRF_ACODEC_CON);
2071                 writel_relaxed(0x1f0013, RK_GRF_VIRT + GRF_ACODEC_CON);
2072                 val = readl_relaxed(RK_GRF_VIRT + GRF_ACODEC_CON);
2073                 printk("GRF_ACODEC_CON is 0x%x\n", val);
2074                 del_timer(&rk312x_priv->timer);
2075         }
2076         if (rk312x_priv->rk312x_for_mid) {
2077                 cancel_delayed_work_sync(&capture_delayed_work);
2078
2079                 if (rk312x_codec_work_capture_type != RK312x_CODEC_WORK_NULL)
2080                         rk312x_codec_work_capture_type = RK312x_CODEC_WORK_NULL;
2081
2082                 rk312x_codec_power_down(RK312x_CODEC_PLAYBACK);
2083                 rk312x_codec_power_down(RK312x_CODEC_ALL);
2084                 snd_soc_write(codec, RK312x_SELECT_CURRENT, 0x1e);
2085                 snd_soc_write(codec, RK312x_SELECT_CURRENT, 0x3e);
2086         } else {
2087                 rk312x_set_bias_level(codec, SND_SOC_BIAS_OFF);
2088         }
2089         return 0;
2090 }
2091
2092 static ssize_t gpio_show(struct kobject *kobj, struct kobj_attribute *attr,
2093                          char *buf)
2094 {
2095         return 0;
2096 }
2097
2098 static ssize_t gpio_store(struct kobject *kobj, struct kobj_attribute *attr,
2099                           const char *buf, size_t n)
2100 {
2101         const char *buftmp = buf;
2102         char cmd;
2103         int ret;
2104         struct rk312x_codec_priv *rk312x =
2105                         snd_soc_codec_get_drvdata(rk312x_priv->codec);
2106
2107         ret = sscanf(buftmp, "%c ", &cmd);
2108         if (ret == 0)
2109                 return ret;
2110         switch (cmd) {
2111         case 'd':
2112                 if (rk312x->spk_ctl_gpio != INVALID_GPIO) {
2113                         gpio_set_value(rk312x->spk_ctl_gpio, !rk312x->spk_active_level);
2114                         DBG(KERN_INFO"%s : spk gpio disable\n",__func__);
2115                 }
2116
2117                 if (rk312x->hp_ctl_gpio != INVALID_GPIO) {
2118                         gpio_set_value(rk312x->hp_ctl_gpio, !rk312x->hp_active_level);
2119                         DBG(KERN_INFO"%s : disable hp gpio \n",__func__);
2120                 }
2121                 break;
2122         case 'e':
2123                 if (rk312x->spk_ctl_gpio != INVALID_GPIO) {
2124                         gpio_set_value(rk312x->spk_ctl_gpio, rk312x->spk_active_level);
2125                         DBG(KERN_INFO"%s : spk gpio enable\n",__func__);
2126                 }
2127
2128                 if (rk312x->hp_ctl_gpio != INVALID_GPIO) {
2129                 gpio_set_value(rk312x->hp_ctl_gpio, rk312x->hp_active_level);
2130                 DBG("%s : enable hp gpio \n",__func__);
2131         }
2132                 break;
2133         default:
2134                 DBG(KERN_ERR"--rk312x codec %s-- unknown cmd\n", __func__);
2135                 break;
2136         }
2137         return n;
2138 }
2139 static struct kobject *gpio_kobj;
2140 struct gpio_attribute {
2141
2142         struct attribute    attr;
2143
2144         ssize_t (*show)(struct kobject *kobj, struct kobj_attribute *attr,
2145                         char *buf);
2146         ssize_t (*store)(struct kobject *kobj, struct kobj_attribute *attr,
2147                          const char *buf, size_t n);
2148 };
2149
2150 static struct gpio_attribute gpio_attrs[] = {
2151         /*     node_name    permision       show_func   store_func */
2152         __ATTR(spk-ctl,  S_IRUGO | S_IWUSR,  gpio_show, gpio_store),
2153 };
2154
2155 static int rk312x_resume(struct snd_soc_codec *codec)
2156 {
2157         unsigned int val=0;
2158         if(rk312x_priv->codec_hp_det)
2159         {
2160                 /* enable hp det interrupt */
2161                 snd_soc_write(codec, RK312x_DAC_CTL, 0x08);
2162                 printk("0xa0 -- 0x%x\n",snd_soc_read(codec, RK312x_DAC_CTL));
2163                 val = readl_relaxed(RK_GRF_VIRT + GRF_ACODEC_CON);
2164                 writel_relaxed(0x1f001f, RK_GRF_VIRT + GRF_ACODEC_CON);
2165                 val = readl_relaxed(RK_GRF_VIRT + GRF_ACODEC_CON);
2166                 printk("GRF_ACODEC_CON is 0x%x\n", val);
2167                 add_timer(&rk312x_priv->timer);
2168         }
2169         if (!rk312x_priv->rk312x_for_mid)
2170                 rk312x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2171         return 0;
2172 }
2173
2174 static irqreturn_t codec_hp_det_isr(int irq, void *data)
2175 {
2176         unsigned int val = 0;
2177         val = readl_relaxed(RK_GRF_VIRT + GRF_ACODEC_CON);
2178         DBG("%s GRF_ACODEC_CON -- 0x%x\n", __func__, val);
2179         if (val&0x1) {
2180                 DBG("%s hp det rising\n", __func__);
2181                 writel_relaxed(val|0x10001, RK_GRF_VIRT + GRF_ACODEC_CON);
2182         } else if (val&0x2) {
2183                 DBG("%s hp det falling\n", __func__);
2184                 writel_relaxed(val|0x20002, RK_GRF_VIRT + GRF_ACODEC_CON);
2185         }
2186         del_timer(&rk312x_priv->timer);
2187         add_timer(&rk312x_priv->timer);
2188         return IRQ_HANDLED;
2189 }
2190 static void hp_det_timer_func(unsigned long data)
2191 {
2192         unsigned int val = 0;
2193
2194         val = readl_relaxed(RK_GRF_VIRT + GRF_SOC_STATUS0);
2195         DBG("%s GRF_SOC_STATUS0 -- 0x%x\n", __func__, val);
2196         if (val & 0x80000000) {
2197                 DBG("%s hp det high\n", __func__);
2198                 DBG("%s no headset\n", __func__);
2199                 switch_set_state(&rk312x_priv->sdev, 0);
2200         } else {
2201                 DBG("%s hp det low\n", __func__);
2202                 DBG("%s headset inserted\n", __func__);
2203                 switch_set_state(&rk312x_priv->sdev, BIT_HEADSET_NO_MIC);
2204         }
2205         return;
2206 }
2207 static ssize_t h2w_print_name(struct switch_dev *sdev, char *buf)
2208 {
2209     return sprintf(buf, "Headset\n");
2210 }
2211 static int rk312x_probe(struct snd_soc_codec *codec)
2212 {
2213         struct rk312x_codec_priv *rk312x_codec =
2214                                 snd_soc_codec_get_drvdata(codec);
2215         unsigned int val;
2216         int ret;
2217         int i = 0;
2218
2219         rk312x_codec->codec = codec;
2220         clk_prepare_enable(rk312x_codec->pclk);
2221
2222         ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C);
2223         if (ret != 0)
2224                 goto err__;
2225         codec->hw_read = rk312x_codec_read;
2226         codec->hw_write = (hw_write_t)rk312x_hw_write;
2227         codec->read = rk312x_codec_read;
2228         codec->write = rk312x_codec_write;
2229
2230         rk312x_codec->playback_active = 0;
2231         rk312x_codec->capture_active = 0;
2232
2233         rk312x_codec_workq = create_freezable_workqueue("rk312x-codec");
2234
2235         if (rk312x_codec_workq == NULL) {
2236                 DBG("%s : rk312x_codec_workq is NULL!\n", __func__);
2237                 ret = -ENOMEM;
2238                 goto err__;
2239         }
2240
2241         val = snd_soc_read(codec, RK312x_RESET);
2242         if (val != rk312x_reg_defaults[RK312x_RESET]) {
2243                 DBG("%s : codec register 0: %x is not a 0x00000003\n",
2244                     __func__, val);
2245                 ret = -ENODEV;
2246                 goto err__;
2247         }
2248
2249         rk312x_reset(codec);
2250
2251         if (!rk312x_priv->rk312x_for_mid) {
2252                 codec->dapm.bias_level = SND_SOC_BIAS_OFF;
2253                 rk312x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2254         }
2255
2256 #ifdef WITH_CAP
2257         snd_soc_write(codec, RK312x_SELECT_CURRENT, 0x1e);
2258         snd_soc_write(codec, RK312x_SELECT_CURRENT, 0x3e);
2259 #endif
2260
2261         snd_soc_add_codec_controls(codec, rk312x_snd_path_controls,
2262                                    ARRAY_SIZE(rk312x_snd_path_controls));
2263         if (rk312x_codec->gpio_debug) {
2264                 gpio_kobj = kobject_create_and_add("codec-spk-ctl", NULL);
2265
2266                 if (!gpio_kobj)
2267                         return -ENOMEM;
2268                 for (i = 0; i < ARRAY_SIZE(gpio_attrs); i++) {
2269                         ret = sysfs_create_file(gpio_kobj, &gpio_attrs[i].attr);
2270                         if (ret != 0) {
2271                                 DBG(KERN_ERR"create codec-spk-ctl sysfs %d error\n", i);
2272                                 /* return ret; */
2273                         }
2274                 }
2275         }
2276         if(rk312x_codec->codec_hp_det)
2277         {
2278                 /*init codec_hp_det interrupt */
2279                 ret =request_irq(96, codec_hp_det_isr, IRQF_TRIGGER_RISING, "codec_hp_det", NULL);
2280                 if(ret < 0) {
2281                         printk(" codec_hp_det request_irq failed %d\n", ret);
2282                 }
2283                 init_timer(&rk312x_codec->timer);
2284                 rk312x_codec->timer.function = hp_det_timer_func;
2285                 rk312x_codec->timer.expires = jiffies + HZ/100;
2286                 rk312x_codec->sdev.name = "h2w";
2287                 rk312x_codec->sdev.print_name = h2w_print_name;
2288                 ret = switch_dev_register(&rk312x_codec->sdev);
2289                 if(ret)
2290                         printk(KERN_ERR"register switch dev failed\n");
2291                 val = readl_relaxed(RK_GRF_VIRT + GRF_ACODEC_CON);
2292                 writel_relaxed(0x1f001f, RK_GRF_VIRT + GRF_ACODEC_CON);
2293                 val = readl_relaxed(RK_GRF_VIRT + GRF_ACODEC_CON);
2294                 printk("GRF_ACODEC_CON 3334is 0x%x\n", val);
2295                 snd_soc_write(codec, RK312x_DAC_CTL, 0x08);
2296                 printk("0xa0 -- 0x%x\n",snd_soc_read(codec, RK312x_DAC_CTL));
2297                 /* codec hp det once */
2298                 add_timer(&rk312x_priv->timer);
2299         }
2300
2301         return 0;
2302
2303 err__:
2304         dbg_codec(2, "%s err ret=%d\n", __func__, ret);
2305         return ret;
2306 }
2307
2308 /* power down chip */
2309 static int rk312x_remove(struct snd_soc_codec *codec)
2310 {
2311
2312         DBG("%s\n", __func__);
2313         if (!rk312x_priv) {
2314                 DBG("%s : rk312x_priv is NULL\n", __func__);
2315                 return 0;
2316         }
2317
2318         if (rk312x_priv->spk_ctl_gpio != INVALID_GPIO)
2319                 gpio_set_value(rk312x_priv->spk_ctl_gpio, !rk312x_priv->spk_active_level);
2320
2321         if (rk312x_priv->hp_ctl_gpio != INVALID_GPIO)
2322                 gpio_set_value(rk312x_priv->hp_ctl_gpio, !rk312x_priv->hp_active_level);
2323
2324         mdelay(10);
2325
2326         if (rk312x_priv->rk312x_for_mid) {
2327                 cancel_delayed_work_sync(&capture_delayed_work);
2328
2329                 if (rk312x_codec_work_capture_type != RK312x_CODEC_WORK_NULL)
2330                         rk312x_codec_work_capture_type = RK312x_CODEC_WORK_NULL;
2331         }
2332         snd_soc_write(codec, RK312x_RESET, 0xfc);
2333         mdelay(10);
2334         snd_soc_write(codec, RK312x_RESET, 0x3);
2335         mdelay(10);
2336
2337         /* if (rk312x_priv) */
2338         kfree(rk312x_priv);
2339
2340         return 0;
2341 }
2342
2343
2344 static struct snd_soc_codec_driver soc_codec_dev_rk312x = {
2345         .probe = rk312x_probe,
2346         .remove = rk312x_remove,
2347         .suspend = rk312x_suspend,
2348         .resume = rk312x_resume,
2349         .set_bias_level = rk312x_set_bias_level,
2350         .reg_cache_size = ARRAY_SIZE(rk312x_reg_defaults),
2351         .reg_word_size = sizeof(unsigned int),
2352         .reg_cache_default = rk312x_reg_defaults,
2353         .volatile_register = rk312x_volatile_register,
2354         .readable_register = rk312x_codec_register,
2355         .reg_cache_step = sizeof(unsigned int),
2356 };
2357
2358 static int rk312x_platform_probe(struct platform_device *pdev)
2359 {
2360         struct device_node *rk312x_np = pdev->dev.of_node;
2361         struct rk312x_codec_priv *rk312x;
2362         struct resource *res;
2363         int ret;
2364
2365         rk312x = devm_kzalloc(&pdev->dev, sizeof(*rk312x), GFP_KERNEL);
2366         if (!rk312x) {
2367                 dbg_codec(2, "%s : rk312x priv kzalloc failed!\n",
2368                           __func__);
2369                 return -ENOMEM;
2370         }
2371         rk312x_priv = rk312x;
2372         platform_set_drvdata(pdev, rk312x);
2373
2374 #if 0
2375         rk312x->spk_hp_switch_gpio = of_get_named_gpio_flags(rk312x_np,
2376                                                  "spk_hp_switch_gpio", 0, &rk312x->spk_io);
2377         rk312x->spk_io = !rk312x->spk_io;
2378         if (!gpio_is_valid(rk312x->spk_hp_switch_gpio)) {
2379                 dbg_codec(2, "invalid spk hp switch_gpio : %d\n",
2380                           rk312x->spk_hp_switch_gpio);
2381                 rk312x->spk_hp_switch_gpio = INVALID_GPIO;
2382                 /* ret = -ENOENT; */
2383                 /* goto err__; */
2384         }
2385         DBG("%s : spk_hp_switch_gpio %d spk  active_level %d \n", __func__,
2386                 rk312x->spk_hp_switch_gpio, rk312x->spk_io);
2387
2388         if(rk312x->spk_hp_switch_gpio != INVALID_GPIO) {
2389                 ret = devm_gpio_request(&pdev->dev, rk312x->spk_hp_switch_gpio, "spk_hp_switch");
2390                 if (ret < 0) {
2391                         dbg_codec(2, "rk312x_platform_probe spk_hp_switch_gpio fail\n");
2392                         /* goto err__; */
2393                         rk312x->spk_hp_switch_gpio = INVALID_GPIO;
2394                 }
2395         }
2396 #endif
2397         rk312x->hp_ctl_gpio = of_get_named_gpio_flags(rk312x_np,
2398                                                  "hp_ctl_io", 0, &rk312x->hp_active_level);
2399         rk312x->hp_active_level = !rk312x->hp_active_level;
2400         if (!gpio_is_valid(rk312x->hp_ctl_gpio)) {
2401                 dbg_codec(2, "invalid hp_ctl_gpio: %d\n",
2402                           rk312x->hp_ctl_gpio);
2403         rk312x->hp_ctl_gpio = INVALID_GPIO;
2404                 /* ret = -ENOENT; */
2405                 /* goto err__; */
2406         }
2407         DBG("%s : hp_ctl_gpio %d active_level %d \n", __func__,
2408                 rk312x->hp_ctl_gpio, rk312x->hp_active_level);
2409
2410         if(rk312x->hp_ctl_gpio != INVALID_GPIO) {
2411                 ret = devm_gpio_request(&pdev->dev, rk312x->hp_ctl_gpio, "hp_ctl");
2412                 if (ret < 0) {
2413                         dbg_codec(2, "rk312x_platform_probe hp_ctl_gpio fail\n");
2414                         /* goto err__; */
2415                         rk312x->hp_ctl_gpio = INVALID_GPIO;
2416                 }
2417                 gpio_direction_output(rk312x->hp_ctl_gpio, !rk312x->hp_active_level);
2418         }
2419
2420         rk312x->spk_ctl_gpio = of_get_named_gpio_flags(rk312x_np,
2421                                                  "spk_ctl_io", 0, &rk312x->spk_active_level);
2422         if (!gpio_is_valid(rk312x->spk_ctl_gpio)) {
2423                 dbg_codec(2, "invalid spk_ctl_gpio: %d\n",
2424                           rk312x->spk_ctl_gpio);
2425                 rk312x->spk_ctl_gpio = INVALID_GPIO;
2426                 /* ret = -ENOENT; */
2427                 /* goto err__; */
2428         }
2429
2430         rk312x->spk_active_level = !rk312x->spk_active_level;
2431         if (rk312x->spk_ctl_gpio != INVALID_GPIO) {
2432                 ret = devm_gpio_request(&pdev->dev, rk312x->spk_ctl_gpio, "spk_ctl");
2433                 if (ret < 0) {
2434                         dbg_codec(2, "rk312x_platform_probe spk_ctl_gpio fail\n");
2435                         /* goto err_; */
2436                         rk312x->spk_ctl_gpio = INVALID_GPIO;
2437                 }
2438                 gpio_direction_output(rk312x->spk_ctl_gpio, !rk312x->spk_active_level);
2439         }
2440         DBG(KERN_INFO"%s : spk_ctl_gpio %d active_level %d \n", __func__,
2441                 rk312x->spk_ctl_gpio, rk312x->spk_active_level);
2442
2443         ret = of_property_read_u32(rk312x_np, "spk-mute-delay",
2444                                    &rk312x->spk_mute_delay);
2445         if (ret < 0) {
2446                 DBG(KERN_ERR "%s() Can not read property spk-mute-delay\n",
2447                         __func__);
2448                 rk312x->spk_mute_delay = 0;
2449         }
2450
2451         ret = of_property_read_u32(rk312x_np, "hp-mute-delay",
2452                                    &rk312x->hp_mute_delay);
2453         if (ret < 0) {
2454                 DBG(KERN_ERR"%s() Can not read property hp-mute-delay\n",
2455                        __func__);
2456                 rk312x->hp_mute_delay = 0;
2457         }
2458         DBG("spk mute delay %dms --- hp mute delay %dms\n",rk312x->spk_mute_delay,rk312x->hp_mute_delay);
2459
2460         ret = of_property_read_u32(rk312x_np, "rk312x_for_mid",
2461                                    &rk312x->rk312x_for_mid);
2462         if (ret < 0) {
2463                 DBG(KERN_ERR"%s() Can not read property rk312x_for_mid, default  for mid\n",
2464                         __func__);
2465                 rk312x->rk312x_for_mid = 1;
2466         }
2467         ret = of_property_read_u32(rk312x_np, "is_rk3128",
2468                                    &rk312x->is_rk3128);
2469         if (ret < 0) {
2470                 DBG(KERN_ERR"%s() Can not read property is_rk3128, default rk3126\n",
2471                         __func__);
2472                 rk312x->is_rk3128 = 0;
2473         }
2474         ret = of_property_read_u32(rk312x_np, "spk_volume",
2475                                    &rk312x->spk_volume);
2476         if (ret < 0) {
2477                 DBG(KERN_ERR"%s() Can not read property spk_volume, default 25\n",
2478                         __func__);
2479                 rk312x->spk_volume = 25;
2480         }
2481         ret = of_property_read_u32(rk312x_np, "hp_volume",
2482                                    &rk312x->hp_volume);
2483         if (ret < 0) {
2484                 DBG(KERN_ERR"%s() Can not read property hp_volume, default 25\n",
2485                        __func__);
2486                 rk312x->hp_volume = 25;
2487         }
2488         ret = of_property_read_u32(rk312x_np, "capture_volume",
2489         &rk312x->capture_volume);
2490         if (ret < 0) {
2491                 DBG(KERN_ERR"%s() Can not read property capture_volume, default 26\n",
2492                         __func__);
2493                 rk312x->capture_volume = 26;
2494         }
2495         ret = of_property_read_u32(rk312x_np, "gpio_debug", &rk312x->gpio_debug);
2496         if (ret < 0) {
2497                 DBG(KERN_ERR"%s() Can not read property gpio_debug\n", __func__);
2498                 rk312x->gpio_debug = 0;
2499         }
2500         ret = of_property_read_u32(rk312x_np, "codec_hp_det", &rk312x->codec_hp_det);
2501
2502         if (ret < 0) {
2503                 DBG(KERN_ERR"%s() Can not read property gpio_debug\n", __func__);
2504                 rk312x->codec_hp_det = 0;
2505         }
2506
2507         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2508         rk312x->regbase = devm_ioremap_resource(&pdev->dev, res);
2509         if (IS_ERR(rk312x->regbase))
2510                 return PTR_ERR(rk312x->regbase);
2511
2512         rk312x->pclk = devm_clk_get(&pdev->dev, "g_pclk_acodec");
2513         if (IS_ERR(rk312x->pclk)) {
2514                 dev_err(&pdev->dev, "Unable to get acodec hclk\n");
2515                 ret = -ENXIO;
2516                 goto err__;
2517         }
2518
2519         return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_rk312x,
2520                                 rk312x_dai, ARRAY_SIZE(rk312x_dai));
2521
2522 err__:
2523         platform_set_drvdata(pdev, NULL);
2524         rk312x_priv = NULL;
2525         return ret;
2526 }
2527
2528 static int rk312x_platform_remove(struct platform_device *pdev)
2529 {
2530         DBG("%s\n", __func__);
2531         rk312x_priv = NULL;
2532         snd_soc_unregister_codec(&pdev->dev);
2533         return 0;
2534 }
2535
2536 void rk312x_platform_shutdown(struct platform_device *pdev)
2537 {
2538         DBG("%s\n", __func__);
2539         if (!rk312x_priv || !rk312x_priv->codec) {
2540                 DBG("%s : rk312x_priv or rk312x_priv->codec is NULL\n",
2541                     __func__);
2542                 return;
2543         }
2544
2545         if (rk312x_priv->spk_ctl_gpio != INVALID_GPIO)
2546                 gpio_set_value(rk312x_priv->spk_ctl_gpio, !rk312x_priv->spk_active_level);
2547
2548         if (rk312x_priv->hp_ctl_gpio != INVALID_GPIO)
2549                 gpio_set_value(rk312x_priv->hp_ctl_gpio, !rk312x_priv->hp_active_level);
2550
2551         mdelay(10);
2552
2553         if (rk312x_priv->rk312x_for_mid) {
2554                 cancel_delayed_work_sync(&capture_delayed_work);
2555                 if (rk312x_codec_work_capture_type !=
2556                                         RK312x_CODEC_WORK_NULL)
2557                         rk312x_codec_work_capture_type =
2558                                         RK312x_CODEC_WORK_NULL;
2559         }
2560
2561         writel(0xfc, rk312x_priv->regbase+RK312x_RESET);
2562         mdelay(10);
2563         writel(0x03, rk312x_priv->regbase+RK312x_RESET);
2564
2565         /* if (rk312x_priv) */
2566         kfree(rk312x_priv);
2567 }
2568
2569 #ifdef CONFIG_OF
2570 static const struct of_device_id rk3126_codec_of_match[] = {
2571         { .compatible = "rk312x-codec" },
2572         {},
2573 };
2574 MODULE_DEVICE_TABLE(of, rk3126_codec_of_match);
2575 #endif
2576
2577 static struct platform_driver rk312x_codec_driver = {
2578         .driver = {
2579                    .name = "rk312x-codec",
2580                    .owner = THIS_MODULE,
2581                    .of_match_table = of_match_ptr(rk3126_codec_of_match),
2582                    },
2583         .probe = rk312x_platform_probe,
2584         .remove = rk312x_platform_remove,
2585         .shutdown = rk312x_platform_shutdown,
2586 };
2587 module_platform_driver(rk312x_codec_driver);
2588
2589 /* Module information */
2590 MODULE_AUTHOR("rockchip");
2591 MODULE_DESCRIPTION("ROCKCHIP i2s ASoC Interface");
2592 MODULE_LICENSE("GPL");