2 * rk3026.h -- RK3026 CODEC ALSA SoC audio driver
4 * Copyright 2013 Rockship
5 * Author: chenjq <chenjq@rock-chips.com>
9 #ifndef __RK3026_CODEC_H__
10 #define __RK3026_CODEC_H__
15 #define RK3026_CODEC_BASE (0x0)
17 #define RK3026_RESET (RK3026_CODEC_BASE + 0x00)
18 #define RK3026_ADC_INT_CTL1 (RK3026_CODEC_BASE + 0x08)
19 #define RK3026_ADC_INT_CTL2 (RK3026_CODEC_BASE + 0x0c)
20 #define RK3026_DAC_INT_CTL1 (RK3026_CODEC_BASE + 0x10)
21 #define RK3026_DAC_INT_CTL2 (RK3026_CODEC_BASE + 0x14)
22 #define RK3026_DAC_INT_CTL3 (RK3026_CODEC_BASE + 0x18)
23 #define RK3026_ADC_MIC_CTL (RK3026_CODEC_BASE + 0x88)
24 #define RK3026_BST_CTL (RK3026_CODEC_BASE + 0x8c)
25 #define RK3026_ALC_MUNIN_CTL (RK3026_CODEC_BASE + 0x90)
26 #define RK3026_BSTL_ALCL_CTL (RK3026_CODEC_BASE + 0x94)
27 #define RK3026_ALCR_GAIN_CTL (RK3026_CODEC_BASE + 0x98)
28 #define RK3026_ADC_ENABLE (RK3026_CODEC_BASE + 0x9c)
29 #define RK3026_DAC_CTL (RK3026_CODEC_BASE + 0xa0)
30 #define RK3026_DAC_ENABLE (RK3026_CODEC_BASE + 0xa4)
31 #define RK3026_HPMIX_CTL (RK3026_CODEC_BASE + 0xa8)
32 #define RK3026_HPMIX_S_SELECT (RK3026_CODEC_BASE + 0xac)
33 #define RK3026_HPOUT_CTL (RK3026_CODEC_BASE + 0xB0)
34 #define RK3026_HPOUTL_GAIN (RK3026_CODEC_BASE + 0xB4)
35 #define RK3026_HPOUTR_GAIN (RK3026_CODEC_BASE + 0xB8)
36 #define RK3026_SELECT_CURRENT (RK3026_CODEC_BASE + 0xBC)
37 #define RK3026_PGAL_AGC_CTL1 (RK3026_CODEC_BASE + 0x100)
38 #define RK3026_PGAL_AGC_CTL2 (RK3026_CODEC_BASE + 0x104)
39 #define RK3026_PGAL_AGC_CTL3 (RK3026_CODEC_BASE + 0x108)
40 #define RK3026_PGAL_AGC_CTL4 (RK3026_CODEC_BASE + 0x10c)
41 #define RK3026_PGAL_ASR_CTL (RK3026_CODEC_BASE + 0x110)
42 #define RK3026_PGAL_AGC_MAX_H (RK3026_CODEC_BASE + 0x114)
43 #define RK3026_PGAL_AGC_MAX_L (RK3026_CODEC_BASE + 0x118)
44 #define RK3026_PGAL_AGC_MIN_H (RK3026_CODEC_BASE + 0x11c)
45 #define RK3026_PGAL_AGC_MIN_L (RK3026_CODEC_BASE + 0x120)
46 #define RK3026_PGAL_AGC_CTL5 (RK3026_CODEC_BASE + 0x124)
47 #define RK3026_PGAR_AGC_CTL1 (RK3026_CODEC_BASE + 0x140)
48 #define RK3026_PGAR_AGC_CTL2 (RK3026_CODEC_BASE + 0x144)
49 #define RK3026_PGAR_AGC_CTL3 (RK3026_CODEC_BASE + 0x148)
50 #define RK3026_PGAR_AGC_CTL4 (RK3026_CODEC_BASE + 0x14c)
51 #define RK3026_PGAR_ASR_CTL (RK3026_CODEC_BASE + 0x150)
52 #define RK3026_PGAR_AGC_MAX_H (RK3026_CODEC_BASE + 0x154)
53 #define RK3026_PGAR_AGC_MAX_L (RK3026_CODEC_BASE + 0x158)
54 #define RK3026_PGAR_AGC_MIN_H (RK3026_CODEC_BASE + 0x15c)
55 #define RK3026_PGAR_AGC_MIN_L (RK3026_CODEC_BASE + 0x160)
56 #define RK3026_PGAR_AGC_CTL5 (RK3026_CODEC_BASE + 0x164)
58 /* ADC Interface Control 1 (0x08) */
59 #define RK3026_ALRCK_POL_MASK (0x1 << 7)
60 #define RK3026_ALRCK_POL_SFT 7
61 #define RK3026_ALRCK_POL_EN (0x1 << 7)
62 #define RK3026_ALRCK_POL_DIS (0x0 << 7)
64 #define RK3026_ADC_VWL_MASK (0x3 << 5)
65 #define RK3026_ADC_VWL_SFT 5
66 #define RK3026_ADC_VWL_32 (0x3 << 5)
67 #define RK3026_ADC_VWL_24 (0x2 << 5)
68 #define RK3026_ADC_VWL_20 (0x1 << 5)
69 #define RK3026_ADC_VWL_16 (0x0 << 5)
71 #define RK3026_ADC_DF_MASK (0x3 << 3)
72 #define RK3026_ADC_DF_SFT 3
73 #define RK3026_ADC_DF_PCM (0x3 << 3)
74 #define RK3026_ADC_DF_I2S (0x2 << 3)
75 #define RK3026_ADC_DF_LJ (0x1 << 3)
76 #define RK3026_ADC_DF_RJ (0x0 << 3)
78 #define RK3026_ADC_SWAP_MASK (0x1 << 1)
79 #define RK3026_ADC_SWAP_SFT 1
80 #define RK3026_ADC_SWAP_EN (0x1 << 1)
81 #define RK3026_ADC_SWAP_DIS (0x0 << 1)
83 #define RK3026_ADC_TYPE_MASK 0x1
84 #define RK3026_ADC_TYPE_SFT 0
85 #define RK3026_ADC_TYPE_MONO 0x1
86 #define RK3026_ADC_TYPE_STEREO 0x0
88 /* ADC Interface Control 2 (0x0c) */
89 #define RK3026_I2S_MODE_MASK (0x1 << 4)
90 #define RK3026_I2S_MODE_SFT (4)
91 #define RK3026_I2S_MODE_MST (0x1 << 4)
92 #define RK3026_I2S_MODE_SLV (0x0 << 4)
94 #define RK3026_ADC_WL_MASK (0x3 << 2)
95 #define RK3026_ADC_WL_SFT (2)
96 #define RK3026_ADC_WL_32 (0x3 << 2)
97 #define RK3026_ADC_WL_24 (0x2 << 2)
98 #define RK3026_ADC_WL_20 (0x1 << 2)
99 #define RK3026_ADC_WL_16 (0x0 << 2)
101 #define RK3026_ADC_RST_MASK (0x1 << 1)
102 #define RK3026_ADC_RST_SFT 91)
103 #define RK3026_ADC_RST_DIS (0x1 << 1)
104 #define RK3026_ADC_RST_EN (0x0 << 1)
106 #define RK3026_ABCLK_POL_MASK 0x1
107 #define RK3026_ABCLK_POL_SFT 0
108 #define RK3026_ABCLK_POL_EN 0x1
109 #define RK3026_ABCLK_POL_DIS 0x0
111 /* DAC Interface Control 1 (0x10) */
112 #define RK3026_DLRCK_POL_MASK (0x1 << 7)
113 #define RK3026_DLRCK_POL_SFT 7
114 #define RK3026_DLRCK_POL_EN (0x1 << 7)
115 #define RK3026_DLRCK_POL_DIS (0x0 << 7)
117 #define RK3026_DAC_VWL_MASK (0x3 << 5)
118 #define RK3026_DAC_VWL_SFT 5
119 #define RK3026_DAC_VWL_32 (0x3 << 5)
120 #define RK3026_DAC_VWL_24 (0x2 << 5)
121 #define RK3026_DAC_VWL_20 (0x1 << 5)
122 #define RK3026_DAC_VWL_16 (0x0 << 5)
124 #define RK3026_DAC_DF_MASK (0x3 << 3)
125 #define RK3026_DAC_DF_SFT 3
126 #define RK3026_DAC_DF_PCM (0x3 << 3)
127 #define RK3026_DAC_DF_I2S (0x2 << 3)
128 #define RK3026_DAC_DF_LJ (0x1 << 3)
129 #define RK3026_DAC_DF_RJ (0x0 << 3)
131 #define RK3026_DAC_SWAP_MASK (0x1 << 2)
132 #define RK3026_DAC_SWAP_SFT 2
133 #define RK3026_DAC_SWAP_EN (0x1 << 2)
134 #define RK3026_DAC_SWAP_DIS (0x0 << 2)
136 /* DAC Interface Control 2 (0x14) */
137 #define RK3026_DAC_WL_MASK (0x3 << 2)
138 #define RK3026_DAC_WL_SFT 2
139 #define RK3026_DAC_WL_32 (0x3 << 2)
140 #define RK3026_DAC_WL_24 (0x2 << 2)
141 #define RK3026_DAC_WL_20 (0x1 << 2)
142 #define RK3026_DAC_WL_16 (0x0 << 2)
144 #define RK3026_DAC_RST_MASK (0x1 << 1)
145 #define RK3026_DAC_RST_SFT 1
146 #define RK3026_DAC_RST_DIS (0x1 << 1)
147 #define RK3026_DAC_RST_EN (0x0 << 1)
149 #define RK3026_DBCLK_POL_MASK 0x1
150 #define RK3026_DBCLK_POL_SFT 0
151 #define RK3026_DBCLK_POL_EN 0x1
152 #define RK3026_DBCLK_POL_DIS 0x0
154 /* ADC & MICBIAS (0x88) */
155 #define RK3026_ADC_CURRENT_ENABLE (0x1 << 7)
156 #define RK3026_ADC_CURRENT_DISABLE (0x0 << 7)
158 #define RK3026_MICBIAS_VOL_ENABLE (6)
160 #define RK3026_ADCL_ZERO_DET_EN_SFT (5)
161 #define RK3026_ADCL_ZERO_DET_EN (0x1 << 5)
162 #define RK3026_ADCL_ZERO_DET_DIS (0x0 << 5)
164 #define RK3026_ADCR_ZERO_DET_EN_SFT (4)
165 #define RK3026_ADCR_ZERO_DET_EN (0x1 << 4)
166 #define RK3026_ADCR_ZERO_DET_DIS (0x0 << 4)
168 #define RK3026_MICBIAS_VOL_SHT 0
169 #define RK3026_MICBIAS_VOL_MSK 7
170 #define RK3026_MICBIAS_VOL_MIN (0x0 << 0)
171 #define RK3026_MICBIAS_VOL_MAX (0x7 << 0)
173 /* BST_L BST_R CONTROL (0x8C) */
174 #define RK3026_BSTL_PWRD_SFT (6)
175 #define RK3026_BSTL_EN (0x1 << 6)
176 #define RK3026_BSTL_DIS (0x0 << 6)
177 #define RK3026_BSTL_GAIN_SHT (5)
178 #define RK3026_BSTL_GAIN_20 (0x1 << 5)
179 #define RK3026_BSTL_GAIN_0 (0x0 << 5)
180 #define RK3026_BSTL_MUTE_SHT (4)
182 #define RK3026_BSTR_PWRD_SFT (2)
183 #define RK3026_BSTR_EN (0x1 << 2)
184 #define RK3026_BSTR_DIS (0x0 << 2)
185 #define RK3026_BSTR_GAIN_SHT (1)
186 #define RK3026_BSTR_GAIN_20 (0x1 << 1)
187 #define RK3026_BSTR_GAIN_0 (0x0 << 1)
188 #define RK3026_BSTR_MUTE_SHT (0)
191 /* MUXINL ALCL MUXINR ALCR (0x90) */
192 #define RK3026_MUXINL_F_SHT (6)
193 #define RK3026_MUXINL_F_MSK (0x03 << 6)
194 #define RK3026_MUXINL_F_INL (0x02 << 6)
195 #define RK3026_MUXINL_F_BSTL (0x01 << 6)
196 #define RK3026_ALCL_PWR_SHT (5)
197 #define RK3026_ALCL_EN (0x1 << 5)
198 #define RK3026_ALCL_DIS (0x0 << 5)
199 #define RK3026_ALCL_MUTE_SHT (4)
200 #define RK3026_MUXINR_F_SHT (2)
201 #define RK3026_MUXINR_F_MSK (0x03 << 2)
202 #define RK3026_MUXINR_F_INR (0x02 << 2)
203 #define RK3026_MUXINR_F_BSTR (0x01 << 2)
204 #define RK3026_ALCR_PWR_SHT (1)
205 #define RK3026_ALCR_EN (0x1 << 1)
206 #define RK3026_ALCR_DIS (0x0 << 1)
207 #define RK3026_ALCR_MUTE_SHT (0)
209 /* BST_L MODE & ALC_L GAIN (0x94) */
210 #define RK3026_BSTL_MODE_SFT (5)
211 #define RK3026_BSTL_MODE_SINGLE (0x1 << 5)
212 #define RK3026_BSTL_MODE_DIFF (0x0 << 5)
214 #define RK3026_ALCL_GAIN_SHT (0)
215 #define RK3026_ALCL_GAIN_MSK (0x1f)
217 /* ALC_R GAIN (0x98) */
218 #define RK3026_ALCR_GAIN_SHT (0)
219 #define RK3026_ALCR_GAIN_MSK (0x1f)
221 /* ADC control (0x9C) */
222 #define RK3026_ADCL_REF_VOL_EN_SFT (3)
223 #define RK3026_ADCL_REF_VOL_EN (0x1 << 7)
224 #define RK3026_ADCL_REF_VOL_DIS (0x0 << 7)
226 #define RK3026_ADCL_CLK_EN_SFT (6)
227 #define RK3026_ADCL_CLK_EN (0x1 << 6)
228 #define RK3026_ADCL_CLK_DIS (0x0 << 6)
230 #define RK3026_ADCL_AMP_EN_SFT (5)
231 #define RK3026_ADCL_AMP_EN (0x1 << 5)
232 #define RK3026_ADCL_AMP_DIS (0x0 << 5)
234 #define RK3026_ADCL_RST_EN (0x1 << 4)
235 #define RK3026_ADCL_RST_DIS (0x0 << 4)
237 #define RK3026_ADCR_REF_VOL_EN_SFT (3)
238 #define RK3026_ADCR_REF_VOL_EN (0x1 << 3)
239 #define RK3026_ADCR_REF_VOL_DIS (0x0 << 3)
241 #define RK3026_ADCR_CLK_EN_SFT (2)
242 #define RK3026_ADCR_CLK_EN (0x1 << 2)
243 #define RK3026_ADCR_CLK_DIS (0x0 << 2)
245 #define RK3026_ADCR_AMP_EN_SFT (1)
246 #define RK3026_ADCR_AMP_EN (0x1 << 1)
247 #define RK3026_ADCR_AMP_DIS (0x0 << 1)
249 #define RK3026_ADCR_RST_EN (0x1 << 0)
250 #define RK3026_ADCR_RST_DIS (0x0 << 0)
252 /* DAC & VOUT Control (0xa0) */
253 #define RK3026_CURRENT_EN (0x1 << 6)
254 #define RK3026_CURRENT_DIS (0x0 << 6)
255 #define RK3026_REF_VOL_DACL_EN_SFT (5)
256 #define RK3026_REF_VOL_DACL_EN (0x1 << 5)
257 #define RK3026_REF_VOL_DACL_DIS (0x0 << 5)
258 #define RK3026_ZO_DET_VOUTL_SFT (4)
259 #define RK3026_ZO_DET_VOUTL_EN (0x1 << 4)
260 #define RK3026_ZO_DET_VOUTL_DIS (0x0 << 4)
261 #define RK3026_DET_ERAPHONE_DIS (0x0 << 3)
262 #define RK3026_DET_ERAPHONE_EN (0x1 << 3)
263 #define RK3026_REF_VOL_DACR_EN_SFT (1)
264 #define RK3026_REF_VOL_DACR_EN (0x1 << 1)
265 #define RK3026_REF_VOL_DACR_DIS (0x0 << 1)
266 #define RK3026_ZO_DET_VOUTR_SFT (0)
267 #define RK3026_ZO_DET_VOUTR_EN (0x1 << 0)
268 #define RK3026_ZO_DET_VOUTR_DIS (0x0 << 0)
270 /* DAC control (0xa4) */
271 #define RK3026_DACL_REF_VOL_EN_SFT (7)
272 #define RK3026_DACL_REF_VOL_EN (0x1 << 7)
273 #define RK3026_DACL_REF_VOL_DIS (0x0 << 7)
275 #define RK3026_DACL_CLK_EN (0x1 << 6)
276 #define RK3026_DACL_CLK_DIS (0x0 << 6)
278 #define RK3026_DACL_EN (0x1 << 5)
279 #define RK3026_DACL_DIS (0x0 << 5)
281 #define RK3026_DACL_INIT (0x0 << 4)
282 #define RK3026_DACL_WORK (0x1 << 4)
284 #define RK3026_DACR_REF_VOL_EN_SFT (3)
285 #define RK3026_DACR_REF_VOL_EN (0x1 << 3)
286 #define RK3026_DACR_REF_VOL_DIS (0x0 << 3)
288 #define RK3026_DACR_CLK_EN (0x1 << 2)
289 #define RK3026_DACR_CLK_DIS (0x0 << 2)
291 #define RK3026_DACR_EN (0x1 << 1)
292 #define RK3026_DACR_DIS (0x0 << 1)
294 #define RK3026_DACR_INIT (0x0 << 0)
295 #define RK3026_DACR_WORK (0x1 << 0)
297 /* HPMIXL HPMIXR Control (0xa8) */
298 #define RK3026_HPMIXL_SFT (6)
299 #define RK3026_HPMIXL_EN (0x1 << 6)
300 #define RK3026_HPMIXL_DIS (0x0 << 6)
301 #define RK3026_HPMIXL_INIT1 (0x0 << 5)
302 #define RK3026_HPMIXL_WORK1 (0x1 << 5)
303 #define RK3026_HPMIXL_INIT2 (0x0 << 4)
304 #define RK3026_HPMIXL_WORK2 (0x1 << 4)
305 #define RK3026_HPMIXR_SFT (2)
306 #define RK3026_HPMIXR_EN (0x1 << 2)
307 #define RK3026_HPMIXR_DIS (0x0 << 2)
308 #define RK3026_HPMIXR_INIT1 (0x0 << 1)
309 #define RK3026_HPMIXR_WORK1 (0x1 << 1)
310 #define RK3026_HPMIXR_INIT2 (0x0 << 0)
311 #define RK3026_HPMIXR_WORK2 (0x1 << 0)
313 /* HPMIXL Control (0xac) */
314 #define RK3026_HPMIXL_BYPASS_SFT (7)
315 #define RK3026_HPMIXL_SEL_ALCL_SFT (6)
316 #define RK3026_HPMIXL_SEL_ALCR_SFT (5)
317 #define RK3026_HPMIXL_SEL_DACL_SFT (4)
318 #define RK3026_HPMIXR_BYPASS_SFT (3)
319 #define RK3026_HPMIXR_SEL_ALCL_SFT (2)
320 #define RK3026_HPMIXR_SEL_ALCR_SFT (1)
321 #define RK3026_HPMIXR_SEL_DACR_SFT (0)
323 /* HPOUT Control (0xb0) */
324 #define RK3026_HPOUTL_PWR_SHT (7)
325 #define RK3026_HPOUTL_MSK (0x1 << 7)
326 #define RK3026_HPOUTL_EN (0x1 << 7)
327 #define RK3026_HPOUTL_DIS (0x0 << 7)
328 #define RK3026_HPOUTL_INIT_MSK (0x1 << 6)
329 #define RK3026_HPOUTL_INIT (0x0 << 6)
330 #define RK3026_HPOUTL_WORK (0x1 << 6)
331 #define RK3026_HPOUTL_MUTE_SHT (5)
332 #define RK3026_HPOUTL_MUTE_MSK (0x1 << 5)
333 #define RK3026_HPOUTL_MUTE_EN (0x0 << 5)
334 #define RK3026_HPOUTL_MUTE_DIS (0x1 << 5)
335 #define RK3026_HPOUTR_PWR_SHT (4)
336 #define RK3026_HPOUTR_MSK (0x1 << 4)
337 #define RK3026_HPOUTR_EN (0x1 << 4)
338 #define RK3026_HPOUTR_DIS (0x0 << 4)
339 #define RK3026_HPOUTR_INIT_MSK (0x1 << 3)
340 #define RK3026_HPOUTR_WORK (0x1 << 3)
341 #define RK3026_HPOUTR_INIT (0x0 << 3)
342 #define RK3026_HPOUTR_MUTE_SHT (2)
343 #define RK3026_HPOUTR_MUTE_MSK (0x1 << 2)
344 #define RK3026_HPOUTR_MUTE_EN (0x0 << 2)
345 #define RK3026_HPOUTR_MUTE_DIS (0x1 << 2)
347 #define RK3026_HPVREF_PWR_SHT (1)
348 #define RK3026_HPVREF_EN (0x1 << 1)
349 #define RK3026_HPVREF_DIS (0x0 << 1)
350 #define RK3026_HPVREF_WORK (0x1 << 0)
351 #define RK3026_HPVREF_INIT (0x0 << 0)
353 /* HPOUT GAIN (0xb4 0xb8) */
354 #define RK3026_HPOUT_GAIN_SFT (0)
356 /* SELECT CURR prechagrge/discharge (0xbc) */
357 #define RK3026_PRE_HPOUT (0x1 << 5)
358 #define RK3026_DIS_HPOUT (0x0 << 5)
359 #define RK3026_CUR_10UA_EN (0x0 << 4)
360 #define RK3026_CUR_10UA_DIS (0x1 << 4)
361 #define RK3026_CUR_I_EN (0x0 << 3)
362 #define RK3026_CUR_I_DIS (0x1 << 3)
363 #define RK3026_CUR_2I_EN (0x0 << 2)
364 #define RK3026_CUR_2I_DIS (0x1 << 2)
365 #define RK3026_CUR_4I_EN (0x0 << 0)
366 #define RK3026_CUR_4I_DIS (0x3 << 0)
368 /* PGA AGC control 1 (0xc0 0x100) */
369 #define RK3026_PGA_AGC_WAY_MASK (0x1 << 6)
370 #define RK3026_PGA_AGC_WAY_SFT 6
371 #define RK3026_PGA_AGC_WAY_JACK (0x1 << 6)
372 #define RK3026_PGA_AGC_WAY_NOR (0x0 << 6)
374 #define RK3026_PGA_AGC_BK_WAY_SFT 4
375 #define RK3026_PGA_AGC_BK_WAY_JACK1 (0x1 << 4)
376 #define RK3026_PGA_AGC_BK_WAY_NOR (0x0 << 4)
377 #define RK3026_PGA_AGC_BK_WAY_JACK2 (0x2 << 4)
378 #define RK3026_PGA_AGC_BK_WAY_JACK3 (0x3 << 4)
380 #define RK3026_PGA_AGC_HOLD_T_MASK 0xf
381 #define RK3026_PGA_AGC_HOLD_T_SFT 0
382 #define RK3026_PGA_AGC_HOLD_T_1024 0xa
383 #define RK3026_PGA_AGC_HOLD_T_512 0x9
384 #define RK3026_PGA_AGC_HOLD_T_256 0x8
385 #define RK3026_PGA_AGC_HOLD_T_128 0x7
386 #define RK3026_PGA_AGC_HOLD_T_64 0x6
387 #define RK3026_PGA_AGC_HOLD_T_32 0x5
388 #define RK3026_PGA_AGC_HOLD_T_16 0x4
389 #define RK3026_PGA_AGC_HOLD_T_8 0x3
390 #define RK3026_PGA_AGC_HOLD_T_4 0x2
391 #define RK3026_PGA_AGC_HOLD_T_2 0x1
392 #define RK3026_PGA_AGC_HOLD_T_0 0x0
394 /* PGA AGC control 2 (0xc4 0x104) */
395 #define RK3026_PGA_AGC_GRU_T_MASK (0xf << 4)
396 #define RK3026_PGA_AGC_GRU_T_SFT 4
397 #define RK3026_PGA_AGC_GRU_T_512 (0xa << 4)
398 #define RK3026_PGA_AGC_GRU_T_256 (0x9 << 4)
399 #define RK3026_PGA_AGC_GRU_T_128 (0x8 << 4)
400 #define RK3026_PGA_AGC_GRU_T_64 (0x7 << 4)
401 #define RK3026_PGA_AGC_GRU_T_32 (0x6 << 4)
402 #define RK3026_PGA_AGC_GRU_T_16 (0x5 << 4)
403 #define RK3026_PGA_AGC_GRU_T_8 (0x4 << 4)
404 #define RK3026_PGA_AGC_GRU_T_4 (0x3 << 4)
405 #define RK3026_PGA_AGC_GRU_T_2 (0x2 << 4)
406 #define RK3026_PGA_AGC_GRU_T_1 (0x1 << 4)
407 #define RK3026_PGA_AGC_GRU_T_0_5 (0x0 << 4)
409 #define RK3026_PGA_AGC_GRD_T_MASK 0xf
410 #define RK3026_PGA_AGC_GRD_T_SFT 0
411 #define RK3026_PGA_AGC_GRD_T_128_32 0xa
412 #define RK3026_PGA_AGC_GRD_T_64_16 0x9
413 #define RK3026_PGA_AGC_GRD_T_32_8 0x8
414 #define RK3026_PGA_AGC_GRD_T_16_4 0x7
415 #define RK3026_PGA_AGC_GRD_T_8_2 0x6
416 #define RK3026_PGA_AGC_GRD_T_4_1 0x5
417 #define RK3026_PGA_AGC_GRD_T_2_0_512 0x4
418 #define RK3026_PGA_AGC_GRD_T_1_0_256 0x3
419 #define RK3026_PGA_AGC_GRD_T_0_500_128 0x2
420 #define RK3026_PGA_AGC_GRD_T_0_250_64 0x1
421 #define RK3026_PGA_AGC_GRD_T_0_125_32 0x0
423 /* PGA AGC control 3 (0xc8 0x108) */
424 #define RK3026_PGA_AGC_MODE_MASK (0x1 << 7)
425 #define RK3026_PGA_AGC_MODE_SFT 7
426 #define RK3026_PGA_AGC_MODE_LIMIT (0x1 << 7)
427 #define RK3026_PGA_AGC_MODE_NOR (0x0 << 7)
429 #define RK3026_PGA_AGC_ZO_MASK (0x1 << 6)
430 #define RK3026_PGA_AGC_ZO_SFT 6
431 #define RK3026_PGA_AGC_ZO_EN (0x1 << 6)
432 #define RK3026_PGA_AGC_ZO_DIS (0x0 << 6)
434 #define RK3026_PGA_AGC_REC_MODE_MASK (0x1 << 5)
435 #define RK3026_PGA_AGC_REC_MODE_SFT 5
436 #define RK3026_PGA_AGC_REC_MODE_AC (0x1 << 5)
437 #define RK3026_PGA_AGC_REC_MODE_RN (0x0 << 5)
439 #define RK3026_PGA_AGC_FAST_D_MASK (0x1 << 4)
440 #define RK3026_PGA_AGC_FAST_D_SFT 4
441 #define RK3026_PGA_AGC_FAST_D_EN (0x1 << 4)
442 #define RK3026_PGA_AGC_FAST_D_DIS (0x0 << 4)
444 #define RK3026_PGA_AGC_NG_MASK (0x1 << 3)
445 #define RK3026_PGA_AGC_NG_SFT 3
446 #define RK3026_PGA_AGC_NG_EN (0x1 << 3)
447 #define RK3026_PGA_AGC_NG_DIS (0x0 << 3)
449 #define RK3026_PGA_AGC_NG_THR_MASK 0x7
450 #define RK3026_PGA_AGC_NG_THR_SFT 0
451 #define RK3026_PGA_AGC_NG_THR_N81DB 0x7
452 #define RK3026_PGA_AGC_NG_THR_N75DB 0x6
453 #define RK3026_PGA_AGC_NG_THR_N69DB 0x5
454 #define RK3026_PGA_AGC_NG_THR_N63DB 0x4
455 #define RK3026_PGA_AGC_NG_THR_N57DB 0x3
456 #define RK3026_PGA_AGC_NG_THR_N51DB 0x2
457 #define RK3026_PGA_AGC_NG_THR_N45DB 0x1
458 #define RK3026_PGA_AGC_NG_THR_N39DB 0x0
460 /* PGA AGC Control 4 (0xcc 0x10c) */
461 #define RK3026_PGA_AGC_ZO_MODE_MASK (0x1 << 5)
462 #define RK3026_PGA_AGC_ZO_MODE_SFT 5
463 #define RK3026_PGA_AGC_ZO_MODE_UWRC (0x1 << 5)
464 #define RK3026_PGA_AGC_ZO_MODE_UARC (0x0 << 5)
466 #define RK3026_PGA_AGC_VOL_MASK 0x1f
467 #define RK3026_PGA_AGC_VOL_SFT 0
469 /* PGA ASR Control (0xd0 0x110) */
470 #define RK3026_PGA_SLOW_CLK_MASK (0x1 << 3)
471 #define RK3026_PGA_SLOW_CLK_SFT 3
472 #define RK3026_PGA_SLOW_CLK_EN (0x1 << 3)
473 #define RK3026_PGA_SLOW_CLK_DIS (0x0 << 3)
475 #define RK3026_PGA_ASR_MASK 0x7
476 #define RK3026_PGA_ASR_SFT 0
477 #define RK3026_PGA_ASR_8KHz 0x7
478 #define RK3026_PGA_ASR_12KHz 0x6
479 #define RK3026_PGA_ASR_16KHz 0x5
480 #define RK3026_PGA_ASR_24KHz 0x4
481 #define RK3026_PGA_ASR_32KHz 0x3
482 #define RK3026_PGA_ASR_441KHz 0x2
483 #define RK3026_PGA_ASR_48KHz 0x1
484 #define RK3026_PGA_ASR_96KHz 0x0
486 /* PGA AGC Control 5 (0xe4 0x124) */
487 #define RK3026_PGA_AGC_MASK (0x1 << 6)
488 #define RK3026_PGA_AGC_SFT 6
489 #define RK3026_PGA_AGC_EN (0x1 << 6)
490 #define RK3026_PGA_AGC_DIS (0x0 << 6)
492 #define RK3026_PGA_AGC_MAX_G_MASK (0x7 << 3)
493 #define RK3026_PGA_AGC_MAX_G_SFT 3
494 #define RK3026_PGA_AGC_MAX_G_28_5DB (0x7 << 3)
495 #define RK3026_PGA_AGC_MAX_G_22_5DB (0x6 << 3)
496 #define RK3026_PGA_AGC_MAX_G_16_5DB (0x5 << 3)
497 #define RK3026_PGA_AGC_MAX_G_10_5DB (0x4 << 3)
498 #define RK3026_PGA_AGC_MAX_G_4_5DB (0x3 << 3)
499 #define RK3026_PGA_AGC_MAX_G_N1_5DB (0x2 << 3)
500 #define RK3026_PGA_AGC_MAX_G_N7_5DB (0x1 << 3)
501 #define RK3026_PGA_AGC_MAX_G_N13_5DB (0x0 << 3)
503 #define RK3026_PGA_AGC_MIN_G_MASK 0x7
504 #define RK3026_PGA_AGC_MIN_G_SFT 0
505 #define RK3026_PGA_AGC_MIN_G_24DB 0x7
506 #define RK3026_PGA_AGC_MIN_G_18DB 0x6
507 #define RK3026_PGA_AGC_MIN_G_12DB 0x5
508 #define RK3026_PGA_AGC_MIN_G_6DB 0x4
509 #define RK3026_PGA_AGC_MIN_G_0DB 0x3
510 #define RK3026_PGA_AGC_MIN_G_N6DB 0x2
511 #define RK3026_PGA_AGC_MIN_G_N12DB 0x1
512 #define RK3026_PGA_AGC_MIN_G_N18DB 0x0
545 struct rk3026_reg_val_typ {
550 struct rk3026_init_bit_typ {
552 unsigned int power_bit;
553 unsigned int init2_bit;
554 unsigned int init1_bit;
555 unsigned int init0_bit;
558 struct rk3026_codec_pdata {
564 #endif //__RK3026_CODEC_H__