2 * \file Codec Firmware Declarations
5 #ifndef CFW_FIRMWARE_H_
6 #define CFW_FIRMWARE_H_
8 /** \defgroup bt Basic Types */
10 #ifndef AIC3XXX_CFW_HOST_BLD
11 #include <asm-generic/int-ll64.h>
13 typedef unsigned char u8;
14 typedef unsigned short int u16;
15 typedef unsigned long int u32;
17 typedef signed char i8;
18 typedef signed short int i16;
19 typedef signed long int i32;
21 #define CFW_FW_MAGIC 0xC0D1F1ED
25 /** \defgroup pd Arbitrary Limitations */
28 # define CFW_MAX_ID (64) ///<Max length of string identifies
31 # define CFW_MAX_DESC (512) ///<Max length of description
34 # define CFW_MAX_NOVLY (4) ///<Max number of overlays per PFW
38 # define CFW_MAX_NCFG (16) ///<Max number of configurations per PFW
41 #ifndef CFW_MAX_TRANSITIONS
42 # define CFW_MAX_TRANSITIONS (32) ///<max number of pre-defined transition
46 # define CFW_MAX_NPFW (16) ///<Max number fo process flows
50 # define CFW_MAX_MODES (32) ///<Max number of modes
54 # define CFW_MAX_ASI (4) ///<Max number ASIs in a single device
61 /** \defgroup st Enums, Flags, Macros and Supporting Types */
69 CFW_FS_8KHZ = 0x0001u,
70 CFW_FS_11KHZ = 0x0002u,
71 CFW_FS_16KHZ = 0x0004u,
72 CFW_FS_22KHZ = 0x0008u,
73 CFW_FS_24KHZ = 0x0010u,
74 CFW_FS_32KHZ = 0x0020u,
75 CFW_FS_44KHZ = 0x0040u,
76 CFW_FS_48KHZ = 0x0080u,
77 CFW_FS_88KHZ = 0x0100u,
78 CFW_FS_96KHZ = 0x0200u,
79 CFW_FS_176KHZ = 0x0400u,
80 CFW_FS_192KHZ = 0x0800u,
107 * Device Family Identifier
110 typedef enum __attribute__ ((__packed__)) cfw_dfamily {
120 typedef enum __attribute__ ((__packed__)) cfw_device {
145 * Transition Sequence Identifier
148 typedef enum cfw_transition_t {
156 static const char * const cfw_transition_id[] = {
157 [CFW_TRN_INIT] "INIT",
158 [CFW_TRN_RESUME] "RESUME",
159 [CFW_TRN_NEUTRAL] "NEUTRAL",
160 [CFW_TRN_SUSPEND] "SUSPEND",
161 [CFW_TRN_EXIT] "EXIT",
166 /** \defgroup ds Data Structures */
172 * These commands do not appear in the register
174 * Mainly delay, wait and set_bits.
176 typedef enum __attribute__ ((__packed__)) cfw_meta_cmd {
177 CFW_META_DELAY = 0x80,
185 * Used for the meta command delay
186 * Has one parameter of delay time in ms
188 typedef struct cfw_meta_delay {
195 * CFW set_bits or wait
196 * Both these meta commands have same arguments
197 * mcmd will be used to specify which command it is
198 * has parameters of book, page, offset and mask
200 typedef struct cfw_meta_bitop {
208 * Contains the data structures for the meta commands
210 typedef union cfw_meta_register {
216 cfw_meta_delay delay;
217 cfw_meta_bitop bitop;
227 typedef union cfw_register {
235 cfw_meta_register meta;
241 * A single I2C/SPI burst write sequence
244 typedef struct cfw_burst {
261 * -# single register write,
262 * -# a burst write, or
266 typedef union cfw_cmd {
278 typedef enum __attribute__ ((__packed__)) cfw_block_t {
279 CFW_BLOCK_SYSTEM_PRE,
290 CFW_BLOCK_SYSTEM_POST,
292 CFW_BLOCK_BURSTS = 0x80
294 #define CFW_BLOCK_BURSTS(x) ((x)&CFW_BLOCK_BURSTS)
295 #define CFW_BLOCK_D_A_COEF CFW_BLOCK_D_A1_COEF
296 #define CFW_BLOCK_D_B_COEF CFW_BLOCK_D_B1_COEF
301 * A block of logically grouped sequences/commands/meta-commands
304 typedef struct cfw_block {
314 * A downloadable image
316 typedef struct cfw_image {
317 char name[CFW_MAX_ID]; ///< Name of the pfw/overlay/configuration
318 char desc[CFW_MAX_DESC]; ///< User string
319 cfw_block *block[CFW_BLOCK_N];
327 typedef enum __attribute__ ((__packed__)) cfw_sclk_source {
335 CFW_SYSCLK_HF_REF_CLK,
336 CFW_SYSCLK_HF_OSC_CLK,
345 * Complete description of a process flow
347 typedef struct cfw_pfw {
348 char name[CFW_MAX_ID]; ///< Name of the process flow
349 char desc[CFW_MAX_DESC]; ///< User string
351 u16 supported_fs; ///< Sampling rates at which this process flow may run (bit mask; see \ref cfw_fs)
354 int novly; ///< Number of overlays (1 or more)
355 int ncfg; ///< Number of configurations (0 or more)
357 cfw_image *base; ///< Base sequence
358 cfw_image *ovly_cfg[CFW_MAX_NOVLY][CFW_MAX_NCFG]; ///< Overlay and cfg
359 ///< patches (if any)
366 * Sequence for specific state transisitions within the driver
369 typedef struct cfw_transition {
371 char name[CFW_MAX_ID]; ///< Name of the transition
372 char desc[CFW_MAX_DESC]; ///< User string
379 * Structure linking various operating modes to process flows,
380 * configurations and sequences
383 typedef struct cfw_mode {
385 char name[CFW_MAX_ID];
386 char desc[CFW_MAX_DESC]; ///< User string
399 * Top level structure describing the CFW project
401 typedef struct cfw_project {
408 char name[CFW_MAX_ID]; ///< Project name
409 char desc[CFW_MAX_DESC]; ///< User string
413 cfw_sclk_source clksrc; ///< Clock source
414 u32 clkfreq; ///< Clock frequency
415 cfw_transition *transition[CFW_MAX_TRANSITIONS];
416 u16 npfw; ///< Number of process flows
417 u16 nmode; ///< Number of operating modes
418 cfw_pfw *pfw[CFW_MAX_NPFW]; ///< Indices to PFW locations
419 cfw_mode *mode[CFW_MAX_MODES];
425 #endif /* CFW_FIRMWARE_H_ */