2 * atmel_ssc_dai.c -- ALSA SoC ATMEL SSC Audio Layer Platform driver
4 * Copyright (C) 2005 SAN People
5 * Copyright (C) 2008 Atmel
7 * Author: Sedji Gaouaou <sedji.gaouaou@atmel.com>
10 * Based on at91-ssc.c by
11 * Frank Mandarino <fmandarino@endrelia.com>
12 * Based on pxa2xx Platform drivers by
13 * Liam Girdwood <lrg@slimlogic.co.uk>
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
30 #include <linux/init.h>
31 #include <linux/module.h>
32 #include <linux/interrupt.h>
33 #include <linux/device.h>
34 #include <linux/delay.h>
35 #include <linux/clk.h>
36 #include <linux/atmel_pdc.h>
38 #include <linux/atmel-ssc.h>
39 #include <sound/core.h>
40 #include <sound/pcm.h>
41 #include <sound/pcm_params.h>
42 #include <sound/initval.h>
43 #include <sound/soc.h>
45 #include "atmel-pcm.h"
46 #include "atmel_ssc_dai.h"
49 #define NUM_SSC_DEVICES 3
52 * SSC PDC registers required by the PCM DMA engine.
54 static struct atmel_pdc_regs pdc_tx_reg = {
57 .xnpr = ATMEL_PDC_TNPR,
58 .xncr = ATMEL_PDC_TNCR,
61 static struct atmel_pdc_regs pdc_rx_reg = {
64 .xnpr = ATMEL_PDC_RNPR,
65 .xncr = ATMEL_PDC_RNCR,
69 * SSC & PDC status bits for transmit and receive.
71 static struct atmel_ssc_mask ssc_tx_mask = {
72 .ssc_enable = SSC_BIT(CR_TXEN),
73 .ssc_disable = SSC_BIT(CR_TXDIS),
74 .ssc_endx = SSC_BIT(SR_ENDTX),
75 .ssc_endbuf = SSC_BIT(SR_TXBUFE),
76 .pdc_enable = ATMEL_PDC_TXTEN,
77 .pdc_disable = ATMEL_PDC_TXTDIS,
80 static struct atmel_ssc_mask ssc_rx_mask = {
81 .ssc_enable = SSC_BIT(CR_RXEN),
82 .ssc_disable = SSC_BIT(CR_RXDIS),
83 .ssc_endx = SSC_BIT(SR_ENDRX),
84 .ssc_endbuf = SSC_BIT(SR_RXBUFF),
85 .pdc_enable = ATMEL_PDC_RXTEN,
86 .pdc_disable = ATMEL_PDC_RXTDIS,
93 static struct atmel_pcm_dma_params ssc_dma_params[NUM_SSC_DEVICES][2] = {
95 .name = "SSC0 PCM out",
100 .name = "SSC0 PCM in",
102 .mask = &ssc_rx_mask,
105 .name = "SSC1 PCM out",
107 .mask = &ssc_tx_mask,
110 .name = "SSC1 PCM in",
112 .mask = &ssc_rx_mask,
115 .name = "SSC2 PCM out",
117 .mask = &ssc_tx_mask,
120 .name = "SSC2 PCM in",
122 .mask = &ssc_rx_mask,
127 static struct atmel_ssc_info ssc_info[NUM_SSC_DEVICES] = {
130 .lock = __SPIN_LOCK_UNLOCKED(ssc_info[0].lock),
131 .dir_mask = SSC_DIR_MASK_UNUSED,
136 .lock = __SPIN_LOCK_UNLOCKED(ssc_info[1].lock),
137 .dir_mask = SSC_DIR_MASK_UNUSED,
142 .lock = __SPIN_LOCK_UNLOCKED(ssc_info[2].lock),
143 .dir_mask = SSC_DIR_MASK_UNUSED,
150 * SSC interrupt handler. Passes PDC interrupts to the DMA
151 * interrupt handler in the PCM driver.
153 static irqreturn_t atmel_ssc_interrupt(int irq, void *dev_id)
155 struct atmel_ssc_info *ssc_p = dev_id;
156 struct atmel_pcm_dma_params *dma_params;
158 u32 ssc_substream_mask;
161 ssc_sr = (unsigned long)ssc_readl(ssc_p->ssc->regs, SR)
162 & (unsigned long)ssc_readl(ssc_p->ssc->regs, IMR);
165 * Loop through the substreams attached to this SSC. If
166 * a DMA-related interrupt occurred on that substream, call
167 * the DMA interrupt handler function, if one has been
168 * registered in the dma_params structure by the PCM driver.
170 for (i = 0; i < ARRAY_SIZE(ssc_p->dma_params); i++) {
171 dma_params = ssc_p->dma_params[i];
173 if ((dma_params != NULL) &&
174 (dma_params->dma_intr_handler != NULL)) {
175 ssc_substream_mask = (dma_params->mask->ssc_endx |
176 dma_params->mask->ssc_endbuf);
177 if (ssc_sr & ssc_substream_mask) {
178 dma_params->dma_intr_handler(ssc_sr,
189 /*-------------------------------------------------------------------------*\
191 \*-------------------------------------------------------------------------*/
193 * Startup. Only that one substream allowed in each direction.
195 static int atmel_ssc_startup(struct snd_pcm_substream *substream,
196 struct snd_soc_dai *dai)
198 struct atmel_ssc_info *ssc_p = &ssc_info[dai->id];
201 pr_debug("atmel_ssc_startup: SSC_SR=0x%u\n",
202 ssc_readl(ssc_p->ssc->regs, SR));
204 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
205 dir_mask = SSC_DIR_MASK_PLAYBACK;
207 dir_mask = SSC_DIR_MASK_CAPTURE;
209 spin_lock_irq(&ssc_p->lock);
210 if (ssc_p->dir_mask & dir_mask) {
211 spin_unlock_irq(&ssc_p->lock);
214 ssc_p->dir_mask |= dir_mask;
215 spin_unlock_irq(&ssc_p->lock);
221 * Shutdown. Clear DMA parameters and shutdown the SSC if there
222 * are no other substreams open.
224 static void atmel_ssc_shutdown(struct snd_pcm_substream *substream,
225 struct snd_soc_dai *dai)
227 struct atmel_ssc_info *ssc_p = &ssc_info[dai->id];
228 struct atmel_pcm_dma_params *dma_params;
231 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
236 dma_params = ssc_p->dma_params[dir];
238 if (dma_params != NULL) {
239 ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_disable);
240 pr_debug("atmel_ssc_shutdown: %s disabled SSC_SR=0x%08x\n",
241 (dir ? "receive" : "transmit"),
242 ssc_readl(ssc_p->ssc->regs, SR));
244 dma_params->ssc = NULL;
245 dma_params->substream = NULL;
246 ssc_p->dma_params[dir] = NULL;
251 spin_lock_irq(&ssc_p->lock);
252 ssc_p->dir_mask &= ~dir_mask;
253 if (!ssc_p->dir_mask) {
254 if (ssc_p->initialized) {
255 /* Shutdown the SSC clock. */
256 pr_debug("atmel_ssc_dau: Stopping clock\n");
257 clk_disable(ssc_p->ssc->clk);
259 free_irq(ssc_p->ssc->irq, ssc_p);
260 ssc_p->initialized = 0;
264 ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST));
265 /* Clear the SSC dividers */
266 ssc_p->cmr_div = ssc_p->tcmr_period = ssc_p->rcmr_period = 0;
268 spin_unlock_irq(&ssc_p->lock);
273 * Record the DAI format for use in hw_params().
275 static int atmel_ssc_set_dai_fmt(struct snd_soc_dai *cpu_dai,
278 struct atmel_ssc_info *ssc_p = &ssc_info[cpu_dai->id];
285 * Record SSC clock dividers for use in hw_params().
287 static int atmel_ssc_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
290 struct atmel_ssc_info *ssc_p = &ssc_info[cpu_dai->id];
293 case ATMEL_SSC_CMR_DIV:
295 * The same master clock divider is used for both
296 * transmit and receive, so if a value has already
297 * been set, it must match this value.
299 if (ssc_p->cmr_div == 0)
300 ssc_p->cmr_div = div;
302 if (div != ssc_p->cmr_div)
306 case ATMEL_SSC_TCMR_PERIOD:
307 ssc_p->tcmr_period = div;
310 case ATMEL_SSC_RCMR_PERIOD:
311 ssc_p->rcmr_period = div;
324 static int atmel_ssc_hw_params(struct snd_pcm_substream *substream,
325 struct snd_pcm_hw_params *params,
326 struct snd_soc_dai *dai)
328 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
330 struct atmel_ssc_info *ssc_p = &ssc_info[id];
331 struct atmel_pcm_dma_params *dma_params;
332 int dir, channels, bits;
333 u32 tfmr, rfmr, tcmr, rcmr;
338 * Currently, there is only one set of dma params for
339 * each direction. If more are added, this code will
340 * have to be changed to select the proper set.
342 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
347 dma_params = &ssc_dma_params[id][dir];
348 dma_params->ssc = ssc_p->ssc;
349 dma_params->substream = substream;
351 ssc_p->dma_params[dir] = dma_params;
354 * The snd_soc_pcm_stream->dma_data field is only used to communicate
355 * the appropriate DMA parameters to the pcm driver hw_params()
356 * function. It should not be used for other purposes
357 * as it is common to all substreams.
359 snd_soc_dai_set_dma_data(rtd->cpu_dai, substream, dma_params);
361 channels = params_channels(params);
364 * Determine sample size in bits and the PDC increment.
366 switch (params_format(params)) {
367 case SNDRV_PCM_FORMAT_S8:
369 dma_params->pdc_xfer_size = 1;
371 case SNDRV_PCM_FORMAT_S16_LE:
373 dma_params->pdc_xfer_size = 2;
375 case SNDRV_PCM_FORMAT_S24_LE:
377 dma_params->pdc_xfer_size = 4;
379 case SNDRV_PCM_FORMAT_S32_LE:
381 dma_params->pdc_xfer_size = 4;
384 printk(KERN_WARNING "atmel_ssc_dai: unsupported PCM format");
389 * The SSC only supports up to 16-bit samples in I2S format, due
390 * to the size of the Frame Mode Register FSLEN field.
392 if ((ssc_p->daifmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_I2S
395 "atmel_ssc_dai: sample size %d "
396 "is too large for I2S\n", bits);
401 * Compute SSC register settings.
403 switch (ssc_p->daifmt
404 & (SND_SOC_DAIFMT_FORMAT_MASK | SND_SOC_DAIFMT_MASTER_MASK)) {
406 case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS:
408 * I2S format, SSC provides BCLK and LRC clocks.
410 * The SSC transmit and receive clocks are generated
411 * from the MCK divider, and the BCLK signal
412 * is output on the SSC TK line.
414 rcmr = SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period)
415 | SSC_BF(RCMR_STTDLY, START_DELAY)
416 | SSC_BF(RCMR_START, SSC_START_FALLING_RF)
417 | SSC_BF(RCMR_CKI, SSC_CKI_RISING)
418 | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
419 | SSC_BF(RCMR_CKS, SSC_CKS_DIV);
421 rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
422 | SSC_BF(RFMR_FSOS, SSC_FSOS_NEGATIVE)
423 | SSC_BF(RFMR_FSLEN, (bits - 1))
424 | SSC_BF(RFMR_DATNB, (channels - 1))
426 | SSC_BF(RFMR_LOOP, 0)
427 | SSC_BF(RFMR_DATLEN, (bits - 1));
429 tcmr = SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period)
430 | SSC_BF(TCMR_STTDLY, START_DELAY)
431 | SSC_BF(TCMR_START, SSC_START_FALLING_RF)
432 | SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
433 | SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS)
434 | SSC_BF(TCMR_CKS, SSC_CKS_DIV);
436 tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
437 | SSC_BF(TFMR_FSDEN, 0)
438 | SSC_BF(TFMR_FSOS, SSC_FSOS_NEGATIVE)
439 | SSC_BF(TFMR_FSLEN, (bits - 1))
440 | SSC_BF(TFMR_DATNB, (channels - 1))
442 | SSC_BF(TFMR_DATDEF, 0)
443 | SSC_BF(TFMR_DATLEN, (bits - 1));
446 case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM:
448 * I2S format, CODEC supplies BCLK and LRC clocks.
450 * The SSC transmit clock is obtained from the BCLK signal on
451 * on the TK line, and the SSC receive clock is
452 * generated from the transmit clock.
454 * For single channel data, one sample is transferred
455 * on the falling edge of the LRC clock.
456 * For two channel data, one sample is
457 * transferred on both edges of the LRC clock.
459 start_event = ((channels == 1)
460 ? SSC_START_FALLING_RF
461 : SSC_START_EDGE_RF);
463 rcmr = SSC_BF(RCMR_PERIOD, 0)
464 | SSC_BF(RCMR_STTDLY, START_DELAY)
465 | SSC_BF(RCMR_START, start_event)
466 | SSC_BF(RCMR_CKI, SSC_CKI_RISING)
467 | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
468 | SSC_BF(RCMR_CKS, SSC_CKS_CLOCK);
470 rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
471 | SSC_BF(RFMR_FSOS, SSC_FSOS_NONE)
472 | SSC_BF(RFMR_FSLEN, 0)
473 | SSC_BF(RFMR_DATNB, 0)
475 | SSC_BF(RFMR_LOOP, 0)
476 | SSC_BF(RFMR_DATLEN, (bits - 1));
478 tcmr = SSC_BF(TCMR_PERIOD, 0)
479 | SSC_BF(TCMR_STTDLY, START_DELAY)
480 | SSC_BF(TCMR_START, start_event)
481 | SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
482 | SSC_BF(TCMR_CKO, SSC_CKO_NONE)
483 | SSC_BF(TCMR_CKS, SSC_CKS_PIN);
485 tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
486 | SSC_BF(TFMR_FSDEN, 0)
487 | SSC_BF(TFMR_FSOS, SSC_FSOS_NONE)
488 | SSC_BF(TFMR_FSLEN, 0)
489 | SSC_BF(TFMR_DATNB, 0)
491 | SSC_BF(TFMR_DATDEF, 0)
492 | SSC_BF(TFMR_DATLEN, (bits - 1));
495 case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBS_CFS:
497 * DSP/PCM Mode A format, SSC provides BCLK and LRC clocks.
499 * The SSC transmit and receive clocks are generated from the
500 * MCK divider, and the BCLK signal is output
501 * on the SSC TK line.
503 rcmr = SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period)
504 | SSC_BF(RCMR_STTDLY, 1)
505 | SSC_BF(RCMR_START, SSC_START_RISING_RF)
506 | SSC_BF(RCMR_CKI, SSC_CKI_RISING)
507 | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
508 | SSC_BF(RCMR_CKS, SSC_CKS_DIV);
510 rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
511 | SSC_BF(RFMR_FSOS, SSC_FSOS_POSITIVE)
512 | SSC_BF(RFMR_FSLEN, 0)
513 | SSC_BF(RFMR_DATNB, (channels - 1))
515 | SSC_BF(RFMR_LOOP, 0)
516 | SSC_BF(RFMR_DATLEN, (bits - 1));
518 tcmr = SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period)
519 | SSC_BF(TCMR_STTDLY, 1)
520 | SSC_BF(TCMR_START, SSC_START_RISING_RF)
521 | SSC_BF(TCMR_CKI, SSC_CKI_RISING)
522 | SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS)
523 | SSC_BF(TCMR_CKS, SSC_CKS_DIV);
525 tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
526 | SSC_BF(TFMR_FSDEN, 0)
527 | SSC_BF(TFMR_FSOS, SSC_FSOS_POSITIVE)
528 | SSC_BF(TFMR_FSLEN, 0)
529 | SSC_BF(TFMR_DATNB, (channels - 1))
531 | SSC_BF(TFMR_DATDEF, 0)
532 | SSC_BF(TFMR_DATLEN, (bits - 1));
535 case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBM_CFM:
537 * DSP/PCM Mode A format, CODEC supplies BCLK and LRC clocks.
539 * The SSC transmit clock is obtained from the BCLK signal on
540 * on the TK line, and the SSC receive clock is
541 * generated from the transmit clock.
543 * Data is transferred on first BCLK after LRC pulse rising
544 * edge.If stereo, the right channel data is contiguous with
545 * the left channel data.
547 rcmr = SSC_BF(RCMR_PERIOD, 0)
548 | SSC_BF(RCMR_STTDLY, START_DELAY)
549 | SSC_BF(RCMR_START, SSC_START_RISING_RF)
550 | SSC_BF(RCMR_CKI, SSC_CKI_RISING)
551 | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
552 | SSC_BF(RCMR_CKS, SSC_CKS_PIN);
554 rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
555 | SSC_BF(RFMR_FSOS, SSC_FSOS_NONE)
556 | SSC_BF(RFMR_FSLEN, 0)
557 | SSC_BF(RFMR_DATNB, (channels - 1))
559 | SSC_BF(RFMR_LOOP, 0)
560 | SSC_BF(RFMR_DATLEN, (bits - 1));
562 tcmr = SSC_BF(TCMR_PERIOD, 0)
563 | SSC_BF(TCMR_STTDLY, START_DELAY)
564 | SSC_BF(TCMR_START, SSC_START_RISING_RF)
565 | SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
566 | SSC_BF(TCMR_CKO, SSC_CKO_NONE)
567 | SSC_BF(TCMR_CKS, SSC_CKS_PIN);
569 tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
570 | SSC_BF(TFMR_FSDEN, 0)
571 | SSC_BF(TFMR_FSOS, SSC_FSOS_NONE)
572 | SSC_BF(TFMR_FSLEN, 0)
573 | SSC_BF(TFMR_DATNB, (channels - 1))
575 | SSC_BF(TFMR_DATDEF, 0)
576 | SSC_BF(TFMR_DATLEN, (bits - 1));
580 printk(KERN_WARNING "atmel_ssc_dai: unsupported DAI format 0x%x\n",
584 pr_debug("atmel_ssc_hw_params: "
585 "RCMR=%08x RFMR=%08x TCMR=%08x TFMR=%08x\n",
586 rcmr, rfmr, tcmr, tfmr);
588 if (!ssc_p->initialized) {
590 /* Enable PMC peripheral clock for this SSC */
591 pr_debug("atmel_ssc_dai: Starting clock\n");
592 clk_enable(ssc_p->ssc->clk);
594 /* Reset the SSC and its PDC registers */
595 ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST));
597 ssc_writel(ssc_p->ssc->regs, PDC_RPR, 0);
598 ssc_writel(ssc_p->ssc->regs, PDC_RCR, 0);
599 ssc_writel(ssc_p->ssc->regs, PDC_RNPR, 0);
600 ssc_writel(ssc_p->ssc->regs, PDC_RNCR, 0);
602 ssc_writel(ssc_p->ssc->regs, PDC_TPR, 0);
603 ssc_writel(ssc_p->ssc->regs, PDC_TCR, 0);
604 ssc_writel(ssc_p->ssc->regs, PDC_TNPR, 0);
605 ssc_writel(ssc_p->ssc->regs, PDC_TNCR, 0);
607 ret = request_irq(ssc_p->ssc->irq, atmel_ssc_interrupt, 0,
611 "atmel_ssc_dai: request_irq failure\n");
612 pr_debug("Atmel_ssc_dai: Stoping clock\n");
613 clk_disable(ssc_p->ssc->clk);
617 ssc_p->initialized = 1;
620 /* set SSC clock mode register */
621 ssc_writel(ssc_p->ssc->regs, CMR, ssc_p->cmr_div);
623 /* set receive clock mode and format */
624 ssc_writel(ssc_p->ssc->regs, RCMR, rcmr);
625 ssc_writel(ssc_p->ssc->regs, RFMR, rfmr);
627 /* set transmit clock mode and format */
628 ssc_writel(ssc_p->ssc->regs, TCMR, tcmr);
629 ssc_writel(ssc_p->ssc->regs, TFMR, tfmr);
631 pr_debug("atmel_ssc_dai,hw_params: SSC initialized\n");
636 static int atmel_ssc_prepare(struct snd_pcm_substream *substream,
637 struct snd_soc_dai *dai)
639 struct atmel_ssc_info *ssc_p = &ssc_info[dai->id];
640 struct atmel_pcm_dma_params *dma_params;
643 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
648 dma_params = ssc_p->dma_params[dir];
650 ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_enable);
652 pr_debug("%s enabled SSC_SR=0x%08x\n",
653 dir ? "receive" : "transmit",
654 ssc_readl(ssc_p->ssc->regs, SR));
660 static int atmel_ssc_suspend(struct snd_soc_dai *cpu_dai)
662 struct atmel_ssc_info *ssc_p;
664 if (!cpu_dai->active)
667 ssc_p = &ssc_info[cpu_dai->id];
669 /* Save the status register before disabling transmit and receive */
670 ssc_p->ssc_state.ssc_sr = ssc_readl(ssc_p->ssc->regs, SR);
671 ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_TXDIS) | SSC_BIT(CR_RXDIS));
673 /* Save the current interrupt mask, then disable unmasked interrupts */
674 ssc_p->ssc_state.ssc_imr = ssc_readl(ssc_p->ssc->regs, IMR);
675 ssc_writel(ssc_p->ssc->regs, IDR, ssc_p->ssc_state.ssc_imr);
677 ssc_p->ssc_state.ssc_cmr = ssc_readl(ssc_p->ssc->regs, CMR);
678 ssc_p->ssc_state.ssc_rcmr = ssc_readl(ssc_p->ssc->regs, RCMR);
679 ssc_p->ssc_state.ssc_rfmr = ssc_readl(ssc_p->ssc->regs, RFMR);
680 ssc_p->ssc_state.ssc_tcmr = ssc_readl(ssc_p->ssc->regs, TCMR);
681 ssc_p->ssc_state.ssc_tfmr = ssc_readl(ssc_p->ssc->regs, TFMR);
688 static int atmel_ssc_resume(struct snd_soc_dai *cpu_dai)
690 struct atmel_ssc_info *ssc_p;
693 if (!cpu_dai->active)
696 ssc_p = &ssc_info[cpu_dai->id];
698 /* restore SSC register settings */
699 ssc_writel(ssc_p->ssc->regs, TFMR, ssc_p->ssc_state.ssc_tfmr);
700 ssc_writel(ssc_p->ssc->regs, TCMR, ssc_p->ssc_state.ssc_tcmr);
701 ssc_writel(ssc_p->ssc->regs, RFMR, ssc_p->ssc_state.ssc_rfmr);
702 ssc_writel(ssc_p->ssc->regs, RCMR, ssc_p->ssc_state.ssc_rcmr);
703 ssc_writel(ssc_p->ssc->regs, CMR, ssc_p->ssc_state.ssc_cmr);
705 /* re-enable interrupts */
706 ssc_writel(ssc_p->ssc->regs, IER, ssc_p->ssc_state.ssc_imr);
708 /* Re-enable receive and transmit as appropriate */
711 (ssc_p->ssc_state.ssc_sr & SSC_BIT(SR_RXEN)) ? SSC_BIT(CR_RXEN) : 0;
713 (ssc_p->ssc_state.ssc_sr & SSC_BIT(SR_TXEN)) ? SSC_BIT(CR_TXEN) : 0;
714 ssc_writel(ssc_p->ssc->regs, CR, cr);
718 #else /* CONFIG_PM */
719 # define atmel_ssc_suspend NULL
720 # define atmel_ssc_resume NULL
721 #endif /* CONFIG_PM */
723 #define ATMEL_SSC_RATES (SNDRV_PCM_RATE_8000_96000)
725 #define ATMEL_SSC_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
726 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
728 static const struct snd_soc_dai_ops atmel_ssc_dai_ops = {
729 .startup = atmel_ssc_startup,
730 .shutdown = atmel_ssc_shutdown,
731 .prepare = atmel_ssc_prepare,
732 .hw_params = atmel_ssc_hw_params,
733 .set_fmt = atmel_ssc_set_dai_fmt,
734 .set_clkdiv = atmel_ssc_set_dai_clkdiv,
737 static struct snd_soc_dai_driver atmel_ssc_dai = {
738 .suspend = atmel_ssc_suspend,
739 .resume = atmel_ssc_resume,
743 .rates = ATMEL_SSC_RATES,
744 .formats = ATMEL_SSC_FORMATS,},
748 .rates = ATMEL_SSC_RATES,
749 .formats = ATMEL_SSC_FORMATS,},
750 .ops = &atmel_ssc_dai_ops,
753 static const struct snd_soc_component_driver atmel_ssc_component = {
757 static int asoc_ssc_init(struct device *dev)
759 struct platform_device *pdev = to_platform_device(dev);
760 struct ssc_device *ssc = platform_get_drvdata(pdev);
763 ret = snd_soc_register_component(dev, &atmel_ssc_component,
766 dev_err(dev, "Could not register DAI: %d\n", ret);
770 if (ssc->pdata->use_dma)
771 ret = atmel_pcm_dma_platform_register(dev);
773 ret = atmel_pcm_pdc_platform_register(dev);
776 dev_err(dev, "Could not register PCM: %d\n", ret);
777 goto err_unregister_dai;
783 snd_soc_unregister_component(dev);
788 static void asoc_ssc_exit(struct device *dev)
790 struct platform_device *pdev = to_platform_device(dev);
791 struct ssc_device *ssc = platform_get_drvdata(pdev);
793 if (ssc->pdata->use_dma)
794 atmel_pcm_dma_platform_unregister(dev);
796 atmel_pcm_pdc_platform_unregister(dev);
798 snd_soc_unregister_component(dev);
802 * atmel_ssc_set_audio - Allocate the specified SSC for audio use.
804 int atmel_ssc_set_audio(int ssc_id)
806 struct ssc_device *ssc;
809 /* If we can grab the SSC briefly to parent the DAI device off it */
810 ssc = ssc_request(ssc_id);
812 pr_err("Unable to parent ASoC SSC DAI on SSC: %ld\n",
816 ssc_info[ssc_id].ssc = ssc;
819 ret = asoc_ssc_init(&ssc->pdev->dev);
823 EXPORT_SYMBOL_GPL(atmel_ssc_set_audio);
825 void atmel_ssc_put_audio(int ssc_id)
827 struct ssc_device *ssc = ssc_info[ssc_id].ssc;
829 asoc_ssc_exit(&ssc->pdev->dev);
832 EXPORT_SYMBOL_GPL(atmel_ssc_put_audio);
834 /* Module information */
835 MODULE_AUTHOR("Sedji Gaouaou, sedji.gaouaou@atmel.com, www.atmel.com");
836 MODULE_DESCRIPTION("ATMEL SSC ASoC Interface");
837 MODULE_LICENSE("GPL");