3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
9 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
12 * Wu Fengguang <wfg@linux.intel.com>
15 * Wu Fengguang <wfg@linux.intel.com>
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the Free
19 * Software Foundation; either version 2 of the License, or (at your option)
22 * This program is distributed in the hope that it will be useful, but
23 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
24 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software Foundation,
29 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
32 #include <linux/init.h>
33 #include <linux/delay.h>
34 #include <linux/slab.h>
35 #include <linux/module.h>
36 #include <sound/core.h>
37 #include <sound/jack.h>
38 #include <sound/asoundef.h>
39 #include <sound/tlv.h>
40 #include <sound/hdaudio.h>
41 #include <sound/hda_i915.h>
42 #include "hda_codec.h"
43 #include "hda_local.h"
46 static bool static_hdmi_pcm;
47 module_param(static_hdmi_pcm, bool, 0644);
48 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
50 #define is_haswell(codec) ((codec)->core.vendor_id == 0x80862807)
51 #define is_broadwell(codec) ((codec)->core.vendor_id == 0x80862808)
52 #define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809)
53 #define is_broxton(codec) ((codec)->core.vendor_id == 0x8086280a)
54 #define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \
55 || is_skylake(codec) || is_broxton(codec))
57 #define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882)
58 #define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883)
59 #define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec))
61 struct hdmi_spec_per_cvt {
64 unsigned int channels_min;
65 unsigned int channels_max;
71 /* max. connections to a widget */
72 #define HDA_MAX_CONNECTIONS 32
74 struct hdmi_spec_per_pin {
77 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
81 struct hda_codec *codec;
82 struct hdmi_eld sink_eld;
84 struct delayed_work work;
85 struct snd_kcontrol *eld_ctl;
87 bool setup; /* the stream has been set up by prepare callback */
88 int channels; /* current number of channels */
90 bool chmap_set; /* channel-map override by ALSA API? */
91 unsigned char chmap[8]; /* ALSA API channel-map */
92 #ifdef CONFIG_SND_PROC_FS
93 struct snd_info_entry *proc_entry;
97 struct cea_channel_speaker_allocation;
99 /* operations used by generic code that can be overridden by patches */
101 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
102 unsigned char *buf, int *eld_size);
104 /* get and set channel assigned to each HDMI ASP (audio sample packet) slot */
105 int (*pin_get_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
107 int (*pin_set_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
108 int asp_slot, int channel);
110 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
111 int ca, int active_channels, int conn_type);
113 /* enable/disable HBR (HD passthrough) */
114 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
116 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
117 hda_nid_t pin_nid, u32 stream_tag, int format);
119 /* Helpers for producing the channel map TLVs. These can be overridden
120 * for devices that have non-standard mapping requirements. */
121 int (*chmap_cea_alloc_validate_get_type)(struct cea_channel_speaker_allocation *cap,
123 void (*cea_alloc_to_tlv_chmap)(struct cea_channel_speaker_allocation *cap,
124 unsigned int *chmap, int channels);
126 /* check that the user-given chmap is supported */
127 int (*chmap_validate)(int ca, int channels, unsigned char *chmap);
132 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
133 hda_nid_t cvt_nids[4]; /* only for haswell fix */
136 struct snd_array pins; /* struct hdmi_spec_per_pin */
137 struct hda_pcm *pcm_rec[16];
138 unsigned int channels_max; /* max over all cvts */
140 struct hdmi_eld temp_eld;
146 * Non-generic VIA/NVIDIA specific
148 struct hda_multi_out multiout;
149 struct hda_pcm_stream pcm_playback;
151 /* i915/powerwell (Haswell+/Valleyview+) specific */
152 struct i915_audio_component_audio_ops i915_audio_ops;
156 struct hdmi_audio_infoframe {
163 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
167 u8 LFEPBL01_LSV36_DM_INH7;
170 struct dp_audio_infoframe {
173 u8 ver; /* 0x11 << 2 */
175 u8 CC02_CT47; /* match with HDMI infoframe from this on */
179 u8 LFEPBL01_LSV36_DM_INH7;
182 union audio_infoframe {
183 struct hdmi_audio_infoframe hdmi;
184 struct dp_audio_infoframe dp;
189 * CEA speaker placement:
192 * FLW FL FLC FC FRC FR FRW
199 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
200 * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
202 enum cea_speaker_placement {
203 FL = (1 << 0), /* Front Left */
204 FC = (1 << 1), /* Front Center */
205 FR = (1 << 2), /* Front Right */
206 FLC = (1 << 3), /* Front Left Center */
207 FRC = (1 << 4), /* Front Right Center */
208 RL = (1 << 5), /* Rear Left */
209 RC = (1 << 6), /* Rear Center */
210 RR = (1 << 7), /* Rear Right */
211 RLC = (1 << 8), /* Rear Left Center */
212 RRC = (1 << 9), /* Rear Right Center */
213 LFE = (1 << 10), /* Low Frequency Effect */
214 FLW = (1 << 11), /* Front Left Wide */
215 FRW = (1 << 12), /* Front Right Wide */
216 FLH = (1 << 13), /* Front Left High */
217 FCH = (1 << 14), /* Front Center High */
218 FRH = (1 << 15), /* Front Right High */
219 TC = (1 << 16), /* Top Center */
223 * ELD SA bits in the CEA Speaker Allocation data block
225 static int eld_speaker_allocation_bits[] = {
233 /* the following are not defined in ELD yet */
240 struct cea_channel_speaker_allocation {
244 /* derived values, just for convenience */
252 * surround40 surround41 surround50 surround51 surround71
253 * ch0 front left = = = =
254 * ch1 front right = = = =
255 * ch2 rear left = = = =
256 * ch3 rear right = = = =
257 * ch4 LFE center center center
262 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
264 static int hdmi_channel_mapping[0x32][8] = {
266 [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
268 [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
270 [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
272 [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
274 [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
276 [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
278 [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
280 [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
282 [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
286 * This is an ordered list!
288 * The preceding ones have better chances to be selected by
289 * hdmi_channel_allocation().
291 static struct cea_channel_speaker_allocation channel_allocations[] = {
292 /* channel: 7 6 5 4 3 2 1 0 */
293 { .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
295 { .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
297 { .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
299 { .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
301 { .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
303 { .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
305 { .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
307 { .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
309 { .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
311 { .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
312 { .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
313 { .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
314 { .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
315 { .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
316 { .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
317 { .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
318 { .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
319 { .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
320 { .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
321 { .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
322 { .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
323 { .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
324 { .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
325 { .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
326 { .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
327 { .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
328 { .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
329 { .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
330 { .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
331 { .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
332 { .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
333 { .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
334 { .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
335 { .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
336 { .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
337 { .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
338 { .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
339 { .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
340 { .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
341 { .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
342 { .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
343 { .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
344 { .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
345 { .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
346 { .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
347 { .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
348 { .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
349 { .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
350 { .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
351 { .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
359 #define get_pin(spec, idx) \
360 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
361 #define get_cvt(spec, idx) \
362 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
363 #define get_pcm_rec(spec, idx) ((spec)->pcm_rec[idx])
365 static int pin_nid_to_pin_index(struct hda_codec *codec, hda_nid_t pin_nid)
367 struct hdmi_spec *spec = codec->spec;
370 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
371 if (get_pin(spec, pin_idx)->pin_nid == pin_nid)
374 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
378 static int hinfo_to_pin_index(struct hda_codec *codec,
379 struct hda_pcm_stream *hinfo)
381 struct hdmi_spec *spec = codec->spec;
384 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
385 if (get_pcm_rec(spec, pin_idx)->stream == hinfo)
388 codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo);
392 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
394 struct hdmi_spec *spec = codec->spec;
397 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
398 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
401 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
405 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
406 struct snd_ctl_elem_info *uinfo)
408 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
409 struct hdmi_spec *spec = codec->spec;
410 struct hdmi_spec_per_pin *per_pin;
411 struct hdmi_eld *eld;
414 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
416 pin_idx = kcontrol->private_value;
417 per_pin = get_pin(spec, pin_idx);
418 eld = &per_pin->sink_eld;
420 mutex_lock(&per_pin->lock);
421 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
422 mutex_unlock(&per_pin->lock);
427 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
428 struct snd_ctl_elem_value *ucontrol)
430 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
431 struct hdmi_spec *spec = codec->spec;
432 struct hdmi_spec_per_pin *per_pin;
433 struct hdmi_eld *eld;
436 pin_idx = kcontrol->private_value;
437 per_pin = get_pin(spec, pin_idx);
438 eld = &per_pin->sink_eld;
440 mutex_lock(&per_pin->lock);
441 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) ||
442 eld->eld_size > ELD_MAX_SIZE) {
443 mutex_unlock(&per_pin->lock);
448 memset(ucontrol->value.bytes.data, 0,
449 ARRAY_SIZE(ucontrol->value.bytes.data));
451 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
453 mutex_unlock(&per_pin->lock);
458 static struct snd_kcontrol_new eld_bytes_ctl = {
459 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
460 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
462 .info = hdmi_eld_ctl_info,
463 .get = hdmi_eld_ctl_get,
466 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx,
469 struct snd_kcontrol *kctl;
470 struct hdmi_spec *spec = codec->spec;
473 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
476 kctl->private_value = pin_idx;
477 kctl->id.device = device;
479 err = snd_hda_ctl_add(codec, get_pin(spec, pin_idx)->pin_nid, kctl);
483 get_pin(spec, pin_idx)->eld_ctl = kctl;
488 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
489 int *packet_index, int *byte_index)
493 val = snd_hda_codec_read(codec, pin_nid, 0,
494 AC_VERB_GET_HDMI_DIP_INDEX, 0);
496 *packet_index = val >> 5;
497 *byte_index = val & 0x1f;
501 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
502 int packet_index, int byte_index)
506 val = (packet_index << 5) | (byte_index & 0x1f);
508 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
511 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
514 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
517 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
519 struct hdmi_spec *spec = codec->spec;
523 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
524 snd_hda_codec_write(codec, pin_nid, 0,
525 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
527 if (spec->dyn_pin_out)
528 /* Disable pin out until stream is active */
531 /* Enable pin out: some machines with GM965 gets broken output
532 * when the pin is disabled or changed while using with HDMI
536 snd_hda_codec_write(codec, pin_nid, 0,
537 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
540 static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid)
542 return 1 + snd_hda_codec_read(codec, cvt_nid, 0,
543 AC_VERB_GET_CVT_CHAN_COUNT, 0);
546 static void hdmi_set_channel_count(struct hda_codec *codec,
547 hda_nid_t cvt_nid, int chs)
549 if (chs != hdmi_get_channel_count(codec, cvt_nid))
550 snd_hda_codec_write(codec, cvt_nid, 0,
551 AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
558 #ifdef CONFIG_SND_PROC_FS
559 static void print_eld_info(struct snd_info_entry *entry,
560 struct snd_info_buffer *buffer)
562 struct hdmi_spec_per_pin *per_pin = entry->private_data;
564 mutex_lock(&per_pin->lock);
565 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
566 mutex_unlock(&per_pin->lock);
569 static void write_eld_info(struct snd_info_entry *entry,
570 struct snd_info_buffer *buffer)
572 struct hdmi_spec_per_pin *per_pin = entry->private_data;
574 mutex_lock(&per_pin->lock);
575 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
576 mutex_unlock(&per_pin->lock);
579 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
582 struct hda_codec *codec = per_pin->codec;
583 struct snd_info_entry *entry;
586 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
587 err = snd_card_proc_new(codec->card, name, &entry);
591 snd_info_set_text_ops(entry, per_pin, print_eld_info);
592 entry->c.text.write = write_eld_info;
593 entry->mode |= S_IWUSR;
594 per_pin->proc_entry = entry;
599 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
601 if (!per_pin->codec->bus->shutdown) {
602 snd_info_free_entry(per_pin->proc_entry);
603 per_pin->proc_entry = NULL;
607 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
612 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
618 * Channel mapping routines
622 * Compute derived values in channel_allocations[].
624 static void init_channel_allocations(void)
627 struct cea_channel_speaker_allocation *p;
629 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
630 p = channel_allocations + i;
633 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
634 if (p->speakers[j]) {
636 p->spk_mask |= p->speakers[j];
641 static int get_channel_allocation_order(int ca)
645 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
646 if (channel_allocations[i].ca_index == ca)
653 * The transformation takes two steps:
655 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
656 * spk_mask => (channel_allocations[]) => ai->CA
658 * TODO: it could select the wrong CA from multiple candidates.
660 static int hdmi_channel_allocation(struct hda_codec *codec,
661 struct hdmi_eld *eld, int channels)
666 char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
669 * CA defaults to 0 for basic stereo audio
675 * expand ELD's speaker allocation mask
677 * ELD tells the speaker mask in a compact(paired) form,
678 * expand ELD's notions to match the ones used by Audio InfoFrame.
680 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
681 if (eld->info.spk_alloc & (1 << i))
682 spk_mask |= eld_speaker_allocation_bits[i];
685 /* search for the first working match in the CA table */
686 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
687 if (channels == channel_allocations[i].channels &&
688 (spk_mask & channel_allocations[i].spk_mask) ==
689 channel_allocations[i].spk_mask) {
690 ca = channel_allocations[i].ca_index;
696 /* if there was no match, select the regular ALSA channel
697 * allocation with the matching number of channels */
698 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
699 if (channels == channel_allocations[i].channels) {
700 ca = channel_allocations[i].ca_index;
706 snd_print_channel_allocation(eld->info.spk_alloc, buf, sizeof(buf));
707 codec_dbg(codec, "HDMI: select CA 0x%x for %d-channel allocation: %s\n",
713 static void hdmi_debug_channel_mapping(struct hda_codec *codec,
716 #ifdef CONFIG_SND_DEBUG_VERBOSE
717 struct hdmi_spec *spec = codec->spec;
721 for (i = 0; i < 8; i++) {
722 channel = spec->ops.pin_get_slot_channel(codec, pin_nid, i);
723 codec_dbg(codec, "HDMI: ASP channel %d => slot %d\n",
729 static void hdmi_std_setup_channel_mapping(struct hda_codec *codec,
734 struct hdmi_spec *spec = codec->spec;
735 struct cea_channel_speaker_allocation *ch_alloc;
739 int non_pcm_mapping[8];
741 order = get_channel_allocation_order(ca);
742 ch_alloc = &channel_allocations[order];
744 if (hdmi_channel_mapping[ca][1] == 0) {
746 /* fill actual channel mappings in ALSA channel (i) order */
747 for (i = 0; i < ch_alloc->channels; i++) {
748 while (!ch_alloc->speakers[7 - hdmi_slot] && !WARN_ON(hdmi_slot >= 8))
749 hdmi_slot++; /* skip zero slots */
751 hdmi_channel_mapping[ca][i] = (i << 4) | hdmi_slot++;
753 /* fill the rest of the slots with ALSA channel 0xf */
754 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++)
755 if (!ch_alloc->speakers[7 - hdmi_slot])
756 hdmi_channel_mapping[ca][i++] = (0xf << 4) | hdmi_slot;
760 for (i = 0; i < ch_alloc->channels; i++)
761 non_pcm_mapping[i] = (i << 4) | i;
763 non_pcm_mapping[i] = (0xf << 4) | i;
766 for (i = 0; i < 8; i++) {
767 int slotsetup = non_pcm ? non_pcm_mapping[i] : hdmi_channel_mapping[ca][i];
768 int hdmi_slot = slotsetup & 0x0f;
769 int channel = (slotsetup & 0xf0) >> 4;
770 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot, channel);
772 codec_dbg(codec, "HDMI: channel mapping failed\n");
778 struct channel_map_table {
779 unsigned char map; /* ALSA API channel map position */
780 int spk_mask; /* speaker position bit mask */
783 static struct channel_map_table map_tables[] = {
784 { SNDRV_CHMAP_FL, FL },
785 { SNDRV_CHMAP_FR, FR },
786 { SNDRV_CHMAP_RL, RL },
787 { SNDRV_CHMAP_RR, RR },
788 { SNDRV_CHMAP_LFE, LFE },
789 { SNDRV_CHMAP_FC, FC },
790 { SNDRV_CHMAP_RLC, RLC },
791 { SNDRV_CHMAP_RRC, RRC },
792 { SNDRV_CHMAP_RC, RC },
793 { SNDRV_CHMAP_FLC, FLC },
794 { SNDRV_CHMAP_FRC, FRC },
795 { SNDRV_CHMAP_TFL, FLH },
796 { SNDRV_CHMAP_TFR, FRH },
797 { SNDRV_CHMAP_FLW, FLW },
798 { SNDRV_CHMAP_FRW, FRW },
799 { SNDRV_CHMAP_TC, TC },
800 { SNDRV_CHMAP_TFC, FCH },
804 /* from ALSA API channel position to speaker bit mask */
805 static int to_spk_mask(unsigned char c)
807 struct channel_map_table *t = map_tables;
808 for (; t->map; t++) {
815 /* from ALSA API channel position to CEA slot */
816 static int to_cea_slot(int ordered_ca, unsigned char pos)
818 int mask = to_spk_mask(pos);
822 for (i = 0; i < 8; i++) {
823 if (channel_allocations[ordered_ca].speakers[7 - i] == mask)
831 /* from speaker bit mask to ALSA API channel position */
832 static int spk_to_chmap(int spk)
834 struct channel_map_table *t = map_tables;
835 for (; t->map; t++) {
836 if (t->spk_mask == spk)
842 /* from CEA slot to ALSA API channel position */
843 static int from_cea_slot(int ordered_ca, unsigned char slot)
845 int mask = channel_allocations[ordered_ca].speakers[7 - slot];
847 return spk_to_chmap(mask);
850 /* get the CA index corresponding to the given ALSA API channel map */
851 static int hdmi_manual_channel_allocation(int chs, unsigned char *map)
853 int i, spks = 0, spk_mask = 0;
855 for (i = 0; i < chs; i++) {
856 int mask = to_spk_mask(map[i]);
863 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
864 if ((chs == channel_allocations[i].channels ||
865 spks == channel_allocations[i].channels) &&
866 (spk_mask & channel_allocations[i].spk_mask) ==
867 channel_allocations[i].spk_mask)
868 return channel_allocations[i].ca_index;
873 /* set up the channel slots for the given ALSA API channel map */
874 static int hdmi_manual_setup_channel_mapping(struct hda_codec *codec,
876 int chs, unsigned char *map,
879 struct hdmi_spec *spec = codec->spec;
880 int ordered_ca = get_channel_allocation_order(ca);
881 int alsa_pos, hdmi_slot;
882 int assignments[8] = {[0 ... 7] = 0xf};
884 for (alsa_pos = 0; alsa_pos < chs; alsa_pos++) {
886 hdmi_slot = to_cea_slot(ordered_ca, map[alsa_pos]);
889 continue; /* unassigned channel */
891 assignments[hdmi_slot] = alsa_pos;
894 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++) {
897 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot,
898 assignments[hdmi_slot]);
905 /* store ALSA API channel map from the current default map */
906 static void hdmi_setup_fake_chmap(unsigned char *map, int ca)
909 int ordered_ca = get_channel_allocation_order(ca);
910 for (i = 0; i < 8; i++) {
911 if (i < channel_allocations[ordered_ca].channels)
912 map[i] = from_cea_slot(ordered_ca, hdmi_channel_mapping[ca][i] & 0x0f);
918 static void hdmi_setup_channel_mapping(struct hda_codec *codec,
919 hda_nid_t pin_nid, bool non_pcm, int ca,
920 int channels, unsigned char *map,
923 if (!non_pcm && chmap_set) {
924 hdmi_manual_setup_channel_mapping(codec, pin_nid,
927 hdmi_std_setup_channel_mapping(codec, pin_nid, non_pcm, ca);
928 hdmi_setup_fake_chmap(map, ca);
931 hdmi_debug_channel_mapping(codec, pin_nid);
934 static int hdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
935 int asp_slot, int channel)
937 return snd_hda_codec_write(codec, pin_nid, 0,
938 AC_VERB_SET_HDMI_CHAN_SLOT,
939 (channel << 4) | asp_slot);
942 static int hdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
945 return (snd_hda_codec_read(codec, pin_nid, 0,
946 AC_VERB_GET_HDMI_CHAN_SLOT,
947 asp_slot) & 0xf0) >> 4;
951 * Audio InfoFrame routines
955 * Enable Audio InfoFrame Transmission
957 static void hdmi_start_infoframe_trans(struct hda_codec *codec,
960 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
961 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
966 * Disable Audio InfoFrame Transmission
968 static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
971 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
972 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
976 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
978 #ifdef CONFIG_SND_DEBUG_VERBOSE
982 size = snd_hdmi_get_eld_size(codec, pin_nid);
983 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
985 for (i = 0; i < 8; i++) {
986 size = snd_hda_codec_read(codec, pin_nid, 0,
987 AC_VERB_GET_HDMI_DIP_SIZE, i);
988 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
993 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
999 for (i = 0; i < 8; i++) {
1000 size = snd_hda_codec_read(codec, pin_nid, 0,
1001 AC_VERB_GET_HDMI_DIP_SIZE, i);
1005 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
1006 for (j = 1; j < 1000; j++) {
1007 hdmi_write_dip_byte(codec, pin_nid, 0x0);
1008 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
1010 codec_dbg(codec, "dip index %d: %d != %d\n",
1012 if (bi == 0) /* byte index wrapped around */
1016 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
1022 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
1024 u8 *bytes = (u8 *)hdmi_ai;
1028 hdmi_ai->checksum = 0;
1030 for (i = 0; i < sizeof(*hdmi_ai); i++)
1033 hdmi_ai->checksum = -sum;
1036 static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
1042 hdmi_debug_dip_size(codec, pin_nid);
1043 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
1045 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
1046 for (i = 0; i < size; i++)
1047 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
1050 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
1056 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
1060 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
1061 for (i = 0; i < size; i++) {
1062 val = snd_hda_codec_read(codec, pin_nid, 0,
1063 AC_VERB_GET_HDMI_DIP_DATA, 0);
1071 static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
1073 int ca, int active_channels,
1076 union audio_infoframe ai;
1078 memset(&ai, 0, sizeof(ai));
1079 if (conn_type == 0) { /* HDMI */
1080 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
1082 hdmi_ai->type = 0x84;
1083 hdmi_ai->ver = 0x01;
1084 hdmi_ai->len = 0x0a;
1085 hdmi_ai->CC02_CT47 = active_channels - 1;
1087 hdmi_checksum_audio_infoframe(hdmi_ai);
1088 } else if (conn_type == 1) { /* DisplayPort */
1089 struct dp_audio_infoframe *dp_ai = &ai.dp;
1093 dp_ai->ver = 0x11 << 2;
1094 dp_ai->CC02_CT47 = active_channels - 1;
1097 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
1103 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
1104 * sizeof(*dp_ai) to avoid partial match/update problems when
1105 * the user switches between HDMI/DP monitors.
1107 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
1110 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
1112 active_channels, ca);
1113 hdmi_stop_infoframe_trans(codec, pin_nid);
1114 hdmi_fill_audio_infoframe(codec, pin_nid,
1115 ai.bytes, sizeof(ai));
1116 hdmi_start_infoframe_trans(codec, pin_nid);
1120 static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
1121 struct hdmi_spec_per_pin *per_pin,
1124 struct hdmi_spec *spec = codec->spec;
1125 hda_nid_t pin_nid = per_pin->pin_nid;
1126 int channels = per_pin->channels;
1127 int active_channels;
1128 struct hdmi_eld *eld;
1134 if (is_haswell_plus(codec))
1135 snd_hda_codec_write(codec, pin_nid, 0,
1136 AC_VERB_SET_AMP_GAIN_MUTE,
1139 eld = &per_pin->sink_eld;
1141 if (!non_pcm && per_pin->chmap_set)
1142 ca = hdmi_manual_channel_allocation(channels, per_pin->chmap);
1144 ca = hdmi_channel_allocation(codec, eld, channels);
1148 ordered_ca = get_channel_allocation_order(ca);
1149 active_channels = channel_allocations[ordered_ca].channels;
1151 hdmi_set_channel_count(codec, per_pin->cvt_nid, active_channels);
1154 * always configure channel mapping, it may have been changed by the
1155 * user in the meantime
1157 hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
1158 channels, per_pin->chmap,
1159 per_pin->chmap_set);
1161 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
1162 eld->info.conn_type);
1164 per_pin->non_pcm = non_pcm;
1168 * Unsolicited events
1171 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
1173 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid)
1175 struct hdmi_spec *spec = codec->spec;
1176 int pin_idx = pin_nid_to_pin_index(codec, nid);
1180 if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
1181 snd_hda_jack_report_sync(codec);
1184 static void jack_callback(struct hda_codec *codec,
1185 struct hda_jack_callback *jack)
1187 check_presence_and_report(codec, jack->tbl->nid);
1190 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
1192 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1193 struct hda_jack_tbl *jack;
1194 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
1196 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
1199 jack->jack_dirty = 1;
1202 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
1203 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
1204 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
1206 check_presence_and_report(codec, jack->nid);
1209 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
1211 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1212 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1213 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
1214 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
1217 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
1232 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
1234 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1235 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1237 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
1238 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
1243 hdmi_intrinsic_event(codec, res);
1245 hdmi_non_intrinsic_event(codec, res);
1248 static void haswell_verify_D0(struct hda_codec *codec,
1249 hda_nid_t cvt_nid, hda_nid_t nid)
1253 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
1254 * thus pins could only choose converter 0 for use. Make sure the
1255 * converters are in correct power state */
1256 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
1257 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
1259 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
1260 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
1263 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
1264 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
1265 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
1273 /* HBR should be Non-PCM, 8 channels */
1274 #define is_hbr_format(format) \
1275 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
1277 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
1280 int pinctl, new_pinctl;
1282 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
1283 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1284 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1287 return hbr ? -EINVAL : 0;
1289 new_pinctl = pinctl & ~AC_PINCTL_EPT;
1291 new_pinctl |= AC_PINCTL_EPT_HBR;
1293 new_pinctl |= AC_PINCTL_EPT_NATIVE;
1296 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
1298 pinctl == new_pinctl ? "" : "new-",
1301 if (pinctl != new_pinctl)
1302 snd_hda_codec_write(codec, pin_nid, 0,
1303 AC_VERB_SET_PIN_WIDGET_CONTROL,
1311 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
1312 hda_nid_t pin_nid, u32 stream_tag, int format)
1314 struct hdmi_spec *spec = codec->spec;
1317 if (is_haswell_plus(codec))
1318 haswell_verify_D0(codec, cvt_nid, pin_nid);
1320 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
1323 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
1327 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
1331 static int hdmi_choose_cvt(struct hda_codec *codec,
1332 int pin_idx, int *cvt_id, int *mux_id)
1334 struct hdmi_spec *spec = codec->spec;
1335 struct hdmi_spec_per_pin *per_pin;
1336 struct hdmi_spec_per_cvt *per_cvt = NULL;
1337 int cvt_idx, mux_idx = 0;
1339 per_pin = get_pin(spec, pin_idx);
1341 /* Dynamically assign converter to stream */
1342 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1343 per_cvt = get_cvt(spec, cvt_idx);
1345 /* Must not already be assigned */
1346 if (per_cvt->assigned)
1348 /* Must be in pin's mux's list of converters */
1349 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1350 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
1352 /* Not in mux list */
1353 if (mux_idx == per_pin->num_mux_nids)
1358 /* No free converters */
1359 if (cvt_idx == spec->num_cvts)
1362 per_pin->mux_idx = mux_idx;
1372 /* Assure the pin select the right convetor */
1373 static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
1374 struct hdmi_spec_per_pin *per_pin)
1376 hda_nid_t pin_nid = per_pin->pin_nid;
1379 mux_idx = per_pin->mux_idx;
1380 curr = snd_hda_codec_read(codec, pin_nid, 0,
1381 AC_VERB_GET_CONNECT_SEL, 0);
1382 if (curr != mux_idx)
1383 snd_hda_codec_write_cache(codec, pin_nid, 0,
1384 AC_VERB_SET_CONNECT_SEL,
1388 /* Intel HDMI workaround to fix audio routing issue:
1389 * For some Intel display codecs, pins share the same connection list.
1390 * So a conveter can be selected by multiple pins and playback on any of these
1391 * pins will generate sound on the external display, because audio flows from
1392 * the same converter to the display pipeline. Also muting one pin may make
1393 * other pins have no sound output.
1394 * So this function assures that an assigned converter for a pin is not selected
1395 * by any other pins.
1397 static void intel_not_share_assigned_cvt(struct hda_codec *codec,
1398 hda_nid_t pin_nid, int mux_idx)
1400 struct hdmi_spec *spec = codec->spec;
1403 struct hdmi_spec_per_cvt *per_cvt;
1405 /* configure all pins, including "no physical connection" ones */
1406 for_each_hda_codec_node(nid, codec) {
1407 unsigned int wid_caps = get_wcaps(codec, nid);
1408 unsigned int wid_type = get_wcaps_type(wid_caps);
1410 if (wid_type != AC_WID_PIN)
1416 curr = snd_hda_codec_read(codec, nid, 0,
1417 AC_VERB_GET_CONNECT_SEL, 0);
1418 if (curr != mux_idx)
1421 /* choose an unassigned converter. The conveters in the
1422 * connection list are in the same order as in the codec.
1424 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1425 per_cvt = get_cvt(spec, cvt_idx);
1426 if (!per_cvt->assigned) {
1428 "choose cvt %d for pin nid %d\n",
1430 snd_hda_codec_write_cache(codec, nid, 0,
1431 AC_VERB_SET_CONNECT_SEL,
1442 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1443 struct hda_codec *codec,
1444 struct snd_pcm_substream *substream)
1446 struct hdmi_spec *spec = codec->spec;
1447 struct snd_pcm_runtime *runtime = substream->runtime;
1448 int pin_idx, cvt_idx, mux_idx = 0;
1449 struct hdmi_spec_per_pin *per_pin;
1450 struct hdmi_eld *eld;
1451 struct hdmi_spec_per_cvt *per_cvt = NULL;
1454 /* Validate hinfo */
1455 pin_idx = hinfo_to_pin_index(codec, hinfo);
1456 if (snd_BUG_ON(pin_idx < 0))
1458 per_pin = get_pin(spec, pin_idx);
1459 eld = &per_pin->sink_eld;
1461 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, &mux_idx);
1465 per_cvt = get_cvt(spec, cvt_idx);
1466 /* Claim converter */
1467 per_cvt->assigned = 1;
1468 per_pin->cvt_nid = per_cvt->cvt_nid;
1469 hinfo->nid = per_cvt->cvt_nid;
1471 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1472 AC_VERB_SET_CONNECT_SEL,
1475 /* configure unused pins to choose other converters */
1476 if (is_haswell_plus(codec) || is_valleyview_plus(codec))
1477 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, mux_idx);
1479 snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid);
1481 /* Initially set the converter's capabilities */
1482 hinfo->channels_min = per_cvt->channels_min;
1483 hinfo->channels_max = per_cvt->channels_max;
1484 hinfo->rates = per_cvt->rates;
1485 hinfo->formats = per_cvt->formats;
1486 hinfo->maxbps = per_cvt->maxbps;
1488 /* Restrict capabilities by ELD if this isn't disabled */
1489 if (!static_hdmi_pcm && eld->eld_valid) {
1490 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
1491 if (hinfo->channels_min > hinfo->channels_max ||
1492 !hinfo->rates || !hinfo->formats) {
1493 per_cvt->assigned = 0;
1495 snd_hda_spdif_ctls_unassign(codec, pin_idx);
1500 /* Store the updated parameters */
1501 runtime->hw.channels_min = hinfo->channels_min;
1502 runtime->hw.channels_max = hinfo->channels_max;
1503 runtime->hw.formats = hinfo->formats;
1504 runtime->hw.rates = hinfo->rates;
1506 snd_pcm_hw_constraint_step(substream->runtime, 0,
1507 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1512 * HDA/HDMI auto parsing
1514 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
1516 struct hdmi_spec *spec = codec->spec;
1517 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1518 hda_nid_t pin_nid = per_pin->pin_nid;
1520 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1522 "HDMI: pin %d wcaps %#x does not support connection list\n",
1523 pin_nid, get_wcaps(codec, pin_nid));
1527 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1529 HDA_MAX_CONNECTIONS);
1534 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1536 struct hda_jack_tbl *jack;
1537 struct hda_codec *codec = per_pin->codec;
1538 struct hdmi_spec *spec = codec->spec;
1539 struct hdmi_eld *eld = &spec->temp_eld;
1540 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1541 hda_nid_t pin_nid = per_pin->pin_nid;
1543 * Always execute a GetPinSense verb here, even when called from
1544 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1545 * response's PD bit is not the real PD value, but indicates that
1546 * the real PD value changed. An older version of the HD-audio
1547 * specification worked this way. Hence, we just ignore the data in
1548 * the unsolicited response to avoid custom WARs.
1551 bool update_eld = false;
1552 bool eld_changed = false;
1555 snd_hda_power_up_pm(codec);
1556 present = snd_hda_pin_sense(codec, pin_nid);
1558 mutex_lock(&per_pin->lock);
1559 pin_eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1560 if (pin_eld->monitor_present)
1561 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1563 eld->eld_valid = false;
1566 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
1567 codec->addr, pin_nid, pin_eld->monitor_present, eld->eld_valid);
1569 if (eld->eld_valid) {
1570 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1571 &eld->eld_size) < 0)
1572 eld->eld_valid = false;
1574 memset(&eld->info, 0, sizeof(struct parsed_hdmi_eld));
1575 if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1577 eld->eld_valid = false;
1580 if (eld->eld_valid) {
1581 snd_hdmi_show_eld(codec, &eld->info);
1585 schedule_delayed_work(&per_pin->work,
1586 msecs_to_jiffies(300));
1591 if (pin_eld->eld_valid != eld->eld_valid)
1594 if (pin_eld->eld_valid && !eld->eld_valid)
1598 bool old_eld_valid = pin_eld->eld_valid;
1599 pin_eld->eld_valid = eld->eld_valid;
1600 if (pin_eld->eld_size != eld->eld_size ||
1601 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1602 eld->eld_size) != 0) {
1603 memcpy(pin_eld->eld_buffer, eld->eld_buffer,
1607 pin_eld->eld_size = eld->eld_size;
1608 pin_eld->info = eld->info;
1611 * Re-setup pin and infoframe. This is needed e.g. when
1612 * - sink is first plugged-in (infoframe is not set up if !monitor_present)
1613 * - transcoder can change during stream playback on Haswell
1614 * and this can make HW reset converter selection on a pin.
1616 if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1617 if (is_haswell_plus(codec) ||
1618 is_valleyview_plus(codec)) {
1619 intel_verify_pin_cvt_connect(codec, per_pin);
1620 intel_not_share_assigned_cvt(codec, pin_nid,
1624 hdmi_setup_audio_infoframe(codec, per_pin,
1630 snd_ctl_notify(codec->card,
1631 SNDRV_CTL_EVENT_MASK_VALUE | SNDRV_CTL_EVENT_MASK_INFO,
1632 &per_pin->eld_ctl->id);
1634 ret = !repoll || !pin_eld->monitor_present || pin_eld->eld_valid;
1636 jack = snd_hda_jack_tbl_get(codec, pin_nid);
1638 jack->block_report = !ret;
1640 mutex_unlock(&per_pin->lock);
1641 snd_hda_power_down_pm(codec);
1645 static void hdmi_repoll_eld(struct work_struct *work)
1647 struct hdmi_spec_per_pin *per_pin =
1648 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1650 if (per_pin->repoll_count++ > 6)
1651 per_pin->repoll_count = 0;
1653 if (hdmi_present_sense(per_pin, per_pin->repoll_count))
1654 snd_hda_jack_report_sync(per_pin->codec);
1657 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1660 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1662 struct hdmi_spec *spec = codec->spec;
1663 unsigned int caps, config;
1665 struct hdmi_spec_per_pin *per_pin;
1668 caps = snd_hda_query_pin_caps(codec, pin_nid);
1669 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1672 config = snd_hda_codec_get_pincfg(codec, pin_nid);
1673 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1676 if (is_haswell_plus(codec))
1677 intel_haswell_fixup_connect_list(codec, pin_nid);
1679 pin_idx = spec->num_pins;
1680 per_pin = snd_array_new(&spec->pins);
1684 per_pin->pin_nid = pin_nid;
1685 per_pin->non_pcm = false;
1687 err = hdmi_read_pin_conn(codec, pin_idx);
1696 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1698 struct hdmi_spec *spec = codec->spec;
1699 struct hdmi_spec_per_cvt *per_cvt;
1703 chans = get_wcaps(codec, cvt_nid);
1704 chans = get_wcaps_channels(chans);
1706 per_cvt = snd_array_new(&spec->cvts);
1710 per_cvt->cvt_nid = cvt_nid;
1711 per_cvt->channels_min = 2;
1713 per_cvt->channels_max = chans;
1714 if (chans > spec->channels_max)
1715 spec->channels_max = chans;
1718 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1725 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1726 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1732 static int hdmi_parse_codec(struct hda_codec *codec)
1737 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid);
1738 if (!nid || nodes < 0) {
1739 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
1743 for (i = 0; i < nodes; i++, nid++) {
1747 caps = get_wcaps(codec, nid);
1748 type = get_wcaps_type(caps);
1750 if (!(caps & AC_WCAP_DIGITAL))
1754 case AC_WID_AUD_OUT:
1755 hdmi_add_cvt(codec, nid);
1758 hdmi_add_pin(codec, nid);
1768 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1770 struct hda_spdif_out *spdif;
1773 mutex_lock(&codec->spdif_mutex);
1774 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1775 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1776 mutex_unlock(&codec->spdif_mutex);
1780 /* There is a fixed mapping between audio pin node and display port
1781 * on current Intel platforms:
1782 * Pin Widget 5 - PORT B (port = 1 in i915 driver)
1783 * Pin Widget 6 - PORT C (port = 2 in i915 driver)
1784 * Pin Widget 7 - PORT D (port = 3 in i915 driver)
1786 static int intel_pin2port(hda_nid_t pin_nid)
1795 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1796 struct hda_codec *codec,
1797 unsigned int stream_tag,
1798 unsigned int format,
1799 struct snd_pcm_substream *substream)
1801 hda_nid_t cvt_nid = hinfo->nid;
1802 struct hdmi_spec *spec = codec->spec;
1803 int pin_idx = hinfo_to_pin_index(codec, hinfo);
1804 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1805 hda_nid_t pin_nid = per_pin->pin_nid;
1806 struct snd_pcm_runtime *runtime = substream->runtime;
1807 struct i915_audio_component *acomp = codec->bus->core.audio_component;
1811 if (is_haswell_plus(codec) || is_valleyview_plus(codec)) {
1812 /* Verify pin:cvt selections to avoid silent audio after S3.
1813 * After S3, the audio driver restores pin:cvt selections
1814 * but this can happen before gfx is ready and such selection
1815 * is overlooked by HW. Thus multiple pins can share a same
1816 * default convertor and mute control will affect each other,
1817 * which can cause a resumed audio playback become silent
1820 intel_verify_pin_cvt_connect(codec, per_pin);
1821 intel_not_share_assigned_cvt(codec, pin_nid, per_pin->mux_idx);
1824 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
1825 /* Todo: add DP1.2 MST audio support later */
1826 if (acomp && acomp->ops && acomp->ops->sync_audio_rate)
1827 acomp->ops->sync_audio_rate(acomp->dev,
1828 intel_pin2port(pin_nid),
1831 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
1832 mutex_lock(&per_pin->lock);
1833 per_pin->channels = substream->runtime->channels;
1834 per_pin->setup = true;
1836 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1837 mutex_unlock(&per_pin->lock);
1839 if (spec->dyn_pin_out) {
1840 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1841 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1842 snd_hda_codec_write(codec, pin_nid, 0,
1843 AC_VERB_SET_PIN_WIDGET_CONTROL,
1847 return spec->ops.setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
1850 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1851 struct hda_codec *codec,
1852 struct snd_pcm_substream *substream)
1854 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1858 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1859 struct hda_codec *codec,
1860 struct snd_pcm_substream *substream)
1862 struct hdmi_spec *spec = codec->spec;
1863 int cvt_idx, pin_idx;
1864 struct hdmi_spec_per_cvt *per_cvt;
1865 struct hdmi_spec_per_pin *per_pin;
1869 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
1870 if (snd_BUG_ON(cvt_idx < 0))
1872 per_cvt = get_cvt(spec, cvt_idx);
1874 snd_BUG_ON(!per_cvt->assigned);
1875 per_cvt->assigned = 0;
1878 pin_idx = hinfo_to_pin_index(codec, hinfo);
1879 if (snd_BUG_ON(pin_idx < 0))
1881 per_pin = get_pin(spec, pin_idx);
1883 if (spec->dyn_pin_out) {
1884 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1885 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1886 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1887 AC_VERB_SET_PIN_WIDGET_CONTROL,
1891 snd_hda_spdif_ctls_unassign(codec, pin_idx);
1893 mutex_lock(&per_pin->lock);
1894 per_pin->chmap_set = false;
1895 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1897 per_pin->setup = false;
1898 per_pin->channels = 0;
1899 mutex_unlock(&per_pin->lock);
1905 static const struct hda_pcm_ops generic_ops = {
1906 .open = hdmi_pcm_open,
1907 .close = hdmi_pcm_close,
1908 .prepare = generic_hdmi_playback_pcm_prepare,
1909 .cleanup = generic_hdmi_playback_pcm_cleanup,
1913 * ALSA API channel-map control callbacks
1915 static int hdmi_chmap_ctl_info(struct snd_kcontrol *kcontrol,
1916 struct snd_ctl_elem_info *uinfo)
1918 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1919 struct hda_codec *codec = info->private_data;
1920 struct hdmi_spec *spec = codec->spec;
1921 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1922 uinfo->count = spec->channels_max;
1923 uinfo->value.integer.min = 0;
1924 uinfo->value.integer.max = SNDRV_CHMAP_LAST;
1928 static int hdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
1931 /* If the speaker allocation matches the channel count, it is OK.*/
1932 if (cap->channels != channels)
1935 /* all channels are remappable freely */
1936 return SNDRV_CTL_TLVT_CHMAP_VAR;
1939 static void hdmi_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
1940 unsigned int *chmap, int channels)
1945 for (c = 7; c >= 0; c--) {
1946 int spk = cap->speakers[c];
1950 chmap[count++] = spk_to_chmap(spk);
1953 WARN_ON(count != channels);
1956 static int hdmi_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag,
1957 unsigned int size, unsigned int __user *tlv)
1959 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1960 struct hda_codec *codec = info->private_data;
1961 struct hdmi_spec *spec = codec->spec;
1962 unsigned int __user *dst;
1967 if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv))
1971 for (chs = 2; chs <= spec->channels_max; chs++) {
1973 struct cea_channel_speaker_allocation *cap;
1974 cap = channel_allocations;
1975 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++, cap++) {
1976 int chs_bytes = chs * 4;
1977 int type = spec->ops.chmap_cea_alloc_validate_get_type(cap, chs);
1978 unsigned int tlv_chmap[8];
1984 if (put_user(type, dst) ||
1985 put_user(chs_bytes, dst + 1))
1990 if (size < chs_bytes)
1994 spec->ops.cea_alloc_to_tlv_chmap(cap, tlv_chmap, chs);
1995 if (copy_to_user(dst, tlv_chmap, chs_bytes))
2000 if (put_user(count, tlv + 1))
2005 static int hdmi_chmap_ctl_get(struct snd_kcontrol *kcontrol,
2006 struct snd_ctl_elem_value *ucontrol)
2008 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
2009 struct hda_codec *codec = info->private_data;
2010 struct hdmi_spec *spec = codec->spec;
2011 int pin_idx = kcontrol->private_value;
2012 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2015 for (i = 0; i < ARRAY_SIZE(per_pin->chmap); i++)
2016 ucontrol->value.integer.value[i] = per_pin->chmap[i];
2020 static int hdmi_chmap_ctl_put(struct snd_kcontrol *kcontrol,
2021 struct snd_ctl_elem_value *ucontrol)
2023 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
2024 struct hda_codec *codec = info->private_data;
2025 struct hdmi_spec *spec = codec->spec;
2026 int pin_idx = kcontrol->private_value;
2027 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2028 unsigned int ctl_idx;
2029 struct snd_pcm_substream *substream;
2030 unsigned char chmap[8];
2031 int i, err, ca, prepared = 0;
2033 ctl_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
2034 substream = snd_pcm_chmap_substream(info, ctl_idx);
2035 if (!substream || !substream->runtime)
2036 return 0; /* just for avoiding error from alsactl restore */
2037 switch (substream->runtime->status->state) {
2038 case SNDRV_PCM_STATE_OPEN:
2039 case SNDRV_PCM_STATE_SETUP:
2041 case SNDRV_PCM_STATE_PREPARED:
2047 memset(chmap, 0, sizeof(chmap));
2048 for (i = 0; i < ARRAY_SIZE(chmap); i++)
2049 chmap[i] = ucontrol->value.integer.value[i];
2050 if (!memcmp(chmap, per_pin->chmap, sizeof(chmap)))
2052 ca = hdmi_manual_channel_allocation(ARRAY_SIZE(chmap), chmap);
2055 if (spec->ops.chmap_validate) {
2056 err = spec->ops.chmap_validate(ca, ARRAY_SIZE(chmap), chmap);
2060 mutex_lock(&per_pin->lock);
2061 per_pin->chmap_set = true;
2062 memcpy(per_pin->chmap, chmap, sizeof(chmap));
2064 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
2065 mutex_unlock(&per_pin->lock);
2070 static int generic_hdmi_build_pcms(struct hda_codec *codec)
2072 struct hdmi_spec *spec = codec->spec;
2075 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2076 struct hda_pcm *info;
2077 struct hda_pcm_stream *pstr;
2079 info = snd_hda_codec_pcm_new(codec, "HDMI %d", pin_idx);
2082 spec->pcm_rec[pin_idx] = info;
2083 info->pcm_type = HDA_PCM_TYPE_HDMI;
2084 info->own_chmap = true;
2086 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2087 pstr->substreams = 1;
2088 pstr->ops = generic_ops;
2089 /* other pstr fields are set in open */
2095 static int generic_hdmi_build_jack(struct hda_codec *codec, int pin_idx)
2097 char hdmi_str[32] = "HDMI/DP";
2098 struct hdmi_spec *spec = codec->spec;
2099 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2100 int pcmdev = get_pcm_rec(spec, pin_idx)->device;
2104 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
2105 phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid);
2107 strncat(hdmi_str, " Phantom",
2108 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
2110 return snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str,
2114 static int generic_hdmi_build_controls(struct hda_codec *codec)
2116 struct hdmi_spec *spec = codec->spec;
2120 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2121 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2123 err = generic_hdmi_build_jack(codec, pin_idx);
2127 err = snd_hda_create_dig_out_ctls(codec,
2129 per_pin->mux_nids[0],
2133 snd_hda_spdif_ctls_unassign(codec, pin_idx);
2135 /* add control for ELD Bytes */
2136 err = hdmi_create_eld_ctl(codec, pin_idx,
2137 get_pcm_rec(spec, pin_idx)->device);
2142 hdmi_present_sense(per_pin, 0);
2145 /* add channel maps */
2146 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2147 struct hda_pcm *pcm;
2148 struct snd_pcm_chmap *chmap;
2149 struct snd_kcontrol *kctl;
2152 pcm = spec->pcm_rec[pin_idx];
2153 if (!pcm || !pcm->pcm)
2155 err = snd_pcm_add_chmap_ctls(pcm->pcm,
2156 SNDRV_PCM_STREAM_PLAYBACK,
2157 NULL, 0, pin_idx, &chmap);
2160 /* override handlers */
2161 chmap->private_data = codec;
2163 for (i = 0; i < kctl->count; i++)
2164 kctl->vd[i].access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
2165 kctl->info = hdmi_chmap_ctl_info;
2166 kctl->get = hdmi_chmap_ctl_get;
2167 kctl->put = hdmi_chmap_ctl_put;
2168 kctl->tlv.c = hdmi_chmap_ctl_tlv;
2174 static int generic_hdmi_init_per_pins(struct hda_codec *codec)
2176 struct hdmi_spec *spec = codec->spec;
2179 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2180 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2182 per_pin->codec = codec;
2183 mutex_init(&per_pin->lock);
2184 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
2185 eld_proc_new(per_pin, pin_idx);
2190 static int generic_hdmi_init(struct hda_codec *codec)
2192 struct hdmi_spec *spec = codec->spec;
2195 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2196 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2197 hda_nid_t pin_nid = per_pin->pin_nid;
2199 hdmi_init_pin(codec, pin_nid);
2200 snd_hda_jack_detect_enable_callback(codec, pin_nid,
2201 codec->jackpoll_interval > 0 ? jack_callback : NULL);
2206 static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2208 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2209 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2212 static void hdmi_array_free(struct hdmi_spec *spec)
2214 snd_array_free(&spec->pins);
2215 snd_array_free(&spec->cvts);
2218 static void generic_hdmi_free(struct hda_codec *codec)
2220 struct hdmi_spec *spec = codec->spec;
2223 if (is_haswell_plus(codec) || is_valleyview_plus(codec))
2224 snd_hdac_i915_register_notifier(NULL);
2226 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2227 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2229 cancel_delayed_work_sync(&per_pin->work);
2230 eld_proc_free(per_pin);
2233 hdmi_array_free(spec);
2238 static int generic_hdmi_resume(struct hda_codec *codec)
2240 struct hdmi_spec *spec = codec->spec;
2243 codec->patch_ops.init(codec);
2244 regcache_sync(codec->core.regmap);
2246 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2247 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2248 hdmi_present_sense(per_pin, 1);
2254 static const struct hda_codec_ops generic_hdmi_patch_ops = {
2255 .init = generic_hdmi_init,
2256 .free = generic_hdmi_free,
2257 .build_pcms = generic_hdmi_build_pcms,
2258 .build_controls = generic_hdmi_build_controls,
2259 .unsol_event = hdmi_unsol_event,
2261 .resume = generic_hdmi_resume,
2265 static const struct hdmi_ops generic_standard_hdmi_ops = {
2266 .pin_get_eld = snd_hdmi_get_eld,
2267 .pin_get_slot_channel = hdmi_pin_get_slot_channel,
2268 .pin_set_slot_channel = hdmi_pin_set_slot_channel,
2269 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2270 .pin_hbr_setup = hdmi_pin_hbr_setup,
2271 .setup_stream = hdmi_setup_stream,
2272 .chmap_cea_alloc_validate_get_type = hdmi_chmap_cea_alloc_validate_get_type,
2273 .cea_alloc_to_tlv_chmap = hdmi_cea_alloc_to_tlv_chmap,
2277 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2280 struct hdmi_spec *spec = codec->spec;
2284 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2285 if (nconns == spec->num_cvts &&
2286 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
2289 /* override pins connection list */
2290 codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid);
2291 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
2294 #define INTEL_VENDOR_NID 0x08
2295 #define INTEL_GET_VENDOR_VERB 0xf81
2296 #define INTEL_SET_VENDOR_VERB 0x781
2297 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2298 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2300 static void intel_haswell_enable_all_pins(struct hda_codec *codec,
2303 unsigned int vendor_param;
2305 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2306 INTEL_GET_VENDOR_VERB, 0);
2307 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2310 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2311 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2312 INTEL_SET_VENDOR_VERB, vendor_param);
2313 if (vendor_param == -1)
2317 snd_hda_codec_update_widgets(codec);
2320 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2322 unsigned int vendor_param;
2324 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2325 INTEL_GET_VENDOR_VERB, 0);
2326 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2329 /* enable DP1.2 mode */
2330 vendor_param |= INTEL_EN_DP12;
2331 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
2332 snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0,
2333 INTEL_SET_VENDOR_VERB, vendor_param);
2336 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2337 * Otherwise you may get severe h/w communication errors.
2339 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2340 unsigned int power_state)
2342 if (power_state == AC_PWRST_D0) {
2343 intel_haswell_enable_all_pins(codec, false);
2344 intel_haswell_fixup_enable_dp12(codec);
2347 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2348 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2351 static void intel_pin_eld_notify(void *audio_ptr, int port)
2353 struct hda_codec *codec = audio_ptr;
2354 int pin_nid = port + 0x04;
2356 /* skip notification during system suspend (but not in runtime PM);
2357 * the state will be updated at resume
2359 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0)
2362 check_presence_and_report(codec, pin_nid);
2365 static int patch_generic_hdmi(struct hda_codec *codec)
2367 struct hdmi_spec *spec;
2369 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2373 spec->ops = generic_standard_hdmi_ops;
2375 hdmi_array_init(spec, 4);
2377 if (is_haswell_plus(codec)) {
2378 intel_haswell_enable_all_pins(codec, true);
2379 intel_haswell_fixup_enable_dp12(codec);
2382 /* For Valleyview/Cherryview, only the display codec is in the display
2383 * power well and can use link_power ops to request/release the power.
2384 * For Haswell/Broadwell, the controller is also in the power well and
2385 * can cover the codec power request, and so need not set this flag.
2386 * For previous platforms, there is no such power well feature.
2388 if (is_valleyview_plus(codec) || is_skylake(codec) ||
2390 codec->core.link_power_control = 1;
2392 if (is_haswell_plus(codec) || is_valleyview_plus(codec)) {
2393 codec->depop_delay = 0;
2394 spec->i915_audio_ops.audio_ptr = codec;
2395 spec->i915_audio_ops.pin_eld_notify = intel_pin_eld_notify;
2396 snd_hdac_i915_register_notifier(&spec->i915_audio_ops);
2399 if (hdmi_parse_codec(codec) < 0) {
2404 codec->patch_ops = generic_hdmi_patch_ops;
2405 if (is_haswell_plus(codec)) {
2406 codec->patch_ops.set_power_state = haswell_set_power_state;
2407 codec->dp_mst = true;
2410 /* Enable runtime pm for HDMI audio codec of HSW/BDW/SKL/BYT/BSW */
2411 if (is_haswell_plus(codec) || is_valleyview_plus(codec))
2412 codec->auto_runtime_pm = 1;
2414 generic_hdmi_init_per_pins(codec);
2416 init_channel_allocations();
2422 * Shared non-generic implementations
2425 static int simple_playback_build_pcms(struct hda_codec *codec)
2427 struct hdmi_spec *spec = codec->spec;
2428 struct hda_pcm *info;
2430 struct hda_pcm_stream *pstr;
2431 struct hdmi_spec_per_cvt *per_cvt;
2433 per_cvt = get_cvt(spec, 0);
2434 chans = get_wcaps(codec, per_cvt->cvt_nid);
2435 chans = get_wcaps_channels(chans);
2437 info = snd_hda_codec_pcm_new(codec, "HDMI 0");
2440 spec->pcm_rec[0] = info;
2441 info->pcm_type = HDA_PCM_TYPE_HDMI;
2442 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2443 *pstr = spec->pcm_playback;
2444 pstr->nid = per_cvt->cvt_nid;
2445 if (pstr->channels_max <= 2 && chans && chans <= 16)
2446 pstr->channels_max = chans;
2451 /* unsolicited event for jack sensing */
2452 static void simple_hdmi_unsol_event(struct hda_codec *codec,
2455 snd_hda_jack_set_dirty_all(codec);
2456 snd_hda_jack_report_sync(codec);
2459 /* generic_hdmi_build_jack can be used for simple_hdmi, too,
2460 * as long as spec->pins[] is set correctly
2462 #define simple_hdmi_build_jack generic_hdmi_build_jack
2464 static int simple_playback_build_controls(struct hda_codec *codec)
2466 struct hdmi_spec *spec = codec->spec;
2467 struct hdmi_spec_per_cvt *per_cvt;
2470 per_cvt = get_cvt(spec, 0);
2471 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
2476 return simple_hdmi_build_jack(codec, 0);
2479 static int simple_playback_init(struct hda_codec *codec)
2481 struct hdmi_spec *spec = codec->spec;
2482 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2483 hda_nid_t pin = per_pin->pin_nid;
2485 snd_hda_codec_write(codec, pin, 0,
2486 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2487 /* some codecs require to unmute the pin */
2488 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2489 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2491 snd_hda_jack_detect_enable(codec, pin);
2495 static void simple_playback_free(struct hda_codec *codec)
2497 struct hdmi_spec *spec = codec->spec;
2499 hdmi_array_free(spec);
2504 * Nvidia specific implementations
2507 #define Nv_VERB_SET_Channel_Allocation 0xF79
2508 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
2509 #define Nv_VERB_SET_Audio_Protection_On 0xF98
2510 #define Nv_VERB_SET_Audio_Protection_Off 0xF99
2512 #define nvhdmi_master_con_nid_7x 0x04
2513 #define nvhdmi_master_pin_nid_7x 0x05
2515 static const hda_nid_t nvhdmi_con_nids_7x[4] = {
2516 /*front, rear, clfe, rear_surr */
2520 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2521 /* set audio protect on */
2522 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2523 /* enable digital output on pin widget */
2524 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2528 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
2529 /* set audio protect on */
2530 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2531 /* enable digital output on pin widget */
2532 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2533 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2534 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2535 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2536 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2540 #ifdef LIMITED_RATE_FMT_SUPPORT
2541 /* support only the safe format and rate */
2542 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000
2543 #define SUPPORTED_MAXBPS 16
2544 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
2546 /* support all rates and formats */
2547 #define SUPPORTED_RATES \
2548 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2549 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2550 SNDRV_PCM_RATE_192000)
2551 #define SUPPORTED_MAXBPS 24
2552 #define SUPPORTED_FORMATS \
2553 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2556 static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2558 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2562 static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
2564 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
2568 static unsigned int channels_2_6_8[] = {
2572 static unsigned int channels_2_8[] = {
2576 static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2577 .count = ARRAY_SIZE(channels_2_6_8),
2578 .list = channels_2_6_8,
2582 static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2583 .count = ARRAY_SIZE(channels_2_8),
2584 .list = channels_2_8,
2588 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2589 struct hda_codec *codec,
2590 struct snd_pcm_substream *substream)
2592 struct hdmi_spec *spec = codec->spec;
2593 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2595 switch (codec->preset->vendor_id) {
2600 hw_constraints_channels = &hw_constraints_2_8_channels;
2603 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2609 if (hw_constraints_channels != NULL) {
2610 snd_pcm_hw_constraint_list(substream->runtime, 0,
2611 SNDRV_PCM_HW_PARAM_CHANNELS,
2612 hw_constraints_channels);
2614 snd_pcm_hw_constraint_step(substream->runtime, 0,
2615 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
2618 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2621 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2622 struct hda_codec *codec,
2623 struct snd_pcm_substream *substream)
2625 struct hdmi_spec *spec = codec->spec;
2626 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2629 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2630 struct hda_codec *codec,
2631 unsigned int stream_tag,
2632 unsigned int format,
2633 struct snd_pcm_substream *substream)
2635 struct hdmi_spec *spec = codec->spec;
2636 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2637 stream_tag, format, substream);
2640 static const struct hda_pcm_stream simple_pcm_playback = {
2645 .open = simple_playback_pcm_open,
2646 .close = simple_playback_pcm_close,
2647 .prepare = simple_playback_pcm_prepare
2651 static const struct hda_codec_ops simple_hdmi_patch_ops = {
2652 .build_controls = simple_playback_build_controls,
2653 .build_pcms = simple_playback_build_pcms,
2654 .init = simple_playback_init,
2655 .free = simple_playback_free,
2656 .unsol_event = simple_hdmi_unsol_event,
2659 static int patch_simple_hdmi(struct hda_codec *codec,
2660 hda_nid_t cvt_nid, hda_nid_t pin_nid)
2662 struct hdmi_spec *spec;
2663 struct hdmi_spec_per_cvt *per_cvt;
2664 struct hdmi_spec_per_pin *per_pin;
2666 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2671 hdmi_array_init(spec, 1);
2673 spec->multiout.num_dacs = 0; /* no analog */
2674 spec->multiout.max_channels = 2;
2675 spec->multiout.dig_out_nid = cvt_nid;
2678 per_pin = snd_array_new(&spec->pins);
2679 per_cvt = snd_array_new(&spec->cvts);
2680 if (!per_pin || !per_cvt) {
2681 simple_playback_free(codec);
2684 per_cvt->cvt_nid = cvt_nid;
2685 per_pin->pin_nid = pin_nid;
2686 spec->pcm_playback = simple_pcm_playback;
2688 codec->patch_ops = simple_hdmi_patch_ops;
2693 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2696 unsigned int chanmask;
2697 int chan = channels ? (channels - 1) : 1;
2716 /* Set the audio infoframe channel allocation and checksum fields. The
2717 * channel count is computed implicitly by the hardware. */
2718 snd_hda_codec_write(codec, 0x1, 0,
2719 Nv_VERB_SET_Channel_Allocation, chanmask);
2721 snd_hda_codec_write(codec, 0x1, 0,
2722 Nv_VERB_SET_Info_Frame_Checksum,
2723 (0x71 - chan - chanmask));
2726 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2727 struct hda_codec *codec,
2728 struct snd_pcm_substream *substream)
2730 struct hdmi_spec *spec = codec->spec;
2733 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2734 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2735 for (i = 0; i < 4; i++) {
2736 /* set the stream id */
2737 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2738 AC_VERB_SET_CHANNEL_STREAMID, 0);
2739 /* set the stream format */
2740 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2741 AC_VERB_SET_STREAM_FORMAT, 0);
2744 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
2745 * streams are disabled. */
2746 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2748 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2751 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
2752 struct hda_codec *codec,
2753 unsigned int stream_tag,
2754 unsigned int format,
2755 struct snd_pcm_substream *substream)
2758 unsigned int dataDCC2, channel_id;
2760 struct hdmi_spec *spec = codec->spec;
2761 struct hda_spdif_out *spdif;
2762 struct hdmi_spec_per_cvt *per_cvt;
2764 mutex_lock(&codec->spdif_mutex);
2765 per_cvt = get_cvt(spec, 0);
2766 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
2768 chs = substream->runtime->channels;
2772 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
2773 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
2774 snd_hda_codec_write(codec,
2775 nvhdmi_master_con_nid_7x,
2777 AC_VERB_SET_DIGI_CONVERT_1,
2778 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
2780 /* set the stream id */
2781 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2782 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
2784 /* set the stream format */
2785 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2786 AC_VERB_SET_STREAM_FORMAT, format);
2788 /* turn on again (if needed) */
2789 /* enable and set the channel status audio/data flag */
2790 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
2791 snd_hda_codec_write(codec,
2792 nvhdmi_master_con_nid_7x,
2794 AC_VERB_SET_DIGI_CONVERT_1,
2795 spdif->ctls & 0xff);
2796 snd_hda_codec_write(codec,
2797 nvhdmi_master_con_nid_7x,
2799 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2802 for (i = 0; i < 4; i++) {
2808 /* turn off SPDIF once;
2809 *otherwise the IEC958 bits won't be updated
2811 if (codec->spdif_status_reset &&
2812 (spdif->ctls & AC_DIG1_ENABLE))
2813 snd_hda_codec_write(codec,
2814 nvhdmi_con_nids_7x[i],
2816 AC_VERB_SET_DIGI_CONVERT_1,
2817 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
2818 /* set the stream id */
2819 snd_hda_codec_write(codec,
2820 nvhdmi_con_nids_7x[i],
2822 AC_VERB_SET_CHANNEL_STREAMID,
2823 (stream_tag << 4) | channel_id);
2824 /* set the stream format */
2825 snd_hda_codec_write(codec,
2826 nvhdmi_con_nids_7x[i],
2828 AC_VERB_SET_STREAM_FORMAT,
2830 /* turn on again (if needed) */
2831 /* enable and set the channel status audio/data flag */
2832 if (codec->spdif_status_reset &&
2833 (spdif->ctls & AC_DIG1_ENABLE)) {
2834 snd_hda_codec_write(codec,
2835 nvhdmi_con_nids_7x[i],
2837 AC_VERB_SET_DIGI_CONVERT_1,
2838 spdif->ctls & 0xff);
2839 snd_hda_codec_write(codec,
2840 nvhdmi_con_nids_7x[i],
2842 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2846 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
2848 mutex_unlock(&codec->spdif_mutex);
2852 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
2856 .nid = nvhdmi_master_con_nid_7x,
2857 .rates = SUPPORTED_RATES,
2858 .maxbps = SUPPORTED_MAXBPS,
2859 .formats = SUPPORTED_FORMATS,
2861 .open = simple_playback_pcm_open,
2862 .close = nvhdmi_8ch_7x_pcm_close,
2863 .prepare = nvhdmi_8ch_7x_pcm_prepare
2867 static int patch_nvhdmi_2ch(struct hda_codec *codec)
2869 struct hdmi_spec *spec;
2870 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
2871 nvhdmi_master_pin_nid_7x);
2875 codec->patch_ops.init = nvhdmi_7x_init_2ch;
2876 /* override the PCM rates, etc, as the codec doesn't give full list */
2878 spec->pcm_playback.rates = SUPPORTED_RATES;
2879 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
2880 spec->pcm_playback.formats = SUPPORTED_FORMATS;
2884 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
2886 struct hdmi_spec *spec = codec->spec;
2887 int err = simple_playback_build_pcms(codec);
2889 struct hda_pcm *info = get_pcm_rec(spec, 0);
2890 info->own_chmap = true;
2895 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
2897 struct hdmi_spec *spec = codec->spec;
2898 struct hda_pcm *info;
2899 struct snd_pcm_chmap *chmap;
2902 err = simple_playback_build_controls(codec);
2906 /* add channel maps */
2907 info = get_pcm_rec(spec, 0);
2908 err = snd_pcm_add_chmap_ctls(info->pcm,
2909 SNDRV_PCM_STREAM_PLAYBACK,
2910 snd_pcm_alt_chmaps, 8, 0, &chmap);
2913 switch (codec->preset->vendor_id) {
2918 chmap->channel_mask = (1U << 2) | (1U << 8);
2921 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
2926 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
2928 struct hdmi_spec *spec;
2929 int err = patch_nvhdmi_2ch(codec);
2933 spec->multiout.max_channels = 8;
2934 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
2935 codec->patch_ops.init = nvhdmi_7x_init_8ch;
2936 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
2937 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
2939 /* Initialize the audio infoframe channel mask and checksum to something
2941 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2947 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
2951 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
2954 if (cap->ca_index == 0x00 && channels == 2)
2955 return SNDRV_CTL_TLVT_CHMAP_FIXED;
2957 return hdmi_chmap_cea_alloc_validate_get_type(cap, channels);
2960 static int nvhdmi_chmap_validate(int ca, int chs, unsigned char *map)
2962 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
2968 static int patch_nvhdmi(struct hda_codec *codec)
2970 struct hdmi_spec *spec;
2973 err = patch_generic_hdmi(codec);
2978 spec->dyn_pin_out = true;
2980 spec->ops.chmap_cea_alloc_validate_get_type =
2981 nvhdmi_chmap_cea_alloc_validate_get_type;
2982 spec->ops.chmap_validate = nvhdmi_chmap_validate;
2988 * The HDA codec on NVIDIA Tegra contains two scratch registers that are
2989 * accessed using vendor-defined verbs. These registers can be used for
2990 * interoperability between the HDA and HDMI drivers.
2993 /* Audio Function Group node */
2994 #define NVIDIA_AFG_NID 0x01
2997 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
2998 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
2999 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
3000 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
3001 * additional bit (at position 30) to signal the validity of the format.
3003 * | 31 | 30 | 29 16 | 15 0 |
3004 * +---------+-------+--------+--------+
3005 * | TRIGGER | VALID | UNUSED | FORMAT |
3006 * +-----------------------------------|
3008 * Note that for the trigger bit to take effect it needs to change value
3009 * (i.e. it needs to be toggled).
3011 #define NVIDIA_GET_SCRATCH0 0xfa6
3012 #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7
3013 #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8
3014 #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9
3015 #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa
3016 #define NVIDIA_SCRATCH_TRIGGER (1 << 7)
3017 #define NVIDIA_SCRATCH_VALID (1 << 6)
3019 #define NVIDIA_GET_SCRATCH1 0xfab
3020 #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac
3021 #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad
3022 #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae
3023 #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf
3026 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
3027 * the format is invalidated so that the HDMI codec can be disabled.
3029 static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format)
3033 /* bits [31:30] contain the trigger and valid bits */
3034 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0,
3035 NVIDIA_GET_SCRATCH0, 0);
3036 value = (value >> 24) & 0xff;
3038 /* bits [15:0] are used to store the HDA format */
3039 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3040 NVIDIA_SET_SCRATCH0_BYTE0,
3041 (format >> 0) & 0xff);
3042 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3043 NVIDIA_SET_SCRATCH0_BYTE1,
3044 (format >> 8) & 0xff);
3046 /* bits [16:24] are unused */
3047 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3048 NVIDIA_SET_SCRATCH0_BYTE2, 0);
3051 * Bit 30 signals that the data is valid and hence that HDMI audio can
3055 value &= ~NVIDIA_SCRATCH_VALID;
3057 value |= NVIDIA_SCRATCH_VALID;
3060 * Whenever the trigger bit is toggled, an interrupt is raised in the
3061 * HDMI codec. The HDMI driver will use that as trigger to update its
3064 value ^= NVIDIA_SCRATCH_TRIGGER;
3066 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3067 NVIDIA_SET_SCRATCH0_BYTE3, value);
3070 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
3071 struct hda_codec *codec,
3072 unsigned int stream_tag,
3073 unsigned int format,
3074 struct snd_pcm_substream *substream)
3078 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
3083 /* notify the HDMI codec of the format change */
3084 tegra_hdmi_set_format(codec, format);
3089 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
3090 struct hda_codec *codec,
3091 struct snd_pcm_substream *substream)
3093 /* invalidate the format in the HDMI codec */
3094 tegra_hdmi_set_format(codec, 0);
3096 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
3099 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
3101 struct hdmi_spec *spec = codec->spec;
3104 for (i = 0; i < spec->num_pins; i++) {
3105 struct hda_pcm *pcm = get_pcm_rec(spec, i);
3107 if (pcm->pcm_type == type)
3114 static int tegra_hdmi_build_pcms(struct hda_codec *codec)
3116 struct hda_pcm_stream *stream;
3117 struct hda_pcm *pcm;
3120 err = generic_hdmi_build_pcms(codec);
3124 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
3129 * Override ->prepare() and ->cleanup() operations to notify the HDMI
3130 * codec about format changes.
3132 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
3133 stream->ops.prepare = tegra_hdmi_pcm_prepare;
3134 stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
3139 static int patch_tegra_hdmi(struct hda_codec *codec)
3143 err = patch_generic_hdmi(codec);
3147 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
3153 * ATI/AMD-specific implementations
3156 #define is_amdhdmi_rev3_or_later(codec) \
3157 ((codec)->core.vendor_id == 0x1002aa01 && \
3158 ((codec)->core.revision_id & 0xff00) >= 0x0300)
3159 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
3161 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
3162 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
3163 #define ATI_VERB_SET_DOWNMIX_INFO 0x772
3164 #define ATI_VERB_SET_MULTICHANNEL_01 0x777
3165 #define ATI_VERB_SET_MULTICHANNEL_23 0x778
3166 #define ATI_VERB_SET_MULTICHANNEL_45 0x779
3167 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a
3168 #define ATI_VERB_SET_HBR_CONTROL 0x77c
3169 #define ATI_VERB_SET_MULTICHANNEL_1 0x785
3170 #define ATI_VERB_SET_MULTICHANNEL_3 0x786
3171 #define ATI_VERB_SET_MULTICHANNEL_5 0x787
3172 #define ATI_VERB_SET_MULTICHANNEL_7 0x788
3173 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
3174 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
3175 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72
3176 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77
3177 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78
3178 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79
3179 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
3180 #define ATI_VERB_GET_HBR_CONTROL 0xf7c
3181 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85
3182 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86
3183 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87
3184 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88
3185 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
3187 /* AMD specific HDA cvt verbs */
3188 #define ATI_VERB_SET_RAMP_RATE 0x770
3189 #define ATI_VERB_GET_RAMP_RATE 0xf70
3191 #define ATI_OUT_ENABLE 0x1
3193 #define ATI_MULTICHANNEL_MODE_PAIRED 0
3194 #define ATI_MULTICHANNEL_MODE_SINGLE 1
3196 #define ATI_HBR_CAPABLE 0x01
3197 #define ATI_HBR_ENABLE 0x10
3199 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
3200 unsigned char *buf, int *eld_size)
3202 /* call hda_eld.c ATI/AMD-specific function */
3203 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
3204 is_amdhdmi_rev3_or_later(codec));
3207 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
3208 int active_channels, int conn_type)
3210 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
3213 static int atihdmi_paired_swap_fc_lfe(int pos)
3216 * ATI/AMD have automatic FC/LFE swap built-in
3217 * when in pairwise mapping mode.
3221 /* see channel_allocations[].speakers[] */
3230 static int atihdmi_paired_chmap_validate(int ca, int chs, unsigned char *map)
3232 struct cea_channel_speaker_allocation *cap;
3235 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3237 cap = &channel_allocations[get_channel_allocation_order(ca)];
3238 for (i = 0; i < chs; ++i) {
3239 int mask = to_spk_mask(map[i]);
3241 bool companion_ok = false;
3246 for (j = 0 + i % 2; j < 8; j += 2) {
3247 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3248 if (cap->speakers[chan_idx] == mask) {
3249 /* channel is in a supported position */
3252 if (i % 2 == 0 && i + 1 < chs) {
3253 /* even channel, check the odd companion */
3254 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
3255 int comp_mask_req = to_spk_mask(map[i+1]);
3256 int comp_mask_act = cap->speakers[comp_chan_idx];
3258 if (comp_mask_req == comp_mask_act)
3259 companion_ok = true;
3271 i++; /* companion channel already checked */
3277 static int atihdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
3278 int hdmi_slot, int stream_channel)
3281 int ati_channel_setup = 0;
3286 if (!has_amd_full_remap_support(codec)) {
3287 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3289 /* In case this is an odd slot but without stream channel, do not
3290 * disable the slot since the corresponding even slot could have a
3291 * channel. In case neither have a channel, the slot pair will be
3292 * disabled when this function is called for the even slot. */
3293 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3296 hdmi_slot -= hdmi_slot % 2;
3298 if (stream_channel != 0xf)
3299 stream_channel -= stream_channel % 2;
3302 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3304 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3306 if (stream_channel != 0xf)
3307 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3309 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3312 static int atihdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
3315 bool was_odd = false;
3316 int ati_asp_slot = asp_slot;
3318 int ati_channel_setup;
3323 if (!has_amd_full_remap_support(codec)) {
3324 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3325 if (ati_asp_slot % 2 != 0) {
3331 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3333 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3335 if (!(ati_channel_setup & ATI_OUT_ENABLE))
3338 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3341 static int atihdmi_paired_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
3347 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3348 * we need to take that into account (a single channel may take 2
3349 * channel slots if we need to carry a silent channel next to it).
3350 * On Rev3+ AMD codecs this function is not used.
3354 /* We only produce even-numbered channel count TLVs */
3355 if ((channels % 2) != 0)
3358 for (c = 0; c < 7; c += 2) {
3359 if (cap->speakers[c] || cap->speakers[c+1])
3363 if (chanpairs * 2 != channels)
3366 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3369 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
3370 unsigned int *chmap, int channels)
3372 /* produce paired maps for pre-rev3 ATI/AMD codecs */
3376 for (c = 7; c >= 0; c--) {
3377 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3378 int spk = cap->speakers[chan];
3380 /* add N/A channel if the companion channel is occupied */
3381 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3382 chmap[count++] = SNDRV_CHMAP_NA;
3387 chmap[count++] = spk_to_chmap(spk);
3390 WARN_ON(count != channels);
3393 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3396 int hbr_ctl, hbr_ctl_new;
3398 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
3399 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
3401 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3403 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3406 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
3408 hbr_ctl == hbr_ctl_new ? "" : "new-",
3411 if (hbr_ctl != hbr_ctl_new)
3412 snd_hda_codec_write(codec, pin_nid, 0,
3413 ATI_VERB_SET_HBR_CONTROL,
3422 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3423 hda_nid_t pin_nid, u32 stream_tag, int format)
3426 if (is_amdhdmi_rev3_or_later(codec)) {
3427 int ramp_rate = 180; /* default as per AMD spec */
3428 /* disable ramp-up/down for non-pcm as per AMD spec */
3429 if (format & AC_FMT_TYPE_NON_PCM)
3432 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3435 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3439 static int atihdmi_init(struct hda_codec *codec)
3441 struct hdmi_spec *spec = codec->spec;
3444 err = generic_hdmi_init(codec);
3449 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3450 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3452 /* make sure downmix information in infoframe is zero */
3453 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3455 /* enable channel-wise remap mode if supported */
3456 if (has_amd_full_remap_support(codec))
3457 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3458 ATI_VERB_SET_MULTICHANNEL_MODE,
3459 ATI_MULTICHANNEL_MODE_SINGLE);
3465 static int patch_atihdmi(struct hda_codec *codec)
3467 struct hdmi_spec *spec;
3468 struct hdmi_spec_per_cvt *per_cvt;
3471 err = patch_generic_hdmi(codec);
3476 codec->patch_ops.init = atihdmi_init;
3480 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
3481 spec->ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
3482 spec->ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
3483 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
3484 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
3485 spec->ops.setup_stream = atihdmi_setup_stream;
3487 if (!has_amd_full_remap_support(codec)) {
3488 /* override to ATI/AMD-specific versions with pairwise mapping */
3489 spec->ops.chmap_cea_alloc_validate_get_type =
3490 atihdmi_paired_chmap_cea_alloc_validate_get_type;
3491 spec->ops.cea_alloc_to_tlv_chmap = atihdmi_paired_cea_alloc_to_tlv_chmap;
3492 spec->ops.chmap_validate = atihdmi_paired_chmap_validate;
3495 /* ATI/AMD converters do not advertise all of their capabilities */
3496 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
3497 per_cvt = get_cvt(spec, cvt_idx);
3498 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
3499 per_cvt->rates |= SUPPORTED_RATES;
3500 per_cvt->formats |= SUPPORTED_FORMATS;
3501 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
3504 spec->channels_max = max(spec->channels_max, 8u);
3509 /* VIA HDMI Implementation */
3510 #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
3511 #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
3513 static int patch_via_hdmi(struct hda_codec *codec)
3515 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3521 static const struct hda_device_id snd_hda_id_hdmi[] = {
3522 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi),
3523 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi),
3524 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi),
3525 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi),
3526 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi),
3527 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi),
3528 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi),
3529 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3530 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3531 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3532 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3533 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x),
3534 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi),
3535 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi),
3536 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi),
3537 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi),
3538 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi),
3539 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi),
3540 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi),
3541 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi),
3542 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi),
3543 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi),
3544 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi),
3545 /* 17 is known to be absent */
3546 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi),
3547 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi),
3548 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi),
3549 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi),
3550 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi),
3551 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi),
3552 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi),
3553 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi),
3554 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
3555 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi),
3556 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi),
3557 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi),
3558 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi),
3559 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi),
3560 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi),
3561 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi),
3562 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch),
3563 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi),
3564 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi),
3565 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi),
3566 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi),
3567 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch),
3568 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi),
3569 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi),
3570 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi),
3571 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi),
3572 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_generic_hdmi),
3573 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi),
3574 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi),
3575 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi),
3576 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_generic_hdmi),
3577 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_generic_hdmi),
3578 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_generic_hdmi),
3579 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_generic_hdmi),
3580 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_generic_hdmi),
3581 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_generic_hdmi),
3582 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_generic_hdmi),
3583 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi),
3584 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_generic_hdmi),
3585 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_generic_hdmi),
3586 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi),
3587 /* special ID for generic HDMI */
3588 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
3591 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
3593 MODULE_LICENSE("GPL");
3594 MODULE_DESCRIPTION("HDMI HD-audio codec");
3595 MODULE_ALIAS("snd-hda-codec-intelhdmi");
3596 MODULE_ALIAS("snd-hda-codec-nvhdmi");
3597 MODULE_ALIAS("snd-hda-codec-atihdmi");
3599 static struct hda_codec_driver hdmi_driver = {
3600 .id = snd_hda_id_hdmi,
3603 module_hda_codec_driver(hdmi_driver);