2 * HD audio interface patch for Creative CA0132 chip
4 * Copyright (c) 2011, Creative Technology Ltd.
6 * Based on patch_ca0110.c
7 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
9 * This driver is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This driver is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #include <linux/init.h>
25 #include <linux/delay.h>
26 #include <linux/slab.h>
27 #include <linux/mutex.h>
28 #include <linux/module.h>
29 #include <linux/firmware.h>
30 #include <sound/core.h>
31 #include "hda_codec.h"
32 #include "hda_local.h"
33 #include "hda_auto_parser.h"
36 #include "ca0132_regs.h"
38 /* Enable this to see controls for tuning purpose. */
39 /*#define ENABLE_TUNING_CONTROLS*/
41 #define FLOAT_ZERO 0x00000000
42 #define FLOAT_ONE 0x3f800000
43 #define FLOAT_TWO 0x40000000
44 #define FLOAT_MINUS_5 0xc0a00000
46 #define UNSOL_TAG_HP 0x10
47 #define UNSOL_TAG_AMIC1 0x12
48 #define UNSOL_TAG_DSP 0x16
50 #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
51 #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
53 #define DMA_TRANSFER_FRAME_SIZE_NWORDS 8
54 #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32
55 #define DMA_OVERLAY_FRAME_SIZE_NWORDS 2
57 #define MASTERCONTROL 0x80
58 #define MASTERCONTROL_ALLOC_DMA_CHAN 10
59 #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60
61 #define WIDGET_CHIP_CTRL 0x15
62 #define WIDGET_DSP_CTRL 0x16
64 #define MEM_CONNID_MICIN1 3
65 #define MEM_CONNID_MICIN2 5
66 #define MEM_CONNID_MICOUT1 12
67 #define MEM_CONNID_MICOUT2 14
68 #define MEM_CONNID_WUH 10
69 #define MEM_CONNID_DSP 16
70 #define MEM_CONNID_DMIC 100
75 #define EFX_FILE "ctefx.bin"
77 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
78 MODULE_FIRMWARE(EFX_FILE);
81 static char *dirstr[2] = { "Playback", "Capture" };
94 #define VNODE_START_NID 0x80
95 VNID_SPK = VNODE_START_NID, /* Speaker vnid */
102 #define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID)
104 #define EFFECT_START_NID 0x90
105 #define OUT_EFFECT_START_NID EFFECT_START_NID
106 SURROUND = OUT_EFFECT_START_NID,
113 #define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
115 #define IN_EFFECT_START_NID OUT_EFFECT_END_NID
116 ECHO_CANCELLATION = IN_EFFECT_START_NID,
121 #define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
123 VOICEFX = IN_EFFECT_END_NID,
127 #define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID)
130 /* Effects values size*/
131 #define EFFECT_VALS_MAX_COUNT 12
133 /* Latency introduced by DSP blocks in milliseconds. */
134 #define DSP_CAPTURE_INIT_LATENCY 0
135 #define DSP_CRYSTAL_VOICE_LATENCY 124
136 #define DSP_PLAYBACK_INIT_LATENCY 13
137 #define DSP_PLAY_ENHANCEMENT_LATENCY 30
138 #define DSP_SPEAKER_OUT_LATENCY 7
141 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
143 int mid; /*effect module ID*/
144 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
145 int direct; /* 0:output; 1:input*/
146 int params; /* number of default non-on/off params */
147 /*effect default values, 1st is on/off. */
148 unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
151 #define EFX_DIR_OUT 0
154 static struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
155 { .name = "Surround",
159 .direct = EFX_DIR_OUT,
161 .def_vals = {0x3F800000, 0x3F2B851F}
163 { .name = "Crystalizer",
167 .direct = EFX_DIR_OUT,
169 .def_vals = {0x3F800000, 0x3F266666}
171 { .name = "Dialog Plus",
175 .direct = EFX_DIR_OUT,
177 .def_vals = {0x00000000, 0x3F000000}
179 { .name = "Smart Volume",
183 .direct = EFX_DIR_OUT,
185 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
190 .reqs = {24, 23, 25},
191 .direct = EFX_DIR_OUT,
193 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
195 { .name = "Equalizer",
198 .reqs = {9, 10, 11, 12, 13, 14,
199 15, 16, 17, 18, 19, 20},
200 .direct = EFX_DIR_OUT,
202 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
203 0x00000000, 0x00000000, 0x00000000, 0x00000000,
204 0x00000000, 0x00000000, 0x00000000, 0x00000000}
206 { .name = "Echo Cancellation",
207 .nid = ECHO_CANCELLATION,
209 .reqs = {0, 1, 2, 3},
210 .direct = EFX_DIR_IN,
212 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
214 { .name = "Voice Focus",
217 .reqs = {6, 7, 8, 9},
218 .direct = EFX_DIR_IN,
220 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
226 .direct = EFX_DIR_IN,
228 .def_vals = {0x00000000, 0x3F3D70A4}
230 { .name = "Noise Reduction",
231 .nid = NOISE_REDUCTION,
234 .direct = EFX_DIR_IN,
236 .def_vals = {0x3F800000, 0x3F000000}
241 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
242 .direct = EFX_DIR_IN,
244 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
245 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
250 /* Tuning controls */
251 #ifdef ENABLE_TUNING_CONTROLS
254 #define TUNING_CTL_START_NID 0xC0
255 WEDGE_ANGLE = TUNING_CTL_START_NID,
268 #define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
271 struct ct_tuning_ctl {
272 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
273 hda_nid_t parent_nid;
275 int mid; /*effect module ID*/
276 int req; /*effect module request*/
277 int direct; /* 0:output; 1:input*/
278 unsigned int def_val;/*effect default values*/
281 static struct ct_tuning_ctl ca0132_tuning_ctls[] = {
282 { .name = "Wedge Angle",
283 .parent_nid = VOICE_FOCUS,
287 .direct = EFX_DIR_IN,
288 .def_val = 0x41F00000
290 { .name = "SVM Level",
291 .parent_nid = MIC_SVM,
295 .direct = EFX_DIR_IN,
296 .def_val = 0x3F3D70A4
298 { .name = "EQ Band0",
299 .parent_nid = EQUALIZER,
300 .nid = EQUALIZER_BAND_0,
303 .direct = EFX_DIR_OUT,
304 .def_val = 0x00000000
306 { .name = "EQ Band1",
307 .parent_nid = EQUALIZER,
308 .nid = EQUALIZER_BAND_1,
311 .direct = EFX_DIR_OUT,
312 .def_val = 0x00000000
314 { .name = "EQ Band2",
315 .parent_nid = EQUALIZER,
316 .nid = EQUALIZER_BAND_2,
319 .direct = EFX_DIR_OUT,
320 .def_val = 0x00000000
322 { .name = "EQ Band3",
323 .parent_nid = EQUALIZER,
324 .nid = EQUALIZER_BAND_3,
327 .direct = EFX_DIR_OUT,
328 .def_val = 0x00000000
330 { .name = "EQ Band4",
331 .parent_nid = EQUALIZER,
332 .nid = EQUALIZER_BAND_4,
335 .direct = EFX_DIR_OUT,
336 .def_val = 0x00000000
338 { .name = "EQ Band5",
339 .parent_nid = EQUALIZER,
340 .nid = EQUALIZER_BAND_5,
343 .direct = EFX_DIR_OUT,
344 .def_val = 0x00000000
346 { .name = "EQ Band6",
347 .parent_nid = EQUALIZER,
348 .nid = EQUALIZER_BAND_6,
351 .direct = EFX_DIR_OUT,
352 .def_val = 0x00000000
354 { .name = "EQ Band7",
355 .parent_nid = EQUALIZER,
356 .nid = EQUALIZER_BAND_7,
359 .direct = EFX_DIR_OUT,
360 .def_val = 0x00000000
362 { .name = "EQ Band8",
363 .parent_nid = EQUALIZER,
364 .nid = EQUALIZER_BAND_8,
367 .direct = EFX_DIR_OUT,
368 .def_val = 0x00000000
370 { .name = "EQ Band9",
371 .parent_nid = EQUALIZER,
372 .nid = EQUALIZER_BAND_9,
375 .direct = EFX_DIR_OUT,
376 .def_val = 0x00000000
381 /* Voice FX Presets */
382 #define VOICEFX_MAX_PARAM_COUNT 9
388 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
391 struct ct_voicefx_preset {
392 char *name; /*preset name*/
393 unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
396 static struct ct_voicefx ca0132_voicefx = {
397 .name = "VoiceFX Capture Switch",
400 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
403 static struct ct_voicefx_preset ca0132_voicefx_presets[] = {
405 .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
406 0x44FA0000, 0x3F800000, 0x3F800000,
407 0x3F800000, 0x00000000, 0x00000000 }
409 { .name = "Female2Male",
410 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
411 0x44FA0000, 0x3F19999A, 0x3F866666,
412 0x3F800000, 0x00000000, 0x00000000 }
414 { .name = "Male2Female",
415 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
416 0x450AC000, 0x4017AE14, 0x3F6B851F,
417 0x3F800000, 0x00000000, 0x00000000 }
419 { .name = "ScrappyKid",
420 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
421 0x44FA0000, 0x40400000, 0x3F28F5C3,
422 0x3F800000, 0x00000000, 0x00000000 }
425 .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
426 0x44E10000, 0x3FB33333, 0x3FB9999A,
427 0x3F800000, 0x3E3A2E43, 0x00000000 }
430 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
431 0x45098000, 0x3F266666, 0x3FC00000,
432 0x3F800000, 0x00000000, 0x00000000 }
435 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
436 0x45193000, 0x3F8E147B, 0x3F75C28F,
437 0x3F800000, 0x00000000, 0x00000000 }
440 .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
441 0x45007000, 0x3F451EB8, 0x3F7851EC,
442 0x3F800000, 0x00000000, 0x00000000 }
444 { .name = "AlienBrute",
445 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
446 0x451F6000, 0x3F266666, 0x3FA7D945,
447 0x3F800000, 0x3CF5C28F, 0x00000000 }
450 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
451 0x44FA0000, 0x3FB2718B, 0x3F800000,
452 0xBC07010E, 0x00000000, 0x00000000 }
455 .vals = { 0x3F800000, 0x43C20000, 0x44906000,
456 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
457 0x3F0A3D71, 0x00000000, 0x00000000 }
460 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
461 0x44FA0000, 0x3F800000, 0x3F800000,
462 0x3E4CCCCD, 0x00000000, 0x00000000 }
464 { .name = "DeepVoice",
465 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
466 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
467 0x3F800000, 0x00000000, 0x00000000 }
469 { .name = "Munchkin",
470 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
471 0x44FA0000, 0x3F800000, 0x3F1A043C,
472 0x3F800000, 0x00000000, 0x00000000 }
476 enum hda_cmd_vendor_io {
478 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
479 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100,
481 VENDOR_DSPIO_STATUS = 0xF01,
482 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702,
483 VENDOR_DSPIO_SCP_READ_DATA = 0xF02,
484 VENDOR_DSPIO_DSP_INIT = 0x703,
485 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704,
486 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04,
488 /* for ChipIO node */
489 VENDOR_CHIPIO_ADDRESS_LOW = 0x000,
490 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100,
491 VENDOR_CHIPIO_STREAM_FORMAT = 0x200,
492 VENDOR_CHIPIO_DATA_LOW = 0x300,
493 VENDOR_CHIPIO_DATA_HIGH = 0x400,
495 VENDOR_CHIPIO_GET_PARAMETER = 0xF00,
496 VENDOR_CHIPIO_STATUS = 0xF01,
497 VENDOR_CHIPIO_HIC_POST_READ = 0x702,
498 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03,
500 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707,
501 VENDOR_CHIPIO_8051_DATA_READ = 0xF07,
503 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
504 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A,
506 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C,
507 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C,
508 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D,
509 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E,
510 VENDOR_CHIPIO_FLAG_SET = 0x70F,
511 VENDOR_CHIPIO_FLAGS_GET = 0xF0F,
512 VENDOR_CHIPIO_PARAM_SET = 0x710,
513 VENDOR_CHIPIO_PARAM_GET = 0xF10,
515 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711,
516 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712,
517 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12,
518 VENDOR_CHIPIO_PORT_FREE_SET = 0x713,
520 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17,
521 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717,
522 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18,
523 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718,
525 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788,
526 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88,
527 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789,
528 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89,
529 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A,
530 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A,
532 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D
538 enum control_flag_id {
539 /* Connection manager stream setup is bypassed/enabled */
540 CONTROL_FLAG_C_MGR = 0,
541 /* DSP DMA is bypassed/enabled */
542 CONTROL_FLAG_DMA = 1,
543 /* 8051 'idle' mode is disabled/enabled */
544 CONTROL_FLAG_IDLE_ENABLE = 2,
545 /* Tracker for the SPDIF-in path is bypassed/enabled */
546 CONTROL_FLAG_TRACKER = 3,
547 /* DigitalOut to Spdif2Out connection is disabled/enabled */
548 CONTROL_FLAG_SPDIF2OUT = 4,
549 /* Digital Microphone is disabled/enabled */
550 CONTROL_FLAG_DMIC = 5,
551 /* ADC_B rate is 48 kHz/96 kHz */
552 CONTROL_FLAG_ADC_B_96KHZ = 6,
553 /* ADC_C rate is 48 kHz/96 kHz */
554 CONTROL_FLAG_ADC_C_96KHZ = 7,
555 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
556 CONTROL_FLAG_DAC_96KHZ = 8,
557 /* DSP rate is 48 kHz/96 kHz */
558 CONTROL_FLAG_DSP_96KHZ = 9,
559 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
560 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10,
561 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
562 CONTROL_FLAG_SRC_RATE_96KHZ = 11,
563 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
564 CONTROL_FLAG_DECODE_LOOP = 12,
565 /* De-emphasis filter on DAC-1 disabled/enabled */
566 CONTROL_FLAG_DAC1_DEEMPHASIS = 13,
567 /* De-emphasis filter on DAC-2 disabled/enabled */
568 CONTROL_FLAG_DAC2_DEEMPHASIS = 14,
569 /* De-emphasis filter on DAC-3 disabled/enabled */
570 CONTROL_FLAG_DAC3_DEEMPHASIS = 15,
571 /* High-pass filter on ADC_B disabled/enabled */
572 CONTROL_FLAG_ADC_B_HIGH_PASS = 16,
573 /* High-pass filter on ADC_C disabled/enabled */
574 CONTROL_FLAG_ADC_C_HIGH_PASS = 17,
575 /* Common mode on Port_A disabled/enabled */
576 CONTROL_FLAG_PORT_A_COMMON_MODE = 18,
577 /* Common mode on Port_D disabled/enabled */
578 CONTROL_FLAG_PORT_D_COMMON_MODE = 19,
579 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
580 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20,
581 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
582 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21,
583 /* ASI rate is 48kHz/96kHz */
584 CONTROL_FLAG_ASI_96KHZ = 22,
585 /* DAC power settings able to control attached ports no/yes */
586 CONTROL_FLAG_DACS_CONTROL_PORTS = 23,
587 /* Clock Stop OK reporting is disabled/enabled */
588 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
589 /* Number of control flags */
590 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
594 * Control parameter IDs
596 enum control_param_id {
597 /* 0: None, 1: Mic1In*/
598 CONTROL_PARAM_VIP_SOURCE = 1,
599 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
600 CONTROL_PARAM_SPDIF1_SOURCE = 2,
601 /* Port A output stage gain setting to use when 16 Ohm output
602 * impedance is selected*/
603 CONTROL_PARAM_PORTA_160OHM_GAIN = 8,
604 /* Port D output stage gain setting to use when 16 Ohm output
605 * impedance is selected*/
606 CONTROL_PARAM_PORTD_160OHM_GAIN = 10,
610 /* Select stream with the given ID */
611 CONTROL_PARAM_STREAM_ID = 24,
612 /* Source connection point for the selected stream */
613 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
614 /* Destination connection point for the selected stream */
615 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26,
616 /* Number of audio channels in the selected stream */
617 CONTROL_PARAM_STREAMS_CHANNELS = 27,
618 /*Enable control for the selected stream */
619 CONTROL_PARAM_STREAM_CONTROL = 28,
621 /* Connection Point Control */
623 /* Select connection point with the given ID */
624 CONTROL_PARAM_CONN_POINT_ID = 29,
625 /* Connection point sample rate */
626 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30,
630 /* Select HDA node with the given ID */
631 CONTROL_PARAM_NODE_ID = 31
635 * Dsp Io Status codes
637 enum hda_vendor_status_dspio {
639 VENDOR_STATUS_DSPIO_OK = 0x00,
640 /* Busy, unable to accept new command, the host must retry */
641 VENDOR_STATUS_DSPIO_BUSY = 0x01,
642 /* SCP command queue is full */
643 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02,
644 /* SCP response queue is empty */
645 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
649 * Chip Io Status codes
651 enum hda_vendor_status_chipio {
653 VENDOR_STATUS_CHIPIO_OK = 0x00,
654 /* Busy, unable to accept new command, the host must retry */
655 VENDOR_STATUS_CHIPIO_BUSY = 0x01
661 enum ca0132_sample_rate {
681 SR_RATE_UNKNOWN = 0x1F
684 enum dsp_download_state {
685 DSP_DOWNLOAD_FAILED = -1,
686 DSP_DOWNLOAD_INIT = 0,
691 /* retrieve parameters from hda format */
692 #define get_hdafmt_chs(fmt) (fmt & 0xf)
693 #define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7)
694 #define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f)
695 #define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1)
702 struct snd_kcontrol_new *mixers[5];
703 unsigned int num_mixers;
704 const struct hda_verb *base_init_verbs;
705 const struct hda_verb *base_exit_verbs;
706 const struct hda_verb *init_verbs[5];
707 unsigned int num_init_verbs; /* exclude base init verbs */
708 struct auto_pin_cfg autocfg;
710 /* Nodes configurations */
711 struct hda_multi_out multiout;
712 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
713 hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
714 unsigned int num_outputs;
715 hda_nid_t input_pins[AUTO_PIN_LAST];
716 hda_nid_t adcs[AUTO_PIN_LAST];
719 unsigned int num_inputs;
720 hda_nid_t shared_mic_nid;
721 hda_nid_t shared_out_nid;
722 struct hda_pcm pcm_rec[5]; /* PCM information */
725 struct mutex chipio_mutex; /* chip access mutex */
728 /* DSP download related */
729 enum dsp_download_state dsp_state;
730 unsigned int dsp_stream_id;
731 unsigned int wait_scp;
732 unsigned int wait_scp_header;
733 unsigned int wait_num_data;
734 unsigned int scp_resp_header;
735 unsigned int scp_resp_data[4];
736 unsigned int scp_resp_count;
738 /* mixer and effects related */
739 unsigned char dmic_ctl;
742 long vnode_lvol[VNODES_COUNT];
743 long vnode_rvol[VNODES_COUNT];
744 long vnode_lswitch[VNODES_COUNT];
745 long vnode_rswitch[VNODES_COUNT];
746 long effects_switch[EFFECTS_COUNT];
750 struct hda_codec *codec;
751 struct delayed_work unsol_hp_work;
753 #ifdef ENABLE_TUNING_CONTROLS
754 long cur_ctl_vals[TUNING_CTLS_COUNT];
759 * CA0132 codec access
761 static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
762 unsigned int verb, unsigned int parm, unsigned int *res)
764 unsigned int response;
765 response = snd_hda_codec_read(codec, nid, 0, verb, parm);
768 return ((response == -1) ? -1 : 0);
771 static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
772 unsigned short converter_format, unsigned int *res)
774 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
775 converter_format & 0xffff, res);
778 static int codec_set_converter_stream_channel(struct hda_codec *codec,
779 hda_nid_t nid, unsigned char stream,
780 unsigned char channel, unsigned int *res)
782 unsigned char converter_stream_channel = 0;
784 converter_stream_channel = (stream << 4) | (channel & 0x0f);
785 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
786 converter_stream_channel, res);
789 /* Chip access helper function */
790 static int chipio_send(struct hda_codec *codec,
795 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
797 /* send bits of data specified by reg */
799 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
801 if (res == VENDOR_STATUS_CHIPIO_OK)
804 } while (time_before(jiffies, timeout));
810 * Write chip address through the vendor widget -- NOT protected by the Mutex!
812 static int chipio_write_address(struct hda_codec *codec,
813 unsigned int chip_addx)
815 struct ca0132_spec *spec = codec->spec;
818 if (spec->curr_chip_addx == chip_addx)
821 /* send low 16 bits of the address */
822 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
826 /* send high 16 bits of the address */
827 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
831 spec->curr_chip_addx = (res < 0) ? ~0UL : chip_addx;
837 * Write data through the vendor widget -- NOT protected by the Mutex!
839 static int chipio_write_data(struct hda_codec *codec, unsigned int data)
841 struct ca0132_spec *spec = codec->spec;
844 /* send low 16 bits of the data */
845 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
848 /* send high 16 bits of the data */
849 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
853 /*If no error encountered, automatically increment the address
854 as per chip behaviour*/
855 spec->curr_chip_addx = (res != -EIO) ?
856 (spec->curr_chip_addx + 4) : ~0UL;
861 * Write multiple data through the vendor widget -- NOT protected by the Mutex!
863 static int chipio_write_data_multiple(struct hda_codec *codec,
870 codec_dbg(codec, "chipio_write_data null ptr\n");
874 while ((count-- != 0) && (status == 0))
875 status = chipio_write_data(codec, *data++);
882 * Read data through the vendor widget -- NOT protected by the Mutex!
884 static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
886 struct ca0132_spec *spec = codec->spec;
890 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
894 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
899 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
900 VENDOR_CHIPIO_HIC_READ_DATA,
904 /*If no error encountered, automatically increment the address
905 as per chip behaviour*/
906 spec->curr_chip_addx = (res != -EIO) ?
907 (spec->curr_chip_addx + 4) : ~0UL;
912 * Write given value to the given address through the chip I/O widget.
913 * protected by the Mutex
915 static int chipio_write(struct hda_codec *codec,
916 unsigned int chip_addx, const unsigned int data)
918 struct ca0132_spec *spec = codec->spec;
921 mutex_lock(&spec->chipio_mutex);
923 /* write the address, and if successful proceed to write data */
924 err = chipio_write_address(codec, chip_addx);
928 err = chipio_write_data(codec, data);
933 mutex_unlock(&spec->chipio_mutex);
938 * Write multiple values to the given address through the chip I/O widget.
939 * protected by the Mutex
941 static int chipio_write_multiple(struct hda_codec *codec,
946 struct ca0132_spec *spec = codec->spec;
949 mutex_lock(&spec->chipio_mutex);
950 status = chipio_write_address(codec, chip_addx);
954 status = chipio_write_data_multiple(codec, data, count);
956 mutex_unlock(&spec->chipio_mutex);
962 * Read the given address through the chip I/O widget
963 * protected by the Mutex
965 static int chipio_read(struct hda_codec *codec,
966 unsigned int chip_addx, unsigned int *data)
968 struct ca0132_spec *spec = codec->spec;
971 mutex_lock(&spec->chipio_mutex);
973 /* write the address, and if successful proceed to write data */
974 err = chipio_write_address(codec, chip_addx);
978 err = chipio_read_data(codec, data);
983 mutex_unlock(&spec->chipio_mutex);
988 * Set chip control flags through the chip I/O widget.
990 static void chipio_set_control_flag(struct hda_codec *codec,
991 enum control_flag_id flag_id,
995 unsigned int flag_bit;
997 flag_bit = (flag_state ? 1 : 0);
998 val = (flag_bit << 7) | (flag_id);
999 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1000 VENDOR_CHIPIO_FLAG_SET, val);
1004 * Set chip parameters through the chip I/O widget.
1006 static void chipio_set_control_param(struct hda_codec *codec,
1007 enum control_param_id param_id, int param_val)
1009 struct ca0132_spec *spec = codec->spec;
1012 if ((param_id < 32) && (param_val < 8)) {
1013 val = (param_val << 5) | (param_id);
1014 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1015 VENDOR_CHIPIO_PARAM_SET, val);
1017 mutex_lock(&spec->chipio_mutex);
1018 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1019 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1020 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1022 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1023 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1026 mutex_unlock(&spec->chipio_mutex);
1031 * Set sampling rate of the connection point.
1033 static void chipio_set_conn_rate(struct hda_codec *codec,
1034 int connid, enum ca0132_sample_rate rate)
1036 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1037 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1044 static void chipio_enable_clocks(struct hda_codec *codec)
1046 struct ca0132_spec *spec = codec->spec;
1048 mutex_lock(&spec->chipio_mutex);
1049 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1050 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
1051 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1052 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1053 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1054 VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
1055 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1056 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
1057 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1058 VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
1059 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1060 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1061 mutex_unlock(&spec->chipio_mutex);
1065 * CA0132 DSP IO stuffs
1067 static int dspio_send(struct hda_codec *codec, unsigned int reg,
1071 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1073 /* send bits of data specified by reg to dsp */
1075 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
1076 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
1079 } while (time_before(jiffies, timeout));
1085 * Wait for DSP to be ready for commands
1087 static void dspio_write_wait(struct hda_codec *codec)
1090 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1093 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1094 VENDOR_DSPIO_STATUS, 0);
1095 if ((status == VENDOR_STATUS_DSPIO_OK) ||
1096 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
1099 } while (time_before(jiffies, timeout));
1103 * Write SCP data to DSP
1105 static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
1107 struct ca0132_spec *spec = codec->spec;
1110 dspio_write_wait(codec);
1112 mutex_lock(&spec->chipio_mutex);
1113 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
1118 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
1123 /* OK, now check if the write itself has executed*/
1124 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1125 VENDOR_DSPIO_STATUS, 0);
1127 mutex_unlock(&spec->chipio_mutex);
1129 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
1134 * Write multiple SCP data to DSP
1136 static int dspio_write_multiple(struct hda_codec *codec,
1137 unsigned int *buffer, unsigned int size)
1142 if ((buffer == NULL))
1146 while (count < size) {
1147 status = dspio_write(codec, *buffer++);
1156 static int dspio_read(struct hda_codec *codec, unsigned int *data)
1160 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
1164 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
1165 if (status == -EIO ||
1166 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
1169 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1170 VENDOR_DSPIO_SCP_READ_DATA, 0);
1175 static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
1176 unsigned int *buf_size, unsigned int size_count)
1179 unsigned int size = *buf_size;
1181 unsigned int skip_count;
1184 if ((buffer == NULL))
1188 while (count < size && count < size_count) {
1189 status = dspio_read(codec, buffer++);
1197 while (skip_count < size) {
1198 status = dspio_read(codec, &dummy);
1210 * Construct the SCP header using corresponding fields
1212 static inline unsigned int
1213 make_scp_header(unsigned int target_id, unsigned int source_id,
1214 unsigned int get_flag, unsigned int req,
1215 unsigned int device_flag, unsigned int resp_flag,
1216 unsigned int error_flag, unsigned int data_size)
1218 unsigned int header = 0;
1220 header = (data_size & 0x1f) << 27;
1221 header |= (error_flag & 0x01) << 26;
1222 header |= (resp_flag & 0x01) << 25;
1223 header |= (device_flag & 0x01) << 24;
1224 header |= (req & 0x7f) << 17;
1225 header |= (get_flag & 0x01) << 16;
1226 header |= (source_id & 0xff) << 8;
1227 header |= target_id & 0xff;
1233 * Extract corresponding fields from SCP header
1236 extract_scp_header(unsigned int header,
1237 unsigned int *target_id, unsigned int *source_id,
1238 unsigned int *get_flag, unsigned int *req,
1239 unsigned int *device_flag, unsigned int *resp_flag,
1240 unsigned int *error_flag, unsigned int *data_size)
1243 *data_size = (header >> 27) & 0x1f;
1245 *error_flag = (header >> 26) & 0x01;
1247 *resp_flag = (header >> 25) & 0x01;
1249 *device_flag = (header >> 24) & 0x01;
1251 *req = (header >> 17) & 0x7f;
1253 *get_flag = (header >> 16) & 0x01;
1255 *source_id = (header >> 8) & 0xff;
1257 *target_id = header & 0xff;
1260 #define SCP_MAX_DATA_WORDS (16)
1262 /* Structure to contain any SCP message */
1265 unsigned int data[SCP_MAX_DATA_WORDS];
1268 static void dspio_clear_response_queue(struct hda_codec *codec)
1270 unsigned int dummy = 0;
1273 /* clear all from the response queue */
1275 status = dspio_read(codec, &dummy);
1276 } while (status == 0);
1279 static int dspio_get_response_data(struct hda_codec *codec)
1281 struct ca0132_spec *spec = codec->spec;
1282 unsigned int data = 0;
1285 if (dspio_read(codec, &data) < 0)
1288 if ((data & 0x00ffffff) == spec->wait_scp_header) {
1289 spec->scp_resp_header = data;
1290 spec->scp_resp_count = data >> 27;
1291 count = spec->wait_num_data;
1292 dspio_read_multiple(codec, spec->scp_resp_data,
1293 &spec->scp_resp_count, count);
1301 * Send SCP message to DSP
1303 static int dspio_send_scp_message(struct hda_codec *codec,
1304 unsigned char *send_buf,
1305 unsigned int send_buf_size,
1306 unsigned char *return_buf,
1307 unsigned int return_buf_size,
1308 unsigned int *bytes_returned)
1310 struct ca0132_spec *spec = codec->spec;
1312 unsigned int scp_send_size = 0;
1313 unsigned int total_size;
1314 bool waiting_for_resp = false;
1315 unsigned int header;
1316 struct scp_msg *ret_msg;
1317 unsigned int resp_src_id, resp_target_id;
1318 unsigned int data_size, src_id, target_id, get_flag, device_flag;
1321 *bytes_returned = 0;
1323 /* get scp header from buffer */
1324 header = *((unsigned int *)send_buf);
1325 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
1326 &device_flag, NULL, NULL, &data_size);
1327 scp_send_size = data_size + 1;
1328 total_size = (scp_send_size * 4);
1330 if (send_buf_size < total_size)
1333 if (get_flag || device_flag) {
1334 if (!return_buf || return_buf_size < 4 || !bytes_returned)
1337 spec->wait_scp_header = *((unsigned int *)send_buf);
1339 /* swap source id with target id */
1340 resp_target_id = src_id;
1341 resp_src_id = target_id;
1342 spec->wait_scp_header &= 0xffff0000;
1343 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
1344 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
1346 waiting_for_resp = true;
1349 status = dspio_write_multiple(codec, (unsigned int *)send_buf,
1356 if (waiting_for_resp) {
1357 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1358 memset(return_buf, 0, return_buf_size);
1361 } while (spec->wait_scp && time_before(jiffies, timeout));
1362 waiting_for_resp = false;
1363 if (!spec->wait_scp) {
1364 ret_msg = (struct scp_msg *)return_buf;
1365 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
1366 memcpy(&ret_msg->data, spec->scp_resp_data,
1367 spec->wait_num_data);
1368 *bytes_returned = (spec->scp_resp_count + 1) * 4;
1380 * Prepare and send the SCP message to DSP
1381 * @codec: the HDA codec
1382 * @mod_id: ID of the DSP module to send the command
1383 * @req: ID of request to send to the DSP module
1385 * @data: pointer to the data to send with the request, request specific
1386 * @len: length of the data, in bytes
1387 * @reply: point to the buffer to hold data returned for a reply
1388 * @reply_len: length of the reply buffer returned from GET
1390 * Returns zero or a negative error code.
1392 static int dspio_scp(struct hda_codec *codec,
1393 int mod_id, int req, int dir, void *data, unsigned int len,
1394 void *reply, unsigned int *reply_len)
1397 struct scp_msg scp_send, scp_reply;
1398 unsigned int ret_bytes, send_size, ret_size;
1399 unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
1400 unsigned int reply_data_size;
1402 memset(&scp_send, 0, sizeof(scp_send));
1403 memset(&scp_reply, 0, sizeof(scp_reply));
1405 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
1408 if (dir == SCP_GET && reply == NULL) {
1409 codec_dbg(codec, "dspio_scp get but has no buffer\n");
1413 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
1414 codec_dbg(codec, "dspio_scp bad resp buf len parms\n");
1418 scp_send.hdr = make_scp_header(mod_id, 0x20, (dir == SCP_GET), req,
1419 0, 0, 0, len/sizeof(unsigned int));
1420 if (data != NULL && len > 0) {
1421 len = min((unsigned int)(sizeof(scp_send.data)), len);
1422 memcpy(scp_send.data, data, len);
1426 send_size = sizeof(unsigned int) + len;
1427 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
1428 send_size, (unsigned char *)&scp_reply,
1429 sizeof(scp_reply), &ret_bytes);
1432 codec_dbg(codec, "dspio_scp: send scp msg failed\n");
1436 /* extract send and reply headers members */
1437 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
1438 NULL, NULL, NULL, NULL, NULL);
1439 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
1440 &reply_resp_flag, &reply_error_flag,
1446 if (reply_resp_flag && !reply_error_flag) {
1447 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
1448 / sizeof(unsigned int);
1450 if (*reply_len < ret_size*sizeof(unsigned int)) {
1451 codec_dbg(codec, "reply too long for buf\n");
1453 } else if (ret_size != reply_data_size) {
1454 codec_dbg(codec, "RetLen and HdrLen .NE.\n");
1457 *reply_len = ret_size*sizeof(unsigned int);
1458 memcpy(reply, scp_reply.data, *reply_len);
1461 codec_dbg(codec, "reply ill-formed or errflag set\n");
1469 * Set DSP parameters
1471 static int dspio_set_param(struct hda_codec *codec, int mod_id,
1472 int req, void *data, unsigned int len)
1474 return dspio_scp(codec, mod_id, req, SCP_SET, data, len, NULL, NULL);
1477 static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
1478 int req, unsigned int data)
1480 return dspio_set_param(codec, mod_id, req, &data, sizeof(unsigned int));
1484 * Allocate a DSP DMA channel via an SCP message
1486 static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
1489 unsigned int size = sizeof(dma_chan);
1491 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n");
1492 status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN,
1493 SCP_GET, NULL, 0, dma_chan, &size);
1496 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n");
1500 if ((*dma_chan + 1) == 0) {
1501 codec_dbg(codec, "no free dma channels to allocate\n");
1505 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
1506 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n");
1512 * Free a DSP DMA via an SCP message
1514 static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
1517 unsigned int dummy = 0;
1519 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n");
1520 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan);
1522 status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN,
1523 SCP_SET, &dma_chan, sizeof(dma_chan), NULL, &dummy);
1526 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n");
1530 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n");
1538 static int dsp_set_run_state(struct hda_codec *codec)
1540 unsigned int dbg_ctrl_reg;
1541 unsigned int halt_state;
1544 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
1548 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
1549 DSP_DBGCNTL_STATE_LOBIT;
1551 if (halt_state != 0) {
1552 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
1553 DSP_DBGCNTL_SS_MASK);
1554 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1559 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
1560 DSP_DBGCNTL_EXEC_MASK;
1561 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1573 static int dsp_reset(struct hda_codec *codec)
1578 codec_dbg(codec, "dsp_reset\n");
1580 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
1582 } while (res == -EIO && retry);
1585 codec_dbg(codec, "dsp_reset timeout\n");
1593 * Convert chip address to DSP address
1595 static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
1596 bool *code, bool *yram)
1598 *code = *yram = false;
1600 if (UC_RANGE(chip_addx, 1)) {
1602 return UC_OFF(chip_addx);
1603 } else if (X_RANGE_ALL(chip_addx, 1)) {
1604 return X_OFF(chip_addx);
1605 } else if (Y_RANGE_ALL(chip_addx, 1)) {
1607 return Y_OFF(chip_addx);
1610 return INVALID_CHIP_ADDRESS;
1614 * Check if the DSP DMA is active
1616 static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
1618 unsigned int dma_chnlstart_reg;
1620 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
1622 return ((dma_chnlstart_reg & (1 <<
1623 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
1626 static int dsp_dma_setup_common(struct hda_codec *codec,
1627 unsigned int chip_addx,
1628 unsigned int dma_chan,
1629 unsigned int port_map_mask,
1633 unsigned int chnl_prop;
1634 unsigned int dsp_addx;
1635 unsigned int active;
1638 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n");
1640 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
1641 codec_dbg(codec, "dma chan num invalid\n");
1645 if (dsp_is_dma_active(codec, dma_chan)) {
1646 codec_dbg(codec, "dma already active\n");
1650 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
1652 if (dsp_addx == INVALID_CHIP_ADDRESS) {
1653 codec_dbg(codec, "invalid chip addr\n");
1657 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
1660 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n");
1663 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
1667 codec_dbg(codec, "read CHNLPROP Reg fail\n");
1670 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n");
1674 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1676 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1678 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
1680 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
1682 codec_dbg(codec, "write CHNLPROP Reg fail\n");
1685 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n");
1688 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
1692 codec_dbg(codec, "read ACTIVE Reg fail\n");
1695 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n");
1698 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
1699 DSPDMAC_ACTIVE_AAR_MASK;
1701 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
1703 codec_dbg(codec, "write ACTIVE Reg fail\n");
1707 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n");
1709 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
1712 codec_dbg(codec, "write AUDCHSEL Reg fail\n");
1715 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n");
1717 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
1718 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
1720 codec_dbg(codec, "write IRQCNT Reg fail\n");
1723 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n");
1726 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
1727 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
1728 chip_addx, dsp_addx, dma_chan,
1729 port_map_mask, chnl_prop, active);
1731 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n");
1737 * Setup the DSP DMA per-transfer-specific registers
1739 static int dsp_dma_setup(struct hda_codec *codec,
1740 unsigned int chip_addx,
1742 unsigned int dma_chan)
1746 unsigned int dsp_addx;
1747 unsigned int addr_field;
1748 unsigned int incr_field;
1749 unsigned int base_cnt;
1750 unsigned int cur_cnt;
1751 unsigned int dma_cfg = 0;
1752 unsigned int adr_ofs = 0;
1753 unsigned int xfr_cnt = 0;
1754 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
1755 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
1757 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n");
1759 if (count > max_dma_count) {
1760 codec_dbg(codec, "count too big\n");
1764 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
1765 if (dsp_addx == INVALID_CHIP_ADDRESS) {
1766 codec_dbg(codec, "invalid chip addr\n");
1770 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n");
1772 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
1778 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
1780 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
1783 dma_cfg = addr_field + incr_field;
1784 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
1787 codec_dbg(codec, "write DMACFG Reg fail\n");
1790 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n");
1792 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
1795 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
1798 codec_dbg(codec, "write DSPADROFS Reg fail\n");
1801 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n");
1803 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
1805 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
1807 xfr_cnt = base_cnt | cur_cnt;
1809 status = chipio_write(codec,
1810 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
1812 codec_dbg(codec, "write XFRCNT Reg fail\n");
1815 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n");
1818 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
1819 "ADROFS=0x%x, XFRCNT=0x%x\n",
1820 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
1822 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n");
1830 static int dsp_dma_start(struct hda_codec *codec,
1831 unsigned int dma_chan, bool ovly)
1833 unsigned int reg = 0;
1836 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n");
1839 status = chipio_read(codec,
1840 DSPDMAC_CHNLSTART_INST_OFFSET, ®);
1843 codec_dbg(codec, "read CHNLSTART reg fail\n");
1846 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n");
1848 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
1849 DSPDMAC_CHNLSTART_DIS_MASK);
1852 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
1853 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
1855 codec_dbg(codec, "write CHNLSTART reg fail\n");
1858 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n");
1866 static int dsp_dma_stop(struct hda_codec *codec,
1867 unsigned int dma_chan, bool ovly)
1869 unsigned int reg = 0;
1872 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n");
1875 status = chipio_read(codec,
1876 DSPDMAC_CHNLSTART_INST_OFFSET, ®);
1879 codec_dbg(codec, "read CHNLSTART reg fail\n");
1882 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n");
1883 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
1884 DSPDMAC_CHNLSTART_DIS_MASK);
1887 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
1888 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
1890 codec_dbg(codec, "write CHNLSTART reg fail\n");
1893 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n");
1899 * Allocate router ports
1901 * @codec: the HDA codec
1902 * @num_chans: number of channels in the stream
1903 * @ports_per_channel: number of ports per channel
1904 * @start_device: start device
1905 * @port_map: pointer to the port list to hold the allocated ports
1907 * Returns zero or a negative error code.
1909 static int dsp_allocate_router_ports(struct hda_codec *codec,
1910 unsigned int num_chans,
1911 unsigned int ports_per_channel,
1912 unsigned int start_device,
1913 unsigned int *port_map)
1919 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1923 val = start_device << 6;
1924 val |= (ports_per_channel - 1) << 4;
1925 val |= num_chans - 1;
1927 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1928 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
1931 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1932 VENDOR_CHIPIO_PORT_ALLOC_SET,
1935 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1939 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1940 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
1944 return (res < 0) ? res : 0;
1950 static int dsp_free_router_ports(struct hda_codec *codec)
1954 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1958 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1959 VENDOR_CHIPIO_PORT_FREE_SET,
1962 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1968 * Allocate DSP ports for the download stream
1970 static int dsp_allocate_ports(struct hda_codec *codec,
1971 unsigned int num_chans,
1972 unsigned int rate_multi, unsigned int *port_map)
1976 codec_dbg(codec, " dsp_allocate_ports() -- begin\n");
1978 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
1979 codec_dbg(codec, "bad rate multiple\n");
1983 status = dsp_allocate_router_ports(codec, num_chans,
1984 rate_multi, 0, port_map);
1986 codec_dbg(codec, " dsp_allocate_ports() -- complete\n");
1991 static int dsp_allocate_ports_format(struct hda_codec *codec,
1992 const unsigned short fmt,
1993 unsigned int *port_map)
1996 unsigned int num_chans;
1998 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
1999 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
2000 unsigned int rate_multi = sample_rate_mul / sample_rate_div;
2002 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2003 codec_dbg(codec, "bad rate multiple\n");
2007 num_chans = get_hdafmt_chs(fmt) + 1;
2009 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2017 static int dsp_free_ports(struct hda_codec *codec)
2021 codec_dbg(codec, " dsp_free_ports() -- begin\n");
2023 status = dsp_free_router_ports(codec);
2025 codec_dbg(codec, "free router ports fail\n");
2028 codec_dbg(codec, " dsp_free_ports() -- complete\n");
2034 * HDA DMA engine stuffs for DSP code download
2037 struct hda_codec *codec;
2038 unsigned short m_converter_format;
2039 struct snd_dma_buffer *dmab;
2040 unsigned int buf_size;
2049 static int dma_convert_to_hda_format(struct hda_codec *codec,
2050 unsigned int sample_rate,
2051 unsigned short channels,
2052 unsigned short *hda_format)
2054 unsigned int format_val;
2056 format_val = snd_hda_calc_stream_format(codec,
2059 SNDRV_PCM_FORMAT_S32_LE,
2063 *hda_format = (unsigned short)format_val;
2069 * Reset DMA for DSP download
2071 static int dma_reset(struct dma_engine *dma)
2073 struct hda_codec *codec = dma->codec;
2074 struct ca0132_spec *spec = codec->spec;
2077 if (dma->dmab->area)
2078 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
2080 status = snd_hda_codec_load_dsp_prepare(codec,
2081 dma->m_converter_format,
2086 spec->dsp_stream_id = status;
2090 static int dma_set_state(struct dma_engine *dma, enum dma_state state)
2095 case DMA_STATE_STOP:
2105 snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
2109 static unsigned int dma_get_buffer_size(struct dma_engine *dma)
2111 return dma->dmab->bytes;
2114 static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
2116 return dma->dmab->area;
2119 static int dma_xfer(struct dma_engine *dma,
2120 const unsigned int *data,
2123 memcpy(dma->dmab->area, data, count);
2127 static void dma_get_converter_format(
2128 struct dma_engine *dma,
2129 unsigned short *format)
2132 *format = dma->m_converter_format;
2135 static unsigned int dma_get_stream_id(struct dma_engine *dma)
2137 struct ca0132_spec *spec = dma->codec->spec;
2139 return spec->dsp_stream_id;
2142 struct dsp_image_seg {
2149 static const u32 g_magic_value = 0x4c46584d;
2150 static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
2152 static bool is_valid(const struct dsp_image_seg *p)
2154 return p->magic == g_magic_value;
2157 static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
2159 return g_chip_addr_magic_value == p->chip_addr;
2162 static bool is_last(const struct dsp_image_seg *p)
2164 return p->count == 0;
2167 static size_t dsp_sizeof(const struct dsp_image_seg *p)
2169 return sizeof(*p) + p->count*sizeof(u32);
2172 static const struct dsp_image_seg *get_next_seg_ptr(
2173 const struct dsp_image_seg *p)
2175 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
2179 * CA0132 chip DSP transfer stuffs. For DSP download.
2181 #define INVALID_DMA_CHANNEL (~0U)
2184 * Program a list of address/data pairs via the ChipIO widget.
2185 * The segment data is in the format of successive pairs of words.
2186 * These are repeated as indicated by the segment's count field.
2188 static int dspxfr_hci_write(struct hda_codec *codec,
2189 const struct dsp_image_seg *fls)
2195 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
2196 codec_dbg(codec, "hci_write invalid params\n");
2201 data = (u32 *)(fls->data);
2202 while (count >= 2) {
2203 status = chipio_write(codec, data[0], data[1]);
2205 codec_dbg(codec, "hci_write chipio failed\n");
2215 * Write a block of data into DSP code or data RAM using pre-allocated
2218 * @codec: the HDA codec
2219 * @fls: pointer to a fast load image
2220 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2222 * @dma_engine: pointer to DMA engine to be used for DSP download
2223 * @dma_chan: The number of DMA channels used for DSP download
2224 * @port_map_mask: port mapping
2225 * @ovly: TRUE if overlay format is required
2227 * Returns zero or a negative error code.
2229 static int dspxfr_one_seg(struct hda_codec *codec,
2230 const struct dsp_image_seg *fls,
2232 struct dma_engine *dma_engine,
2233 unsigned int dma_chan,
2234 unsigned int port_map_mask,
2238 bool comm_dma_setup_done = false;
2239 const unsigned int *data;
2240 unsigned int chip_addx;
2241 unsigned int words_to_write;
2242 unsigned int buffer_size_words;
2243 unsigned char *buffer_addx;
2244 unsigned short hda_format;
2245 unsigned int sample_rate_div;
2246 unsigned int sample_rate_mul;
2247 unsigned int num_chans;
2248 unsigned int hda_frame_size_words;
2249 unsigned int remainder_words;
2250 const u32 *data_remainder;
2251 u32 chip_addx_remainder;
2252 unsigned int run_size_words;
2253 const struct dsp_image_seg *hci_write = NULL;
2254 unsigned long timeout;
2259 if (is_hci_prog_list_seg(fls)) {
2261 fls = get_next_seg_ptr(fls);
2264 if (hci_write && (!fls || is_last(fls))) {
2265 codec_dbg(codec, "hci_write\n");
2266 return dspxfr_hci_write(codec, hci_write);
2269 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
2270 codec_dbg(codec, "Invalid Params\n");
2275 chip_addx = fls->chip_addr,
2276 words_to_write = fls->count;
2278 if (!words_to_write)
2279 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
2281 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
2283 if (!UC_RANGE(chip_addx, words_to_write) &&
2284 !X_RANGE_ALL(chip_addx, words_to_write) &&
2285 !Y_RANGE_ALL(chip_addx, words_to_write)) {
2286 codec_dbg(codec, "Invalid chip_addx Params\n");
2290 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
2293 buffer_addx = dma_get_buffer_addr(dma_engine);
2295 if (buffer_addx == NULL) {
2296 codec_dbg(codec, "dma_engine buffer NULL\n");
2300 dma_get_converter_format(dma_engine, &hda_format);
2301 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
2302 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
2303 num_chans = get_hdafmt_chs(hda_format) + 1;
2305 hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
2306 (num_chans * sample_rate_mul / sample_rate_div));
2308 if (hda_frame_size_words == 0) {
2309 codec_dbg(codec, "frmsz zero\n");
2313 buffer_size_words = min(buffer_size_words,
2314 (unsigned int)(UC_RANGE(chip_addx, 1) ?
2316 buffer_size_words -= buffer_size_words % hda_frame_size_words;
2318 "chpadr=0x%08x frmsz=%u nchan=%u "
2319 "rate_mul=%u div=%u bufsz=%u\n",
2320 chip_addx, hda_frame_size_words, num_chans,
2321 sample_rate_mul, sample_rate_div, buffer_size_words);
2323 if (buffer_size_words < hda_frame_size_words) {
2324 codec_dbg(codec, "dspxfr_one_seg:failed\n");
2328 remainder_words = words_to_write % hda_frame_size_words;
2329 data_remainder = data;
2330 chip_addx_remainder = chip_addx;
2332 data += remainder_words;
2333 chip_addx += remainder_words*sizeof(u32);
2334 words_to_write -= remainder_words;
2336 while (words_to_write != 0) {
2337 run_size_words = min(buffer_size_words, words_to_write);
2338 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
2339 words_to_write, run_size_words, remainder_words);
2340 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
2341 if (!comm_dma_setup_done) {
2342 status = dsp_dma_stop(codec, dma_chan, ovly);
2345 status = dsp_dma_setup_common(codec, chip_addx,
2346 dma_chan, port_map_mask, ovly);
2349 comm_dma_setup_done = true;
2352 status = dsp_dma_setup(codec, chip_addx,
2353 run_size_words, dma_chan);
2356 status = dsp_dma_start(codec, dma_chan, ovly);
2359 if (!dsp_is_dma_active(codec, dma_chan)) {
2360 codec_dbg(codec, "dspxfr:DMA did not start\n");
2363 status = dma_set_state(dma_engine, DMA_STATE_RUN);
2366 if (remainder_words != 0) {
2367 status = chipio_write_multiple(codec,
2368 chip_addx_remainder,
2373 remainder_words = 0;
2376 status = dspxfr_hci_write(codec, hci_write);
2382 timeout = jiffies + msecs_to_jiffies(2000);
2384 dma_active = dsp_is_dma_active(codec, dma_chan);
2388 } while (time_before(jiffies, timeout));
2392 codec_dbg(codec, "+++++ DMA complete\n");
2393 dma_set_state(dma_engine, DMA_STATE_STOP);
2394 status = dma_reset(dma_engine);
2399 data += run_size_words;
2400 chip_addx += run_size_words*sizeof(u32);
2401 words_to_write -= run_size_words;
2404 if (remainder_words != 0) {
2405 status = chipio_write_multiple(codec, chip_addx_remainder,
2406 data_remainder, remainder_words);
2413 * Write the entire DSP image of a DSP code/data overlay to DSP memories
2415 * @codec: the HDA codec
2416 * @fls_data: pointer to a fast load image
2417 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2419 * @sample_rate: sampling rate of the stream used for DSP download
2420 * @number_channels: channels of the stream used for DSP download
2421 * @ovly: TRUE if overlay format is required
2423 * Returns zero or a negative error code.
2425 static int dspxfr_image(struct hda_codec *codec,
2426 const struct dsp_image_seg *fls_data,
2428 unsigned int sample_rate,
2429 unsigned short channels,
2432 struct ca0132_spec *spec = codec->spec;
2434 unsigned short hda_format = 0;
2435 unsigned int response;
2436 unsigned char stream_id = 0;
2437 struct dma_engine *dma_engine;
2438 unsigned int dma_chan;
2439 unsigned int port_map_mask;
2441 if (fls_data == NULL)
2444 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
2448 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
2449 if (!dma_engine->dmab) {
2454 dma_engine->codec = codec;
2455 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format);
2456 dma_engine->m_converter_format = hda_format;
2457 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
2458 DSP_DMA_WRITE_BUFLEN_INIT) * 2;
2460 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
2462 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
2463 hda_format, &response);
2466 codec_dbg(codec, "set converter format fail\n");
2470 status = snd_hda_codec_load_dsp_prepare(codec,
2471 dma_engine->m_converter_format,
2472 dma_engine->buf_size,
2476 spec->dsp_stream_id = status;
2479 status = dspio_alloc_dma_chan(codec, &dma_chan);
2481 codec_dbg(codec, "alloc dmachan fail\n");
2482 dma_chan = INVALID_DMA_CHANNEL;
2488 status = dsp_allocate_ports_format(codec, hda_format,
2491 codec_dbg(codec, "alloc ports fail\n");
2495 stream_id = dma_get_stream_id(dma_engine);
2496 status = codec_set_converter_stream_channel(codec,
2497 WIDGET_CHIP_CTRL, stream_id, 0, &response);
2499 codec_dbg(codec, "set stream chan fail\n");
2503 while ((fls_data != NULL) && !is_last(fls_data)) {
2504 if (!is_valid(fls_data)) {
2505 codec_dbg(codec, "FLS check fail\n");
2509 status = dspxfr_one_seg(codec, fls_data, reloc,
2510 dma_engine, dma_chan,
2511 port_map_mask, ovly);
2515 if (is_hci_prog_list_seg(fls_data))
2516 fls_data = get_next_seg_ptr(fls_data);
2518 if ((fls_data != NULL) && !is_last(fls_data))
2519 fls_data = get_next_seg_ptr(fls_data);
2522 if (port_map_mask != 0)
2523 status = dsp_free_ports(codec);
2528 status = codec_set_converter_stream_channel(codec,
2529 WIDGET_CHIP_CTRL, 0, 0, &response);
2532 if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
2533 dspio_free_dma_chan(codec, dma_chan);
2535 if (dma_engine->dmab->area)
2536 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
2537 kfree(dma_engine->dmab);
2544 * CA0132 DSP download stuffs.
2546 static void dspload_post_setup(struct hda_codec *codec)
2548 codec_dbg(codec, "---- dspload_post_setup ------\n");
2550 /*set DSP speaker to 2.0 configuration*/
2551 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
2552 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
2554 /*update write pointer*/
2555 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
2559 * Download DSP from a DSP Image Fast Load structure. This structure is a
2560 * linear, non-constant sized element array of structures, each of which
2561 * contain the count of the data to be loaded, the data itself, and the
2562 * corresponding starting chip address of the starting data location.
2564 * @codec: the HDA codec
2565 * @fls: pointer to a fast load image
2566 * @ovly: TRUE if overlay format is required
2567 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2569 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
2570 * @router_chans: number of audio router channels to be allocated (0 means use
2571 * internal defaults; max is 32)
2573 * Returns zero or a negative error code.
2575 static int dspload_image(struct hda_codec *codec,
2576 const struct dsp_image_seg *fls,
2583 unsigned int sample_rate;
2584 unsigned short channels;
2586 codec_dbg(codec, "---- dspload_image begin ------\n");
2587 if (router_chans == 0) {
2589 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
2591 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
2594 sample_rate = 48000;
2595 channels = (unsigned short)router_chans;
2597 while (channels > 16) {
2603 codec_dbg(codec, "Ready to program DMA\n");
2605 status = dsp_reset(codec);
2610 codec_dbg(codec, "dsp_reset() complete\n");
2611 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
2617 codec_dbg(codec, "dspxfr_image() complete\n");
2618 if (autostart && !ovly) {
2619 dspload_post_setup(codec);
2620 status = dsp_set_run_state(codec);
2623 codec_dbg(codec, "LOAD FINISHED\n");
2629 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
2630 static bool dspload_is_loaded(struct hda_codec *codec)
2632 unsigned int data = 0;
2635 status = chipio_read(codec, 0x40004, &data);
2636 if ((status < 0) || (data != 1))
2642 #define dspload_is_loaded(codec) false
2645 static bool dspload_wait_loaded(struct hda_codec *codec)
2647 unsigned long timeout = jiffies + msecs_to_jiffies(2000);
2650 if (dspload_is_loaded(codec)) {
2651 pr_info("ca0132 DOWNLOAD OK :-) DSP IS RUNNING.\n");
2655 } while (time_before(jiffies, timeout));
2657 pr_err("ca0132 DOWNLOAD FAILED!!! DSP IS NOT RUNNING.\n");
2664 static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2665 struct hda_codec *codec,
2666 unsigned int stream_tag,
2667 unsigned int format,
2668 struct snd_pcm_substream *substream)
2670 struct ca0132_spec *spec = codec->spec;
2672 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
2677 static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
2678 struct hda_codec *codec,
2679 struct snd_pcm_substream *substream)
2681 struct ca0132_spec *spec = codec->spec;
2683 if (spec->dsp_state == DSP_DOWNLOADING)
2686 /*If Playback effects are on, allow stream some time to flush
2688 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
2691 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
2696 static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info,
2697 struct hda_codec *codec,
2698 struct snd_pcm_substream *substream)
2700 struct ca0132_spec *spec = codec->spec;
2701 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
2702 struct snd_pcm_runtime *runtime = substream->runtime;
2704 if (spec->dsp_state != DSP_DOWNLOADED)
2707 /* Add latency if playback enhancement and either effect is enabled. */
2708 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
2709 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
2710 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
2711 latency += DSP_PLAY_ENHANCEMENT_LATENCY;
2714 /* Applying Speaker EQ adds latency as well. */
2715 if (spec->cur_out_type == SPEAKER_OUT)
2716 latency += DSP_SPEAKER_OUT_LATENCY;
2718 return (latency * runtime->rate) / 1000;
2724 static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
2725 struct hda_codec *codec,
2726 struct snd_pcm_substream *substream)
2728 struct ca0132_spec *spec = codec->spec;
2729 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2732 static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2733 struct hda_codec *codec,
2734 unsigned int stream_tag,
2735 unsigned int format,
2736 struct snd_pcm_substream *substream)
2738 struct ca0132_spec *spec = codec->spec;
2739 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2740 stream_tag, format, substream);
2743 static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
2744 struct hda_codec *codec,
2745 struct snd_pcm_substream *substream)
2747 struct ca0132_spec *spec = codec->spec;
2748 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
2751 static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
2752 struct hda_codec *codec,
2753 struct snd_pcm_substream *substream)
2755 struct ca0132_spec *spec = codec->spec;
2756 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2762 static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
2763 struct hda_codec *codec,
2764 unsigned int stream_tag,
2765 unsigned int format,
2766 struct snd_pcm_substream *substream)
2768 snd_hda_codec_setup_stream(codec, hinfo->nid,
2769 stream_tag, 0, format);
2774 static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
2775 struct hda_codec *codec,
2776 struct snd_pcm_substream *substream)
2778 struct ca0132_spec *spec = codec->spec;
2780 if (spec->dsp_state == DSP_DOWNLOADING)
2783 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
2787 static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info,
2788 struct hda_codec *codec,
2789 struct snd_pcm_substream *substream)
2791 struct ca0132_spec *spec = codec->spec;
2792 unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
2793 struct snd_pcm_runtime *runtime = substream->runtime;
2795 if (spec->dsp_state != DSP_DOWNLOADED)
2798 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
2799 latency += DSP_CRYSTAL_VOICE_LATENCY;
2801 return (latency * runtime->rate) / 1000;
2809 * Mixer controls helpers.
2811 #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
2812 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2814 .subdevice = HDA_SUBDEV_AMP_FLAG, \
2815 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2816 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
2817 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
2818 .info = ca0132_volume_info, \
2819 .get = ca0132_volume_get, \
2820 .put = ca0132_volume_put, \
2821 .tlv = { .c = ca0132_volume_tlv }, \
2822 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
2824 #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
2825 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2827 .subdevice = HDA_SUBDEV_AMP_FLAG, \
2828 .info = snd_hda_mixer_amp_switch_info, \
2829 .get = ca0132_switch_get, \
2830 .put = ca0132_switch_put, \
2831 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
2834 #define CA0132_CODEC_VOL(xname, nid, dir) \
2835 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
2836 #define CA0132_CODEC_MUTE(xname, nid, dir) \
2837 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
2839 /* The followings are for tuning of products */
2840 #ifdef ENABLE_TUNING_CONTROLS
2842 static unsigned int voice_focus_vals_lookup[] = {
2843 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
2844 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
2845 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
2846 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
2847 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
2848 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
2849 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
2850 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
2851 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
2852 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
2853 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
2854 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
2855 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
2856 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
2857 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
2858 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
2859 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
2860 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
2861 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
2862 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
2863 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
2864 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
2865 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
2866 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
2867 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
2868 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
2869 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
2872 static unsigned int mic_svm_vals_lookup[] = {
2873 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
2874 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
2875 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
2876 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
2877 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
2878 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
2879 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
2880 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
2881 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
2882 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
2883 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
2884 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
2885 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
2886 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
2887 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
2888 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
2889 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
2892 static unsigned int equalizer_vals_lookup[] = {
2893 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
2894 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
2895 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
2896 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
2897 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
2898 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
2899 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
2900 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
2904 static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
2905 unsigned int *lookup, int idx)
2909 for (i = 0; i < TUNING_CTLS_COUNT; i++)
2910 if (nid == ca0132_tuning_ctls[i].nid)
2913 snd_hda_power_up(codec);
2914 dspio_set_param(codec, ca0132_tuning_ctls[i].mid,
2915 ca0132_tuning_ctls[i].req,
2916 &(lookup[idx]), sizeof(unsigned int));
2917 snd_hda_power_down(codec);
2922 static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
2923 struct snd_ctl_elem_value *ucontrol)
2925 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2926 struct ca0132_spec *spec = codec->spec;
2927 hda_nid_t nid = get_amp_nid(kcontrol);
2928 long *valp = ucontrol->value.integer.value;
2929 int idx = nid - TUNING_CTL_START_NID;
2931 *valp = spec->cur_ctl_vals[idx];
2935 static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
2936 struct snd_ctl_elem_info *uinfo)
2938 int chs = get_amp_channels(kcontrol);
2939 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2940 uinfo->count = chs == 3 ? 2 : 1;
2941 uinfo->value.integer.min = 20;
2942 uinfo->value.integer.max = 180;
2943 uinfo->value.integer.step = 1;
2948 static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
2949 struct snd_ctl_elem_value *ucontrol)
2951 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2952 struct ca0132_spec *spec = codec->spec;
2953 hda_nid_t nid = get_amp_nid(kcontrol);
2954 long *valp = ucontrol->value.integer.value;
2957 idx = nid - TUNING_CTL_START_NID;
2959 if (spec->cur_ctl_vals[idx] == *valp)
2962 spec->cur_ctl_vals[idx] = *valp;
2965 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
2970 static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
2971 struct snd_ctl_elem_info *uinfo)
2973 int chs = get_amp_channels(kcontrol);
2974 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2975 uinfo->count = chs == 3 ? 2 : 1;
2976 uinfo->value.integer.min = 0;
2977 uinfo->value.integer.max = 100;
2978 uinfo->value.integer.step = 1;
2983 static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
2984 struct snd_ctl_elem_value *ucontrol)
2986 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2987 struct ca0132_spec *spec = codec->spec;
2988 hda_nid_t nid = get_amp_nid(kcontrol);
2989 long *valp = ucontrol->value.integer.value;
2992 idx = nid - TUNING_CTL_START_NID;
2994 if (spec->cur_ctl_vals[idx] == *valp)
2997 spec->cur_ctl_vals[idx] = *valp;
3000 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
3005 static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
3006 struct snd_ctl_elem_info *uinfo)
3008 int chs = get_amp_channels(kcontrol);
3009 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3010 uinfo->count = chs == 3 ? 2 : 1;
3011 uinfo->value.integer.min = 0;
3012 uinfo->value.integer.max = 48;
3013 uinfo->value.integer.step = 1;
3018 static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
3019 struct snd_ctl_elem_value *ucontrol)
3021 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3022 struct ca0132_spec *spec = codec->spec;
3023 hda_nid_t nid = get_amp_nid(kcontrol);
3024 long *valp = ucontrol->value.integer.value;
3027 idx = nid - TUNING_CTL_START_NID;
3029 if (spec->cur_ctl_vals[idx] == *valp)
3032 spec->cur_ctl_vals[idx] = *valp;
3035 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
3040 static const DECLARE_TLV_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
3041 static const DECLARE_TLV_DB_SCALE(eq_db_scale, -2400, 100, 0);
3043 static int add_tuning_control(struct hda_codec *codec,
3044 hda_nid_t pnid, hda_nid_t nid,
3045 const char *name, int dir)
3047 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
3048 int type = dir ? HDA_INPUT : HDA_OUTPUT;
3049 struct snd_kcontrol_new knew =
3050 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
3052 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
3053 SNDRV_CTL_ELEM_ACCESS_TLV_READ;
3058 knew.info = voice_focus_ctl_info;
3059 knew.get = tuning_ctl_get;
3060 knew.put = voice_focus_ctl_put;
3061 knew.tlv.p = voice_focus_db_scale;
3064 knew.info = mic_svm_ctl_info;
3065 knew.get = tuning_ctl_get;
3066 knew.put = mic_svm_ctl_put;
3069 knew.info = equalizer_ctl_info;
3070 knew.get = tuning_ctl_get;
3071 knew.put = equalizer_ctl_put;
3072 knew.tlv.p = eq_db_scale;
3077 knew.private_value =
3078 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
3079 sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
3080 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3083 static int add_tuning_ctls(struct hda_codec *codec)
3088 for (i = 0; i < TUNING_CTLS_COUNT; i++) {
3089 err = add_tuning_control(codec,
3090 ca0132_tuning_ctls[i].parent_nid,
3091 ca0132_tuning_ctls[i].nid,
3092 ca0132_tuning_ctls[i].name,
3093 ca0132_tuning_ctls[i].direct);
3101 static void ca0132_init_tuning_defaults(struct hda_codec *codec)
3103 struct ca0132_spec *spec = codec->spec;
3106 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */
3107 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
3108 /* SVM level defaults to 0.74. */
3109 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
3111 /* EQ defaults to 0dB. */
3112 for (i = 2; i < TUNING_CTLS_COUNT; i++)
3113 spec->cur_ctl_vals[i] = 24;
3115 #endif /*ENABLE_TUNING_CONTROLS*/
3118 * Select the active output.
3119 * If autodetect is enabled, output will be selected based on jack detection.
3120 * If jack inserted, headphone will be selected, else built-in speakers
3121 * If autodetect is disabled, output will be selected based on selection.
3123 static int ca0132_select_out(struct hda_codec *codec)
3125 struct ca0132_spec *spec = codec->spec;
3126 unsigned int pin_ctl;
3132 codec_dbg(codec, "ca0132_select_out\n");
3134 snd_hda_power_up(codec);
3136 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3139 jack_present = snd_hda_jack_detect(codec, spec->out_pins[1]);
3142 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
3145 spec->cur_out_type = HEADPHONE_OUT;
3147 spec->cur_out_type = SPEAKER_OUT;
3149 if (spec->cur_out_type == SPEAKER_OUT) {
3150 codec_dbg(codec, "ca0132_select_out speaker\n");
3151 /*speaker out config*/
3153 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3156 /*enable speaker EQ*/
3158 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3163 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3164 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3165 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3166 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3167 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3168 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3169 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3170 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3172 /* disable headphone node */
3173 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3174 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3175 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3177 /* enable speaker node */
3178 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3179 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3180 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3183 codec_dbg(codec, "ca0132_select_out hp\n");
3184 /*headphone out config*/
3186 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3189 /*disable speaker EQ*/
3191 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3196 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3197 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3198 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3199 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3200 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3201 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3202 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3203 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3205 /* disable speaker*/
3206 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3207 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3208 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3210 /* enable headphone*/
3211 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3212 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3213 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3218 snd_hda_power_down(codec);
3220 return err < 0 ? err : 0;
3223 static void ca0132_unsol_hp_delayed(struct work_struct *work)
3225 struct ca0132_spec *spec = container_of(
3226 to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
3227 ca0132_select_out(spec->codec);
3228 snd_hda_jack_report_sync(spec->codec);
3231 static void ca0132_set_dmic(struct hda_codec *codec, int enable);
3232 static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
3233 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
3236 * Select the active VIP source
3238 static int ca0132_set_vipsource(struct hda_codec *codec, int val)
3240 struct ca0132_spec *spec = codec->spec;
3243 if (spec->dsp_state != DSP_DOWNLOADED)
3246 /* if CrystalVoice if off, vipsource should be 0 */
3247 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
3249 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
3250 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
3251 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
3252 if (spec->cur_mic_type == DIGITAL_MIC)
3256 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
3258 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
3260 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
3261 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
3262 if (spec->cur_mic_type == DIGITAL_MIC)
3266 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
3268 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
3270 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
3277 * Select the active microphone.
3278 * If autodetect is enabled, mic will be selected based on jack detection.
3279 * If jack inserted, ext.mic will be selected, else built-in mic
3280 * If autodetect is disabled, mic will be selected based on selection.
3282 static int ca0132_select_mic(struct hda_codec *codec)
3284 struct ca0132_spec *spec = codec->spec;
3288 codec_dbg(codec, "ca0132_select_mic\n");
3290 snd_hda_power_up(codec);
3292 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
3295 jack_present = snd_hda_jack_detect(codec, spec->input_pins[0]);
3298 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
3301 spec->cur_mic_type = LINE_MIC_IN;
3303 spec->cur_mic_type = DIGITAL_MIC;
3305 if (spec->cur_mic_type == DIGITAL_MIC) {
3306 /* enable digital Mic */
3307 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
3308 ca0132_set_dmic(codec, 1);
3309 ca0132_mic_boost_set(codec, 0);
3310 /* set voice focus */
3311 ca0132_effects_set(codec, VOICE_FOCUS,
3312 spec->effects_switch
3313 [VOICE_FOCUS - EFFECT_START_NID]);
3315 /* disable digital Mic */
3316 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
3317 ca0132_set_dmic(codec, 0);
3318 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
3319 /* disable voice focus */
3320 ca0132_effects_set(codec, VOICE_FOCUS, 0);
3323 snd_hda_power_down(codec);
3329 * Check if VNODE settings take effect immediately.
3331 static bool ca0132_is_vnode_effective(struct hda_codec *codec,
3333 hda_nid_t *shared_nid)
3335 struct ca0132_spec *spec = codec->spec;
3340 nid = spec->shared_out_nid;
3343 nid = spec->shared_mic_nid;
3356 * The following functions are control change helpers.
3357 * They return 0 if no changed. Return 1 if changed.
3359 static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
3361 struct ca0132_spec *spec = codec->spec;
3364 /* based on CrystalVoice state to enable VoiceFX. */
3366 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
3367 FLOAT_ONE : FLOAT_ZERO;
3372 dspio_set_uint_param(codec, ca0132_voicefx.mid,
3373 ca0132_voicefx.reqs[0], tmp);
3379 * Set the effects parameters
3381 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
3383 struct ca0132_spec *spec = codec->spec;
3385 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
3387 int idx = nid - EFFECT_START_NID;
3389 if ((idx < 0) || (idx >= num_fx))
3390 return 0; /* no changed */
3392 /* for out effect, qualify with PE */
3393 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
3394 /* if PE if off, turn off out effects. */
3395 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3399 /* for in effect, qualify with CrystalVoice */
3400 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
3401 /* if CrystalVoice if off, turn off in effects. */
3402 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
3405 /* Voice Focus applies to 2-ch Mic, Digital Mic */
3406 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
3410 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n",
3413 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
3414 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
3415 ca0132_effects[idx].reqs[0], on);
3418 return 0; /* no changed */
3424 * Turn on/off Playback Enhancements
3426 static int ca0132_pe_switch_set(struct hda_codec *codec)
3428 struct ca0132_spec *spec = codec->spec;
3432 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n",
3433 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
3435 i = OUT_EFFECT_START_NID - EFFECT_START_NID;
3436 nid = OUT_EFFECT_START_NID;
3437 /* PE affects all out effects */
3438 for (; nid < OUT_EFFECT_END_NID; nid++, i++)
3439 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
3444 /* Check if Mic1 is streaming, if so, stop streaming */
3445 static int stop_mic1(struct hda_codec *codec)
3447 struct ca0132_spec *spec = codec->spec;
3448 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
3449 AC_VERB_GET_CONV, 0);
3451 snd_hda_codec_write(codec, spec->adcs[0], 0,
3452 AC_VERB_SET_CHANNEL_STREAMID,
3457 /* Resume Mic1 streaming if it was stopped. */
3458 static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
3460 struct ca0132_spec *spec = codec->spec;
3461 /* Restore the previous stream and channel */
3463 snd_hda_codec_write(codec, spec->adcs[0], 0,
3464 AC_VERB_SET_CHANNEL_STREAMID,
3469 * Turn on/off CrystalVoice
3471 static int ca0132_cvoice_switch_set(struct hda_codec *codec)
3473 struct ca0132_spec *spec = codec->spec;
3476 unsigned int oldval;
3478 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n",
3479 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
3481 i = IN_EFFECT_START_NID - EFFECT_START_NID;
3482 nid = IN_EFFECT_START_NID;
3483 /* CrystalVoice affects all in effects */
3484 for (; nid < IN_EFFECT_END_NID; nid++, i++)
3485 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
3487 /* including VoiceFX */
3488 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
3490 /* set correct vipsource */
3491 oldval = stop_mic1(codec);
3492 ret |= ca0132_set_vipsource(codec, 1);
3493 resume_mic1(codec, oldval);
3497 static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
3499 struct ca0132_spec *spec = codec->spec;
3503 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
3504 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
3506 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
3507 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
3512 static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
3513 struct snd_ctl_elem_value *ucontrol)
3515 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3516 hda_nid_t nid = get_amp_nid(kcontrol);
3517 hda_nid_t shared_nid = 0;
3520 struct ca0132_spec *spec = codec->spec;
3523 if (nid == VNID_HP_SEL) {
3525 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3527 ca0132_select_out(codec);
3531 if (nid == VNID_AMIC1_SEL) {
3533 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
3535 ca0132_select_mic(codec);
3539 if (nid == VNID_HP_ASEL) {
3540 ca0132_select_out(codec);
3544 if (nid == VNID_AMIC1_ASEL) {
3545 ca0132_select_mic(codec);
3549 /* if effective conditions, then update hw immediately. */
3550 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
3552 int dir = get_amp_direction(kcontrol);
3553 int ch = get_amp_channels(kcontrol);
3556 mutex_lock(&codec->control_mutex);
3557 pval = kcontrol->private_value;
3558 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
3560 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
3561 kcontrol->private_value = pval;
3562 mutex_unlock(&codec->control_mutex);
3567 /* End of control change helpers. */
3569 static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
3570 struct snd_ctl_elem_info *uinfo)
3572 unsigned int items = sizeof(ca0132_voicefx_presets)
3573 / sizeof(struct ct_voicefx_preset);
3575 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3577 uinfo->value.enumerated.items = items;
3578 if (uinfo->value.enumerated.item >= items)
3579 uinfo->value.enumerated.item = items - 1;
3580 strcpy(uinfo->value.enumerated.name,
3581 ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
3585 static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
3586 struct snd_ctl_elem_value *ucontrol)
3588 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3589 struct ca0132_spec *spec = codec->spec;
3591 ucontrol->value.enumerated.item[0] = spec->voicefx_val;
3595 static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
3596 struct snd_ctl_elem_value *ucontrol)
3598 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3599 struct ca0132_spec *spec = codec->spec;
3601 int sel = ucontrol->value.enumerated.item[0];
3602 unsigned int items = sizeof(ca0132_voicefx_presets)
3603 / sizeof(struct ct_voicefx_preset);
3608 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n",
3609 sel, ca0132_voicefx_presets[sel].name);
3613 * Default needs to qualify with CrystalVoice state.
3615 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
3616 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
3617 ca0132_voicefx.reqs[i],
3618 ca0132_voicefx_presets[sel].vals[i]);
3624 spec->voicefx_val = sel;
3625 /* enable voice fx */
3626 ca0132_voicefx_set(codec, (sel ? 1 : 0));
3632 static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
3633 struct snd_ctl_elem_value *ucontrol)
3635 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3636 struct ca0132_spec *spec = codec->spec;
3637 hda_nid_t nid = get_amp_nid(kcontrol);
3638 int ch = get_amp_channels(kcontrol);
3639 long *valp = ucontrol->value.integer.value;
3642 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
3644 *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
3648 *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
3654 /* effects, include PE and CrystalVoice */
3655 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
3656 *valp = spec->effects_switch[nid - EFFECT_START_NID];
3661 if (nid == spec->input_pins[0]) {
3662 *valp = spec->cur_mic_boost;
3669 static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
3670 struct snd_ctl_elem_value *ucontrol)
3672 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3673 struct ca0132_spec *spec = codec->spec;
3674 hda_nid_t nid = get_amp_nid(kcontrol);
3675 int ch = get_amp_channels(kcontrol);
3676 long *valp = ucontrol->value.integer.value;
3679 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n",
3682 snd_hda_power_up(codec);
3684 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
3686 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
3690 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
3693 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
3698 if (nid == PLAY_ENHANCEMENT) {
3699 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3700 changed = ca0132_pe_switch_set(codec);
3705 if (nid == CRYSTAL_VOICE) {
3706 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3707 changed = ca0132_cvoice_switch_set(codec);
3711 /* out and in effects */
3712 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
3713 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
3714 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3715 changed = ca0132_effects_set(codec, nid, *valp);
3720 if (nid == spec->input_pins[0]) {
3721 spec->cur_mic_boost = *valp;
3723 /* Mic boost does not apply to Digital Mic */
3724 if (spec->cur_mic_type != DIGITAL_MIC)
3725 changed = ca0132_mic_boost_set(codec, *valp);
3730 snd_hda_power_down(codec);
3737 static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
3738 struct snd_ctl_elem_info *uinfo)
3740 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3741 struct ca0132_spec *spec = codec->spec;
3742 hda_nid_t nid = get_amp_nid(kcontrol);
3743 int ch = get_amp_channels(kcontrol);
3744 int dir = get_amp_direction(kcontrol);
3750 /* follow shared_out info */
3751 nid = spec->shared_out_nid;
3752 mutex_lock(&codec->control_mutex);
3753 pval = kcontrol->private_value;
3754 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3755 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3756 kcontrol->private_value = pval;
3757 mutex_unlock(&codec->control_mutex);
3760 /* follow shared_mic info */
3761 nid = spec->shared_mic_nid;
3762 mutex_lock(&codec->control_mutex);
3763 pval = kcontrol->private_value;
3764 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3765 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3766 kcontrol->private_value = pval;
3767 mutex_unlock(&codec->control_mutex);
3770 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3775 static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
3776 struct snd_ctl_elem_value *ucontrol)
3778 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3779 struct ca0132_spec *spec = codec->spec;
3780 hda_nid_t nid = get_amp_nid(kcontrol);
3781 int ch = get_amp_channels(kcontrol);
3782 long *valp = ucontrol->value.integer.value;
3784 /* store the left and right volume */
3786 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
3790 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
3796 static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
3797 struct snd_ctl_elem_value *ucontrol)
3799 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3800 struct ca0132_spec *spec = codec->spec;
3801 hda_nid_t nid = get_amp_nid(kcontrol);
3802 int ch = get_amp_channels(kcontrol);
3803 long *valp = ucontrol->value.integer.value;
3804 hda_nid_t shared_nid = 0;
3808 /* store the left and right volume */
3810 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
3814 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
3818 /* if effective conditions, then update hw immediately. */
3819 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
3821 int dir = get_amp_direction(kcontrol);
3824 snd_hda_power_up(codec);
3825 mutex_lock(&codec->control_mutex);
3826 pval = kcontrol->private_value;
3827 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
3829 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
3830 kcontrol->private_value = pval;
3831 mutex_unlock(&codec->control_mutex);
3832 snd_hda_power_down(codec);
3838 static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
3839 unsigned int size, unsigned int __user *tlv)
3841 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3842 struct ca0132_spec *spec = codec->spec;
3843 hda_nid_t nid = get_amp_nid(kcontrol);
3844 int ch = get_amp_channels(kcontrol);
3845 int dir = get_amp_direction(kcontrol);
3851 /* follow shared_out tlv */
3852 nid = spec->shared_out_nid;
3853 mutex_lock(&codec->control_mutex);
3854 pval = kcontrol->private_value;
3855 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3856 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3857 kcontrol->private_value = pval;
3858 mutex_unlock(&codec->control_mutex);
3861 /* follow shared_mic tlv */
3862 nid = spec->shared_mic_nid;
3863 mutex_lock(&codec->control_mutex);
3864 pval = kcontrol->private_value;
3865 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3866 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3867 kcontrol->private_value = pval;
3868 mutex_unlock(&codec->control_mutex);
3871 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3876 static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
3877 const char *pfx, int dir)
3879 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
3880 int type = dir ? HDA_INPUT : HDA_OUTPUT;
3881 struct snd_kcontrol_new knew =
3882 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
3883 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
3884 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3887 static int add_voicefx(struct hda_codec *codec)
3889 struct snd_kcontrol_new knew =
3890 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
3891 VOICEFX, 1, 0, HDA_INPUT);
3892 knew.info = ca0132_voicefx_info;
3893 knew.get = ca0132_voicefx_get;
3894 knew.put = ca0132_voicefx_put;
3895 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
3899 * When changing Node IDs for Mixer Controls below, make sure to update
3900 * Node IDs in ca0132_config() as well.
3902 static struct snd_kcontrol_new ca0132_mixer[] = {
3903 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
3904 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
3905 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
3906 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
3907 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
3908 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
3909 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
3910 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
3911 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
3912 0x12, 1, HDA_INPUT),
3913 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
3914 VNID_HP_SEL, 1, HDA_OUTPUT),
3915 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
3916 VNID_AMIC1_SEL, 1, HDA_INPUT),
3917 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
3918 VNID_HP_ASEL, 1, HDA_OUTPUT),
3919 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
3920 VNID_AMIC1_ASEL, 1, HDA_INPUT),
3924 static int ca0132_build_controls(struct hda_codec *codec)
3926 struct ca0132_spec *spec = codec->spec;
3930 /* Add Mixer controls */
3931 for (i = 0; i < spec->num_mixers; i++) {
3932 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
3937 /* Add in and out effects controls.
3938 * VoiceFX, PE and CrystalVoice are added separately.
3940 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
3941 for (i = 0; i < num_fx; i++) {
3942 err = add_fx_switch(codec, ca0132_effects[i].nid,
3943 ca0132_effects[i].name,
3944 ca0132_effects[i].direct);
3949 err = add_fx_switch(codec, PLAY_ENHANCEMENT, "PlayEnhancement", 0);
3953 err = add_fx_switch(codec, CRYSTAL_VOICE, "CrystalVoice", 1);
3959 #ifdef ENABLE_TUNING_CONTROLS
3960 add_tuning_ctls(codec);
3963 err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
3967 if (spec->dig_out) {
3968 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
3972 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
3975 /* spec->multiout.share_spdif = 1; */
3979 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
3989 static struct hda_pcm_stream ca0132_pcm_analog_playback = {
3994 .prepare = ca0132_playback_pcm_prepare,
3995 .cleanup = ca0132_playback_pcm_cleanup,
3996 .get_delay = ca0132_playback_pcm_delay,
4000 static struct hda_pcm_stream ca0132_pcm_analog_capture = {
4005 .prepare = ca0132_capture_pcm_prepare,
4006 .cleanup = ca0132_capture_pcm_cleanup,
4007 .get_delay = ca0132_capture_pcm_delay,
4011 static struct hda_pcm_stream ca0132_pcm_digital_playback = {
4016 .open = ca0132_dig_playback_pcm_open,
4017 .close = ca0132_dig_playback_pcm_close,
4018 .prepare = ca0132_dig_playback_pcm_prepare,
4019 .cleanup = ca0132_dig_playback_pcm_cleanup
4023 static struct hda_pcm_stream ca0132_pcm_digital_capture = {
4029 static int ca0132_build_pcms(struct hda_codec *codec)
4031 struct ca0132_spec *spec = codec->spec;
4032 struct hda_pcm *info = spec->pcm_rec;
4034 codec->pcm_info = info;
4035 codec->num_pcms = 0;
4037 info->name = "CA0132 Analog";
4038 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
4039 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
4040 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
4041 spec->multiout.max_channels;
4042 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4043 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4044 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
4048 info->name = "CA0132 Analog Mic-In2";
4049 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4050 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4051 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
4055 info->name = "CA0132 What U Hear";
4056 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4057 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4058 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
4061 if (!spec->dig_out && !spec->dig_in)
4065 info->name = "CA0132 Digital";
4066 info->pcm_type = HDA_PCM_TYPE_SPDIF;
4067 if (spec->dig_out) {
4068 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
4069 ca0132_pcm_digital_playback;
4070 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
4073 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
4074 ca0132_pcm_digital_capture;
4075 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
4082 static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
4085 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
4086 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
4087 snd_hda_codec_write(codec, pin, 0,
4088 AC_VERB_SET_AMP_GAIN_MUTE,
4091 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
4092 snd_hda_codec_write(codec, dac, 0,
4093 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
4096 static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
4099 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
4100 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
4101 snd_hda_codec_write(codec, pin, 0,
4102 AC_VERB_SET_AMP_GAIN_MUTE,
4105 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
4106 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
4109 /* init to 0 dB and unmute. */
4110 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
4111 HDA_AMP_VOLMASK, 0x5a);
4112 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
4117 static void ca0132_init_unsol(struct hda_codec *codec)
4119 snd_hda_jack_detect_enable(codec, UNSOL_TAG_HP, UNSOL_TAG_HP);
4120 snd_hda_jack_detect_enable(codec, UNSOL_TAG_AMIC1, UNSOL_TAG_AMIC1);
4123 static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
4127 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
4128 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
4129 snd_hda_override_amp_caps(codec, nid, dir, caps);
4133 * Switch between Digital built-in mic and analog mic.
4135 static void ca0132_set_dmic(struct hda_codec *codec, int enable)
4137 struct ca0132_spec *spec = codec->spec;
4140 unsigned int oldval;
4142 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable);
4144 oldval = stop_mic1(codec);
4145 ca0132_set_vipsource(codec, 0);
4147 /* set DMic input as 2-ch */
4149 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4151 val = spec->dmic_ctl;
4153 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4154 VENDOR_CHIPIO_DMIC_CTL_SET, val);
4156 if (!(spec->dmic_ctl & 0x20))
4157 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
4159 /* set AMic input as mono */
4161 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4163 val = spec->dmic_ctl;
4164 /* clear bit7 and bit5 to disable dmic */
4166 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4167 VENDOR_CHIPIO_DMIC_CTL_SET, val);
4169 if (!(spec->dmic_ctl & 0x20))
4170 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
4172 ca0132_set_vipsource(codec, 1);
4173 resume_mic1(codec, oldval);
4177 * Initialization for Digital Mic.
4179 static void ca0132_init_dmic(struct hda_codec *codec)
4181 struct ca0132_spec *spec = codec->spec;
4184 /* Setup Digital Mic here, but don't enable.
4185 * Enable based on jack detect.
4188 /* MCLK uses MPIO1, set to enable.
4189 * Bit 2-0: MPIO select
4190 * Bit 3: set to disable
4194 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4195 VENDOR_CHIPIO_DMIC_MCLK_SET, val);
4197 /* Data1 uses MPIO3. Data2 not use
4198 * Bit 2-0: Data1 MPIO select
4199 * Bit 3: set disable Data1
4200 * Bit 6-4: Data2 MPIO select
4201 * Bit 7: set disable Data2
4204 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4205 VENDOR_CHIPIO_DMIC_PIN_SET, val);
4207 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
4208 * Bit 3-0: Channel mask
4209 * Bit 4: set for 48KHz, clear for 32KHz
4211 * Bit 6: set to select Data2, clear for Data1
4212 * Bit 7: set to enable DMic, clear for AMic
4215 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
4216 spec->dmic_ctl = val;
4217 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4218 VENDOR_CHIPIO_DMIC_CTL_SET, val);
4222 * Initialization for Analog Mic 2
4224 static void ca0132_init_analog_mic2(struct hda_codec *codec)
4226 struct ca0132_spec *spec = codec->spec;
4228 mutex_lock(&spec->chipio_mutex);
4229 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4230 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
4231 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4232 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
4233 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4234 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
4235 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4236 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D);
4237 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4238 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
4239 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4240 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
4241 mutex_unlock(&spec->chipio_mutex);
4244 static void ca0132_refresh_widget_caps(struct hda_codec *codec)
4246 struct ca0132_spec *spec = codec->spec;
4250 codec_dbg(codec, "ca0132_refresh_widget_caps.\n");
4251 nid = codec->start_nid;
4252 for (i = 0; i < codec->num_nodes; i++, nid++)
4253 codec->wcaps[i] = snd_hda_param_read(codec, nid,
4254 AC_PAR_AUDIO_WIDGET_CAP);
4256 for (i = 0; i < spec->multiout.num_dacs; i++)
4257 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
4259 for (i = 0; i < spec->num_outputs; i++)
4260 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
4262 for (i = 0; i < spec->num_inputs; i++) {
4263 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
4264 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
4269 * Setup default parameters for DSP
4271 static void ca0132_setup_defaults(struct hda_codec *codec)
4273 struct ca0132_spec *spec = codec->spec;
4278 if (spec->dsp_state != DSP_DOWNLOADED)
4281 /* out, in effects + voicefx */
4282 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
4283 for (idx = 0; idx < num_fx; idx++) {
4284 for (i = 0; i <= ca0132_effects[idx].params; i++) {
4285 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
4286 ca0132_effects[idx].reqs[i],
4287 ca0132_effects[idx].def_vals[i]);
4291 /*remove DSP headroom*/
4293 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
4295 /*set speaker EQ bypass attenuation*/
4296 dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
4298 /* set AMic1 and AMic2 as mono mic */
4300 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4301 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
4303 /* set AMic1 as CrystalVoice input */
4305 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4307 /* set WUH source */
4309 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
4313 * Initialization of flags in chip
4315 static void ca0132_init_flags(struct hda_codec *codec)
4317 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
4318 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
4319 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
4320 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
4321 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
4322 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
4326 * Initialization of parameters in chip
4328 static void ca0132_init_params(struct hda_codec *codec)
4330 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
4331 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
4334 static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
4336 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
4337 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
4338 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
4339 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
4340 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
4341 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
4343 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4344 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4345 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
4348 static bool ca0132_download_dsp_images(struct hda_codec *codec)
4350 bool dsp_loaded = false;
4351 const struct dsp_image_seg *dsp_os_image;
4352 const struct firmware *fw_entry;
4354 if (request_firmware(&fw_entry, EFX_FILE, codec->bus->card->dev) != 0)
4357 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
4358 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
4359 pr_err("ca0132 dspload_image failed.\n");
4363 dsp_loaded = dspload_wait_loaded(codec);
4366 release_firmware(fw_entry);
4371 static void ca0132_download_dsp(struct hda_codec *codec)
4373 struct ca0132_spec *spec = codec->spec;
4375 #ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP
4379 chipio_enable_clocks(codec);
4380 spec->dsp_state = DSP_DOWNLOADING;
4381 if (!ca0132_download_dsp_images(codec))
4382 spec->dsp_state = DSP_DOWNLOAD_FAILED;
4384 spec->dsp_state = DSP_DOWNLOADED;
4386 if (spec->dsp_state == DSP_DOWNLOADED)
4387 ca0132_set_dsp_msr(codec, true);
4390 static void ca0132_process_dsp_response(struct hda_codec *codec)
4392 struct ca0132_spec *spec = codec->spec;
4394 codec_dbg(codec, "ca0132_process_dsp_response\n");
4395 if (spec->wait_scp) {
4396 if (dspio_get_response_data(codec) >= 0)
4400 dspio_clear_response_queue(codec);
4403 static void ca0132_unsol_event(struct hda_codec *codec, unsigned int res)
4405 struct ca0132_spec *spec = codec->spec;
4407 if (((res >> AC_UNSOL_RES_TAG_SHIFT) & 0x3f) == UNSOL_TAG_DSP) {
4408 ca0132_process_dsp_response(codec);
4410 res = snd_hda_jack_get_action(codec,
4411 (res >> AC_UNSOL_RES_TAG_SHIFT) & 0x3f);
4413 codec_dbg(codec, "snd_hda_jack_get_action: 0x%x\n", res);
4417 /* Delay enabling the HP amp, to let the mic-detection
4418 * state machine run.
4420 cancel_delayed_work_sync(&spec->unsol_hp_work);
4421 queue_delayed_work(codec->bus->workq,
4422 &spec->unsol_hp_work,
4423 msecs_to_jiffies(500));
4425 case UNSOL_TAG_AMIC1:
4426 ca0132_select_mic(codec);
4427 snd_hda_jack_report_sync(codec);
4439 /* Sends before DSP download. */
4440 static struct hda_verb ca0132_base_init_verbs[] = {
4441 /*enable ct extension*/
4442 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
4443 /*enable DSP node unsol, needed for DSP download*/
4444 {0x16, AC_VERB_SET_UNSOLICITED_ENABLE, AC_USRSP_EN | UNSOL_TAG_DSP},
4449 static struct hda_verb ca0132_base_exit_verbs[] = {
4451 {0x01, AC_VERB_SET_POWER_STATE, 0x03},
4452 /*disable ct extension*/
4453 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
4457 /* Other verbs tables. Sends after DSP download. */
4458 static struct hda_verb ca0132_init_verbs0[] = {
4459 /* chip init verbs */
4460 {0x15, 0x70D, 0xF0},
4461 {0x15, 0x70E, 0xFE},
4462 {0x15, 0x707, 0x75},
4463 {0x15, 0x707, 0xD3},
4464 {0x15, 0x707, 0x09},
4465 {0x15, 0x707, 0x53},
4466 {0x15, 0x707, 0xD4},
4467 {0x15, 0x707, 0xEF},
4468 {0x15, 0x707, 0x75},
4469 {0x15, 0x707, 0xD3},
4470 {0x15, 0x707, 0x09},
4471 {0x15, 0x707, 0x02},
4472 {0x15, 0x707, 0x37},
4473 {0x15, 0x707, 0x78},
4474 {0x15, 0x53C, 0xCE},
4475 {0x15, 0x575, 0xC9},
4476 {0x15, 0x53D, 0xCE},
4477 {0x15, 0x5B7, 0xC9},
4478 {0x15, 0x70D, 0xE8},
4479 {0x15, 0x70E, 0xFE},
4480 {0x15, 0x707, 0x02},
4481 {0x15, 0x707, 0x68},
4482 {0x15, 0x707, 0x62},
4483 {0x15, 0x53A, 0xCE},
4484 {0x15, 0x546, 0xC9},
4485 {0x15, 0x53B, 0xCE},
4486 {0x15, 0x5E8, 0xC9},
4487 {0x15, 0x717, 0x0D},
4488 {0x15, 0x718, 0x20},
4492 static struct hda_verb ca0132_init_verbs1[] = {
4493 {0x10, AC_VERB_SET_UNSOLICITED_ENABLE, AC_USRSP_EN | UNSOL_TAG_HP},
4494 {0x12, AC_VERB_SET_UNSOLICITED_ENABLE, AC_USRSP_EN | UNSOL_TAG_AMIC1},
4496 {0x0b, 0x78D, 0x00},
4497 /*{0x0b, AC_VERB_SET_EAPD_BTLENABLE, 0x02},*/
4498 /*{0x10, 0x78D, 0x02},*/
4499 /*{0x10, AC_VERB_SET_EAPD_BTLENABLE, 0x02},*/
4503 static void ca0132_init_chip(struct hda_codec *codec)
4505 struct ca0132_spec *spec = codec->spec;
4510 mutex_init(&spec->chipio_mutex);
4512 spec->cur_out_type = SPEAKER_OUT;
4513 spec->cur_mic_type = DIGITAL_MIC;
4514 spec->cur_mic_boost = 0;
4516 for (i = 0; i < VNODES_COUNT; i++) {
4517 spec->vnode_lvol[i] = 0x5a;
4518 spec->vnode_rvol[i] = 0x5a;
4519 spec->vnode_lswitch[i] = 0;
4520 spec->vnode_rswitch[i] = 0;
4524 * Default states for effects are in ca0132_effects[].
4526 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
4527 for (i = 0; i < num_fx; i++) {
4528 on = (unsigned int)ca0132_effects[i].reqs[0];
4529 spec->effects_switch[i] = on ? 1 : 0;
4532 spec->voicefx_val = 0;
4533 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
4534 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
4536 #ifdef ENABLE_TUNING_CONTROLS
4537 ca0132_init_tuning_defaults(codec);
4541 static void ca0132_exit_chip(struct hda_codec *codec)
4543 /* put any chip cleanup stuffs here. */
4545 if (dspload_is_loaded(codec))
4549 static int ca0132_init(struct hda_codec *codec)
4551 struct ca0132_spec *spec = codec->spec;
4552 struct auto_pin_cfg *cfg = &spec->autocfg;
4555 spec->dsp_state = DSP_DOWNLOAD_INIT;
4556 spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
4558 snd_hda_power_up(codec);
4560 ca0132_init_params(codec);
4561 ca0132_init_flags(codec);
4562 snd_hda_sequence_write(codec, spec->base_init_verbs);
4563 ca0132_download_dsp(codec);
4564 ca0132_refresh_widget_caps(codec);
4565 ca0132_setup_defaults(codec);
4566 ca0132_init_analog_mic2(codec);
4567 ca0132_init_dmic(codec);
4569 for (i = 0; i < spec->num_outputs; i++)
4570 init_output(codec, spec->out_pins[i], spec->dacs[0]);
4572 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
4574 for (i = 0; i < spec->num_inputs; i++)
4575 init_input(codec, spec->input_pins[i], spec->adcs[i]);
4577 init_input(codec, cfg->dig_in_pin, spec->dig_in);
4579 for (i = 0; i < spec->num_init_verbs; i++)
4580 snd_hda_sequence_write(codec, spec->init_verbs[i]);
4582 ca0132_init_unsol(codec);
4584 ca0132_select_out(codec);
4585 ca0132_select_mic(codec);
4587 snd_hda_jack_report_sync(codec);
4589 snd_hda_power_down(codec);
4594 static void ca0132_free(struct hda_codec *codec)
4596 struct ca0132_spec *spec = codec->spec;
4598 cancel_delayed_work_sync(&spec->unsol_hp_work);
4599 snd_hda_power_up(codec);
4600 snd_hda_sequence_write(codec, spec->base_exit_verbs);
4601 ca0132_exit_chip(codec);
4602 snd_hda_power_down(codec);
4606 static struct hda_codec_ops ca0132_patch_ops = {
4607 .build_controls = ca0132_build_controls,
4608 .build_pcms = ca0132_build_pcms,
4609 .init = ca0132_init,
4610 .free = ca0132_free,
4611 .unsol_event = ca0132_unsol_event,
4614 static void ca0132_config(struct hda_codec *codec)
4616 struct ca0132_spec *spec = codec->spec;
4617 struct auto_pin_cfg *cfg = &spec->autocfg;
4619 spec->dacs[0] = 0x2;
4620 spec->dacs[1] = 0x3;
4621 spec->dacs[2] = 0x4;
4623 spec->multiout.dac_nids = spec->dacs;
4624 spec->multiout.num_dacs = 3;
4625 spec->multiout.max_channels = 2;
4627 spec->num_outputs = 2;
4628 spec->out_pins[0] = 0x0b; /* speaker out */
4629 spec->out_pins[1] = 0x10; /* headphone out */
4630 spec->shared_out_nid = 0x2;
4632 spec->num_inputs = 3;
4633 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
4634 spec->adcs[1] = 0x8; /* analog mic2 */
4635 spec->adcs[2] = 0xa; /* what u hear */
4636 spec->shared_mic_nid = 0x7;
4638 spec->input_pins[0] = 0x12;
4639 spec->input_pins[1] = 0x11;
4640 spec->input_pins[2] = 0x13;
4643 spec->dig_out = 0x05;
4644 spec->multiout.dig_out_nid = spec->dig_out;
4645 cfg->dig_out_pins[0] = 0x0c;
4647 cfg->dig_out_type[0] = HDA_PCM_TYPE_SPDIF;
4648 spec->dig_in = 0x09;
4649 cfg->dig_in_pin = 0x0e;
4650 cfg->dig_in_type = HDA_PCM_TYPE_SPDIF;
4653 static int patch_ca0132(struct hda_codec *codec)
4655 struct ca0132_spec *spec;
4658 codec_dbg(codec, "patch_ca0132\n");
4660 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
4664 spec->codec = codec;
4666 spec->num_mixers = 1;
4667 spec->mixers[0] = ca0132_mixer;
4669 spec->base_init_verbs = ca0132_base_init_verbs;
4670 spec->base_exit_verbs = ca0132_base_exit_verbs;
4671 spec->init_verbs[0] = ca0132_init_verbs0;
4672 spec->init_verbs[1] = ca0132_init_verbs1;
4673 spec->num_init_verbs = 2;
4675 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
4677 ca0132_init_chip(codec);
4679 ca0132_config(codec);
4681 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
4685 codec->patch_ops = ca0132_patch_ops;
4686 codec->pcm_format_first = 1;
4687 codec->no_sticky_stream = 1;
4695 static struct hda_codec_preset snd_hda_preset_ca0132[] = {
4696 { .id = 0x11020011, .name = "CA0132", .patch = patch_ca0132 },
4700 MODULE_ALIAS("snd-hda-codec-id:11020011");
4702 MODULE_LICENSE("GPL");
4703 MODULE_DESCRIPTION("Creative Sound Core3D codec");
4705 static struct hda_codec_preset_list ca0132_list = {
4706 .preset = snd_hda_preset_ca0132,
4707 .owner = THIS_MODULE,
4710 static int __init patch_ca0132_init(void)
4712 return snd_hda_add_codec_preset(&ca0132_list);
4715 static void __exit patch_ca0132_exit(void)
4717 snd_hda_delete_codec_preset(&ca0132_list);
4720 module_init(patch_ca0132_init)
4721 module_exit(patch_ca0132_exit)