2 * HD audio interface patch for Creative CA0132 chip
4 * Copyright (c) 2011, Creative Technology Ltd.
6 * Based on patch_ca0110.c
7 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
9 * This driver is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This driver is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #include <linux/init.h>
25 #include <linux/delay.h>
26 #include <linux/slab.h>
27 #include <linux/mutex.h>
28 #include <linux/module.h>
29 #include <linux/firmware.h>
30 #include <sound/core.h>
31 #include "hda_codec.h"
32 #include "hda_local.h"
33 #include "hda_auto_parser.h"
36 #include "ca0132_regs.h"
38 /* Enable this to see controls for tuning purpose. */
39 /*#define ENABLE_TUNING_CONTROLS*/
41 #define FLOAT_ZERO 0x00000000
42 #define FLOAT_ONE 0x3f800000
43 #define FLOAT_TWO 0x40000000
44 #define FLOAT_MINUS_5 0xc0a00000
46 #define UNSOL_TAG_DSP 0x16
48 #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
49 #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
51 #define DMA_TRANSFER_FRAME_SIZE_NWORDS 8
52 #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32
53 #define DMA_OVERLAY_FRAME_SIZE_NWORDS 2
55 #define MASTERCONTROL 0x80
56 #define MASTERCONTROL_ALLOC_DMA_CHAN 10
57 #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60
59 #define WIDGET_CHIP_CTRL 0x15
60 #define WIDGET_DSP_CTRL 0x16
62 #define MEM_CONNID_MICIN1 3
63 #define MEM_CONNID_MICIN2 5
64 #define MEM_CONNID_MICOUT1 12
65 #define MEM_CONNID_MICOUT2 14
66 #define MEM_CONNID_WUH 10
67 #define MEM_CONNID_DSP 16
68 #define MEM_CONNID_DMIC 100
73 #define EFX_FILE "ctefx.bin"
75 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
76 MODULE_FIRMWARE(EFX_FILE);
79 static char *dirstr[2] = { "Playback", "Capture" };
92 #define VNODE_START_NID 0x80
93 VNID_SPK = VNODE_START_NID, /* Speaker vnid */
100 #define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID)
102 #define EFFECT_START_NID 0x90
103 #define OUT_EFFECT_START_NID EFFECT_START_NID
104 SURROUND = OUT_EFFECT_START_NID,
111 #define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
113 #define IN_EFFECT_START_NID OUT_EFFECT_END_NID
114 ECHO_CANCELLATION = IN_EFFECT_START_NID,
119 #define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
121 VOICEFX = IN_EFFECT_END_NID,
125 #define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID)
128 /* Effects values size*/
129 #define EFFECT_VALS_MAX_COUNT 12
131 /* Latency introduced by DSP blocks in milliseconds. */
132 #define DSP_CAPTURE_INIT_LATENCY 0
133 #define DSP_CRYSTAL_VOICE_LATENCY 124
134 #define DSP_PLAYBACK_INIT_LATENCY 13
135 #define DSP_PLAY_ENHANCEMENT_LATENCY 30
136 #define DSP_SPEAKER_OUT_LATENCY 7
139 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
141 int mid; /*effect module ID*/
142 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
143 int direct; /* 0:output; 1:input*/
144 int params; /* number of default non-on/off params */
145 /*effect default values, 1st is on/off. */
146 unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
149 #define EFX_DIR_OUT 0
152 static struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
153 { .name = "Surround",
157 .direct = EFX_DIR_OUT,
159 .def_vals = {0x3F800000, 0x3F2B851F}
161 { .name = "Crystalizer",
165 .direct = EFX_DIR_OUT,
167 .def_vals = {0x3F800000, 0x3F266666}
169 { .name = "Dialog Plus",
173 .direct = EFX_DIR_OUT,
175 .def_vals = {0x00000000, 0x3F000000}
177 { .name = "Smart Volume",
181 .direct = EFX_DIR_OUT,
183 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
188 .reqs = {24, 23, 25},
189 .direct = EFX_DIR_OUT,
191 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
193 { .name = "Equalizer",
196 .reqs = {9, 10, 11, 12, 13, 14,
197 15, 16, 17, 18, 19, 20},
198 .direct = EFX_DIR_OUT,
200 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
201 0x00000000, 0x00000000, 0x00000000, 0x00000000,
202 0x00000000, 0x00000000, 0x00000000, 0x00000000}
204 { .name = "Echo Cancellation",
205 .nid = ECHO_CANCELLATION,
207 .reqs = {0, 1, 2, 3},
208 .direct = EFX_DIR_IN,
210 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
212 { .name = "Voice Focus",
215 .reqs = {6, 7, 8, 9},
216 .direct = EFX_DIR_IN,
218 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
224 .direct = EFX_DIR_IN,
226 .def_vals = {0x00000000, 0x3F3D70A4}
228 { .name = "Noise Reduction",
229 .nid = NOISE_REDUCTION,
232 .direct = EFX_DIR_IN,
234 .def_vals = {0x3F800000, 0x3F000000}
239 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
240 .direct = EFX_DIR_IN,
242 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
243 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
248 /* Tuning controls */
249 #ifdef ENABLE_TUNING_CONTROLS
252 #define TUNING_CTL_START_NID 0xC0
253 WEDGE_ANGLE = TUNING_CTL_START_NID,
266 #define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
269 struct ct_tuning_ctl {
270 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
271 hda_nid_t parent_nid;
273 int mid; /*effect module ID*/
274 int req; /*effect module request*/
275 int direct; /* 0:output; 1:input*/
276 unsigned int def_val;/*effect default values*/
279 static struct ct_tuning_ctl ca0132_tuning_ctls[] = {
280 { .name = "Wedge Angle",
281 .parent_nid = VOICE_FOCUS,
285 .direct = EFX_DIR_IN,
286 .def_val = 0x41F00000
288 { .name = "SVM Level",
289 .parent_nid = MIC_SVM,
293 .direct = EFX_DIR_IN,
294 .def_val = 0x3F3D70A4
296 { .name = "EQ Band0",
297 .parent_nid = EQUALIZER,
298 .nid = EQUALIZER_BAND_0,
301 .direct = EFX_DIR_OUT,
302 .def_val = 0x00000000
304 { .name = "EQ Band1",
305 .parent_nid = EQUALIZER,
306 .nid = EQUALIZER_BAND_1,
309 .direct = EFX_DIR_OUT,
310 .def_val = 0x00000000
312 { .name = "EQ Band2",
313 .parent_nid = EQUALIZER,
314 .nid = EQUALIZER_BAND_2,
317 .direct = EFX_DIR_OUT,
318 .def_val = 0x00000000
320 { .name = "EQ Band3",
321 .parent_nid = EQUALIZER,
322 .nid = EQUALIZER_BAND_3,
325 .direct = EFX_DIR_OUT,
326 .def_val = 0x00000000
328 { .name = "EQ Band4",
329 .parent_nid = EQUALIZER,
330 .nid = EQUALIZER_BAND_4,
333 .direct = EFX_DIR_OUT,
334 .def_val = 0x00000000
336 { .name = "EQ Band5",
337 .parent_nid = EQUALIZER,
338 .nid = EQUALIZER_BAND_5,
341 .direct = EFX_DIR_OUT,
342 .def_val = 0x00000000
344 { .name = "EQ Band6",
345 .parent_nid = EQUALIZER,
346 .nid = EQUALIZER_BAND_6,
349 .direct = EFX_DIR_OUT,
350 .def_val = 0x00000000
352 { .name = "EQ Band7",
353 .parent_nid = EQUALIZER,
354 .nid = EQUALIZER_BAND_7,
357 .direct = EFX_DIR_OUT,
358 .def_val = 0x00000000
360 { .name = "EQ Band8",
361 .parent_nid = EQUALIZER,
362 .nid = EQUALIZER_BAND_8,
365 .direct = EFX_DIR_OUT,
366 .def_val = 0x00000000
368 { .name = "EQ Band9",
369 .parent_nid = EQUALIZER,
370 .nid = EQUALIZER_BAND_9,
373 .direct = EFX_DIR_OUT,
374 .def_val = 0x00000000
379 /* Voice FX Presets */
380 #define VOICEFX_MAX_PARAM_COUNT 9
386 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
389 struct ct_voicefx_preset {
390 char *name; /*preset name*/
391 unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
394 static struct ct_voicefx ca0132_voicefx = {
395 .name = "VoiceFX Capture Switch",
398 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
401 static struct ct_voicefx_preset ca0132_voicefx_presets[] = {
403 .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
404 0x44FA0000, 0x3F800000, 0x3F800000,
405 0x3F800000, 0x00000000, 0x00000000 }
407 { .name = "Female2Male",
408 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
409 0x44FA0000, 0x3F19999A, 0x3F866666,
410 0x3F800000, 0x00000000, 0x00000000 }
412 { .name = "Male2Female",
413 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
414 0x450AC000, 0x4017AE14, 0x3F6B851F,
415 0x3F800000, 0x00000000, 0x00000000 }
417 { .name = "ScrappyKid",
418 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
419 0x44FA0000, 0x40400000, 0x3F28F5C3,
420 0x3F800000, 0x00000000, 0x00000000 }
423 .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
424 0x44E10000, 0x3FB33333, 0x3FB9999A,
425 0x3F800000, 0x3E3A2E43, 0x00000000 }
428 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
429 0x45098000, 0x3F266666, 0x3FC00000,
430 0x3F800000, 0x00000000, 0x00000000 }
433 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
434 0x45193000, 0x3F8E147B, 0x3F75C28F,
435 0x3F800000, 0x00000000, 0x00000000 }
438 .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
439 0x45007000, 0x3F451EB8, 0x3F7851EC,
440 0x3F800000, 0x00000000, 0x00000000 }
442 { .name = "AlienBrute",
443 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
444 0x451F6000, 0x3F266666, 0x3FA7D945,
445 0x3F800000, 0x3CF5C28F, 0x00000000 }
448 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
449 0x44FA0000, 0x3FB2718B, 0x3F800000,
450 0xBC07010E, 0x00000000, 0x00000000 }
453 .vals = { 0x3F800000, 0x43C20000, 0x44906000,
454 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
455 0x3F0A3D71, 0x00000000, 0x00000000 }
458 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
459 0x44FA0000, 0x3F800000, 0x3F800000,
460 0x3E4CCCCD, 0x00000000, 0x00000000 }
462 { .name = "DeepVoice",
463 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
464 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
465 0x3F800000, 0x00000000, 0x00000000 }
467 { .name = "Munchkin",
468 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
469 0x44FA0000, 0x3F800000, 0x3F1A043C,
470 0x3F800000, 0x00000000, 0x00000000 }
474 enum hda_cmd_vendor_io {
476 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
477 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100,
479 VENDOR_DSPIO_STATUS = 0xF01,
480 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702,
481 VENDOR_DSPIO_SCP_READ_DATA = 0xF02,
482 VENDOR_DSPIO_DSP_INIT = 0x703,
483 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704,
484 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04,
486 /* for ChipIO node */
487 VENDOR_CHIPIO_ADDRESS_LOW = 0x000,
488 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100,
489 VENDOR_CHIPIO_STREAM_FORMAT = 0x200,
490 VENDOR_CHIPIO_DATA_LOW = 0x300,
491 VENDOR_CHIPIO_DATA_HIGH = 0x400,
493 VENDOR_CHIPIO_GET_PARAMETER = 0xF00,
494 VENDOR_CHIPIO_STATUS = 0xF01,
495 VENDOR_CHIPIO_HIC_POST_READ = 0x702,
496 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03,
498 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707,
499 VENDOR_CHIPIO_8051_DATA_READ = 0xF07,
501 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
502 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A,
504 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C,
505 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C,
506 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D,
507 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E,
508 VENDOR_CHIPIO_FLAG_SET = 0x70F,
509 VENDOR_CHIPIO_FLAGS_GET = 0xF0F,
510 VENDOR_CHIPIO_PARAM_SET = 0x710,
511 VENDOR_CHIPIO_PARAM_GET = 0xF10,
513 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711,
514 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712,
515 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12,
516 VENDOR_CHIPIO_PORT_FREE_SET = 0x713,
518 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17,
519 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717,
520 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18,
521 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718,
523 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788,
524 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88,
525 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789,
526 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89,
527 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A,
528 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A,
530 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D
536 enum control_flag_id {
537 /* Connection manager stream setup is bypassed/enabled */
538 CONTROL_FLAG_C_MGR = 0,
539 /* DSP DMA is bypassed/enabled */
540 CONTROL_FLAG_DMA = 1,
541 /* 8051 'idle' mode is disabled/enabled */
542 CONTROL_FLAG_IDLE_ENABLE = 2,
543 /* Tracker for the SPDIF-in path is bypassed/enabled */
544 CONTROL_FLAG_TRACKER = 3,
545 /* DigitalOut to Spdif2Out connection is disabled/enabled */
546 CONTROL_FLAG_SPDIF2OUT = 4,
547 /* Digital Microphone is disabled/enabled */
548 CONTROL_FLAG_DMIC = 5,
549 /* ADC_B rate is 48 kHz/96 kHz */
550 CONTROL_FLAG_ADC_B_96KHZ = 6,
551 /* ADC_C rate is 48 kHz/96 kHz */
552 CONTROL_FLAG_ADC_C_96KHZ = 7,
553 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
554 CONTROL_FLAG_DAC_96KHZ = 8,
555 /* DSP rate is 48 kHz/96 kHz */
556 CONTROL_FLAG_DSP_96KHZ = 9,
557 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
558 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10,
559 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
560 CONTROL_FLAG_SRC_RATE_96KHZ = 11,
561 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
562 CONTROL_FLAG_DECODE_LOOP = 12,
563 /* De-emphasis filter on DAC-1 disabled/enabled */
564 CONTROL_FLAG_DAC1_DEEMPHASIS = 13,
565 /* De-emphasis filter on DAC-2 disabled/enabled */
566 CONTROL_FLAG_DAC2_DEEMPHASIS = 14,
567 /* De-emphasis filter on DAC-3 disabled/enabled */
568 CONTROL_FLAG_DAC3_DEEMPHASIS = 15,
569 /* High-pass filter on ADC_B disabled/enabled */
570 CONTROL_FLAG_ADC_B_HIGH_PASS = 16,
571 /* High-pass filter on ADC_C disabled/enabled */
572 CONTROL_FLAG_ADC_C_HIGH_PASS = 17,
573 /* Common mode on Port_A disabled/enabled */
574 CONTROL_FLAG_PORT_A_COMMON_MODE = 18,
575 /* Common mode on Port_D disabled/enabled */
576 CONTROL_FLAG_PORT_D_COMMON_MODE = 19,
577 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
578 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20,
579 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
580 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21,
581 /* ASI rate is 48kHz/96kHz */
582 CONTROL_FLAG_ASI_96KHZ = 22,
583 /* DAC power settings able to control attached ports no/yes */
584 CONTROL_FLAG_DACS_CONTROL_PORTS = 23,
585 /* Clock Stop OK reporting is disabled/enabled */
586 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
587 /* Number of control flags */
588 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
592 * Control parameter IDs
594 enum control_param_id {
595 /* 0: None, 1: Mic1In*/
596 CONTROL_PARAM_VIP_SOURCE = 1,
597 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
598 CONTROL_PARAM_SPDIF1_SOURCE = 2,
599 /* Port A output stage gain setting to use when 16 Ohm output
600 * impedance is selected*/
601 CONTROL_PARAM_PORTA_160OHM_GAIN = 8,
602 /* Port D output stage gain setting to use when 16 Ohm output
603 * impedance is selected*/
604 CONTROL_PARAM_PORTD_160OHM_GAIN = 10,
608 /* Select stream with the given ID */
609 CONTROL_PARAM_STREAM_ID = 24,
610 /* Source connection point for the selected stream */
611 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
612 /* Destination connection point for the selected stream */
613 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26,
614 /* Number of audio channels in the selected stream */
615 CONTROL_PARAM_STREAMS_CHANNELS = 27,
616 /*Enable control for the selected stream */
617 CONTROL_PARAM_STREAM_CONTROL = 28,
619 /* Connection Point Control */
621 /* Select connection point with the given ID */
622 CONTROL_PARAM_CONN_POINT_ID = 29,
623 /* Connection point sample rate */
624 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30,
628 /* Select HDA node with the given ID */
629 CONTROL_PARAM_NODE_ID = 31
633 * Dsp Io Status codes
635 enum hda_vendor_status_dspio {
637 VENDOR_STATUS_DSPIO_OK = 0x00,
638 /* Busy, unable to accept new command, the host must retry */
639 VENDOR_STATUS_DSPIO_BUSY = 0x01,
640 /* SCP command queue is full */
641 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02,
642 /* SCP response queue is empty */
643 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
647 * Chip Io Status codes
649 enum hda_vendor_status_chipio {
651 VENDOR_STATUS_CHIPIO_OK = 0x00,
652 /* Busy, unable to accept new command, the host must retry */
653 VENDOR_STATUS_CHIPIO_BUSY = 0x01
659 enum ca0132_sample_rate {
679 SR_RATE_UNKNOWN = 0x1F
682 enum dsp_download_state {
683 DSP_DOWNLOAD_FAILED = -1,
684 DSP_DOWNLOAD_INIT = 0,
689 /* retrieve parameters from hda format */
690 #define get_hdafmt_chs(fmt) (fmt & 0xf)
691 #define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7)
692 #define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f)
693 #define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1)
700 struct snd_kcontrol_new *mixers[5];
701 unsigned int num_mixers;
702 const struct hda_verb *base_init_verbs;
703 const struct hda_verb *base_exit_verbs;
704 const struct hda_verb *chip_init_verbs;
705 struct hda_verb *spec_init_verbs;
706 struct auto_pin_cfg autocfg;
708 /* Nodes configurations */
709 struct hda_multi_out multiout;
710 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
711 hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
712 unsigned int num_outputs;
713 hda_nid_t input_pins[AUTO_PIN_LAST];
714 hda_nid_t adcs[AUTO_PIN_LAST];
717 unsigned int num_inputs;
718 hda_nid_t shared_mic_nid;
719 hda_nid_t shared_out_nid;
720 hda_nid_t unsol_tag_hp;
721 hda_nid_t unsol_tag_amic1;
724 struct mutex chipio_mutex; /* chip access mutex */
727 /* DSP download related */
728 enum dsp_download_state dsp_state;
729 unsigned int dsp_stream_id;
730 unsigned int wait_scp;
731 unsigned int wait_scp_header;
732 unsigned int wait_num_data;
733 unsigned int scp_resp_header;
734 unsigned int scp_resp_data[4];
735 unsigned int scp_resp_count;
737 /* mixer and effects related */
738 unsigned char dmic_ctl;
741 long vnode_lvol[VNODES_COUNT];
742 long vnode_rvol[VNODES_COUNT];
743 long vnode_lswitch[VNODES_COUNT];
744 long vnode_rswitch[VNODES_COUNT];
745 long effects_switch[EFFECTS_COUNT];
749 struct hda_codec *codec;
750 struct delayed_work unsol_hp_work;
753 #ifdef ENABLE_TUNING_CONTROLS
754 long cur_ctl_vals[TUNING_CTLS_COUNT];
759 * CA0132 quirks table
766 static const struct snd_pci_quirk ca0132_quirks[] = {
767 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15", QUIRK_ALIENWARE),
772 * CA0132 codec access
774 static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
775 unsigned int verb, unsigned int parm, unsigned int *res)
777 unsigned int response;
778 response = snd_hda_codec_read(codec, nid, 0, verb, parm);
781 return ((response == -1) ? -1 : 0);
784 static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
785 unsigned short converter_format, unsigned int *res)
787 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
788 converter_format & 0xffff, res);
791 static int codec_set_converter_stream_channel(struct hda_codec *codec,
792 hda_nid_t nid, unsigned char stream,
793 unsigned char channel, unsigned int *res)
795 unsigned char converter_stream_channel = 0;
797 converter_stream_channel = (stream << 4) | (channel & 0x0f);
798 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
799 converter_stream_channel, res);
802 /* Chip access helper function */
803 static int chipio_send(struct hda_codec *codec,
808 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
810 /* send bits of data specified by reg */
812 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
814 if (res == VENDOR_STATUS_CHIPIO_OK)
817 } while (time_before(jiffies, timeout));
823 * Write chip address through the vendor widget -- NOT protected by the Mutex!
825 static int chipio_write_address(struct hda_codec *codec,
826 unsigned int chip_addx)
828 struct ca0132_spec *spec = codec->spec;
831 if (spec->curr_chip_addx == chip_addx)
834 /* send low 16 bits of the address */
835 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
839 /* send high 16 bits of the address */
840 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
844 spec->curr_chip_addx = (res < 0) ? ~0UL : chip_addx;
850 * Write data through the vendor widget -- NOT protected by the Mutex!
852 static int chipio_write_data(struct hda_codec *codec, unsigned int data)
854 struct ca0132_spec *spec = codec->spec;
857 /* send low 16 bits of the data */
858 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
861 /* send high 16 bits of the data */
862 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
866 /*If no error encountered, automatically increment the address
867 as per chip behaviour*/
868 spec->curr_chip_addx = (res != -EIO) ?
869 (spec->curr_chip_addx + 4) : ~0UL;
874 * Write multiple data through the vendor widget -- NOT protected by the Mutex!
876 static int chipio_write_data_multiple(struct hda_codec *codec,
883 codec_dbg(codec, "chipio_write_data null ptr\n");
887 while ((count-- != 0) && (status == 0))
888 status = chipio_write_data(codec, *data++);
895 * Read data through the vendor widget -- NOT protected by the Mutex!
897 static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
899 struct ca0132_spec *spec = codec->spec;
903 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
907 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
912 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
913 VENDOR_CHIPIO_HIC_READ_DATA,
917 /*If no error encountered, automatically increment the address
918 as per chip behaviour*/
919 spec->curr_chip_addx = (res != -EIO) ?
920 (spec->curr_chip_addx + 4) : ~0UL;
925 * Write given value to the given address through the chip I/O widget.
926 * protected by the Mutex
928 static int chipio_write(struct hda_codec *codec,
929 unsigned int chip_addx, const unsigned int data)
931 struct ca0132_spec *spec = codec->spec;
934 mutex_lock(&spec->chipio_mutex);
936 /* write the address, and if successful proceed to write data */
937 err = chipio_write_address(codec, chip_addx);
941 err = chipio_write_data(codec, data);
946 mutex_unlock(&spec->chipio_mutex);
951 * Write multiple values to the given address through the chip I/O widget.
952 * protected by the Mutex
954 static int chipio_write_multiple(struct hda_codec *codec,
959 struct ca0132_spec *spec = codec->spec;
962 mutex_lock(&spec->chipio_mutex);
963 status = chipio_write_address(codec, chip_addx);
967 status = chipio_write_data_multiple(codec, data, count);
969 mutex_unlock(&spec->chipio_mutex);
975 * Read the given address through the chip I/O widget
976 * protected by the Mutex
978 static int chipio_read(struct hda_codec *codec,
979 unsigned int chip_addx, unsigned int *data)
981 struct ca0132_spec *spec = codec->spec;
984 mutex_lock(&spec->chipio_mutex);
986 /* write the address, and if successful proceed to write data */
987 err = chipio_write_address(codec, chip_addx);
991 err = chipio_read_data(codec, data);
996 mutex_unlock(&spec->chipio_mutex);
1001 * Set chip control flags through the chip I/O widget.
1003 static void chipio_set_control_flag(struct hda_codec *codec,
1004 enum control_flag_id flag_id,
1008 unsigned int flag_bit;
1010 flag_bit = (flag_state ? 1 : 0);
1011 val = (flag_bit << 7) | (flag_id);
1012 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1013 VENDOR_CHIPIO_FLAG_SET, val);
1017 * Set chip parameters through the chip I/O widget.
1019 static void chipio_set_control_param(struct hda_codec *codec,
1020 enum control_param_id param_id, int param_val)
1022 struct ca0132_spec *spec = codec->spec;
1025 if ((param_id < 32) && (param_val < 8)) {
1026 val = (param_val << 5) | (param_id);
1027 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1028 VENDOR_CHIPIO_PARAM_SET, val);
1030 mutex_lock(&spec->chipio_mutex);
1031 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1032 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1033 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1035 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1036 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1039 mutex_unlock(&spec->chipio_mutex);
1044 * Set sampling rate of the connection point.
1046 static void chipio_set_conn_rate(struct hda_codec *codec,
1047 int connid, enum ca0132_sample_rate rate)
1049 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1050 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1057 static void chipio_enable_clocks(struct hda_codec *codec)
1059 struct ca0132_spec *spec = codec->spec;
1061 mutex_lock(&spec->chipio_mutex);
1062 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1063 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
1064 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1065 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1066 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1067 VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
1068 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1069 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
1070 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1071 VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
1072 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1073 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1074 mutex_unlock(&spec->chipio_mutex);
1078 * CA0132 DSP IO stuffs
1080 static int dspio_send(struct hda_codec *codec, unsigned int reg,
1084 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1086 /* send bits of data specified by reg to dsp */
1088 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
1089 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
1092 } while (time_before(jiffies, timeout));
1098 * Wait for DSP to be ready for commands
1100 static void dspio_write_wait(struct hda_codec *codec)
1103 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1106 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1107 VENDOR_DSPIO_STATUS, 0);
1108 if ((status == VENDOR_STATUS_DSPIO_OK) ||
1109 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
1112 } while (time_before(jiffies, timeout));
1116 * Write SCP data to DSP
1118 static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
1120 struct ca0132_spec *spec = codec->spec;
1123 dspio_write_wait(codec);
1125 mutex_lock(&spec->chipio_mutex);
1126 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
1131 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
1136 /* OK, now check if the write itself has executed*/
1137 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1138 VENDOR_DSPIO_STATUS, 0);
1140 mutex_unlock(&spec->chipio_mutex);
1142 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
1147 * Write multiple SCP data to DSP
1149 static int dspio_write_multiple(struct hda_codec *codec,
1150 unsigned int *buffer, unsigned int size)
1155 if ((buffer == NULL))
1159 while (count < size) {
1160 status = dspio_write(codec, *buffer++);
1169 static int dspio_read(struct hda_codec *codec, unsigned int *data)
1173 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
1177 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
1178 if (status == -EIO ||
1179 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
1182 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1183 VENDOR_DSPIO_SCP_READ_DATA, 0);
1188 static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
1189 unsigned int *buf_size, unsigned int size_count)
1192 unsigned int size = *buf_size;
1194 unsigned int skip_count;
1197 if ((buffer == NULL))
1201 while (count < size && count < size_count) {
1202 status = dspio_read(codec, buffer++);
1210 while (skip_count < size) {
1211 status = dspio_read(codec, &dummy);
1223 * Construct the SCP header using corresponding fields
1225 static inline unsigned int
1226 make_scp_header(unsigned int target_id, unsigned int source_id,
1227 unsigned int get_flag, unsigned int req,
1228 unsigned int device_flag, unsigned int resp_flag,
1229 unsigned int error_flag, unsigned int data_size)
1231 unsigned int header = 0;
1233 header = (data_size & 0x1f) << 27;
1234 header |= (error_flag & 0x01) << 26;
1235 header |= (resp_flag & 0x01) << 25;
1236 header |= (device_flag & 0x01) << 24;
1237 header |= (req & 0x7f) << 17;
1238 header |= (get_flag & 0x01) << 16;
1239 header |= (source_id & 0xff) << 8;
1240 header |= target_id & 0xff;
1246 * Extract corresponding fields from SCP header
1249 extract_scp_header(unsigned int header,
1250 unsigned int *target_id, unsigned int *source_id,
1251 unsigned int *get_flag, unsigned int *req,
1252 unsigned int *device_flag, unsigned int *resp_flag,
1253 unsigned int *error_flag, unsigned int *data_size)
1256 *data_size = (header >> 27) & 0x1f;
1258 *error_flag = (header >> 26) & 0x01;
1260 *resp_flag = (header >> 25) & 0x01;
1262 *device_flag = (header >> 24) & 0x01;
1264 *req = (header >> 17) & 0x7f;
1266 *get_flag = (header >> 16) & 0x01;
1268 *source_id = (header >> 8) & 0xff;
1270 *target_id = header & 0xff;
1273 #define SCP_MAX_DATA_WORDS (16)
1275 /* Structure to contain any SCP message */
1278 unsigned int data[SCP_MAX_DATA_WORDS];
1281 static void dspio_clear_response_queue(struct hda_codec *codec)
1283 unsigned int dummy = 0;
1286 /* clear all from the response queue */
1288 status = dspio_read(codec, &dummy);
1289 } while (status == 0);
1292 static int dspio_get_response_data(struct hda_codec *codec)
1294 struct ca0132_spec *spec = codec->spec;
1295 unsigned int data = 0;
1298 if (dspio_read(codec, &data) < 0)
1301 if ((data & 0x00ffffff) == spec->wait_scp_header) {
1302 spec->scp_resp_header = data;
1303 spec->scp_resp_count = data >> 27;
1304 count = spec->wait_num_data;
1305 dspio_read_multiple(codec, spec->scp_resp_data,
1306 &spec->scp_resp_count, count);
1314 * Send SCP message to DSP
1316 static int dspio_send_scp_message(struct hda_codec *codec,
1317 unsigned char *send_buf,
1318 unsigned int send_buf_size,
1319 unsigned char *return_buf,
1320 unsigned int return_buf_size,
1321 unsigned int *bytes_returned)
1323 struct ca0132_spec *spec = codec->spec;
1325 unsigned int scp_send_size = 0;
1326 unsigned int total_size;
1327 bool waiting_for_resp = false;
1328 unsigned int header;
1329 struct scp_msg *ret_msg;
1330 unsigned int resp_src_id, resp_target_id;
1331 unsigned int data_size, src_id, target_id, get_flag, device_flag;
1334 *bytes_returned = 0;
1336 /* get scp header from buffer */
1337 header = *((unsigned int *)send_buf);
1338 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
1339 &device_flag, NULL, NULL, &data_size);
1340 scp_send_size = data_size + 1;
1341 total_size = (scp_send_size * 4);
1343 if (send_buf_size < total_size)
1346 if (get_flag || device_flag) {
1347 if (!return_buf || return_buf_size < 4 || !bytes_returned)
1350 spec->wait_scp_header = *((unsigned int *)send_buf);
1352 /* swap source id with target id */
1353 resp_target_id = src_id;
1354 resp_src_id = target_id;
1355 spec->wait_scp_header &= 0xffff0000;
1356 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
1357 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
1359 waiting_for_resp = true;
1362 status = dspio_write_multiple(codec, (unsigned int *)send_buf,
1369 if (waiting_for_resp) {
1370 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1371 memset(return_buf, 0, return_buf_size);
1374 } while (spec->wait_scp && time_before(jiffies, timeout));
1375 waiting_for_resp = false;
1376 if (!spec->wait_scp) {
1377 ret_msg = (struct scp_msg *)return_buf;
1378 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
1379 memcpy(&ret_msg->data, spec->scp_resp_data,
1380 spec->wait_num_data);
1381 *bytes_returned = (spec->scp_resp_count + 1) * 4;
1393 * Prepare and send the SCP message to DSP
1394 * @codec: the HDA codec
1395 * @mod_id: ID of the DSP module to send the command
1396 * @req: ID of request to send to the DSP module
1398 * @data: pointer to the data to send with the request, request specific
1399 * @len: length of the data, in bytes
1400 * @reply: point to the buffer to hold data returned for a reply
1401 * @reply_len: length of the reply buffer returned from GET
1403 * Returns zero or a negative error code.
1405 static int dspio_scp(struct hda_codec *codec,
1406 int mod_id, int req, int dir, void *data, unsigned int len,
1407 void *reply, unsigned int *reply_len)
1410 struct scp_msg scp_send, scp_reply;
1411 unsigned int ret_bytes, send_size, ret_size;
1412 unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
1413 unsigned int reply_data_size;
1415 memset(&scp_send, 0, sizeof(scp_send));
1416 memset(&scp_reply, 0, sizeof(scp_reply));
1418 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
1421 if (dir == SCP_GET && reply == NULL) {
1422 codec_dbg(codec, "dspio_scp get but has no buffer\n");
1426 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
1427 codec_dbg(codec, "dspio_scp bad resp buf len parms\n");
1431 scp_send.hdr = make_scp_header(mod_id, 0x20, (dir == SCP_GET), req,
1432 0, 0, 0, len/sizeof(unsigned int));
1433 if (data != NULL && len > 0) {
1434 len = min((unsigned int)(sizeof(scp_send.data)), len);
1435 memcpy(scp_send.data, data, len);
1439 send_size = sizeof(unsigned int) + len;
1440 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
1441 send_size, (unsigned char *)&scp_reply,
1442 sizeof(scp_reply), &ret_bytes);
1445 codec_dbg(codec, "dspio_scp: send scp msg failed\n");
1449 /* extract send and reply headers members */
1450 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
1451 NULL, NULL, NULL, NULL, NULL);
1452 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
1453 &reply_resp_flag, &reply_error_flag,
1459 if (reply_resp_flag && !reply_error_flag) {
1460 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
1461 / sizeof(unsigned int);
1463 if (*reply_len < ret_size*sizeof(unsigned int)) {
1464 codec_dbg(codec, "reply too long for buf\n");
1466 } else if (ret_size != reply_data_size) {
1467 codec_dbg(codec, "RetLen and HdrLen .NE.\n");
1470 *reply_len = ret_size*sizeof(unsigned int);
1471 memcpy(reply, scp_reply.data, *reply_len);
1474 codec_dbg(codec, "reply ill-formed or errflag set\n");
1482 * Set DSP parameters
1484 static int dspio_set_param(struct hda_codec *codec, int mod_id,
1485 int req, void *data, unsigned int len)
1487 return dspio_scp(codec, mod_id, req, SCP_SET, data, len, NULL, NULL);
1490 static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
1491 int req, unsigned int data)
1493 return dspio_set_param(codec, mod_id, req, &data, sizeof(unsigned int));
1497 * Allocate a DSP DMA channel via an SCP message
1499 static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
1502 unsigned int size = sizeof(dma_chan);
1504 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n");
1505 status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN,
1506 SCP_GET, NULL, 0, dma_chan, &size);
1509 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n");
1513 if ((*dma_chan + 1) == 0) {
1514 codec_dbg(codec, "no free dma channels to allocate\n");
1518 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
1519 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n");
1525 * Free a DSP DMA via an SCP message
1527 static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
1530 unsigned int dummy = 0;
1532 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n");
1533 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan);
1535 status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN,
1536 SCP_SET, &dma_chan, sizeof(dma_chan), NULL, &dummy);
1539 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n");
1543 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n");
1551 static int dsp_set_run_state(struct hda_codec *codec)
1553 unsigned int dbg_ctrl_reg;
1554 unsigned int halt_state;
1557 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
1561 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
1562 DSP_DBGCNTL_STATE_LOBIT;
1564 if (halt_state != 0) {
1565 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
1566 DSP_DBGCNTL_SS_MASK);
1567 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1572 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
1573 DSP_DBGCNTL_EXEC_MASK;
1574 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1586 static int dsp_reset(struct hda_codec *codec)
1591 codec_dbg(codec, "dsp_reset\n");
1593 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
1595 } while (res == -EIO && retry);
1598 codec_dbg(codec, "dsp_reset timeout\n");
1606 * Convert chip address to DSP address
1608 static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
1609 bool *code, bool *yram)
1611 *code = *yram = false;
1613 if (UC_RANGE(chip_addx, 1)) {
1615 return UC_OFF(chip_addx);
1616 } else if (X_RANGE_ALL(chip_addx, 1)) {
1617 return X_OFF(chip_addx);
1618 } else if (Y_RANGE_ALL(chip_addx, 1)) {
1620 return Y_OFF(chip_addx);
1623 return INVALID_CHIP_ADDRESS;
1627 * Check if the DSP DMA is active
1629 static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
1631 unsigned int dma_chnlstart_reg;
1633 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
1635 return ((dma_chnlstart_reg & (1 <<
1636 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
1639 static int dsp_dma_setup_common(struct hda_codec *codec,
1640 unsigned int chip_addx,
1641 unsigned int dma_chan,
1642 unsigned int port_map_mask,
1646 unsigned int chnl_prop;
1647 unsigned int dsp_addx;
1648 unsigned int active;
1651 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n");
1653 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
1654 codec_dbg(codec, "dma chan num invalid\n");
1658 if (dsp_is_dma_active(codec, dma_chan)) {
1659 codec_dbg(codec, "dma already active\n");
1663 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
1665 if (dsp_addx == INVALID_CHIP_ADDRESS) {
1666 codec_dbg(codec, "invalid chip addr\n");
1670 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
1673 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n");
1676 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
1680 codec_dbg(codec, "read CHNLPROP Reg fail\n");
1683 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n");
1687 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1689 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1691 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
1693 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
1695 codec_dbg(codec, "write CHNLPROP Reg fail\n");
1698 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n");
1701 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
1705 codec_dbg(codec, "read ACTIVE Reg fail\n");
1708 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n");
1711 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
1712 DSPDMAC_ACTIVE_AAR_MASK;
1714 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
1716 codec_dbg(codec, "write ACTIVE Reg fail\n");
1720 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n");
1722 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
1725 codec_dbg(codec, "write AUDCHSEL Reg fail\n");
1728 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n");
1730 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
1731 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
1733 codec_dbg(codec, "write IRQCNT Reg fail\n");
1736 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n");
1739 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
1740 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
1741 chip_addx, dsp_addx, dma_chan,
1742 port_map_mask, chnl_prop, active);
1744 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n");
1750 * Setup the DSP DMA per-transfer-specific registers
1752 static int dsp_dma_setup(struct hda_codec *codec,
1753 unsigned int chip_addx,
1755 unsigned int dma_chan)
1759 unsigned int dsp_addx;
1760 unsigned int addr_field;
1761 unsigned int incr_field;
1762 unsigned int base_cnt;
1763 unsigned int cur_cnt;
1764 unsigned int dma_cfg = 0;
1765 unsigned int adr_ofs = 0;
1766 unsigned int xfr_cnt = 0;
1767 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
1768 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
1770 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n");
1772 if (count > max_dma_count) {
1773 codec_dbg(codec, "count too big\n");
1777 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
1778 if (dsp_addx == INVALID_CHIP_ADDRESS) {
1779 codec_dbg(codec, "invalid chip addr\n");
1783 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n");
1785 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
1791 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
1793 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
1796 dma_cfg = addr_field + incr_field;
1797 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
1800 codec_dbg(codec, "write DMACFG Reg fail\n");
1803 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n");
1805 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
1808 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
1811 codec_dbg(codec, "write DSPADROFS Reg fail\n");
1814 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n");
1816 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
1818 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
1820 xfr_cnt = base_cnt | cur_cnt;
1822 status = chipio_write(codec,
1823 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
1825 codec_dbg(codec, "write XFRCNT Reg fail\n");
1828 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n");
1831 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
1832 "ADROFS=0x%x, XFRCNT=0x%x\n",
1833 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
1835 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n");
1843 static int dsp_dma_start(struct hda_codec *codec,
1844 unsigned int dma_chan, bool ovly)
1846 unsigned int reg = 0;
1849 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n");
1852 status = chipio_read(codec,
1853 DSPDMAC_CHNLSTART_INST_OFFSET, ®);
1856 codec_dbg(codec, "read CHNLSTART reg fail\n");
1859 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n");
1861 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
1862 DSPDMAC_CHNLSTART_DIS_MASK);
1865 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
1866 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
1868 codec_dbg(codec, "write CHNLSTART reg fail\n");
1871 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n");
1879 static int dsp_dma_stop(struct hda_codec *codec,
1880 unsigned int dma_chan, bool ovly)
1882 unsigned int reg = 0;
1885 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n");
1888 status = chipio_read(codec,
1889 DSPDMAC_CHNLSTART_INST_OFFSET, ®);
1892 codec_dbg(codec, "read CHNLSTART reg fail\n");
1895 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n");
1896 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
1897 DSPDMAC_CHNLSTART_DIS_MASK);
1900 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
1901 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
1903 codec_dbg(codec, "write CHNLSTART reg fail\n");
1906 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n");
1912 * Allocate router ports
1914 * @codec: the HDA codec
1915 * @num_chans: number of channels in the stream
1916 * @ports_per_channel: number of ports per channel
1917 * @start_device: start device
1918 * @port_map: pointer to the port list to hold the allocated ports
1920 * Returns zero or a negative error code.
1922 static int dsp_allocate_router_ports(struct hda_codec *codec,
1923 unsigned int num_chans,
1924 unsigned int ports_per_channel,
1925 unsigned int start_device,
1926 unsigned int *port_map)
1932 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1936 val = start_device << 6;
1937 val |= (ports_per_channel - 1) << 4;
1938 val |= num_chans - 1;
1940 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1941 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
1944 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1945 VENDOR_CHIPIO_PORT_ALLOC_SET,
1948 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1952 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1953 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
1957 return (res < 0) ? res : 0;
1963 static int dsp_free_router_ports(struct hda_codec *codec)
1967 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1971 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1972 VENDOR_CHIPIO_PORT_FREE_SET,
1975 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1981 * Allocate DSP ports for the download stream
1983 static int dsp_allocate_ports(struct hda_codec *codec,
1984 unsigned int num_chans,
1985 unsigned int rate_multi, unsigned int *port_map)
1989 codec_dbg(codec, " dsp_allocate_ports() -- begin\n");
1991 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
1992 codec_dbg(codec, "bad rate multiple\n");
1996 status = dsp_allocate_router_ports(codec, num_chans,
1997 rate_multi, 0, port_map);
1999 codec_dbg(codec, " dsp_allocate_ports() -- complete\n");
2004 static int dsp_allocate_ports_format(struct hda_codec *codec,
2005 const unsigned short fmt,
2006 unsigned int *port_map)
2009 unsigned int num_chans;
2011 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
2012 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
2013 unsigned int rate_multi = sample_rate_mul / sample_rate_div;
2015 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2016 codec_dbg(codec, "bad rate multiple\n");
2020 num_chans = get_hdafmt_chs(fmt) + 1;
2022 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2030 static int dsp_free_ports(struct hda_codec *codec)
2034 codec_dbg(codec, " dsp_free_ports() -- begin\n");
2036 status = dsp_free_router_ports(codec);
2038 codec_dbg(codec, "free router ports fail\n");
2041 codec_dbg(codec, " dsp_free_ports() -- complete\n");
2047 * HDA DMA engine stuffs for DSP code download
2050 struct hda_codec *codec;
2051 unsigned short m_converter_format;
2052 struct snd_dma_buffer *dmab;
2053 unsigned int buf_size;
2062 static int dma_convert_to_hda_format(struct hda_codec *codec,
2063 unsigned int sample_rate,
2064 unsigned short channels,
2065 unsigned short *hda_format)
2067 unsigned int format_val;
2069 format_val = snd_hdac_calc_stream_format(sample_rate,
2070 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0);
2073 *hda_format = (unsigned short)format_val;
2079 * Reset DMA for DSP download
2081 static int dma_reset(struct dma_engine *dma)
2083 struct hda_codec *codec = dma->codec;
2084 struct ca0132_spec *spec = codec->spec;
2087 if (dma->dmab->area)
2088 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
2090 status = snd_hda_codec_load_dsp_prepare(codec,
2091 dma->m_converter_format,
2096 spec->dsp_stream_id = status;
2100 static int dma_set_state(struct dma_engine *dma, enum dma_state state)
2105 case DMA_STATE_STOP:
2115 snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
2119 static unsigned int dma_get_buffer_size(struct dma_engine *dma)
2121 return dma->dmab->bytes;
2124 static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
2126 return dma->dmab->area;
2129 static int dma_xfer(struct dma_engine *dma,
2130 const unsigned int *data,
2133 memcpy(dma->dmab->area, data, count);
2137 static void dma_get_converter_format(
2138 struct dma_engine *dma,
2139 unsigned short *format)
2142 *format = dma->m_converter_format;
2145 static unsigned int dma_get_stream_id(struct dma_engine *dma)
2147 struct ca0132_spec *spec = dma->codec->spec;
2149 return spec->dsp_stream_id;
2152 struct dsp_image_seg {
2159 static const u32 g_magic_value = 0x4c46584d;
2160 static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
2162 static bool is_valid(const struct dsp_image_seg *p)
2164 return p->magic == g_magic_value;
2167 static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
2169 return g_chip_addr_magic_value == p->chip_addr;
2172 static bool is_last(const struct dsp_image_seg *p)
2174 return p->count == 0;
2177 static size_t dsp_sizeof(const struct dsp_image_seg *p)
2179 return sizeof(*p) + p->count*sizeof(u32);
2182 static const struct dsp_image_seg *get_next_seg_ptr(
2183 const struct dsp_image_seg *p)
2185 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
2189 * CA0132 chip DSP transfer stuffs. For DSP download.
2191 #define INVALID_DMA_CHANNEL (~0U)
2194 * Program a list of address/data pairs via the ChipIO widget.
2195 * The segment data is in the format of successive pairs of words.
2196 * These are repeated as indicated by the segment's count field.
2198 static int dspxfr_hci_write(struct hda_codec *codec,
2199 const struct dsp_image_seg *fls)
2205 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
2206 codec_dbg(codec, "hci_write invalid params\n");
2211 data = (u32 *)(fls->data);
2212 while (count >= 2) {
2213 status = chipio_write(codec, data[0], data[1]);
2215 codec_dbg(codec, "hci_write chipio failed\n");
2225 * Write a block of data into DSP code or data RAM using pre-allocated
2228 * @codec: the HDA codec
2229 * @fls: pointer to a fast load image
2230 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2232 * @dma_engine: pointer to DMA engine to be used for DSP download
2233 * @dma_chan: The number of DMA channels used for DSP download
2234 * @port_map_mask: port mapping
2235 * @ovly: TRUE if overlay format is required
2237 * Returns zero or a negative error code.
2239 static int dspxfr_one_seg(struct hda_codec *codec,
2240 const struct dsp_image_seg *fls,
2242 struct dma_engine *dma_engine,
2243 unsigned int dma_chan,
2244 unsigned int port_map_mask,
2248 bool comm_dma_setup_done = false;
2249 const unsigned int *data;
2250 unsigned int chip_addx;
2251 unsigned int words_to_write;
2252 unsigned int buffer_size_words;
2253 unsigned char *buffer_addx;
2254 unsigned short hda_format;
2255 unsigned int sample_rate_div;
2256 unsigned int sample_rate_mul;
2257 unsigned int num_chans;
2258 unsigned int hda_frame_size_words;
2259 unsigned int remainder_words;
2260 const u32 *data_remainder;
2261 u32 chip_addx_remainder;
2262 unsigned int run_size_words;
2263 const struct dsp_image_seg *hci_write = NULL;
2264 unsigned long timeout;
2269 if (is_hci_prog_list_seg(fls)) {
2271 fls = get_next_seg_ptr(fls);
2274 if (hci_write && (!fls || is_last(fls))) {
2275 codec_dbg(codec, "hci_write\n");
2276 return dspxfr_hci_write(codec, hci_write);
2279 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
2280 codec_dbg(codec, "Invalid Params\n");
2285 chip_addx = fls->chip_addr,
2286 words_to_write = fls->count;
2288 if (!words_to_write)
2289 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
2291 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
2293 if (!UC_RANGE(chip_addx, words_to_write) &&
2294 !X_RANGE_ALL(chip_addx, words_to_write) &&
2295 !Y_RANGE_ALL(chip_addx, words_to_write)) {
2296 codec_dbg(codec, "Invalid chip_addx Params\n");
2300 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
2303 buffer_addx = dma_get_buffer_addr(dma_engine);
2305 if (buffer_addx == NULL) {
2306 codec_dbg(codec, "dma_engine buffer NULL\n");
2310 dma_get_converter_format(dma_engine, &hda_format);
2311 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
2312 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
2313 num_chans = get_hdafmt_chs(hda_format) + 1;
2315 hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
2316 (num_chans * sample_rate_mul / sample_rate_div));
2318 if (hda_frame_size_words == 0) {
2319 codec_dbg(codec, "frmsz zero\n");
2323 buffer_size_words = min(buffer_size_words,
2324 (unsigned int)(UC_RANGE(chip_addx, 1) ?
2326 buffer_size_words -= buffer_size_words % hda_frame_size_words;
2328 "chpadr=0x%08x frmsz=%u nchan=%u "
2329 "rate_mul=%u div=%u bufsz=%u\n",
2330 chip_addx, hda_frame_size_words, num_chans,
2331 sample_rate_mul, sample_rate_div, buffer_size_words);
2333 if (buffer_size_words < hda_frame_size_words) {
2334 codec_dbg(codec, "dspxfr_one_seg:failed\n");
2338 remainder_words = words_to_write % hda_frame_size_words;
2339 data_remainder = data;
2340 chip_addx_remainder = chip_addx;
2342 data += remainder_words;
2343 chip_addx += remainder_words*sizeof(u32);
2344 words_to_write -= remainder_words;
2346 while (words_to_write != 0) {
2347 run_size_words = min(buffer_size_words, words_to_write);
2348 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
2349 words_to_write, run_size_words, remainder_words);
2350 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
2351 if (!comm_dma_setup_done) {
2352 status = dsp_dma_stop(codec, dma_chan, ovly);
2355 status = dsp_dma_setup_common(codec, chip_addx,
2356 dma_chan, port_map_mask, ovly);
2359 comm_dma_setup_done = true;
2362 status = dsp_dma_setup(codec, chip_addx,
2363 run_size_words, dma_chan);
2366 status = dsp_dma_start(codec, dma_chan, ovly);
2369 if (!dsp_is_dma_active(codec, dma_chan)) {
2370 codec_dbg(codec, "dspxfr:DMA did not start\n");
2373 status = dma_set_state(dma_engine, DMA_STATE_RUN);
2376 if (remainder_words != 0) {
2377 status = chipio_write_multiple(codec,
2378 chip_addx_remainder,
2383 remainder_words = 0;
2386 status = dspxfr_hci_write(codec, hci_write);
2392 timeout = jiffies + msecs_to_jiffies(2000);
2394 dma_active = dsp_is_dma_active(codec, dma_chan);
2398 } while (time_before(jiffies, timeout));
2402 codec_dbg(codec, "+++++ DMA complete\n");
2403 dma_set_state(dma_engine, DMA_STATE_STOP);
2404 status = dma_reset(dma_engine);
2409 data += run_size_words;
2410 chip_addx += run_size_words*sizeof(u32);
2411 words_to_write -= run_size_words;
2414 if (remainder_words != 0) {
2415 status = chipio_write_multiple(codec, chip_addx_remainder,
2416 data_remainder, remainder_words);
2423 * Write the entire DSP image of a DSP code/data overlay to DSP memories
2425 * @codec: the HDA codec
2426 * @fls_data: pointer to a fast load image
2427 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2429 * @sample_rate: sampling rate of the stream used for DSP download
2430 * @channels: channels of the stream used for DSP download
2431 * @ovly: TRUE if overlay format is required
2433 * Returns zero or a negative error code.
2435 static int dspxfr_image(struct hda_codec *codec,
2436 const struct dsp_image_seg *fls_data,
2438 unsigned int sample_rate,
2439 unsigned short channels,
2442 struct ca0132_spec *spec = codec->spec;
2444 unsigned short hda_format = 0;
2445 unsigned int response;
2446 unsigned char stream_id = 0;
2447 struct dma_engine *dma_engine;
2448 unsigned int dma_chan;
2449 unsigned int port_map_mask;
2451 if (fls_data == NULL)
2454 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
2458 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
2459 if (!dma_engine->dmab) {
2464 dma_engine->codec = codec;
2465 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format);
2466 dma_engine->m_converter_format = hda_format;
2467 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
2468 DSP_DMA_WRITE_BUFLEN_INIT) * 2;
2470 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
2472 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
2473 hda_format, &response);
2476 codec_dbg(codec, "set converter format fail\n");
2480 status = snd_hda_codec_load_dsp_prepare(codec,
2481 dma_engine->m_converter_format,
2482 dma_engine->buf_size,
2486 spec->dsp_stream_id = status;
2489 status = dspio_alloc_dma_chan(codec, &dma_chan);
2491 codec_dbg(codec, "alloc dmachan fail\n");
2492 dma_chan = INVALID_DMA_CHANNEL;
2498 status = dsp_allocate_ports_format(codec, hda_format,
2501 codec_dbg(codec, "alloc ports fail\n");
2505 stream_id = dma_get_stream_id(dma_engine);
2506 status = codec_set_converter_stream_channel(codec,
2507 WIDGET_CHIP_CTRL, stream_id, 0, &response);
2509 codec_dbg(codec, "set stream chan fail\n");
2513 while ((fls_data != NULL) && !is_last(fls_data)) {
2514 if (!is_valid(fls_data)) {
2515 codec_dbg(codec, "FLS check fail\n");
2519 status = dspxfr_one_seg(codec, fls_data, reloc,
2520 dma_engine, dma_chan,
2521 port_map_mask, ovly);
2525 if (is_hci_prog_list_seg(fls_data))
2526 fls_data = get_next_seg_ptr(fls_data);
2528 if ((fls_data != NULL) && !is_last(fls_data))
2529 fls_data = get_next_seg_ptr(fls_data);
2532 if (port_map_mask != 0)
2533 status = dsp_free_ports(codec);
2538 status = codec_set_converter_stream_channel(codec,
2539 WIDGET_CHIP_CTRL, 0, 0, &response);
2542 if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
2543 dspio_free_dma_chan(codec, dma_chan);
2545 if (dma_engine->dmab->area)
2546 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
2547 kfree(dma_engine->dmab);
2554 * CA0132 DSP download stuffs.
2556 static void dspload_post_setup(struct hda_codec *codec)
2558 codec_dbg(codec, "---- dspload_post_setup ------\n");
2560 /*set DSP speaker to 2.0 configuration*/
2561 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
2562 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
2564 /*update write pointer*/
2565 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
2569 * dspload_image - Download DSP from a DSP Image Fast Load structure.
2571 * @codec: the HDA codec
2572 * @fls: pointer to a fast load image
2573 * @ovly: TRUE if overlay format is required
2574 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2576 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
2577 * @router_chans: number of audio router channels to be allocated (0 means use
2578 * internal defaults; max is 32)
2580 * Download DSP from a DSP Image Fast Load structure. This structure is a
2581 * linear, non-constant sized element array of structures, each of which
2582 * contain the count of the data to be loaded, the data itself, and the
2583 * corresponding starting chip address of the starting data location.
2584 * Returns zero or a negative error code.
2586 static int dspload_image(struct hda_codec *codec,
2587 const struct dsp_image_seg *fls,
2594 unsigned int sample_rate;
2595 unsigned short channels;
2597 codec_dbg(codec, "---- dspload_image begin ------\n");
2598 if (router_chans == 0) {
2600 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
2602 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
2605 sample_rate = 48000;
2606 channels = (unsigned short)router_chans;
2608 while (channels > 16) {
2614 codec_dbg(codec, "Ready to program DMA\n");
2616 status = dsp_reset(codec);
2621 codec_dbg(codec, "dsp_reset() complete\n");
2622 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
2628 codec_dbg(codec, "dspxfr_image() complete\n");
2629 if (autostart && !ovly) {
2630 dspload_post_setup(codec);
2631 status = dsp_set_run_state(codec);
2634 codec_dbg(codec, "LOAD FINISHED\n");
2640 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
2641 static bool dspload_is_loaded(struct hda_codec *codec)
2643 unsigned int data = 0;
2646 status = chipio_read(codec, 0x40004, &data);
2647 if ((status < 0) || (data != 1))
2653 #define dspload_is_loaded(codec) false
2656 static bool dspload_wait_loaded(struct hda_codec *codec)
2658 unsigned long timeout = jiffies + msecs_to_jiffies(2000);
2661 if (dspload_is_loaded(codec)) {
2662 pr_info("ca0132 DOWNLOAD OK :-) DSP IS RUNNING.\n");
2666 } while (time_before(jiffies, timeout));
2668 pr_err("ca0132 DOWNLOAD FAILED!!! DSP IS NOT RUNNING.\n");
2675 static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2676 struct hda_codec *codec,
2677 unsigned int stream_tag,
2678 unsigned int format,
2679 struct snd_pcm_substream *substream)
2681 struct ca0132_spec *spec = codec->spec;
2683 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
2688 static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
2689 struct hda_codec *codec,
2690 struct snd_pcm_substream *substream)
2692 struct ca0132_spec *spec = codec->spec;
2694 if (spec->dsp_state == DSP_DOWNLOADING)
2697 /*If Playback effects are on, allow stream some time to flush
2699 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
2702 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
2707 static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info,
2708 struct hda_codec *codec,
2709 struct snd_pcm_substream *substream)
2711 struct ca0132_spec *spec = codec->spec;
2712 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
2713 struct snd_pcm_runtime *runtime = substream->runtime;
2715 if (spec->dsp_state != DSP_DOWNLOADED)
2718 /* Add latency if playback enhancement and either effect is enabled. */
2719 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
2720 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
2721 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
2722 latency += DSP_PLAY_ENHANCEMENT_LATENCY;
2725 /* Applying Speaker EQ adds latency as well. */
2726 if (spec->cur_out_type == SPEAKER_OUT)
2727 latency += DSP_SPEAKER_OUT_LATENCY;
2729 return (latency * runtime->rate) / 1000;
2735 static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
2736 struct hda_codec *codec,
2737 struct snd_pcm_substream *substream)
2739 struct ca0132_spec *spec = codec->spec;
2740 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2743 static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2744 struct hda_codec *codec,
2745 unsigned int stream_tag,
2746 unsigned int format,
2747 struct snd_pcm_substream *substream)
2749 struct ca0132_spec *spec = codec->spec;
2750 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2751 stream_tag, format, substream);
2754 static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
2755 struct hda_codec *codec,
2756 struct snd_pcm_substream *substream)
2758 struct ca0132_spec *spec = codec->spec;
2759 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
2762 static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
2763 struct hda_codec *codec,
2764 struct snd_pcm_substream *substream)
2766 struct ca0132_spec *spec = codec->spec;
2767 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2773 static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
2774 struct hda_codec *codec,
2775 unsigned int stream_tag,
2776 unsigned int format,
2777 struct snd_pcm_substream *substream)
2779 snd_hda_codec_setup_stream(codec, hinfo->nid,
2780 stream_tag, 0, format);
2785 static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
2786 struct hda_codec *codec,
2787 struct snd_pcm_substream *substream)
2789 struct ca0132_spec *spec = codec->spec;
2791 if (spec->dsp_state == DSP_DOWNLOADING)
2794 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
2798 static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info,
2799 struct hda_codec *codec,
2800 struct snd_pcm_substream *substream)
2802 struct ca0132_spec *spec = codec->spec;
2803 unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
2804 struct snd_pcm_runtime *runtime = substream->runtime;
2806 if (spec->dsp_state != DSP_DOWNLOADED)
2809 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
2810 latency += DSP_CRYSTAL_VOICE_LATENCY;
2812 return (latency * runtime->rate) / 1000;
2820 * Mixer controls helpers.
2822 #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
2823 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2825 .subdevice = HDA_SUBDEV_AMP_FLAG, \
2826 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2827 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
2828 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
2829 .info = ca0132_volume_info, \
2830 .get = ca0132_volume_get, \
2831 .put = ca0132_volume_put, \
2832 .tlv = { .c = ca0132_volume_tlv }, \
2833 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
2835 #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
2836 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2838 .subdevice = HDA_SUBDEV_AMP_FLAG, \
2839 .info = snd_hda_mixer_amp_switch_info, \
2840 .get = ca0132_switch_get, \
2841 .put = ca0132_switch_put, \
2842 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
2845 #define CA0132_CODEC_VOL(xname, nid, dir) \
2846 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
2847 #define CA0132_CODEC_MUTE(xname, nid, dir) \
2848 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
2850 /* The followings are for tuning of products */
2851 #ifdef ENABLE_TUNING_CONTROLS
2853 static unsigned int voice_focus_vals_lookup[] = {
2854 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
2855 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
2856 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
2857 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
2858 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
2859 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
2860 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
2861 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
2862 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
2863 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
2864 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
2865 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
2866 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
2867 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
2868 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
2869 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
2870 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
2871 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
2872 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
2873 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
2874 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
2875 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
2876 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
2877 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
2878 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
2879 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
2880 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
2883 static unsigned int mic_svm_vals_lookup[] = {
2884 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
2885 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
2886 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
2887 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
2888 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
2889 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
2890 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
2891 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
2892 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
2893 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
2894 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
2895 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
2896 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
2897 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
2898 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
2899 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
2900 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
2903 static unsigned int equalizer_vals_lookup[] = {
2904 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
2905 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
2906 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
2907 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
2908 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
2909 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
2910 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
2911 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
2915 static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
2916 unsigned int *lookup, int idx)
2920 for (i = 0; i < TUNING_CTLS_COUNT; i++)
2921 if (nid == ca0132_tuning_ctls[i].nid)
2924 snd_hda_power_up(codec);
2925 dspio_set_param(codec, ca0132_tuning_ctls[i].mid,
2926 ca0132_tuning_ctls[i].req,
2927 &(lookup[idx]), sizeof(unsigned int));
2928 snd_hda_power_down(codec);
2933 static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
2934 struct snd_ctl_elem_value *ucontrol)
2936 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2937 struct ca0132_spec *spec = codec->spec;
2938 hda_nid_t nid = get_amp_nid(kcontrol);
2939 long *valp = ucontrol->value.integer.value;
2940 int idx = nid - TUNING_CTL_START_NID;
2942 *valp = spec->cur_ctl_vals[idx];
2946 static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
2947 struct snd_ctl_elem_info *uinfo)
2949 int chs = get_amp_channels(kcontrol);
2950 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2951 uinfo->count = chs == 3 ? 2 : 1;
2952 uinfo->value.integer.min = 20;
2953 uinfo->value.integer.max = 180;
2954 uinfo->value.integer.step = 1;
2959 static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
2960 struct snd_ctl_elem_value *ucontrol)
2962 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2963 struct ca0132_spec *spec = codec->spec;
2964 hda_nid_t nid = get_amp_nid(kcontrol);
2965 long *valp = ucontrol->value.integer.value;
2968 idx = nid - TUNING_CTL_START_NID;
2970 if (spec->cur_ctl_vals[idx] == *valp)
2973 spec->cur_ctl_vals[idx] = *valp;
2976 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
2981 static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
2982 struct snd_ctl_elem_info *uinfo)
2984 int chs = get_amp_channels(kcontrol);
2985 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2986 uinfo->count = chs == 3 ? 2 : 1;
2987 uinfo->value.integer.min = 0;
2988 uinfo->value.integer.max = 100;
2989 uinfo->value.integer.step = 1;
2994 static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
2995 struct snd_ctl_elem_value *ucontrol)
2997 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2998 struct ca0132_spec *spec = codec->spec;
2999 hda_nid_t nid = get_amp_nid(kcontrol);
3000 long *valp = ucontrol->value.integer.value;
3003 idx = nid - TUNING_CTL_START_NID;
3005 if (spec->cur_ctl_vals[idx] == *valp)
3008 spec->cur_ctl_vals[idx] = *valp;
3011 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
3016 static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
3017 struct snd_ctl_elem_info *uinfo)
3019 int chs = get_amp_channels(kcontrol);
3020 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3021 uinfo->count = chs == 3 ? 2 : 1;
3022 uinfo->value.integer.min = 0;
3023 uinfo->value.integer.max = 48;
3024 uinfo->value.integer.step = 1;
3029 static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
3030 struct snd_ctl_elem_value *ucontrol)
3032 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3033 struct ca0132_spec *spec = codec->spec;
3034 hda_nid_t nid = get_amp_nid(kcontrol);
3035 long *valp = ucontrol->value.integer.value;
3038 idx = nid - TUNING_CTL_START_NID;
3040 if (spec->cur_ctl_vals[idx] == *valp)
3043 spec->cur_ctl_vals[idx] = *valp;
3046 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
3051 static const DECLARE_TLV_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
3052 static const DECLARE_TLV_DB_SCALE(eq_db_scale, -2400, 100, 0);
3054 static int add_tuning_control(struct hda_codec *codec,
3055 hda_nid_t pnid, hda_nid_t nid,
3056 const char *name, int dir)
3058 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
3059 int type = dir ? HDA_INPUT : HDA_OUTPUT;
3060 struct snd_kcontrol_new knew =
3061 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
3063 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
3064 SNDRV_CTL_ELEM_ACCESS_TLV_READ;
3069 knew.info = voice_focus_ctl_info;
3070 knew.get = tuning_ctl_get;
3071 knew.put = voice_focus_ctl_put;
3072 knew.tlv.p = voice_focus_db_scale;
3075 knew.info = mic_svm_ctl_info;
3076 knew.get = tuning_ctl_get;
3077 knew.put = mic_svm_ctl_put;
3080 knew.info = equalizer_ctl_info;
3081 knew.get = tuning_ctl_get;
3082 knew.put = equalizer_ctl_put;
3083 knew.tlv.p = eq_db_scale;
3088 knew.private_value =
3089 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
3090 sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
3091 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3094 static int add_tuning_ctls(struct hda_codec *codec)
3099 for (i = 0; i < TUNING_CTLS_COUNT; i++) {
3100 err = add_tuning_control(codec,
3101 ca0132_tuning_ctls[i].parent_nid,
3102 ca0132_tuning_ctls[i].nid,
3103 ca0132_tuning_ctls[i].name,
3104 ca0132_tuning_ctls[i].direct);
3112 static void ca0132_init_tuning_defaults(struct hda_codec *codec)
3114 struct ca0132_spec *spec = codec->spec;
3117 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */
3118 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
3119 /* SVM level defaults to 0.74. */
3120 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
3122 /* EQ defaults to 0dB. */
3123 for (i = 2; i < TUNING_CTLS_COUNT; i++)
3124 spec->cur_ctl_vals[i] = 24;
3126 #endif /*ENABLE_TUNING_CONTROLS*/
3129 * Select the active output.
3130 * If autodetect is enabled, output will be selected based on jack detection.
3131 * If jack inserted, headphone will be selected, else built-in speakers
3132 * If autodetect is disabled, output will be selected based on selection.
3134 static int ca0132_select_out(struct hda_codec *codec)
3136 struct ca0132_spec *spec = codec->spec;
3137 unsigned int pin_ctl;
3143 codec_dbg(codec, "ca0132_select_out\n");
3145 snd_hda_power_up_pm(codec);
3147 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3150 jack_present = snd_hda_jack_detect(codec, spec->out_pins[1]);
3153 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
3156 spec->cur_out_type = HEADPHONE_OUT;
3158 spec->cur_out_type = SPEAKER_OUT;
3160 if (spec->cur_out_type == SPEAKER_OUT) {
3161 codec_dbg(codec, "ca0132_select_out speaker\n");
3162 /*speaker out config*/
3164 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3167 /*enable speaker EQ*/
3169 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3174 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3175 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3176 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3177 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3178 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3179 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3180 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3181 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3183 /* disable headphone node */
3184 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3185 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3186 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3188 /* enable speaker node */
3189 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3190 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3191 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3194 codec_dbg(codec, "ca0132_select_out hp\n");
3195 /*headphone out config*/
3197 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3200 /*disable speaker EQ*/
3202 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3207 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3208 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3209 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3210 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3211 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3212 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3213 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3214 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3216 /* disable speaker*/
3217 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3218 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3219 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3221 /* enable headphone*/
3222 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3223 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3224 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3229 snd_hda_power_down_pm(codec);
3231 return err < 0 ? err : 0;
3234 static void ca0132_unsol_hp_delayed(struct work_struct *work)
3236 struct ca0132_spec *spec = container_of(
3237 to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
3238 struct hda_jack_tbl *jack;
3240 ca0132_select_out(spec->codec);
3241 jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp);
3243 jack->block_report = 0;
3244 snd_hda_jack_report_sync(spec->codec);
3248 static void ca0132_set_dmic(struct hda_codec *codec, int enable);
3249 static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
3250 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
3253 * Select the active VIP source
3255 static int ca0132_set_vipsource(struct hda_codec *codec, int val)
3257 struct ca0132_spec *spec = codec->spec;
3260 if (spec->dsp_state != DSP_DOWNLOADED)
3263 /* if CrystalVoice if off, vipsource should be 0 */
3264 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
3266 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
3267 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
3268 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
3269 if (spec->cur_mic_type == DIGITAL_MIC)
3273 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
3275 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
3277 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
3278 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
3279 if (spec->cur_mic_type == DIGITAL_MIC)
3283 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
3285 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
3287 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
3294 * Select the active microphone.
3295 * If autodetect is enabled, mic will be selected based on jack detection.
3296 * If jack inserted, ext.mic will be selected, else built-in mic
3297 * If autodetect is disabled, mic will be selected based on selection.
3299 static int ca0132_select_mic(struct hda_codec *codec)
3301 struct ca0132_spec *spec = codec->spec;
3305 codec_dbg(codec, "ca0132_select_mic\n");
3307 snd_hda_power_up_pm(codec);
3309 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
3312 jack_present = snd_hda_jack_detect(codec, spec->input_pins[0]);
3315 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
3318 spec->cur_mic_type = LINE_MIC_IN;
3320 spec->cur_mic_type = DIGITAL_MIC;
3322 if (spec->cur_mic_type == DIGITAL_MIC) {
3323 /* enable digital Mic */
3324 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
3325 ca0132_set_dmic(codec, 1);
3326 ca0132_mic_boost_set(codec, 0);
3327 /* set voice focus */
3328 ca0132_effects_set(codec, VOICE_FOCUS,
3329 spec->effects_switch
3330 [VOICE_FOCUS - EFFECT_START_NID]);
3332 /* disable digital Mic */
3333 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
3334 ca0132_set_dmic(codec, 0);
3335 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
3336 /* disable voice focus */
3337 ca0132_effects_set(codec, VOICE_FOCUS, 0);
3340 snd_hda_power_down_pm(codec);
3346 * Check if VNODE settings take effect immediately.
3348 static bool ca0132_is_vnode_effective(struct hda_codec *codec,
3350 hda_nid_t *shared_nid)
3352 struct ca0132_spec *spec = codec->spec;
3357 nid = spec->shared_out_nid;
3360 nid = spec->shared_mic_nid;
3373 * The following functions are control change helpers.
3374 * They return 0 if no changed. Return 1 if changed.
3376 static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
3378 struct ca0132_spec *spec = codec->spec;
3381 /* based on CrystalVoice state to enable VoiceFX. */
3383 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
3384 FLOAT_ONE : FLOAT_ZERO;
3389 dspio_set_uint_param(codec, ca0132_voicefx.mid,
3390 ca0132_voicefx.reqs[0], tmp);
3396 * Set the effects parameters
3398 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
3400 struct ca0132_spec *spec = codec->spec;
3402 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
3404 int idx = nid - EFFECT_START_NID;
3406 if ((idx < 0) || (idx >= num_fx))
3407 return 0; /* no changed */
3409 /* for out effect, qualify with PE */
3410 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
3411 /* if PE if off, turn off out effects. */
3412 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3416 /* for in effect, qualify with CrystalVoice */
3417 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
3418 /* if CrystalVoice if off, turn off in effects. */
3419 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
3422 /* Voice Focus applies to 2-ch Mic, Digital Mic */
3423 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
3427 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n",
3430 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
3431 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
3432 ca0132_effects[idx].reqs[0], on);
3435 return 0; /* no changed */
3441 * Turn on/off Playback Enhancements
3443 static int ca0132_pe_switch_set(struct hda_codec *codec)
3445 struct ca0132_spec *spec = codec->spec;
3449 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n",
3450 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
3452 i = OUT_EFFECT_START_NID - EFFECT_START_NID;
3453 nid = OUT_EFFECT_START_NID;
3454 /* PE affects all out effects */
3455 for (; nid < OUT_EFFECT_END_NID; nid++, i++)
3456 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
3461 /* Check if Mic1 is streaming, if so, stop streaming */
3462 static int stop_mic1(struct hda_codec *codec)
3464 struct ca0132_spec *spec = codec->spec;
3465 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
3466 AC_VERB_GET_CONV, 0);
3468 snd_hda_codec_write(codec, spec->adcs[0], 0,
3469 AC_VERB_SET_CHANNEL_STREAMID,
3474 /* Resume Mic1 streaming if it was stopped. */
3475 static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
3477 struct ca0132_spec *spec = codec->spec;
3478 /* Restore the previous stream and channel */
3480 snd_hda_codec_write(codec, spec->adcs[0], 0,
3481 AC_VERB_SET_CHANNEL_STREAMID,
3486 * Turn on/off CrystalVoice
3488 static int ca0132_cvoice_switch_set(struct hda_codec *codec)
3490 struct ca0132_spec *spec = codec->spec;
3493 unsigned int oldval;
3495 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n",
3496 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
3498 i = IN_EFFECT_START_NID - EFFECT_START_NID;
3499 nid = IN_EFFECT_START_NID;
3500 /* CrystalVoice affects all in effects */
3501 for (; nid < IN_EFFECT_END_NID; nid++, i++)
3502 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
3504 /* including VoiceFX */
3505 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
3507 /* set correct vipsource */
3508 oldval = stop_mic1(codec);
3509 ret |= ca0132_set_vipsource(codec, 1);
3510 resume_mic1(codec, oldval);
3514 static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
3516 struct ca0132_spec *spec = codec->spec;
3520 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
3521 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
3523 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
3524 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
3529 static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
3530 struct snd_ctl_elem_value *ucontrol)
3532 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3533 hda_nid_t nid = get_amp_nid(kcontrol);
3534 hda_nid_t shared_nid = 0;
3537 struct ca0132_spec *spec = codec->spec;
3540 if (nid == VNID_HP_SEL) {
3542 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3544 ca0132_select_out(codec);
3548 if (nid == VNID_AMIC1_SEL) {
3550 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
3552 ca0132_select_mic(codec);
3556 if (nid == VNID_HP_ASEL) {
3557 ca0132_select_out(codec);
3561 if (nid == VNID_AMIC1_ASEL) {
3562 ca0132_select_mic(codec);
3566 /* if effective conditions, then update hw immediately. */
3567 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
3569 int dir = get_amp_direction(kcontrol);
3570 int ch = get_amp_channels(kcontrol);
3573 mutex_lock(&codec->control_mutex);
3574 pval = kcontrol->private_value;
3575 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
3577 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
3578 kcontrol->private_value = pval;
3579 mutex_unlock(&codec->control_mutex);
3584 /* End of control change helpers. */
3586 static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
3587 struct snd_ctl_elem_info *uinfo)
3589 unsigned int items = sizeof(ca0132_voicefx_presets)
3590 / sizeof(struct ct_voicefx_preset);
3592 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3594 uinfo->value.enumerated.items = items;
3595 if (uinfo->value.enumerated.item >= items)
3596 uinfo->value.enumerated.item = items - 1;
3597 strcpy(uinfo->value.enumerated.name,
3598 ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
3602 static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
3603 struct snd_ctl_elem_value *ucontrol)
3605 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3606 struct ca0132_spec *spec = codec->spec;
3608 ucontrol->value.enumerated.item[0] = spec->voicefx_val;
3612 static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
3613 struct snd_ctl_elem_value *ucontrol)
3615 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3616 struct ca0132_spec *spec = codec->spec;
3618 int sel = ucontrol->value.enumerated.item[0];
3619 unsigned int items = sizeof(ca0132_voicefx_presets)
3620 / sizeof(struct ct_voicefx_preset);
3625 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n",
3626 sel, ca0132_voicefx_presets[sel].name);
3630 * Default needs to qualify with CrystalVoice state.
3632 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
3633 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
3634 ca0132_voicefx.reqs[i],
3635 ca0132_voicefx_presets[sel].vals[i]);
3641 spec->voicefx_val = sel;
3642 /* enable voice fx */
3643 ca0132_voicefx_set(codec, (sel ? 1 : 0));
3649 static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
3650 struct snd_ctl_elem_value *ucontrol)
3652 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3653 struct ca0132_spec *spec = codec->spec;
3654 hda_nid_t nid = get_amp_nid(kcontrol);
3655 int ch = get_amp_channels(kcontrol);
3656 long *valp = ucontrol->value.integer.value;
3659 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
3661 *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
3665 *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
3671 /* effects, include PE and CrystalVoice */
3672 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
3673 *valp = spec->effects_switch[nid - EFFECT_START_NID];
3678 if (nid == spec->input_pins[0]) {
3679 *valp = spec->cur_mic_boost;
3686 static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
3687 struct snd_ctl_elem_value *ucontrol)
3689 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3690 struct ca0132_spec *spec = codec->spec;
3691 hda_nid_t nid = get_amp_nid(kcontrol);
3692 int ch = get_amp_channels(kcontrol);
3693 long *valp = ucontrol->value.integer.value;
3696 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n",
3699 snd_hda_power_up(codec);
3701 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
3703 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
3707 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
3710 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
3715 if (nid == PLAY_ENHANCEMENT) {
3716 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3717 changed = ca0132_pe_switch_set(codec);
3722 if (nid == CRYSTAL_VOICE) {
3723 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3724 changed = ca0132_cvoice_switch_set(codec);
3728 /* out and in effects */
3729 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
3730 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
3731 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3732 changed = ca0132_effects_set(codec, nid, *valp);
3737 if (nid == spec->input_pins[0]) {
3738 spec->cur_mic_boost = *valp;
3740 /* Mic boost does not apply to Digital Mic */
3741 if (spec->cur_mic_type != DIGITAL_MIC)
3742 changed = ca0132_mic_boost_set(codec, *valp);
3747 snd_hda_power_down(codec);
3754 static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
3755 struct snd_ctl_elem_info *uinfo)
3757 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3758 struct ca0132_spec *spec = codec->spec;
3759 hda_nid_t nid = get_amp_nid(kcontrol);
3760 int ch = get_amp_channels(kcontrol);
3761 int dir = get_amp_direction(kcontrol);
3767 /* follow shared_out info */
3768 nid = spec->shared_out_nid;
3769 mutex_lock(&codec->control_mutex);
3770 pval = kcontrol->private_value;
3771 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3772 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3773 kcontrol->private_value = pval;
3774 mutex_unlock(&codec->control_mutex);
3777 /* follow shared_mic info */
3778 nid = spec->shared_mic_nid;
3779 mutex_lock(&codec->control_mutex);
3780 pval = kcontrol->private_value;
3781 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3782 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3783 kcontrol->private_value = pval;
3784 mutex_unlock(&codec->control_mutex);
3787 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3792 static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
3793 struct snd_ctl_elem_value *ucontrol)
3795 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3796 struct ca0132_spec *spec = codec->spec;
3797 hda_nid_t nid = get_amp_nid(kcontrol);
3798 int ch = get_amp_channels(kcontrol);
3799 long *valp = ucontrol->value.integer.value;
3801 /* store the left and right volume */
3803 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
3807 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
3813 static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
3814 struct snd_ctl_elem_value *ucontrol)
3816 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3817 struct ca0132_spec *spec = codec->spec;
3818 hda_nid_t nid = get_amp_nid(kcontrol);
3819 int ch = get_amp_channels(kcontrol);
3820 long *valp = ucontrol->value.integer.value;
3821 hda_nid_t shared_nid = 0;
3825 /* store the left and right volume */
3827 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
3831 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
3835 /* if effective conditions, then update hw immediately. */
3836 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
3838 int dir = get_amp_direction(kcontrol);
3841 snd_hda_power_up(codec);
3842 mutex_lock(&codec->control_mutex);
3843 pval = kcontrol->private_value;
3844 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
3846 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
3847 kcontrol->private_value = pval;
3848 mutex_unlock(&codec->control_mutex);
3849 snd_hda_power_down(codec);
3855 static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
3856 unsigned int size, unsigned int __user *tlv)
3858 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3859 struct ca0132_spec *spec = codec->spec;
3860 hda_nid_t nid = get_amp_nid(kcontrol);
3861 int ch = get_amp_channels(kcontrol);
3862 int dir = get_amp_direction(kcontrol);
3868 /* follow shared_out tlv */
3869 nid = spec->shared_out_nid;
3870 mutex_lock(&codec->control_mutex);
3871 pval = kcontrol->private_value;
3872 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3873 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3874 kcontrol->private_value = pval;
3875 mutex_unlock(&codec->control_mutex);
3878 /* follow shared_mic tlv */
3879 nid = spec->shared_mic_nid;
3880 mutex_lock(&codec->control_mutex);
3881 pval = kcontrol->private_value;
3882 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3883 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3884 kcontrol->private_value = pval;
3885 mutex_unlock(&codec->control_mutex);
3888 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3893 static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
3894 const char *pfx, int dir)
3896 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
3897 int type = dir ? HDA_INPUT : HDA_OUTPUT;
3898 struct snd_kcontrol_new knew =
3899 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
3900 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
3901 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3904 static int add_voicefx(struct hda_codec *codec)
3906 struct snd_kcontrol_new knew =
3907 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
3908 VOICEFX, 1, 0, HDA_INPUT);
3909 knew.info = ca0132_voicefx_info;
3910 knew.get = ca0132_voicefx_get;
3911 knew.put = ca0132_voicefx_put;
3912 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
3916 * When changing Node IDs for Mixer Controls below, make sure to update
3917 * Node IDs in ca0132_config() as well.
3919 static struct snd_kcontrol_new ca0132_mixer[] = {
3920 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
3921 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
3922 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
3923 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
3924 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
3925 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
3926 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
3927 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
3928 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
3929 0x12, 1, HDA_INPUT),
3930 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
3931 VNID_HP_SEL, 1, HDA_OUTPUT),
3932 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
3933 VNID_AMIC1_SEL, 1, HDA_INPUT),
3934 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
3935 VNID_HP_ASEL, 1, HDA_OUTPUT),
3936 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
3937 VNID_AMIC1_ASEL, 1, HDA_INPUT),
3941 static int ca0132_build_controls(struct hda_codec *codec)
3943 struct ca0132_spec *spec = codec->spec;
3947 /* Add Mixer controls */
3948 for (i = 0; i < spec->num_mixers; i++) {
3949 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
3954 /* Add in and out effects controls.
3955 * VoiceFX, PE and CrystalVoice are added separately.
3957 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
3958 for (i = 0; i < num_fx; i++) {
3959 err = add_fx_switch(codec, ca0132_effects[i].nid,
3960 ca0132_effects[i].name,
3961 ca0132_effects[i].direct);
3966 err = add_fx_switch(codec, PLAY_ENHANCEMENT, "PlayEnhancement", 0);
3970 err = add_fx_switch(codec, CRYSTAL_VOICE, "CrystalVoice", 1);
3976 #ifdef ENABLE_TUNING_CONTROLS
3977 add_tuning_ctls(codec);
3980 err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
3984 if (spec->dig_out) {
3985 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
3989 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
3992 /* spec->multiout.share_spdif = 1; */
3996 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
4006 static struct hda_pcm_stream ca0132_pcm_analog_playback = {
4011 .prepare = ca0132_playback_pcm_prepare,
4012 .cleanup = ca0132_playback_pcm_cleanup,
4013 .get_delay = ca0132_playback_pcm_delay,
4017 static struct hda_pcm_stream ca0132_pcm_analog_capture = {
4022 .prepare = ca0132_capture_pcm_prepare,
4023 .cleanup = ca0132_capture_pcm_cleanup,
4024 .get_delay = ca0132_capture_pcm_delay,
4028 static struct hda_pcm_stream ca0132_pcm_digital_playback = {
4033 .open = ca0132_dig_playback_pcm_open,
4034 .close = ca0132_dig_playback_pcm_close,
4035 .prepare = ca0132_dig_playback_pcm_prepare,
4036 .cleanup = ca0132_dig_playback_pcm_cleanup
4040 static struct hda_pcm_stream ca0132_pcm_digital_capture = {
4046 static int ca0132_build_pcms(struct hda_codec *codec)
4048 struct ca0132_spec *spec = codec->spec;
4049 struct hda_pcm *info;
4051 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog");
4054 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
4055 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
4056 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
4057 spec->multiout.max_channels;
4058 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4059 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4060 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
4062 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2");
4065 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4066 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4067 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
4069 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear");
4072 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4073 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4074 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
4076 if (!spec->dig_out && !spec->dig_in)
4079 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
4082 info->pcm_type = HDA_PCM_TYPE_SPDIF;
4083 if (spec->dig_out) {
4084 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
4085 ca0132_pcm_digital_playback;
4086 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
4089 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
4090 ca0132_pcm_digital_capture;
4091 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
4097 static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
4100 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
4101 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
4102 snd_hda_codec_write(codec, pin, 0,
4103 AC_VERB_SET_AMP_GAIN_MUTE,
4106 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
4107 snd_hda_codec_write(codec, dac, 0,
4108 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
4111 static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
4114 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
4115 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
4116 snd_hda_codec_write(codec, pin, 0,
4117 AC_VERB_SET_AMP_GAIN_MUTE,
4120 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
4121 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
4124 /* init to 0 dB and unmute. */
4125 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
4126 HDA_AMP_VOLMASK, 0x5a);
4127 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
4132 static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
4136 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
4137 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
4138 snd_hda_override_amp_caps(codec, nid, dir, caps);
4142 * Switch between Digital built-in mic and analog mic.
4144 static void ca0132_set_dmic(struct hda_codec *codec, int enable)
4146 struct ca0132_spec *spec = codec->spec;
4149 unsigned int oldval;
4151 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable);
4153 oldval = stop_mic1(codec);
4154 ca0132_set_vipsource(codec, 0);
4156 /* set DMic input as 2-ch */
4158 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4160 val = spec->dmic_ctl;
4162 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4163 VENDOR_CHIPIO_DMIC_CTL_SET, val);
4165 if (!(spec->dmic_ctl & 0x20))
4166 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
4168 /* set AMic input as mono */
4170 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4172 val = spec->dmic_ctl;
4173 /* clear bit7 and bit5 to disable dmic */
4175 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4176 VENDOR_CHIPIO_DMIC_CTL_SET, val);
4178 if (!(spec->dmic_ctl & 0x20))
4179 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
4181 ca0132_set_vipsource(codec, 1);
4182 resume_mic1(codec, oldval);
4186 * Initialization for Digital Mic.
4188 static void ca0132_init_dmic(struct hda_codec *codec)
4190 struct ca0132_spec *spec = codec->spec;
4193 /* Setup Digital Mic here, but don't enable.
4194 * Enable based on jack detect.
4197 /* MCLK uses MPIO1, set to enable.
4198 * Bit 2-0: MPIO select
4199 * Bit 3: set to disable
4203 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4204 VENDOR_CHIPIO_DMIC_MCLK_SET, val);
4206 /* Data1 uses MPIO3. Data2 not use
4207 * Bit 2-0: Data1 MPIO select
4208 * Bit 3: set disable Data1
4209 * Bit 6-4: Data2 MPIO select
4210 * Bit 7: set disable Data2
4213 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4214 VENDOR_CHIPIO_DMIC_PIN_SET, val);
4216 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
4217 * Bit 3-0: Channel mask
4218 * Bit 4: set for 48KHz, clear for 32KHz
4220 * Bit 6: set to select Data2, clear for Data1
4221 * Bit 7: set to enable DMic, clear for AMic
4224 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
4225 spec->dmic_ctl = val;
4226 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4227 VENDOR_CHIPIO_DMIC_CTL_SET, val);
4231 * Initialization for Analog Mic 2
4233 static void ca0132_init_analog_mic2(struct hda_codec *codec)
4235 struct ca0132_spec *spec = codec->spec;
4237 mutex_lock(&spec->chipio_mutex);
4238 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4239 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
4240 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4241 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
4242 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4243 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
4244 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4245 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D);
4246 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4247 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
4248 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4249 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
4250 mutex_unlock(&spec->chipio_mutex);
4253 static void ca0132_refresh_widget_caps(struct hda_codec *codec)
4255 struct ca0132_spec *spec = codec->spec;
4258 codec_dbg(codec, "ca0132_refresh_widget_caps.\n");
4259 snd_hda_codec_update_widgets(codec);
4261 for (i = 0; i < spec->multiout.num_dacs; i++)
4262 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
4264 for (i = 0; i < spec->num_outputs; i++)
4265 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
4267 for (i = 0; i < spec->num_inputs; i++) {
4268 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
4269 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
4274 * Setup default parameters for DSP
4276 static void ca0132_setup_defaults(struct hda_codec *codec)
4278 struct ca0132_spec *spec = codec->spec;
4283 if (spec->dsp_state != DSP_DOWNLOADED)
4286 /* out, in effects + voicefx */
4287 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
4288 for (idx = 0; idx < num_fx; idx++) {
4289 for (i = 0; i <= ca0132_effects[idx].params; i++) {
4290 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
4291 ca0132_effects[idx].reqs[i],
4292 ca0132_effects[idx].def_vals[i]);
4296 /*remove DSP headroom*/
4298 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
4300 /*set speaker EQ bypass attenuation*/
4301 dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
4303 /* set AMic1 and AMic2 as mono mic */
4305 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4306 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
4308 /* set AMic1 as CrystalVoice input */
4310 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4312 /* set WUH source */
4314 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
4318 * Initialization of flags in chip
4320 static void ca0132_init_flags(struct hda_codec *codec)
4322 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
4323 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
4324 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
4325 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
4326 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
4327 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
4331 * Initialization of parameters in chip
4333 static void ca0132_init_params(struct hda_codec *codec)
4335 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
4336 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
4339 static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
4341 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
4342 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
4343 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
4344 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
4345 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
4346 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
4348 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4349 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4350 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
4353 static bool ca0132_download_dsp_images(struct hda_codec *codec)
4355 bool dsp_loaded = false;
4356 const struct dsp_image_seg *dsp_os_image;
4357 const struct firmware *fw_entry;
4359 if (request_firmware(&fw_entry, EFX_FILE, codec->card->dev) != 0)
4362 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
4363 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
4364 pr_err("ca0132 dspload_image failed.\n");
4368 dsp_loaded = dspload_wait_loaded(codec);
4371 release_firmware(fw_entry);
4376 static void ca0132_download_dsp(struct hda_codec *codec)
4378 struct ca0132_spec *spec = codec->spec;
4380 #ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP
4384 if (spec->dsp_state == DSP_DOWNLOAD_FAILED)
4385 return; /* don't retry failures */
4387 chipio_enable_clocks(codec);
4388 spec->dsp_state = DSP_DOWNLOADING;
4389 if (!ca0132_download_dsp_images(codec))
4390 spec->dsp_state = DSP_DOWNLOAD_FAILED;
4392 spec->dsp_state = DSP_DOWNLOADED;
4394 if (spec->dsp_state == DSP_DOWNLOADED)
4395 ca0132_set_dsp_msr(codec, true);
4398 static void ca0132_process_dsp_response(struct hda_codec *codec,
4399 struct hda_jack_callback *callback)
4401 struct ca0132_spec *spec = codec->spec;
4403 codec_dbg(codec, "ca0132_process_dsp_response\n");
4404 if (spec->wait_scp) {
4405 if (dspio_get_response_data(codec) >= 0)
4409 dspio_clear_response_queue(codec);
4412 static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
4414 struct ca0132_spec *spec = codec->spec;
4416 /* Delay enabling the HP amp, to let the mic-detection
4417 * state machine run.
4419 cancel_delayed_work_sync(&spec->unsol_hp_work);
4420 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500));
4421 cb->tbl->block_report = 1;
4424 static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
4426 ca0132_select_mic(codec);
4429 static void ca0132_init_unsol(struct hda_codec *codec)
4431 struct ca0132_spec *spec = codec->spec;
4432 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback);
4433 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1,
4435 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP,
4436 ca0132_process_dsp_response);
4443 /* Sends before DSP download. */
4444 static struct hda_verb ca0132_base_init_verbs[] = {
4445 /*enable ct extension*/
4446 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
4451 static struct hda_verb ca0132_base_exit_verbs[] = {
4453 {0x01, AC_VERB_SET_POWER_STATE, 0x03},
4454 /*disable ct extension*/
4455 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
4459 /* Other verbs tables. Sends after DSP download. */
4460 static struct hda_verb ca0132_init_verbs0[] = {
4461 /* chip init verbs */
4462 {0x15, 0x70D, 0xF0},
4463 {0x15, 0x70E, 0xFE},
4464 {0x15, 0x707, 0x75},
4465 {0x15, 0x707, 0xD3},
4466 {0x15, 0x707, 0x09},
4467 {0x15, 0x707, 0x53},
4468 {0x15, 0x707, 0xD4},
4469 {0x15, 0x707, 0xEF},
4470 {0x15, 0x707, 0x75},
4471 {0x15, 0x707, 0xD3},
4472 {0x15, 0x707, 0x09},
4473 {0x15, 0x707, 0x02},
4474 {0x15, 0x707, 0x37},
4475 {0x15, 0x707, 0x78},
4476 {0x15, 0x53C, 0xCE},
4477 {0x15, 0x575, 0xC9},
4478 {0x15, 0x53D, 0xCE},
4479 {0x15, 0x5B7, 0xC9},
4480 {0x15, 0x70D, 0xE8},
4481 {0x15, 0x70E, 0xFE},
4482 {0x15, 0x707, 0x02},
4483 {0x15, 0x707, 0x68},
4484 {0x15, 0x707, 0x62},
4485 {0x15, 0x53A, 0xCE},
4486 {0x15, 0x546, 0xC9},
4487 {0x15, 0x53B, 0xCE},
4488 {0x15, 0x5E8, 0xC9},
4489 {0x15, 0x717, 0x0D},
4490 {0x15, 0x718, 0x20},
4494 static void ca0132_init_chip(struct hda_codec *codec)
4496 struct ca0132_spec *spec = codec->spec;
4501 mutex_init(&spec->chipio_mutex);
4503 spec->cur_out_type = SPEAKER_OUT;
4504 spec->cur_mic_type = DIGITAL_MIC;
4505 spec->cur_mic_boost = 0;
4507 for (i = 0; i < VNODES_COUNT; i++) {
4508 spec->vnode_lvol[i] = 0x5a;
4509 spec->vnode_rvol[i] = 0x5a;
4510 spec->vnode_lswitch[i] = 0;
4511 spec->vnode_rswitch[i] = 0;
4515 * Default states for effects are in ca0132_effects[].
4517 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
4518 for (i = 0; i < num_fx; i++) {
4519 on = (unsigned int)ca0132_effects[i].reqs[0];
4520 spec->effects_switch[i] = on ? 1 : 0;
4523 spec->voicefx_val = 0;
4524 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
4525 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
4527 #ifdef ENABLE_TUNING_CONTROLS
4528 ca0132_init_tuning_defaults(codec);
4532 static void ca0132_exit_chip(struct hda_codec *codec)
4534 /* put any chip cleanup stuffs here. */
4536 if (dspload_is_loaded(codec))
4540 static int ca0132_init(struct hda_codec *codec)
4542 struct ca0132_spec *spec = codec->spec;
4543 struct auto_pin_cfg *cfg = &spec->autocfg;
4546 if (spec->dsp_state != DSP_DOWNLOAD_FAILED)
4547 spec->dsp_state = DSP_DOWNLOAD_INIT;
4548 spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
4550 snd_hda_power_up_pm(codec);
4552 ca0132_init_unsol(codec);
4554 ca0132_init_params(codec);
4555 ca0132_init_flags(codec);
4556 snd_hda_sequence_write(codec, spec->base_init_verbs);
4557 ca0132_download_dsp(codec);
4558 ca0132_refresh_widget_caps(codec);
4559 ca0132_setup_defaults(codec);
4560 ca0132_init_analog_mic2(codec);
4561 ca0132_init_dmic(codec);
4563 for (i = 0; i < spec->num_outputs; i++)
4564 init_output(codec, spec->out_pins[i], spec->dacs[0]);
4566 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
4568 for (i = 0; i < spec->num_inputs; i++)
4569 init_input(codec, spec->input_pins[i], spec->adcs[i]);
4571 init_input(codec, cfg->dig_in_pin, spec->dig_in);
4573 snd_hda_sequence_write(codec, spec->chip_init_verbs);
4574 snd_hda_sequence_write(codec, spec->spec_init_verbs);
4576 ca0132_select_out(codec);
4577 ca0132_select_mic(codec);
4579 snd_hda_jack_report_sync(codec);
4581 snd_hda_power_down_pm(codec);
4586 static void ca0132_free(struct hda_codec *codec)
4588 struct ca0132_spec *spec = codec->spec;
4590 cancel_delayed_work_sync(&spec->unsol_hp_work);
4591 snd_hda_power_up(codec);
4592 snd_hda_sequence_write(codec, spec->base_exit_verbs);
4593 ca0132_exit_chip(codec);
4594 snd_hda_power_down(codec);
4595 kfree(spec->spec_init_verbs);
4599 static struct hda_codec_ops ca0132_patch_ops = {
4600 .build_controls = ca0132_build_controls,
4601 .build_pcms = ca0132_build_pcms,
4602 .init = ca0132_init,
4603 .free = ca0132_free,
4604 .unsol_event = snd_hda_jack_unsol_event,
4607 static void ca0132_config(struct hda_codec *codec)
4609 struct ca0132_spec *spec = codec->spec;
4610 struct auto_pin_cfg *cfg = &spec->autocfg;
4612 spec->dacs[0] = 0x2;
4613 spec->dacs[1] = 0x3;
4614 spec->dacs[2] = 0x4;
4616 spec->multiout.dac_nids = spec->dacs;
4617 spec->multiout.num_dacs = 3;
4618 spec->multiout.max_channels = 2;
4620 spec->num_outputs = 2;
4621 spec->out_pins[0] = 0x0b; /* speaker out */
4622 if (spec->quirk == QUIRK_ALIENWARE) {
4623 codec_dbg(codec, "ca0132_config: QUIRK_ALIENWARE applied.\n");
4624 spec->out_pins[1] = 0x0f;
4626 spec->out_pins[1] = 0x10; /* headphone out */
4628 spec->shared_out_nid = 0x2;
4629 spec->unsol_tag_hp = spec->out_pins[1];
4631 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
4632 spec->adcs[1] = 0x8; /* analog mic2 */
4633 spec->adcs[2] = 0xa; /* what u hear */
4635 spec->num_inputs = 3;
4636 spec->input_pins[0] = 0x12;
4637 spec->input_pins[1] = 0x11;
4638 spec->input_pins[2] = 0x13;
4639 spec->shared_mic_nid = 0x7;
4640 spec->unsol_tag_amic1 = spec->input_pins[0];
4643 spec->dig_out = 0x05;
4644 spec->multiout.dig_out_nid = spec->dig_out;
4645 cfg->dig_out_pins[0] = 0x0c;
4647 cfg->dig_out_type[0] = HDA_PCM_TYPE_SPDIF;
4648 spec->dig_in = 0x09;
4649 cfg->dig_in_pin = 0x0e;
4650 cfg->dig_in_type = HDA_PCM_TYPE_SPDIF;
4653 static int ca0132_prepare_verbs(struct hda_codec *codec)
4655 /* Verbs + terminator (an empty element) */
4656 #define NUM_SPEC_VERBS 4
4657 struct ca0132_spec *spec = codec->spec;
4659 spec->chip_init_verbs = ca0132_init_verbs0;
4660 spec->spec_init_verbs = kzalloc(sizeof(struct hda_verb) * NUM_SPEC_VERBS, GFP_KERNEL);
4661 if (!spec->spec_init_verbs)
4664 /* HP jack autodetection */
4665 spec->spec_init_verbs[0].nid = spec->unsol_tag_hp;
4666 spec->spec_init_verbs[0].param = AC_VERB_SET_UNSOLICITED_ENABLE;
4667 spec->spec_init_verbs[0].verb = AC_USRSP_EN | spec->unsol_tag_hp;
4669 /* MIC1 jack autodetection */
4670 spec->spec_init_verbs[1].nid = spec->unsol_tag_amic1;
4671 spec->spec_init_verbs[1].param = AC_VERB_SET_UNSOLICITED_ENABLE;
4672 spec->spec_init_verbs[1].verb = AC_USRSP_EN | spec->unsol_tag_amic1;
4675 spec->spec_init_verbs[2].nid = 0x0b;
4676 spec->spec_init_verbs[2].param = 0x78D;
4677 spec->spec_init_verbs[2].verb = 0x00;
4679 /* Previously commented configuration */
4681 spec->spec_init_verbs[3].nid = 0x0b;
4682 spec->spec_init_verbs[3].param = AC_VERB_SET_EAPD_BTLENABLE;
4683 spec->spec_init_verbs[3].verb = 0x02;
4685 spec->spec_init_verbs[4].nid = 0x10;
4686 spec->spec_init_verbs[4].param = 0x78D;
4687 spec->spec_init_verbs[4].verb = 0x02;
4689 spec->spec_init_verbs[5].nid = 0x10;
4690 spec->spec_init_verbs[5].param = AC_VERB_SET_EAPD_BTLENABLE;
4691 spec->spec_init_verbs[5].verb = 0x02;
4694 /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */
4698 static int patch_ca0132(struct hda_codec *codec)
4700 struct ca0132_spec *spec;
4702 const struct snd_pci_quirk *quirk;
4704 codec_dbg(codec, "patch_ca0132\n");
4706 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
4710 spec->codec = codec;
4712 codec->patch_ops = ca0132_patch_ops;
4713 codec->pcm_format_first = 1;
4714 codec->no_sticky_stream = 1;
4716 /* Detect codec quirk */
4717 quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks);
4719 spec->quirk = quirk->value;
4721 spec->quirk = QUIRK_NONE;
4723 spec->dsp_state = DSP_DOWNLOAD_INIT;
4724 spec->num_mixers = 1;
4725 spec->mixers[0] = ca0132_mixer;
4727 spec->base_init_verbs = ca0132_base_init_verbs;
4728 spec->base_exit_verbs = ca0132_base_exit_verbs;
4730 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
4732 ca0132_init_chip(codec);
4734 ca0132_config(codec);
4736 err = ca0132_prepare_verbs(codec);
4740 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
4750 static struct hda_codec_preset snd_hda_preset_ca0132[] = {
4751 { .id = 0x11020011, .name = "CA0132", .patch = patch_ca0132 },
4755 MODULE_ALIAS("snd-hda-codec-id:11020011");
4757 MODULE_LICENSE("GPL");
4758 MODULE_DESCRIPTION("Creative Sound Core3D codec");
4760 static struct hda_codec_driver ca0132_driver = {
4761 .preset = snd_hda_preset_ca0132,
4764 module_hda_codec_driver(ca0132_driver);