3 * hda_intel.c - Implementation of primary alsa driver code base
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
48 #include <linux/pm_runtime.h>
49 #include <linux/clocksource.h>
50 #include <linux/time.h>
51 #include <linux/completion.h>
54 /* for snoop control */
55 #include <asm/pgtable.h>
56 #include <asm/cacheflush.h>
58 #include <sound/core.h>
59 #include <sound/initval.h>
60 #include <sound/hdaudio.h>
61 #include <sound/hda_i915.h>
62 #include <linux/vgaarb.h>
63 #include <linux/vga_switcheroo.h>
64 #include <linux/firmware.h>
65 #include "hda_codec.h"
66 #include "hda_controller.h"
67 #include "hda_intel.h"
69 #define CREATE_TRACE_POINTS
70 #include "hda_intel_trace.h"
72 /* position fix mode */
81 /* Defines for ATI HD Audio support in SB450 south bridge */
82 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
83 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
85 /* Defines for Nvidia HDA support */
86 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
87 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
88 #define NVIDIA_HDA_ISTRM_COH 0x4d
89 #define NVIDIA_HDA_OSTRM_COH 0x4c
90 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
92 /* Defines for Intel SCH HDA snoop control */
93 #define INTEL_HDA_CGCTL 0x48
94 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)
95 #define INTEL_SCH_HDA_DEVC 0x78
96 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
98 /* Define IN stream 0 FIFO size offset in VIA controller */
99 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
100 /* Define VIA HD Audio Device ID*/
101 #define VIA_HDAC_DEVICE_ID 0x3288
103 /* max number of SDs */
104 /* ICH, ATI and VIA have 4 playback and 4 capture */
105 #define ICH6_NUM_CAPTURE 4
106 #define ICH6_NUM_PLAYBACK 4
108 /* ULI has 6 playback and 5 capture */
109 #define ULI_NUM_CAPTURE 5
110 #define ULI_NUM_PLAYBACK 6
112 /* ATI HDMI may have up to 8 playbacks and 0 capture */
113 #define ATIHDMI_NUM_CAPTURE 0
114 #define ATIHDMI_NUM_PLAYBACK 8
116 /* TERA has 4 playback and 3 capture */
117 #define TERA_NUM_CAPTURE 3
118 #define TERA_NUM_PLAYBACK 4
121 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
122 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
123 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
124 static char *model[SNDRV_CARDS];
125 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
126 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
127 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
128 static int probe_only[SNDRV_CARDS];
129 static int jackpoll_ms[SNDRV_CARDS];
130 static bool single_cmd;
131 static int enable_msi = -1;
132 #ifdef CONFIG_SND_HDA_PATCH_LOADER
133 static char *patch[SNDRV_CARDS];
135 #ifdef CONFIG_SND_HDA_INPUT_BEEP
136 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
137 CONFIG_SND_HDA_INPUT_BEEP_MODE};
140 module_param_array(index, int, NULL, 0444);
141 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
142 module_param_array(id, charp, NULL, 0444);
143 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
144 module_param_array(enable, bool, NULL, 0444);
145 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
146 module_param_array(model, charp, NULL, 0444);
147 MODULE_PARM_DESC(model, "Use the given board model.");
148 module_param_array(position_fix, int, NULL, 0444);
149 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
150 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
151 module_param_array(bdl_pos_adj, int, NULL, 0644);
152 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
153 module_param_array(probe_mask, int, NULL, 0444);
154 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
155 module_param_array(probe_only, int, NULL, 0444);
156 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
157 module_param_array(jackpoll_ms, int, NULL, 0444);
158 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
159 module_param(single_cmd, bool, 0444);
160 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
161 "(for debugging only).");
162 module_param(enable_msi, bint, 0444);
163 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
164 #ifdef CONFIG_SND_HDA_PATCH_LOADER
165 module_param_array(patch, charp, NULL, 0444);
166 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
168 #ifdef CONFIG_SND_HDA_INPUT_BEEP
169 module_param_array(beep_mode, bool, NULL, 0444);
170 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
171 "(0=off, 1=on) (default=1).");
175 static int param_set_xint(const char *val, const struct kernel_param *kp);
176 static const struct kernel_param_ops param_ops_xint = {
177 .set = param_set_xint,
178 .get = param_get_int,
180 #define param_check_xint param_check_int
182 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
183 module_param(power_save, xint, 0644);
184 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
185 "(in second, 0 = disable).");
187 /* reset the HD-audio controller in power save mode.
188 * this may give more power-saving, but will take longer time to
191 static bool power_save_controller = 1;
192 module_param(power_save_controller, bool, 0644);
193 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
196 #endif /* CONFIG_PM */
198 static int align_buffer_size = -1;
199 module_param(align_buffer_size, bint, 0644);
200 MODULE_PARM_DESC(align_buffer_size,
201 "Force buffer and period sizes to be multiple of 128 bytes.");
204 static int hda_snoop = -1;
205 module_param_named(snoop, hda_snoop, bint, 0444);
206 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
208 #define hda_snoop true
212 MODULE_LICENSE("GPL");
213 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
247 MODULE_DESCRIPTION("Intel HDA driver");
249 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
250 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
251 #define SUPPORT_VGA_SWITCHEROO
267 AZX_DRIVER_ATIHDMI_NS,
277 AZX_NUM_DRIVERS, /* keep this as last entry */
280 #define azx_get_snoop_type(chip) \
281 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
282 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
284 /* quirks for old Intel chipsets */
285 #define AZX_DCAPS_INTEL_ICH \
286 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
288 /* quirks for Intel PCH */
289 #define AZX_DCAPS_INTEL_PCH_NOPM \
290 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
291 AZX_DCAPS_REVERSE_ASSIGN | AZX_DCAPS_SNOOP_TYPE(SCH))
293 #define AZX_DCAPS_INTEL_PCH \
294 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
296 #define AZX_DCAPS_INTEL_HASWELL \
297 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
298 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
299 AZX_DCAPS_SNOOP_TYPE(SCH))
301 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
302 #define AZX_DCAPS_INTEL_BROADWELL \
303 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
304 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
305 AZX_DCAPS_SNOOP_TYPE(SCH))
307 #define AZX_DCAPS_INTEL_BAYTRAIL \
308 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_I915_POWERWELL)
310 #define AZX_DCAPS_INTEL_BRASWELL \
311 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL)
313 #define AZX_DCAPS_INTEL_SKYLAKE \
314 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
315 AZX_DCAPS_I915_POWERWELL)
317 #define AZX_DCAPS_INTEL_BROXTON \
318 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
319 AZX_DCAPS_I915_POWERWELL)
321 /* quirks for ATI SB / AMD Hudson */
322 #define AZX_DCAPS_PRESET_ATI_SB \
323 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
324 AZX_DCAPS_SNOOP_TYPE(ATI))
326 /* quirks for ATI/AMD HDMI */
327 #define AZX_DCAPS_PRESET_ATI_HDMI \
328 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
331 /* quirks for ATI HDMI with snoop off */
332 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
333 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
335 /* quirks for Nvidia */
336 #define AZX_DCAPS_PRESET_NVIDIA \
337 (AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI | /*AZX_DCAPS_ALIGN_BUFSIZE |*/ \
338 AZX_DCAPS_NO_64BIT | AZX_DCAPS_CORBRP_SELF_CLEAR |\
339 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
341 #define AZX_DCAPS_PRESET_CTHDA \
342 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
343 AZX_DCAPS_NO_64BIT |\
344 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
347 * vga_switcheroo support
349 #ifdef SUPPORT_VGA_SWITCHEROO
350 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
352 #define use_vga_switcheroo(chip) 0
355 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
356 ((pci)->device == 0x0c0c) || \
357 ((pci)->device == 0x0d0c) || \
358 ((pci)->device == 0x160c))
360 #define IS_SKL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa170)
361 #define IS_SKL_LP(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9d70)
362 #define IS_KBL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa171)
363 #define IS_KBL_LP(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9d71)
364 #define IS_KBL_H(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa2f0)
365 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
366 #define IS_SKL_PLUS(pci) (IS_SKL(pci) || IS_SKL_LP(pci) || IS_BXT(pci)) || \
367 IS_KBL(pci) || IS_KBL_LP(pci) || IS_KBL_H(pci)
369 static char *driver_short_names[] = {
370 [AZX_DRIVER_ICH] = "HDA Intel",
371 [AZX_DRIVER_PCH] = "HDA Intel PCH",
372 [AZX_DRIVER_SCH] = "HDA Intel MID",
373 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
374 [AZX_DRIVER_ATI] = "HDA ATI SB",
375 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
376 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
377 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
378 [AZX_DRIVER_SIS] = "HDA SIS966",
379 [AZX_DRIVER_ULI] = "HDA ULI M5461",
380 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
381 [AZX_DRIVER_TERA] = "HDA Teradici",
382 [AZX_DRIVER_CTX] = "HDA Creative",
383 [AZX_DRIVER_CTHDA] = "HDA Creative",
384 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
385 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
389 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
395 if (!dmab || !dmab->area || !dmab->bytes)
398 #ifdef CONFIG_SND_DMA_SGBUF
399 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
400 struct snd_sg_buf *sgbuf = dmab->private_data;
401 if (chip->driver_type == AZX_DRIVER_CMEDIA)
402 return; /* deal with only CORB/RIRB buffers */
404 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
406 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
411 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
413 set_memory_wc((unsigned long)dmab->area, pages);
415 set_memory_wb((unsigned long)dmab->area, pages);
418 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
421 __mark_pages_wc(chip, buf, on);
423 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
424 struct snd_pcm_substream *substream, bool on)
426 if (azx_dev->wc_marked != on) {
427 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
428 azx_dev->wc_marked = on;
432 /* NOP for other archs */
433 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
437 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
438 struct snd_pcm_substream *substream, bool on)
443 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
446 * initialize the PCI registers
448 /* update bits in a PCI register byte */
449 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
450 unsigned char mask, unsigned char val)
454 pci_read_config_byte(pci, reg, &data);
456 data |= (val & mask);
457 pci_write_config_byte(pci, reg, data);
460 static void azx_init_pci(struct azx *chip)
462 int snoop_type = azx_get_snoop_type(chip);
464 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
465 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
466 * Ensuring these bits are 0 clears playback static on some HD Audio
468 * The PCI register TCSEL is defined in the Intel manuals.
470 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
471 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
472 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
475 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
476 * we need to enable snoop.
478 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
479 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
481 update_pci_byte(chip->pci,
482 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
483 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
486 /* For NVIDIA HDA, enable snoop */
487 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
488 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
490 update_pci_byte(chip->pci,
491 NVIDIA_HDA_TRANSREG_ADDR,
492 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
493 update_pci_byte(chip->pci,
494 NVIDIA_HDA_ISTRM_COH,
495 0x01, NVIDIA_HDA_ENABLE_COHBIT);
496 update_pci_byte(chip->pci,
497 NVIDIA_HDA_OSTRM_COH,
498 0x01, NVIDIA_HDA_ENABLE_COHBIT);
501 /* Enable SCH/PCH snoop if needed */
502 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
503 unsigned short snoop;
504 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
505 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
506 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
507 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
508 if (!azx_snoop(chip))
509 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
510 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
511 pci_read_config_word(chip->pci,
512 INTEL_SCH_HDA_DEVC, &snoop);
514 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
515 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
516 "Disabled" : "Enabled");
521 * In BXT-P A0, HD-Audio DMA requests is later than expected,
522 * and makes an audio stream sensitive to system latencies when
523 * 24/32 bits are playing.
524 * Adjusting threshold of DMA fifo to force the DMA request
525 * sooner to improve latency tolerance at the expense of power.
527 static void bxt_reduce_dma_latency(struct azx *chip)
531 val = azx_readl(chip, SKL_EM4L);
533 azx_writel(chip, SKL_EM4L, val);
536 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
538 struct hdac_bus *bus = azx_bus(chip);
539 struct pci_dev *pci = chip->pci;
542 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
543 snd_hdac_set_codec_wakeup(bus, true);
544 if (IS_SKL_PLUS(pci)) {
545 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
546 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
547 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
549 azx_init_chip(chip, full_reset);
550 if (IS_SKL_PLUS(pci)) {
551 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
552 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
553 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
555 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
556 snd_hdac_set_codec_wakeup(bus, false);
558 /* reduce dma latency to avoid noise */
560 bxt_reduce_dma_latency(chip);
563 /* calculate runtime delay from LPIB */
564 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
567 struct snd_pcm_substream *substream = azx_dev->core.substream;
568 int stream = substream->stream;
569 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
572 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
573 delay = pos - lpib_pos;
575 delay = lpib_pos - pos;
577 if (delay >= azx_dev->core.delay_negative_threshold)
580 delay += azx_dev->core.bufsize;
583 if (delay >= azx_dev->core.period_bytes) {
584 dev_info(chip->card->dev,
585 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
586 delay, azx_dev->core.period_bytes);
588 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
589 chip->get_delay[stream] = NULL;
592 return bytes_to_frames(substream->runtime, delay);
595 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
597 /* called from IRQ */
598 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
600 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
603 ok = azx_position_ok(chip, azx_dev);
605 azx_dev->irq_pending = 0;
607 } else if (ok == 0) {
608 /* bogus IRQ, process it later */
609 azx_dev->irq_pending = 1;
610 schedule_work(&hda->irq_pending_work);
615 /* Enable/disable i915 display power for the link */
616 static int azx_intel_link_power(struct azx *chip, bool enable)
618 struct hdac_bus *bus = azx_bus(chip);
620 return snd_hdac_display_power(bus, enable);
624 * Check whether the current DMA position is acceptable for updating
625 * periods. Returns non-zero if it's OK.
627 * Many HD-audio controllers appear pretty inaccurate about
628 * the update-IRQ timing. The IRQ is issued before actually the
629 * data is processed. So, we need to process it afterwords in a
632 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
634 struct snd_pcm_substream *substream = azx_dev->core.substream;
635 int stream = substream->stream;
639 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
640 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
641 return -1; /* bogus (too early) interrupt */
643 if (chip->get_position[stream])
644 pos = chip->get_position[stream](chip, azx_dev);
645 else { /* use the position buffer as default */
646 pos = azx_get_pos_posbuf(chip, azx_dev);
647 if (!pos || pos == (u32)-1) {
648 dev_info(chip->card->dev,
649 "Invalid position buffer, using LPIB read method instead.\n");
650 chip->get_position[stream] = azx_get_pos_lpib;
651 if (chip->get_position[0] == azx_get_pos_lpib &&
652 chip->get_position[1] == azx_get_pos_lpib)
653 azx_bus(chip)->use_posbuf = false;
654 pos = azx_get_pos_lpib(chip, azx_dev);
655 chip->get_delay[stream] = NULL;
657 chip->get_position[stream] = azx_get_pos_posbuf;
658 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
659 chip->get_delay[stream] = azx_get_delay_from_lpib;
663 if (pos >= azx_dev->core.bufsize)
666 if (WARN_ONCE(!azx_dev->core.period_bytes,
667 "hda-intel: zero azx_dev->period_bytes"))
668 return -1; /* this shouldn't happen! */
669 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
670 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
671 /* NG - it's below the first next period boundary */
672 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1;
673 azx_dev->core.start_wallclk += wallclk;
674 return 1; /* OK, it's fine */
678 * The work for pending PCM period updates.
680 static void azx_irq_pending_work(struct work_struct *work)
682 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
683 struct azx *chip = &hda->chip;
684 struct hdac_bus *bus = azx_bus(chip);
685 struct hdac_stream *s;
688 if (!hda->irq_pending_warned) {
689 dev_info(chip->card->dev,
690 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
692 hda->irq_pending_warned = 1;
697 spin_lock_irq(&bus->reg_lock);
698 list_for_each_entry(s, &bus->stream_list, list) {
699 struct azx_dev *azx_dev = stream_to_azx_dev(s);
700 if (!azx_dev->irq_pending ||
704 ok = azx_position_ok(chip, azx_dev);
706 azx_dev->irq_pending = 0;
707 spin_unlock(&bus->reg_lock);
708 snd_pcm_period_elapsed(s->substream);
709 spin_lock(&bus->reg_lock);
711 pending = 0; /* too early */
715 spin_unlock_irq(&bus->reg_lock);
722 /* clear irq_pending flags and assure no on-going workq */
723 static void azx_clear_irq_pending(struct azx *chip)
725 struct hdac_bus *bus = azx_bus(chip);
726 struct hdac_stream *s;
728 spin_lock_irq(&bus->reg_lock);
729 list_for_each_entry(s, &bus->stream_list, list) {
730 struct azx_dev *azx_dev = stream_to_azx_dev(s);
731 azx_dev->irq_pending = 0;
733 spin_unlock_irq(&bus->reg_lock);
736 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
738 struct hdac_bus *bus = azx_bus(chip);
740 if (request_irq(chip->pci->irq, azx_interrupt,
741 chip->msi ? 0 : IRQF_SHARED,
742 KBUILD_MODNAME, chip)) {
743 dev_err(chip->card->dev,
744 "unable to grab IRQ %d, disabling device\n",
747 snd_card_disconnect(chip->card);
750 bus->irq = chip->pci->irq;
751 pci_intx(chip->pci, !chip->msi);
755 /* get the current DMA position with correction on VIA chips */
756 static unsigned int azx_via_get_position(struct azx *chip,
757 struct azx_dev *azx_dev)
759 unsigned int link_pos, mini_pos, bound_pos;
760 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
761 unsigned int fifo_size;
763 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
764 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
765 /* Playback, no problem using link position */
771 * use mod to get the DMA position just like old chipset
773 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
774 mod_dma_pos %= azx_dev->core.period_bytes;
776 /* azx_dev->fifo_size can't get FIFO size of in stream.
777 * Get from base address + offset.
779 fifo_size = readw(azx_bus(chip)->remap_addr +
780 VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
782 if (azx_dev->insufficient) {
783 /* Link position never gather than FIFO size */
784 if (link_pos <= fifo_size)
787 azx_dev->insufficient = 0;
790 if (link_pos <= fifo_size)
791 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
793 mini_pos = link_pos - fifo_size;
795 /* Find nearest previous boudary */
796 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
797 mod_link_pos = link_pos % azx_dev->core.period_bytes;
798 if (mod_link_pos >= fifo_size)
799 bound_pos = link_pos - mod_link_pos;
800 else if (mod_dma_pos >= mod_mini_pos)
801 bound_pos = mini_pos - mod_mini_pos;
803 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
804 if (bound_pos >= azx_dev->core.bufsize)
808 /* Calculate real DMA position we want */
809 return bound_pos + mod_dma_pos;
813 static DEFINE_MUTEX(card_list_lock);
814 static LIST_HEAD(card_list);
816 static void azx_add_card_list(struct azx *chip)
818 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
819 mutex_lock(&card_list_lock);
820 list_add(&hda->list, &card_list);
821 mutex_unlock(&card_list_lock);
824 static void azx_del_card_list(struct azx *chip)
826 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
827 mutex_lock(&card_list_lock);
828 list_del_init(&hda->list);
829 mutex_unlock(&card_list_lock);
832 /* trigger power-save check at writing parameter */
833 static int param_set_xint(const char *val, const struct kernel_param *kp)
835 struct hda_intel *hda;
837 int prev = power_save;
838 int ret = param_set_int(val, kp);
840 if (ret || prev == power_save)
843 mutex_lock(&card_list_lock);
844 list_for_each_entry(hda, &card_list, list) {
846 if (!hda->probe_continued || chip->disabled)
848 snd_hda_set_power_save(&chip->bus, power_save * 1000);
850 mutex_unlock(&card_list_lock);
854 #define azx_add_card_list(chip) /* NOP */
855 #define azx_del_card_list(chip) /* NOP */
856 #endif /* CONFIG_PM */
858 /* Intel HSW/BDW display HDA controller is in GPU. Both its power and link BCLK
859 * depends on GPU. Two Extended Mode registers EM4 (M value) and EM5 (N Value)
860 * are used to convert CDClk (Core Display Clock) to 24MHz BCLK:
861 * BCLK = CDCLK * M / N
862 * The values will be lost when the display power well is disabled and need to
863 * be restored to avoid abnormal playback speed.
865 static void haswell_set_bclk(struct hda_intel *hda)
867 struct azx *chip = &hda->chip;
869 unsigned int bclk_m, bclk_n;
871 if (!hda->need_i915_power)
874 cdclk_freq = snd_hdac_get_display_clk(azx_bus(chip));
875 switch (cdclk_freq) {
882 default: /* default CDCLK 450MHz */
898 azx_writew(chip, HSW_EM4, bclk_m);
899 azx_writew(chip, HSW_EM5, bclk_n);
902 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
906 static int azx_suspend(struct device *dev)
908 struct snd_card *card = dev_get_drvdata(dev);
910 struct hda_intel *hda;
911 struct hdac_bus *bus;
916 chip = card->private_data;
917 hda = container_of(chip, struct hda_intel, chip);
918 if (chip->disabled || hda->init_failed || !chip->running)
922 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
923 azx_clear_irq_pending(chip);
925 azx_enter_link_reset(chip);
927 free_irq(bus->irq, chip);
932 pci_disable_msi(chip->pci);
933 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
934 && hda->need_i915_power)
935 snd_hdac_display_power(bus, false);
937 trace_azx_suspend(chip);
941 static int azx_resume(struct device *dev)
943 struct pci_dev *pci = to_pci_dev(dev);
944 struct snd_card *card = dev_get_drvdata(dev);
946 struct hda_intel *hda;
947 struct hdac_bus *bus;
952 chip = card->private_data;
953 hda = container_of(chip, struct hda_intel, chip);
955 if (chip->disabled || hda->init_failed || !chip->running)
958 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
959 snd_hdac_display_power(bus, true);
960 if (hda->need_i915_power)
961 haswell_set_bclk(hda);
965 if (pci_enable_msi(pci) < 0)
967 if (azx_acquire_irq(chip, 1) < 0)
971 hda_intel_init_chip(chip, true);
973 /* power down again for link-controlled chips */
974 if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
975 !hda->need_i915_power)
976 snd_hdac_display_power(bus, false);
978 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
980 trace_azx_resume(chip);
983 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
985 #ifdef CONFIG_PM_SLEEP
986 /* put codec down to D3 at hibernation for Intel SKL+;
987 * otherwise BIOS may still access the codec and screw up the driver
989 static int azx_freeze_noirq(struct device *dev)
991 struct pci_dev *pci = to_pci_dev(dev);
993 if (IS_SKL_PLUS(pci))
994 pci_set_power_state(pci, PCI_D3hot);
999 static int azx_thaw_noirq(struct device *dev)
1001 struct pci_dev *pci = to_pci_dev(dev);
1003 if (IS_SKL_PLUS(pci))
1004 pci_set_power_state(pci, PCI_D0);
1008 #endif /* CONFIG_PM_SLEEP */
1011 static int azx_runtime_suspend(struct device *dev)
1013 struct snd_card *card = dev_get_drvdata(dev);
1015 struct hda_intel *hda;
1020 chip = card->private_data;
1021 hda = container_of(chip, struct hda_intel, chip);
1022 if (chip->disabled || hda->init_failed)
1025 if (!azx_has_pm_runtime(chip))
1028 /* enable controller wake up event */
1029 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1032 azx_stop_chip(chip);
1033 azx_enter_link_reset(chip);
1034 azx_clear_irq_pending(chip);
1035 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
1036 && hda->need_i915_power)
1037 snd_hdac_display_power(azx_bus(chip), false);
1039 trace_azx_runtime_suspend(chip);
1043 static int azx_runtime_resume(struct device *dev)
1045 struct snd_card *card = dev_get_drvdata(dev);
1047 struct hda_intel *hda;
1048 struct hdac_bus *bus;
1049 struct hda_codec *codec;
1055 chip = card->private_data;
1056 hda = container_of(chip, struct hda_intel, chip);
1057 bus = azx_bus(chip);
1058 if (chip->disabled || hda->init_failed)
1061 if (!azx_has_pm_runtime(chip))
1064 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1065 snd_hdac_display_power(bus, true);
1066 if (hda->need_i915_power)
1067 haswell_set_bclk(hda);
1070 /* Read STATESTS before controller reset */
1071 status = azx_readw(chip, STATESTS);
1074 hda_intel_init_chip(chip, true);
1077 list_for_each_codec(codec, &chip->bus)
1078 if (status & (1 << codec->addr))
1079 schedule_delayed_work(&codec->jackpoll_work,
1080 codec->jackpoll_interval);
1083 /* disable controller Wake Up event*/
1084 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1085 ~STATESTS_INT_MASK);
1087 /* power down again for link-controlled chips */
1088 if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
1089 !hda->need_i915_power)
1090 snd_hdac_display_power(bus, false);
1092 trace_azx_runtime_resume(chip);
1096 static int azx_runtime_idle(struct device *dev)
1098 struct snd_card *card = dev_get_drvdata(dev);
1100 struct hda_intel *hda;
1105 chip = card->private_data;
1106 hda = container_of(chip, struct hda_intel, chip);
1107 if (chip->disabled || hda->init_failed)
1110 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1111 azx_bus(chip)->codec_powered || !chip->running)
1117 static const struct dev_pm_ops azx_pm = {
1118 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1119 #ifdef CONFIG_PM_SLEEP
1120 .freeze_noirq = azx_freeze_noirq,
1121 .thaw_noirq = azx_thaw_noirq,
1123 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1126 #define AZX_PM_OPS &azx_pm
1128 #define AZX_PM_OPS NULL
1129 #endif /* CONFIG_PM */
1132 static int azx_probe_continue(struct azx *chip);
1134 #ifdef SUPPORT_VGA_SWITCHEROO
1135 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1137 static void azx_vs_set_state(struct pci_dev *pci,
1138 enum vga_switcheroo_state state)
1140 struct snd_card *card = pci_get_drvdata(pci);
1141 struct azx *chip = card->private_data;
1142 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1145 wait_for_completion(&hda->probe_wait);
1146 if (hda->init_failed)
1149 disabled = (state == VGA_SWITCHEROO_OFF);
1150 if (chip->disabled == disabled)
1153 if (!hda->probe_continued) {
1154 chip->disabled = disabled;
1156 dev_info(chip->card->dev,
1157 "Start delayed initialization\n");
1158 if (azx_probe_continue(chip) < 0) {
1159 dev_err(chip->card->dev, "initialization error\n");
1160 hda->init_failed = true;
1164 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1165 disabled ? "Disabling" : "Enabling");
1167 pm_runtime_put_sync_suspend(card->dev);
1168 azx_suspend(card->dev);
1169 /* when we get suspended by vga_switcheroo we end up in D3cold,
1170 * however we have no ACPI handle, so pci/acpi can't put us there,
1171 * put ourselves there */
1172 pci->current_state = PCI_D3cold;
1173 chip->disabled = true;
1174 if (snd_hda_lock_devices(&chip->bus))
1175 dev_warn(chip->card->dev,
1176 "Cannot lock devices!\n");
1178 snd_hda_unlock_devices(&chip->bus);
1179 pm_runtime_get_noresume(card->dev);
1180 chip->disabled = false;
1181 azx_resume(card->dev);
1186 static bool azx_vs_can_switch(struct pci_dev *pci)
1188 struct snd_card *card = pci_get_drvdata(pci);
1189 struct azx *chip = card->private_data;
1190 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1192 wait_for_completion(&hda->probe_wait);
1193 if (hda->init_failed)
1195 if (chip->disabled || !hda->probe_continued)
1197 if (snd_hda_lock_devices(&chip->bus))
1199 snd_hda_unlock_devices(&chip->bus);
1203 static void init_vga_switcheroo(struct azx *chip)
1205 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1206 struct pci_dev *p = get_bound_vga(chip->pci);
1208 dev_info(chip->card->dev,
1209 "Handle vga_switcheroo audio client\n");
1210 hda->use_vga_switcheroo = 1;
1215 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1216 .set_gpu_state = azx_vs_set_state,
1217 .can_switch = azx_vs_can_switch,
1220 static int register_vga_switcheroo(struct azx *chip)
1222 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1225 if (!hda->use_vga_switcheroo)
1227 /* FIXME: currently only handling DIS controller
1228 * is there any machine with two switchable HDMI audio controllers?
1230 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
1231 VGA_SWITCHEROO_DIS);
1234 hda->vga_switcheroo_registered = 1;
1236 /* register as an optimus hdmi audio power domain */
1237 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
1238 &hda->hdmi_pm_domain);
1242 #define init_vga_switcheroo(chip) /* NOP */
1243 #define register_vga_switcheroo(chip) 0
1244 #define check_hdmi_disabled(pci) false
1245 #endif /* SUPPORT_VGA_SWITCHER */
1250 static int azx_free(struct azx *chip)
1252 struct pci_dev *pci = chip->pci;
1253 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1254 struct hdac_bus *bus = azx_bus(chip);
1256 if (azx_has_pm_runtime(chip) && chip->running)
1257 pm_runtime_get_noresume(&pci->dev);
1259 azx_del_card_list(chip);
1261 hda->init_failed = 1; /* to be sure */
1262 complete_all(&hda->probe_wait);
1264 if (use_vga_switcheroo(hda)) {
1265 if (chip->disabled && hda->probe_continued)
1266 snd_hda_unlock_devices(&chip->bus);
1267 if (hda->vga_switcheroo_registered) {
1268 vga_switcheroo_unregister_client(chip->pci);
1269 vga_switcheroo_fini_domain_pm_ops(chip->card->dev);
1273 if (bus->chip_init) {
1274 azx_clear_irq_pending(chip);
1275 azx_stop_all_streams(chip);
1276 azx_stop_chip(chip);
1280 free_irq(bus->irq, (void*)chip);
1282 pci_disable_msi(chip->pci);
1283 iounmap(bus->remap_addr);
1285 azx_free_stream_pages(chip);
1286 azx_free_streams(chip);
1287 snd_hdac_bus_exit(bus);
1289 if (chip->region_requested)
1290 pci_release_regions(chip->pci);
1292 pci_disable_device(chip->pci);
1293 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1294 release_firmware(chip->fw);
1297 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1298 if (hda->need_i915_power)
1299 snd_hdac_display_power(bus, false);
1300 snd_hdac_i915_exit(bus);
1307 static int azx_dev_disconnect(struct snd_device *device)
1309 struct azx *chip = device->device_data;
1311 chip->bus.shutdown = 1;
1315 static int azx_dev_free(struct snd_device *device)
1317 return azx_free(device->device_data);
1320 #ifdef SUPPORT_VGA_SWITCHEROO
1322 * Check of disabled HDMI controller by vga_switcheroo
1324 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1328 /* check only discrete GPU */
1329 switch (pci->vendor) {
1330 case PCI_VENDOR_ID_ATI:
1331 case PCI_VENDOR_ID_AMD:
1332 case PCI_VENDOR_ID_NVIDIA:
1333 if (pci->devfn == 1) {
1334 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1335 pci->bus->number, 0);
1337 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1347 static bool check_hdmi_disabled(struct pci_dev *pci)
1349 bool vga_inactive = false;
1350 struct pci_dev *p = get_bound_vga(pci);
1353 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1354 vga_inactive = true;
1357 return vga_inactive;
1359 #endif /* SUPPORT_VGA_SWITCHEROO */
1362 * white/black-listing for position_fix
1364 static struct snd_pci_quirk position_fix_list[] = {
1365 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1366 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1367 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1368 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1369 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1370 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1371 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1372 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1373 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1374 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1375 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1376 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1377 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1378 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1382 static int check_position_fix(struct azx *chip, int fix)
1384 const struct snd_pci_quirk *q;
1389 case POS_FIX_POSBUF:
1390 case POS_FIX_VIACOMBO:
1395 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1397 dev_info(chip->card->dev,
1398 "position_fix set to %d for device %04x:%04x\n",
1399 q->value, q->subvendor, q->subdevice);
1403 /* Check VIA/ATI HD Audio Controller exist */
1404 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
1405 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1406 return POS_FIX_VIACOMBO;
1408 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1409 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1410 return POS_FIX_LPIB;
1412 return POS_FIX_AUTO;
1415 static void assign_position_fix(struct azx *chip, int fix)
1417 static azx_get_pos_callback_t callbacks[] = {
1418 [POS_FIX_AUTO] = NULL,
1419 [POS_FIX_LPIB] = azx_get_pos_lpib,
1420 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1421 [POS_FIX_VIACOMBO] = azx_via_get_position,
1422 [POS_FIX_COMBO] = azx_get_pos_lpib,
1425 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1427 /* combo mode uses LPIB only for playback */
1428 if (fix == POS_FIX_COMBO)
1429 chip->get_position[1] = NULL;
1431 if (fix == POS_FIX_POSBUF &&
1432 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1433 chip->get_delay[0] = chip->get_delay[1] =
1434 azx_get_delay_from_lpib;
1440 * black-lists for probe_mask
1442 static struct snd_pci_quirk probe_mask_list[] = {
1443 /* Thinkpad often breaks the controller communication when accessing
1444 * to the non-working (or non-existing) modem codec slot.
1446 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1447 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1448 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1450 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1451 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1452 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1453 /* forced codec slots */
1454 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1455 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1456 /* WinFast VP200 H (Teradici) user reported broken communication */
1457 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1461 #define AZX_FORCE_CODEC_MASK 0x100
1463 static void check_probe_mask(struct azx *chip, int dev)
1465 const struct snd_pci_quirk *q;
1467 chip->codec_probe_mask = probe_mask[dev];
1468 if (chip->codec_probe_mask == -1) {
1469 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1471 dev_info(chip->card->dev,
1472 "probe_mask set to 0x%x for device %04x:%04x\n",
1473 q->value, q->subvendor, q->subdevice);
1474 chip->codec_probe_mask = q->value;
1478 /* check forced option */
1479 if (chip->codec_probe_mask != -1 &&
1480 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1481 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1482 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1483 (int)azx_bus(chip)->codec_mask);
1488 * white/black-list for enable_msi
1490 static struct snd_pci_quirk msi_black_list[] = {
1491 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1492 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1493 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1494 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1495 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1496 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1497 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1498 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1499 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1500 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1504 static void check_msi(struct azx *chip)
1506 const struct snd_pci_quirk *q;
1508 if (enable_msi >= 0) {
1509 chip->msi = !!enable_msi;
1512 chip->msi = 1; /* enable MSI as default */
1513 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1515 dev_info(chip->card->dev,
1516 "msi for device %04x:%04x set to %d\n",
1517 q->subvendor, q->subdevice, q->value);
1518 chip->msi = q->value;
1522 /* NVidia chipsets seem to cause troubles with MSI */
1523 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1524 dev_info(chip->card->dev, "Disabling MSI\n");
1529 /* check the snoop mode availability */
1530 static void azx_check_snoop_available(struct azx *chip)
1532 int snoop = hda_snoop;
1535 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1536 snoop ? "snoop" : "non-snoop");
1537 chip->snoop = snoop;
1542 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1543 chip->driver_type == AZX_DRIVER_VIA) {
1544 /* force to non-snoop mode for a new VIA controller
1548 pci_read_config_byte(chip->pci, 0x42, &val);
1549 if (!(val & 0x80) && chip->pci->revision == 0x30)
1553 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1556 chip->snoop = snoop;
1558 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1561 static void azx_probe_work(struct work_struct *work)
1563 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1564 azx_probe_continue(&hda->chip);
1570 static const struct hdac_io_ops pci_hda_io_ops;
1571 static const struct hda_controller_ops pci_hda_ops;
1573 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1574 int dev, unsigned int driver_caps,
1577 static struct snd_device_ops ops = {
1578 .dev_disconnect = azx_dev_disconnect,
1579 .dev_free = azx_dev_free,
1581 struct hda_intel *hda;
1587 err = pci_enable_device(pci);
1591 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1593 pci_disable_device(pci);
1598 mutex_init(&chip->open_mutex);
1601 chip->ops = &pci_hda_ops;
1602 chip->driver_caps = driver_caps;
1603 chip->driver_type = driver_caps & 0xff;
1605 chip->dev_index = dev;
1606 chip->jackpoll_ms = jackpoll_ms;
1607 INIT_LIST_HEAD(&chip->pcm_list);
1608 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1609 INIT_LIST_HEAD(&hda->list);
1610 init_vga_switcheroo(chip);
1611 init_completion(&hda->probe_wait);
1613 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1615 check_probe_mask(chip, dev);
1617 chip->single_cmd = single_cmd;
1618 azx_check_snoop_available(chip);
1620 if (bdl_pos_adj[dev] < 0) {
1621 switch (chip->driver_type) {
1622 case AZX_DRIVER_ICH:
1623 case AZX_DRIVER_PCH:
1624 bdl_pos_adj[dev] = 1;
1627 bdl_pos_adj[dev] = 32;
1631 chip->bdl_pos_adj = bdl_pos_adj;
1633 err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1636 pci_disable_device(pci);
1640 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1642 dev_err(card->dev, "Error creating device [card]!\n");
1647 /* continue probing in work context as may trigger request module */
1648 INIT_WORK(&hda->probe_work, azx_probe_work);
1655 static int azx_first_init(struct azx *chip)
1657 int dev = chip->dev_index;
1658 struct pci_dev *pci = chip->pci;
1659 struct snd_card *card = chip->card;
1660 struct hdac_bus *bus = azx_bus(chip);
1662 unsigned short gcap;
1663 unsigned int dma_bits = 64;
1665 #if BITS_PER_LONG != 64
1666 /* Fix up base address on ULI M5461 */
1667 if (chip->driver_type == AZX_DRIVER_ULI) {
1669 pci_read_config_word(pci, 0x40, &tmp3);
1670 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1671 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1675 err = pci_request_regions(pci, "ICH HD audio");
1678 chip->region_requested = 1;
1680 bus->addr = pci_resource_start(pci, 0);
1681 bus->remap_addr = pci_ioremap_bar(pci, 0);
1682 if (bus->remap_addr == NULL) {
1683 dev_err(card->dev, "ioremap error\n");
1688 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1689 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1690 pci->no_64bit_msi = true;
1692 if (pci_enable_msi(pci) < 0)
1696 if (azx_acquire_irq(chip, 0) < 0)
1699 pci_set_master(pci);
1700 synchronize_irq(bus->irq);
1702 gcap = azx_readw(chip, GCAP);
1703 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1705 /* AMD devices support 40 or 48bit DMA, take the safe one */
1706 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1709 /* disable SB600 64bit support for safety */
1710 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1711 struct pci_dev *p_smbus;
1713 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1714 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1717 if (p_smbus->revision < 0x30)
1718 gcap &= ~AZX_GCAP_64OK;
1719 pci_dev_put(p_smbus);
1723 /* disable 64bit DMA address on some devices */
1724 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1725 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1726 gcap &= ~AZX_GCAP_64OK;
1729 /* disable buffer size rounding to 128-byte multiples if supported */
1730 if (align_buffer_size >= 0)
1731 chip->align_buffer_size = !!align_buffer_size;
1733 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1734 chip->align_buffer_size = 0;
1736 chip->align_buffer_size = 1;
1739 /* allow 64bit DMA address if supported by H/W */
1740 if (!(gcap & AZX_GCAP_64OK))
1742 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1743 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1745 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1746 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1749 /* read number of streams from GCAP register instead of using
1752 chip->capture_streams = (gcap >> 8) & 0x0f;
1753 chip->playback_streams = (gcap >> 12) & 0x0f;
1754 if (!chip->playback_streams && !chip->capture_streams) {
1755 /* gcap didn't give any info, switching to old method */
1757 switch (chip->driver_type) {
1758 case AZX_DRIVER_ULI:
1759 chip->playback_streams = ULI_NUM_PLAYBACK;
1760 chip->capture_streams = ULI_NUM_CAPTURE;
1762 case AZX_DRIVER_ATIHDMI:
1763 case AZX_DRIVER_ATIHDMI_NS:
1764 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1765 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1767 case AZX_DRIVER_GENERIC:
1769 chip->playback_streams = ICH6_NUM_PLAYBACK;
1770 chip->capture_streams = ICH6_NUM_CAPTURE;
1774 chip->capture_index_offset = 0;
1775 chip->playback_index_offset = chip->capture_streams;
1776 chip->num_streams = chip->playback_streams + chip->capture_streams;
1778 /* initialize streams */
1779 err = azx_init_streams(chip);
1783 err = azx_alloc_stream_pages(chip);
1787 /* initialize chip */
1790 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1791 struct hda_intel *hda;
1793 hda = container_of(chip, struct hda_intel, chip);
1794 haswell_set_bclk(hda);
1797 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1799 /* codec detection */
1800 if (!azx_bus(chip)->codec_mask) {
1801 dev_err(card->dev, "no codecs found!\n");
1805 strcpy(card->driver, "HDA-Intel");
1806 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1807 sizeof(card->shortname));
1808 snprintf(card->longname, sizeof(card->longname),
1809 "%s at 0x%lx irq %i",
1810 card->shortname, bus->addr, bus->irq);
1815 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1816 /* callback from request_firmware_nowait() */
1817 static void azx_firmware_cb(const struct firmware *fw, void *context)
1819 struct snd_card *card = context;
1820 struct azx *chip = card->private_data;
1821 struct pci_dev *pci = chip->pci;
1824 dev_err(card->dev, "Cannot load firmware, aborting\n");
1829 if (!chip->disabled) {
1830 /* continue probing */
1831 if (azx_probe_continue(chip))
1837 snd_card_free(card);
1838 pci_set_drvdata(pci, NULL);
1843 * HDA controller ops.
1846 /* PCI register access. */
1847 static void pci_azx_writel(u32 value, u32 __iomem *addr)
1849 writel(value, addr);
1852 static u32 pci_azx_readl(u32 __iomem *addr)
1857 static void pci_azx_writew(u16 value, u16 __iomem *addr)
1859 writew(value, addr);
1862 static u16 pci_azx_readw(u16 __iomem *addr)
1867 static void pci_azx_writeb(u8 value, u8 __iomem *addr)
1869 writeb(value, addr);
1872 static u8 pci_azx_readb(u8 __iomem *addr)
1877 static int disable_msi_reset_irq(struct azx *chip)
1879 struct hdac_bus *bus = azx_bus(chip);
1882 free_irq(bus->irq, chip);
1884 pci_disable_msi(chip->pci);
1886 err = azx_acquire_irq(chip, 1);
1893 /* DMA page allocation helpers. */
1894 static int dma_alloc_pages(struct hdac_bus *bus,
1897 struct snd_dma_buffer *buf)
1899 struct azx *chip = bus_to_azx(bus);
1902 err = snd_dma_alloc_pages(type,
1907 mark_pages_wc(chip, buf, true);
1911 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
1913 struct azx *chip = bus_to_azx(bus);
1915 mark_pages_wc(chip, buf, false);
1916 snd_dma_free_pages(buf);
1919 static int substream_alloc_pages(struct azx *chip,
1920 struct snd_pcm_substream *substream,
1923 struct azx_dev *azx_dev = get_azx_dev(substream);
1926 mark_runtime_wc(chip, azx_dev, substream, false);
1927 ret = snd_pcm_lib_malloc_pages(substream, size);
1930 mark_runtime_wc(chip, azx_dev, substream, true);
1934 static int substream_free_pages(struct azx *chip,
1935 struct snd_pcm_substream *substream)
1937 struct azx_dev *azx_dev = get_azx_dev(substream);
1938 mark_runtime_wc(chip, azx_dev, substream, false);
1939 return snd_pcm_lib_free_pages(substream);
1942 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1943 struct vm_area_struct *area)
1946 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1947 struct azx *chip = apcm->chip;
1948 if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
1949 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1953 static const struct hdac_io_ops pci_hda_io_ops = {
1954 .reg_writel = pci_azx_writel,
1955 .reg_readl = pci_azx_readl,
1956 .reg_writew = pci_azx_writew,
1957 .reg_readw = pci_azx_readw,
1958 .reg_writeb = pci_azx_writeb,
1959 .reg_readb = pci_azx_readb,
1960 .dma_alloc_pages = dma_alloc_pages,
1961 .dma_free_pages = dma_free_pages,
1964 static const struct hda_controller_ops pci_hda_ops = {
1965 .disable_msi_reset_irq = disable_msi_reset_irq,
1966 .substream_alloc_pages = substream_alloc_pages,
1967 .substream_free_pages = substream_free_pages,
1968 .pcm_mmap_prepare = pcm_mmap_prepare,
1969 .position_check = azx_position_check,
1970 .link_power = azx_intel_link_power,
1973 static int azx_probe(struct pci_dev *pci,
1974 const struct pci_device_id *pci_id)
1977 struct snd_card *card;
1978 struct hda_intel *hda;
1980 bool schedule_probe;
1983 if (dev >= SNDRV_CARDS)
1990 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1993 dev_err(&pci->dev, "Error creating card!\n");
1997 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2000 card->private_data = chip;
2001 hda = container_of(chip, struct hda_intel, chip);
2003 pci_set_drvdata(pci, card);
2005 err = register_vga_switcheroo(chip);
2007 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2011 if (check_hdmi_disabled(pci)) {
2012 dev_info(card->dev, "VGA controller is disabled\n");
2013 dev_info(card->dev, "Delaying initialization\n");
2014 chip->disabled = true;
2017 schedule_probe = !chip->disabled;
2019 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2020 if (patch[dev] && *patch[dev]) {
2021 dev_info(card->dev, "Applying patch firmware '%s'\n",
2023 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2024 &pci->dev, GFP_KERNEL, card,
2028 schedule_probe = false; /* continued in azx_firmware_cb() */
2030 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2032 #ifndef CONFIG_SND_HDA_I915
2033 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2034 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n");
2038 schedule_work(&hda->probe_work);
2042 complete_all(&hda->probe_wait);
2046 snd_card_free(card);
2050 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2051 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2052 [AZX_DRIVER_NVIDIA] = 8,
2053 [AZX_DRIVER_TERA] = 1,
2056 static int azx_probe_continue(struct azx *chip)
2058 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2059 struct hdac_bus *bus = azx_bus(chip);
2060 struct pci_dev *pci = chip->pci;
2061 int dev = chip->dev_index;
2064 hda->probe_continued = 1;
2066 /* Request display power well for the HDA controller or codec. For
2067 * Haswell/Broadwell, both the display HDA controller and codec need
2068 * this power. For other platforms, like Baytrail/Braswell, only the
2069 * display codec needs the power and it can be released after probe.
2071 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
2072 /* HSW/BDW controllers need this power */
2073 if (CONTROLLER_IN_GPU(pci))
2074 hda->need_i915_power = 1;
2076 err = snd_hdac_i915_init(bus);
2078 /* if the controller is bound only with HDMI/DP
2079 * (for HSW and BDW), we need to abort the probe;
2080 * for other chips, still continue probing as other
2081 * codecs can be on the same link.
2083 if (CONTROLLER_IN_GPU(pci))
2089 err = snd_hdac_display_power(bus, true);
2091 dev_err(chip->card->dev,
2092 "Cannot turn on display power on i915\n");
2093 goto i915_power_fail;
2098 err = azx_first_init(chip);
2102 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2103 chip->beep_mode = beep_mode[dev];
2106 /* create codec instances */
2107 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2111 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2113 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2118 release_firmware(chip->fw); /* no longer needed */
2123 if ((probe_only[dev] & 1) == 0) {
2124 err = azx_codec_configure(chip);
2129 err = snd_card_register(chip->card);
2134 azx_add_card_list(chip);
2135 snd_hda_set_power_save(&chip->bus, power_save * 1000);
2136 if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo)
2137 pm_runtime_put_noidle(&pci->dev);
2140 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
2141 && !hda->need_i915_power)
2142 snd_hdac_display_power(bus, false);
2146 hda->init_failed = 1;
2147 complete_all(&hda->probe_wait);
2151 static void azx_remove(struct pci_dev *pci)
2153 struct snd_card *card = pci_get_drvdata(pci);
2155 struct hda_intel *hda;
2158 /* cancel the pending probing work */
2159 chip = card->private_data;
2160 hda = container_of(chip, struct hda_intel, chip);
2161 cancel_work_sync(&hda->probe_work);
2163 snd_card_free(card);
2167 static void azx_shutdown(struct pci_dev *pci)
2169 struct snd_card *card = pci_get_drvdata(pci);
2174 chip = card->private_data;
2175 if (chip && chip->running)
2176 azx_stop_chip(chip);
2180 static const struct pci_device_id azx_ids[] = {
2182 { PCI_DEVICE(0x8086, 0x1c20),
2183 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2185 { PCI_DEVICE(0x8086, 0x1d20),
2186 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2188 { PCI_DEVICE(0x8086, 0x1e20),
2189 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2191 { PCI_DEVICE(0x8086, 0x8c20),
2192 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2194 { PCI_DEVICE(0x8086, 0x8ca0),
2195 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2197 { PCI_DEVICE(0x8086, 0x8d20),
2198 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2199 { PCI_DEVICE(0x8086, 0x8d21),
2200 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2202 { PCI_DEVICE(0x8086, 0xa1f0),
2203 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2204 { PCI_DEVICE(0x8086, 0xa270),
2205 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2207 { PCI_DEVICE(0x8086, 0x9c20),
2208 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2210 { PCI_DEVICE(0x8086, 0x9c21),
2211 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2212 /* Wildcat Point-LP */
2213 { PCI_DEVICE(0x8086, 0x9ca0),
2214 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2216 { PCI_DEVICE(0x8086, 0xa170),
2217 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2218 /* Sunrise Point-LP */
2219 { PCI_DEVICE(0x8086, 0x9d70),
2220 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2222 { PCI_DEVICE(0x8086, 0xa171),
2223 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2225 { PCI_DEVICE(0x8086, 0x9d71),
2226 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2228 { PCI_DEVICE(0x8086, 0xa2f0),
2229 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2230 /* Broxton-P(Apollolake) */
2231 { PCI_DEVICE(0x8086, 0x5a98),
2232 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON },
2234 { PCI_DEVICE(0x8086, 0x1a98),
2235 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON },
2237 { PCI_DEVICE(0x8086, 0x0a0c),
2238 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2239 { PCI_DEVICE(0x8086, 0x0c0c),
2240 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2241 { PCI_DEVICE(0x8086, 0x0d0c),
2242 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2244 { PCI_DEVICE(0x8086, 0x160c),
2245 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2247 { PCI_DEVICE(0x8086, 0x3b56),
2248 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2250 { PCI_DEVICE(0x8086, 0x811b),
2251 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2253 { PCI_DEVICE(0x8086, 0x080a),
2254 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2256 { PCI_DEVICE(0x8086, 0x0f04),
2257 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2259 { PCI_DEVICE(0x8086, 0x2284),
2260 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2262 { PCI_DEVICE(0x8086, 0x2668),
2263 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2265 { PCI_DEVICE(0x8086, 0x27d8),
2266 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2268 { PCI_DEVICE(0x8086, 0x269a),
2269 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2271 { PCI_DEVICE(0x8086, 0x284b),
2272 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2274 { PCI_DEVICE(0x8086, 0x293e),
2275 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2277 { PCI_DEVICE(0x8086, 0x293f),
2278 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2280 { PCI_DEVICE(0x8086, 0x3a3e),
2281 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2283 { PCI_DEVICE(0x8086, 0x3a6e),
2284 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2286 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2287 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2288 .class_mask = 0xffffff,
2289 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2290 /* ATI SB 450/600/700/800/900 */
2291 { PCI_DEVICE(0x1002, 0x437b),
2292 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2293 { PCI_DEVICE(0x1002, 0x4383),
2294 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2296 { PCI_DEVICE(0x1022, 0x780d),
2297 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2299 { PCI_DEVICE(0x1002, 0x0002),
2300 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2301 { PCI_DEVICE(0x1002, 0x1308),
2302 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2303 { PCI_DEVICE(0x1002, 0x157a),
2304 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2305 { PCI_DEVICE(0x1002, 0x15b3),
2306 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2307 { PCI_DEVICE(0x1002, 0x793b),
2308 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2309 { PCI_DEVICE(0x1002, 0x7919),
2310 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2311 { PCI_DEVICE(0x1002, 0x960f),
2312 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2313 { PCI_DEVICE(0x1002, 0x970f),
2314 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2315 { PCI_DEVICE(0x1002, 0x9840),
2316 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2317 { PCI_DEVICE(0x1002, 0xaa00),
2318 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2319 { PCI_DEVICE(0x1002, 0xaa08),
2320 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2321 { PCI_DEVICE(0x1002, 0xaa10),
2322 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2323 { PCI_DEVICE(0x1002, 0xaa18),
2324 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2325 { PCI_DEVICE(0x1002, 0xaa20),
2326 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2327 { PCI_DEVICE(0x1002, 0xaa28),
2328 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2329 { PCI_DEVICE(0x1002, 0xaa30),
2330 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2331 { PCI_DEVICE(0x1002, 0xaa38),
2332 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2333 { PCI_DEVICE(0x1002, 0xaa40),
2334 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2335 { PCI_DEVICE(0x1002, 0xaa48),
2336 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2337 { PCI_DEVICE(0x1002, 0xaa50),
2338 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2339 { PCI_DEVICE(0x1002, 0xaa58),
2340 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2341 { PCI_DEVICE(0x1002, 0xaa60),
2342 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2343 { PCI_DEVICE(0x1002, 0xaa68),
2344 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2345 { PCI_DEVICE(0x1002, 0xaa80),
2346 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2347 { PCI_DEVICE(0x1002, 0xaa88),
2348 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2349 { PCI_DEVICE(0x1002, 0xaa90),
2350 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2351 { PCI_DEVICE(0x1002, 0xaa98),
2352 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2353 { PCI_DEVICE(0x1002, 0x9902),
2354 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2355 { PCI_DEVICE(0x1002, 0xaaa0),
2356 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2357 { PCI_DEVICE(0x1002, 0xaaa8),
2358 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2359 { PCI_DEVICE(0x1002, 0xaab0),
2360 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2361 { PCI_DEVICE(0x1002, 0xaac0),
2362 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2363 { PCI_DEVICE(0x1002, 0xaac8),
2364 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2365 { PCI_DEVICE(0x1002, 0xaad8),
2366 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2367 { PCI_DEVICE(0x1002, 0xaae8),
2368 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2369 { PCI_DEVICE(0x1002, 0xaae0),
2370 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2371 { PCI_DEVICE(0x1002, 0xaaf0),
2372 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2373 /* VIA VT8251/VT8237A */
2374 { PCI_DEVICE(0x1106, 0x3288),
2375 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
2376 /* VIA GFX VT7122/VX900 */
2377 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2378 /* VIA GFX VT6122/VX11 */
2379 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2381 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2383 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2385 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2386 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2387 .class_mask = 0xffffff,
2388 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2390 { PCI_DEVICE(0x6549, 0x1200),
2391 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2392 { PCI_DEVICE(0x6549, 0x2200),
2393 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2394 /* Creative X-Fi (CA0110-IBG) */
2396 { PCI_DEVICE(0x1102, 0x0010),
2397 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2398 { PCI_DEVICE(0x1102, 0x0012),
2399 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2400 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2401 /* the following entry conflicts with snd-ctxfi driver,
2402 * as ctxfi driver mutates from HD-audio to native mode with
2403 * a special command sequence.
2405 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2406 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2407 .class_mask = 0xffffff,
2408 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2409 AZX_DCAPS_NO_64BIT |
2410 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
2412 /* this entry seems still valid -- i.e. without emu20kx chip */
2413 { PCI_DEVICE(0x1102, 0x0009),
2414 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2415 AZX_DCAPS_NO_64BIT |
2416 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
2419 { PCI_DEVICE(0x13f6, 0x5011),
2420 .driver_data = AZX_DRIVER_CMEDIA |
2421 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2423 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2424 /* VMware HDAudio */
2425 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2426 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2427 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2428 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2429 .class_mask = 0xffffff,
2430 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2431 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2432 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2433 .class_mask = 0xffffff,
2434 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2437 MODULE_DEVICE_TABLE(pci, azx_ids);
2439 /* pci_driver definition */
2440 static struct pci_driver azx_driver = {
2441 .name = KBUILD_MODNAME,
2442 .id_table = azx_ids,
2444 .remove = azx_remove,
2445 .shutdown = azx_shutdown,
2451 module_pci_driver(azx_driver);