sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <linux/delay.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/kernel.h>
  40 #include <linux/module.h>
  41 #include <linux/dma-mapping.h>
  42 #include <linux/moduleparam.h>
  43 #include <linux/init.h>
  44 #include <linux/slab.h>
  45 #include <linux/pci.h>
  46 #include <linux/mutex.h>
  47 #include <linux/io.h>
  48 #include <linux/pm_runtime.h>
  49 #include <linux/clocksource.h>
  50 #include <linux/time.h>
  51 #include <linux/completion.h>
  52
  53 #ifdef CONFIG_X86
  54 /* for snoop control */
  55 #include <asm/pgtable.h>
  56 #include <asm/cacheflush.h>
  57 #endif
  58 #include <sound/core.h>
  59 #include <sound/initval.h>
  60 #include <sound/hdaudio.h>
  61 #include <sound/hda_i915.h>
  62 #include <linux/vgaarb.h>
  63 #include <linux/vga_switcheroo.h>
  64 #include <linux/firmware.h>
  65 #include "hda_codec.h"
  66 #include "hda_controller.h"
  67 #include "hda_intel.h"
  68
  69 #define CREATE_TRACE_POINTS
  70 #include "hda_intel_trace.h"
  71
  72 /* position fix mode */
  73 enum {
  74         POS_FIX_AUTO,
  75         POS_FIX_LPIB,
  76         POS_FIX_POSBUF,
  77         POS_FIX_VIACOMBO,
  78         POS_FIX_COMBO,
  79 };
  80
  81 /* Defines for ATI HD Audio support in SB450 south bridge */
  82 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
  83 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
  84
  85 /* Defines for Nvidia HDA support */
  86 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
  87 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
  88 #define NVIDIA_HDA_ISTRM_COH          0x4d
  89 #define NVIDIA_HDA_OSTRM_COH          0x4c
  90 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
  91
  92 /* Defines for Intel SCH HDA snoop control */
  93 #define INTEL_HDA_CGCTL  0x48
  94 #define INTEL_HDA_CGCTL_MISCBDCGE        (0x1 << 6)
  95 #define INTEL_SCH_HDA_DEVC      0x78
  96 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
  97
  98 /* Define IN stream 0 FIFO size offset in VIA controller */
  99 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 100 /* Define VIA HD Audio Device ID*/
 101 #define VIA_HDAC_DEVICE_ID              0x3288
 102
 103 /* max number of SDs */
 104 /* ICH, ATI and VIA have 4 playback and 4 capture */
 105 #define ICH6_NUM_CAPTURE        4
 106 #define ICH6_NUM_PLAYBACK       4
 107
 108 /* ULI has 6 playback and 5 capture */
 109 #define ULI_NUM_CAPTURE         5
 110 #define ULI_NUM_PLAYBACK        6
 111
 112 /* ATI HDMI may have up to 8 playbacks and 0 capture */
 113 #define ATIHDMI_NUM_CAPTURE     0
 114 #define ATIHDMI_NUM_PLAYBACK    8
 115
 116 /* TERA has 4 playback and 3 capture */
 117 #define TERA_NUM_CAPTURE        3
 118 #define TERA_NUM_PLAYBACK       4
 119
 120
 121 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
 122 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
 123 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
 124 static char *model[SNDRV_CARDS];
 125 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 126 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 127 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 128 static int probe_only[SNDRV_CARDS];
 129 static int jackpoll_ms[SNDRV_CARDS];
 130 static bool single_cmd;
 131 static int enable_msi = -1;
 132 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 133 static char *patch[SNDRV_CARDS];
 134 #endif
 135 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 136 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
 137                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
 138 #endif
 139
 140 module_param_array(index, int, NULL, 0444);
 141 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
 142 module_param_array(id, charp, NULL, 0444);
 143 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
 144 module_param_array(enable, bool, NULL, 0444);
 145 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
 146 module_param_array(model, charp, NULL, 0444);
 147 MODULE_PARM_DESC(model, "Use the given board model.");
 148 module_param_array(position_fix, int, NULL, 0444);
 149 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
 150                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
 151 module_param_array(bdl_pos_adj, int, NULL, 0644);
 152 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
 153 module_param_array(probe_mask, int, NULL, 0444);
 154 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
 155 module_param_array(probe_only, int, NULL, 0444);
 156 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
 157 module_param_array(jackpoll_ms, int, NULL, 0444);
 158 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
 159 module_param(single_cmd, bool, 0444);
 160 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
 161                  "(for debugging only).");
 162 module_param(enable_msi, bint, 0444);
 163 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
 164 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 165 module_param_array(patch, charp, NULL, 0444);
 166 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 167 #endif
 168 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 169 module_param_array(beep_mode, bool, NULL, 0444);
 170 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 171                             "(0=off, 1=on) (default=1).");
 172 #endif
 173
 174 #ifdef CONFIG_PM
 175 static int param_set_xint(const char *val, const struct kernel_param *kp);
 176 static const struct kernel_param_ops param_ops_xint = {
 177         .set = param_set_xint,
 178         .get = param_get_int,
 179 };
 180 #define param_check_xint param_check_int
 181
 182 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 183 module_param(power_save, xint, 0644);
 184 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 185                  "(in second, 0 = disable).");
 186
 187 /* reset the HD-audio controller in power save mode.
 188  * this may give more power-saving, but will take longer time to
 189  * wake up.
 190  */
 191 static bool power_save_controller = 1;
 192 module_param(power_save_controller, bool, 0644);
 193 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 194 #else
 195 #define power_save      0
 196 #endif /* CONFIG_PM */
 197
 198 static int align_buffer_size = -1;
 199 module_param(align_buffer_size, bint, 0644);
 200 MODULE_PARM_DESC(align_buffer_size,
 201                 "Force buffer and period sizes to be multiple of 128 bytes.");
 202
 203 #ifdef CONFIG_X86
 204 static int hda_snoop = -1;
 205 module_param_named(snoop, hda_snoop, bint, 0444);
 206 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 207 #else
 208 #define hda_snoop               true
 209 #endif
 210
 211
 212 MODULE_LICENSE("GPL");
 213 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 214                          "{Intel, ICH6M},"
 215                          "{Intel, ICH7},"
 216                          "{Intel, ESB2},"
 217                          "{Intel, ICH8},"
 218                          "{Intel, ICH9},"
 219                          "{Intel, ICH10},"
 220                          "{Intel, PCH},"
 221                          "{Intel, CPT},"
 222                          "{Intel, PPT},"
 223                          "{Intel, LPT},"
 224                          "{Intel, LPT_LP},"
 225                          "{Intel, WPT_LP},"
 226                          "{Intel, SPT},"
 227                          "{Intel, SPT_LP},"
 228                          "{Intel, HPT},"
 229                          "{Intel, PBG},"
 230                          "{Intel, SCH},"
 231                          "{ATI, SB450},"
 232                          "{ATI, SB600},"
 233                          "{ATI, RS600},"
 234                          "{ATI, RS690},"
 235                          "{ATI, RS780},"
 236                          "{ATI, R600},"
 237                          "{ATI, RV630},"
 238                          "{ATI, RV610},"
 239                          "{ATI, RV670},"
 240                          "{ATI, RV635},"
 241                          "{ATI, RV620},"
 242                          "{ATI, RV770},"
 243                          "{VIA, VT8251},"
 244                          "{VIA, VT8237A},"
 245                          "{SiS, SIS966},"
 246                          "{ULI, M5461}}");
 247 MODULE_DESCRIPTION("Intel HDA driver");
 248
 249 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
 250 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
 251 #define SUPPORT_VGA_SWITCHEROO
 252 #endif
 253 #endif
 254
 255
 256 /*
 257  */
 258
 259 /* driver types */
 260 enum {
 261         AZX_DRIVER_ICH,
 262         AZX_DRIVER_PCH,
 263         AZX_DRIVER_SCH,
 264         AZX_DRIVER_HDMI,
 265         AZX_DRIVER_ATI,
 266         AZX_DRIVER_ATIHDMI,
 267         AZX_DRIVER_ATIHDMI_NS,
 268         AZX_DRIVER_VIA,
 269         AZX_DRIVER_SIS,
 270         AZX_DRIVER_ULI,
 271         AZX_DRIVER_NVIDIA,
 272         AZX_DRIVER_TERA,
 273         AZX_DRIVER_CTX,
 274         AZX_DRIVER_CTHDA,
 275         AZX_DRIVER_CMEDIA,
 276         AZX_DRIVER_GENERIC,
 277         AZX_NUM_DRIVERS, /* keep this as last entry */
 278 };
 279
 280 #define azx_get_snoop_type(chip) \
 281         (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
 282 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
 283
 284 /* quirks for old Intel chipsets */
 285 #define AZX_DCAPS_INTEL_ICH \
 286         (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
 287
 288 /* quirks for Intel PCH */
 289 #define AZX_DCAPS_INTEL_PCH_NOPM \
 290         (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
 291          AZX_DCAPS_REVERSE_ASSIGN | AZX_DCAPS_SNOOP_TYPE(SCH))
 292
 293 #define AZX_DCAPS_INTEL_PCH \
 294         (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
 295
 296 #define AZX_DCAPS_INTEL_HASWELL \
 297         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
 298          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
 299          AZX_DCAPS_SNOOP_TYPE(SCH))
 300
 301 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
 302 #define AZX_DCAPS_INTEL_BROADWELL \
 303         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
 304          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
 305          AZX_DCAPS_SNOOP_TYPE(SCH))
 306
 307 #define AZX_DCAPS_INTEL_BAYTRAIL \
 308         (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_I915_POWERWELL)
 309
 310 #define AZX_DCAPS_INTEL_BRASWELL \
 311         (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL)
 312
 313 #define AZX_DCAPS_INTEL_SKYLAKE \
 314         (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
 315          AZX_DCAPS_I915_POWERWELL)
 316
 317 #define AZX_DCAPS_INTEL_BROXTON \
 318         (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
 319          AZX_DCAPS_I915_POWERWELL)
 320
 321 /* quirks for ATI SB / AMD Hudson */
 322 #define AZX_DCAPS_PRESET_ATI_SB \
 323         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
 324          AZX_DCAPS_SNOOP_TYPE(ATI))
 325
 326 /* quirks for ATI/AMD HDMI */
 327 #define AZX_DCAPS_PRESET_ATI_HDMI \
 328         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
 329          AZX_DCAPS_NO_MSI64)
 330
 331 /* quirks for ATI HDMI with snoop off */
 332 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
 333         (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
 334
 335 /* quirks for Nvidia */
 336 #define AZX_DCAPS_PRESET_NVIDIA \
 337         (AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI | /*AZX_DCAPS_ALIGN_BUFSIZE |*/ \
 338          AZX_DCAPS_NO_64BIT | AZX_DCAPS_CORBRP_SELF_CLEAR |\
 339          AZX_DCAPS_SNOOP_TYPE(NVIDIA))
 340
 341 #define AZX_DCAPS_PRESET_CTHDA \
 342         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
 343          AZX_DCAPS_NO_64BIT |\
 344          AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
 345
 346 /*
 347  * vga_switcheroo support
 348  */
 349 #ifdef SUPPORT_VGA_SWITCHEROO
 350 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
 351 #else
 352 #define use_vga_switcheroo(chip)        0
 353 #endif
 354
 355 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
 356                                         ((pci)->device == 0x0c0c) || \
 357                                         ((pci)->device == 0x0d0c) || \
 358                                         ((pci)->device == 0x160c))
 359
 360 #define IS_SKL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa170)
 361 #define IS_SKL_LP(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9d70)
 362 #define IS_KBL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa171)
 363 #define IS_KBL_LP(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9d71)
 364 #define IS_KBL_H(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa2f0)
 365 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
 366 #define IS_SKL_PLUS(pci) (IS_SKL(pci) || IS_SKL_LP(pci) || IS_BXT(pci)) || \
 367                         IS_KBL(pci) || IS_KBL_LP(pci) || IS_KBL_H(pci)
 368
 369 static char *driver_short_names[] = {
 370         [AZX_DRIVER_ICH] = "HDA Intel",
 371         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 372         [AZX_DRIVER_SCH] = "HDA Intel MID",
 373         [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
 374         [AZX_DRIVER_ATI] = "HDA ATI SB",
 375         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 376         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
 377         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 378         [AZX_DRIVER_SIS] = "HDA SIS966",
 379         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 380         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 381         [AZX_DRIVER_TERA] = "HDA Teradici",
 382         [AZX_DRIVER_CTX] = "HDA Creative",
 383         [AZX_DRIVER_CTHDA] = "HDA Creative",
 384         [AZX_DRIVER_CMEDIA] = "HDA C-Media",
 385         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 386 };
 387
 388 #ifdef CONFIG_X86
 389 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
 390 {
 391         int pages;
 392
 393         if (azx_snoop(chip))
 394                 return;
 395         if (!dmab || !dmab->area || !dmab->bytes)
 396                 return;
 397
 398 #ifdef CONFIG_SND_DMA_SGBUF
 399         if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
 400                 struct snd_sg_buf *sgbuf = dmab->private_data;
 401                 if (chip->driver_type == AZX_DRIVER_CMEDIA)
 402                         return; /* deal with only CORB/RIRB buffers */
 403                 if (on)
 404                         set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
 405                 else
 406                         set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
 407                 return;
 408         }
 409 #endif
 410
 411         pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
 412         if (on)
 413                 set_memory_wc((unsigned long)dmab->area, pages);
 414         else
 415                 set_memory_wb((unsigned long)dmab->area, pages);
 416 }
 417
 418 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 419                                  bool on)
 420 {
 421         __mark_pages_wc(chip, buf, on);
 422 }
 423 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 424                                    struct snd_pcm_substream *substream, bool on)
 425 {
 426         if (azx_dev->wc_marked != on) {
 427                 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
 428                 azx_dev->wc_marked = on;
 429         }
 430 }
 431 #else
 432 /* NOP for other archs */
 433 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 434                                  bool on)
 435 {
 436 }
 437 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 438                                    struct snd_pcm_substream *substream, bool on)
 439 {
 440 }
 441 #endif
 442
 443 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 444
 445 /*
 446  * initialize the PCI registers
 447  */
 448 /* update bits in a PCI register byte */
 449 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 450                             unsigned char mask, unsigned char val)
 451 {
 452         unsigned char data;
 453
 454         pci_read_config_byte(pci, reg, &data);
 455         data &= ~mask;
 456         data |= (val & mask);
 457         pci_write_config_byte(pci, reg, data);
 458 }
 459
 460 static void azx_init_pci(struct azx *chip)
 461 {
 462         int snoop_type = azx_get_snoop_type(chip);
 463
 464         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 465          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 466          * Ensuring these bits are 0 clears playback static on some HD Audio
 467          * codecs.
 468          * The PCI register TCSEL is defined in the Intel manuals.
 469          */
 470         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
 471                 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
 472                 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
 473         }
 474
 475         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
 476          * we need to enable snoop.
 477          */
 478         if (snoop_type == AZX_SNOOP_TYPE_ATI) {
 479                 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
 480                         azx_snoop(chip));
 481                 update_pci_byte(chip->pci,
 482                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
 483                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
 484         }
 485
 486         /* For NVIDIA HDA, enable snoop */
 487         if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
 488                 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
 489                         azx_snoop(chip));
 490                 update_pci_byte(chip->pci,
 491                                 NVIDIA_HDA_TRANSREG_ADDR,
 492                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 493                 update_pci_byte(chip->pci,
 494                                 NVIDIA_HDA_ISTRM_COH,
 495                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 496                 update_pci_byte(chip->pci,
 497                                 NVIDIA_HDA_OSTRM_COH,
 498                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 499         }
 500
 501         /* Enable SCH/PCH snoop if needed */
 502         if (snoop_type == AZX_SNOOP_TYPE_SCH) {
 503                 unsigned short snoop;
 504                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 505                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
 506                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
 507                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
 508                         if (!azx_snoop(chip))
 509                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
 510                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
 511                         pci_read_config_word(chip->pci,
 512                                 INTEL_SCH_HDA_DEVC, &snoop);
 513                 }
 514                 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
 515                         (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
 516                         "Disabled" : "Enabled");
 517         }
 518 }
 519
 520 /*
 521  * In BXT-P A0, HD-Audio DMA requests is later than expected,
 522  * and makes an audio stream sensitive to system latencies when
 523  * 24/32 bits are playing.
 524  * Adjusting threshold of DMA fifo to force the DMA request
 525  * sooner to improve latency tolerance at the expense of power.
 526  */
 527 static void bxt_reduce_dma_latency(struct azx *chip)
 528 {
 529         u32 val;
 530
 531         val = azx_readl(chip, SKL_EM4L);
 532         val &= (0x3 << 20);
 533         azx_writel(chip, SKL_EM4L, val);
 534 }
 535
 536 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
 537 {
 538         struct hdac_bus *bus = azx_bus(chip);
 539         struct pci_dev *pci = chip->pci;
 540         u32 val;
 541
 542         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
 543                 snd_hdac_set_codec_wakeup(bus, true);
 544         if (IS_SKL_PLUS(pci)) {
 545                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 546                 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
 547                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 548         }
 549         azx_init_chip(chip, full_reset);
 550         if (IS_SKL_PLUS(pci)) {
 551                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 552                 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
 553                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 554         }
 555         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
 556                 snd_hdac_set_codec_wakeup(bus, false);
 557
 558         /* reduce dma latency to avoid noise */
 559         if (IS_BXT(pci))
 560                 bxt_reduce_dma_latency(chip);
 561 }
 562
 563 /* calculate runtime delay from LPIB */
 564 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
 565                                    unsigned int pos)
 566 {
 567         struct snd_pcm_substream *substream = azx_dev->core.substream;
 568         int stream = substream->stream;
 569         unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
 570         int delay;
 571
 572         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
 573                 delay = pos - lpib_pos;
 574         else
 575                 delay = lpib_pos - pos;
 576         if (delay < 0) {
 577                 if (delay >= azx_dev->core.delay_negative_threshold)
 578                         delay = 0;
 579                 else
 580                         delay += azx_dev->core.bufsize;
 581         }
 582
 583         if (delay >= azx_dev->core.period_bytes) {
 584                 dev_info(chip->card->dev,
 585                          "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
 586                          delay, azx_dev->core.period_bytes);
 587                 delay = 0;
 588                 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
 589                 chip->get_delay[stream] = NULL;
 590         }
 591
 592         return bytes_to_frames(substream->runtime, delay);
 593 }
 594
 595 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
 596
 597 /* called from IRQ */
 598 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
 599 {
 600         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 601         int ok;
 602
 603         ok = azx_position_ok(chip, azx_dev);
 604         if (ok == 1) {
 605                 azx_dev->irq_pending = 0;
 606                 return ok;
 607         } else if (ok == 0) {
 608                 /* bogus IRQ, process it later */
 609                 azx_dev->irq_pending = 1;
 610                 schedule_work(&hda->irq_pending_work);
 611         }
 612         return 0;
 613 }
 614
 615 /* Enable/disable i915 display power for the link */
 616 static int azx_intel_link_power(struct azx *chip, bool enable)
 617 {
 618         struct hdac_bus *bus = azx_bus(chip);
 619
 620         return snd_hdac_display_power(bus, enable);
 621 }
 622
 623 /*
 624  * Check whether the current DMA position is acceptable for updating
 625  * periods.  Returns non-zero if it's OK.
 626  *
 627  * Many HD-audio controllers appear pretty inaccurate about
 628  * the update-IRQ timing.  The IRQ is issued before actually the
 629  * data is processed.  So, we need to process it afterwords in a
 630  * workqueue.
 631  */
 632 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
 633 {
 634         struct snd_pcm_substream *substream = azx_dev->core.substream;
 635         int stream = substream->stream;
 636         u32 wallclk;
 637         unsigned int pos;
 638
 639         wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
 640         if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
 641                 return -1;      /* bogus (too early) interrupt */
 642
 643         if (chip->get_position[stream])
 644                 pos = chip->get_position[stream](chip, azx_dev);
 645         else { /* use the position buffer as default */
 646                 pos = azx_get_pos_posbuf(chip, azx_dev);
 647                 if (!pos || pos == (u32)-1) {
 648                         dev_info(chip->card->dev,
 649                                  "Invalid position buffer, using LPIB read method instead.\n");
 650                         chip->get_position[stream] = azx_get_pos_lpib;
 651                         if (chip->get_position[0] == azx_get_pos_lpib &&
 652                             chip->get_position[1] == azx_get_pos_lpib)
 653                                 azx_bus(chip)->use_posbuf = false;
 654                         pos = azx_get_pos_lpib(chip, azx_dev);
 655                         chip->get_delay[stream] = NULL;
 656                 } else {
 657                         chip->get_position[stream] = azx_get_pos_posbuf;
 658                         if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
 659                                 chip->get_delay[stream] = azx_get_delay_from_lpib;
 660                 }
 661         }
 662
 663         if (pos >= azx_dev->core.bufsize)
 664                 pos = 0;
 665
 666         if (WARN_ONCE(!azx_dev->core.period_bytes,
 667                       "hda-intel: zero azx_dev->period_bytes"))
 668                 return -1; /* this shouldn't happen! */
 669         if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
 670             pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
 671                 /* NG - it's below the first next period boundary */
 672                 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1;
 673         azx_dev->core.start_wallclk += wallclk;
 674         return 1; /* OK, it's fine */
 675 }
 676
 677 /*
 678  * The work for pending PCM period updates.
 679  */
 680 static void azx_irq_pending_work(struct work_struct *work)
 681 {
 682         struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
 683         struct azx *chip = &hda->chip;
 684         struct hdac_bus *bus = azx_bus(chip);
 685         struct hdac_stream *s;
 686         int pending, ok;
 687
 688         if (!hda->irq_pending_warned) {
 689                 dev_info(chip->card->dev,
 690                          "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
 691                          chip->card->number);
 692                 hda->irq_pending_warned = 1;
 693         }
 694
 695         for (;;) {
 696                 pending = 0;
 697                 spin_lock_irq(&bus->reg_lock);
 698                 list_for_each_entry(s, &bus->stream_list, list) {
 699                         struct azx_dev *azx_dev = stream_to_azx_dev(s);
 700                         if (!azx_dev->irq_pending ||
 701                             !s->substream ||
 702                             !s->running)
 703                                 continue;
 704                         ok = azx_position_ok(chip, azx_dev);
 705                         if (ok > 0) {
 706                                 azx_dev->irq_pending = 0;
 707                                 spin_unlock(&bus->reg_lock);
 708                                 snd_pcm_period_elapsed(s->substream);
 709                                 spin_lock(&bus->reg_lock);
 710                         } else if (ok < 0) {
 711                                 pending = 0;    /* too early */
 712                         } else
 713                                 pending++;
 714                 }
 715                 spin_unlock_irq(&bus->reg_lock);
 716                 if (!pending)
 717                         return;
 718                 msleep(1);
 719         }
 720 }
 721
 722 /* clear irq_pending flags and assure no on-going workq */
 723 static void azx_clear_irq_pending(struct azx *chip)
 724 {
 725         struct hdac_bus *bus = azx_bus(chip);
 726         struct hdac_stream *s;
 727
 728         spin_lock_irq(&bus->reg_lock);
 729         list_for_each_entry(s, &bus->stream_list, list) {
 730                 struct azx_dev *azx_dev = stream_to_azx_dev(s);
 731                 azx_dev->irq_pending = 0;
 732         }
 733         spin_unlock_irq(&bus->reg_lock);
 734 }
 735
 736 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
 737 {
 738         struct hdac_bus *bus = azx_bus(chip);
 739
 740         if (request_irq(chip->pci->irq, azx_interrupt,
 741                         chip->msi ? 0 : IRQF_SHARED,
 742                         KBUILD_MODNAME, chip)) {
 743                 dev_err(chip->card->dev,
 744                         "unable to grab IRQ %d, disabling device\n",
 745                         chip->pci->irq);
 746                 if (do_disconnect)
 747                         snd_card_disconnect(chip->card);
 748                 return -1;
 749         }
 750         bus->irq = chip->pci->irq;
 751         pci_intx(chip->pci, !chip->msi);
 752         return 0;
 753 }
 754
 755 /* get the current DMA position with correction on VIA chips */
 756 static unsigned int azx_via_get_position(struct azx *chip,
 757                                          struct azx_dev *azx_dev)
 758 {
 759         unsigned int link_pos, mini_pos, bound_pos;
 760         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
 761         unsigned int fifo_size;
 762
 763         link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 764         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 765                 /* Playback, no problem using link position */
 766                 return link_pos;
 767         }
 768
 769         /* Capture */
 770         /* For new chipset,
 771          * use mod to get the DMA position just like old chipset
 772          */
 773         mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
 774         mod_dma_pos %= azx_dev->core.period_bytes;
 775
 776         /* azx_dev->fifo_size can't get FIFO size of in stream.
 777          * Get from base address + offset.
 778          */
 779         fifo_size = readw(azx_bus(chip)->remap_addr +
 780                           VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
 781
 782         if (azx_dev->insufficient) {
 783                 /* Link position never gather than FIFO size */
 784                 if (link_pos <= fifo_size)
 785                         return 0;
 786
 787                 azx_dev->insufficient = 0;
 788         }
 789
 790         if (link_pos <= fifo_size)
 791                 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
 792         else
 793                 mini_pos = link_pos - fifo_size;
 794
 795         /* Find nearest previous boudary */
 796         mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
 797         mod_link_pos = link_pos % azx_dev->core.period_bytes;
 798         if (mod_link_pos >= fifo_size)
 799                 bound_pos = link_pos - mod_link_pos;
 800         else if (mod_dma_pos >= mod_mini_pos)
 801                 bound_pos = mini_pos - mod_mini_pos;
 802         else {
 803                 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
 804                 if (bound_pos >= azx_dev->core.bufsize)
 805                         bound_pos = 0;
 806         }
 807
 808         /* Calculate real DMA position we want */
 809         return bound_pos + mod_dma_pos;
 810 }
 811
 812 #ifdef CONFIG_PM
 813 static DEFINE_MUTEX(card_list_lock);
 814 static LIST_HEAD(card_list);
 815
 816 static void azx_add_card_list(struct azx *chip)
 817 {
 818         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 819         mutex_lock(&card_list_lock);
 820         list_add(&hda->list, &card_list);
 821         mutex_unlock(&card_list_lock);
 822 }
 823
 824 static void azx_del_card_list(struct azx *chip)
 825 {
 826         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 827         mutex_lock(&card_list_lock);
 828         list_del_init(&hda->list);
 829         mutex_unlock(&card_list_lock);
 830 }
 831
 832 /* trigger power-save check at writing parameter */
 833 static int param_set_xint(const char *val, const struct kernel_param *kp)
 834 {
 835         struct hda_intel *hda;
 836         struct azx *chip;
 837         int prev = power_save;
 838         int ret = param_set_int(val, kp);
 839
 840         if (ret || prev == power_save)
 841                 return ret;
 842
 843         mutex_lock(&card_list_lock);
 844         list_for_each_entry(hda, &card_list, list) {
 845                 chip = &hda->chip;
 846                 if (!hda->probe_continued || chip->disabled)
 847                         continue;
 848                 snd_hda_set_power_save(&chip->bus, power_save * 1000);
 849         }
 850         mutex_unlock(&card_list_lock);
 851         return 0;
 852 }
 853 #else
 854 #define azx_add_card_list(chip) /* NOP */
 855 #define azx_del_card_list(chip) /* NOP */
 856 #endif /* CONFIG_PM */
 857
 858 /* Intel HSW/BDW display HDA controller is in GPU. Both its power and link BCLK
 859  * depends on GPU. Two Extended Mode registers EM4 (M value) and EM5 (N Value)
 860  * are used to convert CDClk (Core Display Clock) to 24MHz BCLK:
 861  * BCLK = CDCLK * M / N
 862  * The values will be lost when the display power well is disabled and need to
 863  * be restored to avoid abnormal playback speed.
 864  */
 865 static void haswell_set_bclk(struct hda_intel *hda)
 866 {
 867         struct azx *chip = &hda->chip;
 868         int cdclk_freq;
 869         unsigned int bclk_m, bclk_n;
 870
 871         if (!hda->need_i915_power)
 872                 return;
 873
 874         cdclk_freq = snd_hdac_get_display_clk(azx_bus(chip));
 875         switch (cdclk_freq) {
 876         case 337500:
 877                 bclk_m = 16;
 878                 bclk_n = 225;
 879                 break;
 880
 881         case 450000:
 882         default: /* default CDCLK 450MHz */
 883                 bclk_m = 4;
 884                 bclk_n = 75;
 885                 break;
 886
 887         case 540000:
 888                 bclk_m = 4;
 889                 bclk_n = 90;
 890                 break;
 891
 892         case 675000:
 893                 bclk_m = 8;
 894                 bclk_n = 225;
 895                 break;
 896         }
 897
 898         azx_writew(chip, HSW_EM4, bclk_m);
 899         azx_writew(chip, HSW_EM5, bclk_n);
 900 }
 901
 902 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
 903 /*
 904  * power management
 905  */
 906 static int azx_suspend(struct device *dev)
 907 {
 908         struct snd_card *card = dev_get_drvdata(dev);
 909         struct azx *chip;
 910         struct hda_intel *hda;
 911         struct hdac_bus *bus;
 912
 913         if (!card)
 914                 return 0;
 915
 916         chip = card->private_data;
 917         hda = container_of(chip, struct hda_intel, chip);
 918         if (chip->disabled || hda->init_failed || !chip->running)
 919                 return 0;
 920
 921         bus = azx_bus(chip);
 922         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
 923         azx_clear_irq_pending(chip);
 924         azx_stop_chip(chip);
 925         azx_enter_link_reset(chip);
 926         if (bus->irq >= 0) {
 927                 free_irq(bus->irq, chip);
 928                 bus->irq = -1;
 929         }
 930
 931         if (chip->msi)
 932                 pci_disable_msi(chip->pci);
 933         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
 934                 && hda->need_i915_power)
 935                 snd_hdac_display_power(bus, false);
 936
 937         trace_azx_suspend(chip);
 938         return 0;
 939 }
 940
 941 static int azx_resume(struct device *dev)
 942 {
 943         struct pci_dev *pci = to_pci_dev(dev);
 944         struct snd_card *card = dev_get_drvdata(dev);
 945         struct azx *chip;
 946         struct hda_intel *hda;
 947         struct hdac_bus *bus;
 948
 949         if (!card)
 950                 return 0;
 951
 952         chip = card->private_data;
 953         hda = container_of(chip, struct hda_intel, chip);
 954         bus = azx_bus(chip);
 955         if (chip->disabled || hda->init_failed || !chip->running)
 956                 return 0;
 957
 958         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
 959                 snd_hdac_display_power(bus, true);
 960                 if (hda->need_i915_power)
 961                         haswell_set_bclk(hda);
 962         }
 963
 964         if (chip->msi)
 965                 if (pci_enable_msi(pci) < 0)
 966                         chip->msi = 0;
 967         if (azx_acquire_irq(chip, 1) < 0)
 968                 return -EIO;
 969         azx_init_pci(chip);
 970
 971         hda_intel_init_chip(chip, true);
 972
 973         /* power down again for link-controlled chips */
 974         if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
 975             !hda->need_i915_power)
 976                 snd_hdac_display_power(bus, false);
 977
 978         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
 979
 980         trace_azx_resume(chip);
 981         return 0;
 982 }
 983 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
 984
 985 #ifdef CONFIG_PM_SLEEP
 986 /* put codec down to D3 at hibernation for Intel SKL+;
 987  * otherwise BIOS may still access the codec and screw up the driver
 988  */
 989 static int azx_freeze_noirq(struct device *dev)
 990 {
 991         struct pci_dev *pci = to_pci_dev(dev);
 992
 993         if (IS_SKL_PLUS(pci))
 994                 pci_set_power_state(pci, PCI_D3hot);
 995
 996         return 0;
 997 }
 998
 999 static int azx_thaw_noirq(struct device *dev)
1000 {
1001         struct pci_dev *pci = to_pci_dev(dev);
1002
1003         if (IS_SKL_PLUS(pci))
1004                 pci_set_power_state(pci, PCI_D0);
1005
1006         return 0;
1007 }
1008 #endif /* CONFIG_PM_SLEEP */
1009
1010 #ifdef CONFIG_PM
1011 static int azx_runtime_suspend(struct device *dev)
1012 {
1013         struct snd_card *card = dev_get_drvdata(dev);
1014         struct azx *chip;
1015         struct hda_intel *hda;
1016
1017         if (!card)
1018                 return 0;
1019
1020         chip = card->private_data;
1021         hda = container_of(chip, struct hda_intel, chip);
1022         if (chip->disabled || hda->init_failed)
1023                 return 0;
1024
1025         if (!azx_has_pm_runtime(chip))
1026                 return 0;
1027
1028         /* enable controller wake up event */
1029         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1030                   STATESTS_INT_MASK);
1031
1032         azx_stop_chip(chip);
1033         azx_enter_link_reset(chip);
1034         azx_clear_irq_pending(chip);
1035         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
1036                 && hda->need_i915_power)
1037                 snd_hdac_display_power(azx_bus(chip), false);
1038
1039         trace_azx_runtime_suspend(chip);
1040         return 0;
1041 }
1042
1043 static int azx_runtime_resume(struct device *dev)
1044 {
1045         struct snd_card *card = dev_get_drvdata(dev);
1046         struct azx *chip;
1047         struct hda_intel *hda;
1048         struct hdac_bus *bus;
1049         struct hda_codec *codec;
1050         int status;
1051
1052         if (!card)
1053                 return 0;
1054
1055         chip = card->private_data;
1056         hda = container_of(chip, struct hda_intel, chip);
1057         bus = azx_bus(chip);
1058         if (chip->disabled || hda->init_failed)
1059                 return 0;
1060
1061         if (!azx_has_pm_runtime(chip))
1062                 return 0;
1063
1064         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1065                 snd_hdac_display_power(bus, true);
1066                 if (hda->need_i915_power)
1067                         haswell_set_bclk(hda);
1068         }
1069
1070         /* Read STATESTS before controller reset */
1071         status = azx_readw(chip, STATESTS);
1072
1073         azx_init_pci(chip);
1074         hda_intel_init_chip(chip, true);
1075
1076         if (status) {
1077                 list_for_each_codec(codec, &chip->bus)
1078                         if (status & (1 << codec->addr))
1079                                 schedule_delayed_work(&codec->jackpoll_work,
1080                                                       codec->jackpoll_interval);
1081         }
1082
1083         /* disable controller Wake Up event*/
1084         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1085                         ~STATESTS_INT_MASK);
1086
1087         /* power down again for link-controlled chips */
1088         if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
1089             !hda->need_i915_power)
1090                 snd_hdac_display_power(bus, false);
1091
1092         trace_azx_runtime_resume(chip);
1093         return 0;
1094 }
1095
1096 static int azx_runtime_idle(struct device *dev)
1097 {
1098         struct snd_card *card = dev_get_drvdata(dev);
1099         struct azx *chip;
1100         struct hda_intel *hda;
1101
1102         if (!card)
1103                 return 0;
1104
1105         chip = card->private_data;
1106         hda = container_of(chip, struct hda_intel, chip);
1107         if (chip->disabled || hda->init_failed)
1108                 return 0;
1109
1110         if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1111             azx_bus(chip)->codec_powered || !chip->running)
1112                 return -EBUSY;
1113
1114         return 0;
1115 }
1116
1117 static const struct dev_pm_ops azx_pm = {
1118         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1119 #ifdef CONFIG_PM_SLEEP
1120         .freeze_noirq = azx_freeze_noirq,
1121         .thaw_noirq = azx_thaw_noirq,
1122 #endif
1123         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1124 };
1125
1126 #define AZX_PM_OPS      &azx_pm
1127 #else
1128 #define AZX_PM_OPS      NULL
1129 #endif /* CONFIG_PM */
1130
1131
1132 static int azx_probe_continue(struct azx *chip);
1133
1134 #ifdef SUPPORT_VGA_SWITCHEROO
1135 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1136
1137 static void azx_vs_set_state(struct pci_dev *pci,
1138                              enum vga_switcheroo_state state)
1139 {
1140         struct snd_card *card = pci_get_drvdata(pci);
1141         struct azx *chip = card->private_data;
1142         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1143         bool disabled;
1144
1145         wait_for_completion(&hda->probe_wait);
1146         if (hda->init_failed)
1147                 return;
1148
1149         disabled = (state == VGA_SWITCHEROO_OFF);
1150         if (chip->disabled == disabled)
1151                 return;
1152
1153         if (!hda->probe_continued) {
1154                 chip->disabled = disabled;
1155                 if (!disabled) {
1156                         dev_info(chip->card->dev,
1157                                  "Start delayed initialization\n");
1158                         if (azx_probe_continue(chip) < 0) {
1159                                 dev_err(chip->card->dev, "initialization error\n");
1160                                 hda->init_failed = true;
1161                         }
1162                 }
1163         } else {
1164                 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1165                          disabled ? "Disabling" : "Enabling");
1166                 if (disabled) {
1167                         pm_runtime_put_sync_suspend(card->dev);
1168                         azx_suspend(card->dev);
1169                         /* when we get suspended by vga_switcheroo we end up in D3cold,
1170                          * however we have no ACPI handle, so pci/acpi can't put us there,
1171                          * put ourselves there */
1172                         pci->current_state = PCI_D3cold;
1173                         chip->disabled = true;
1174                         if (snd_hda_lock_devices(&chip->bus))
1175                                 dev_warn(chip->card->dev,
1176                                          "Cannot lock devices!\n");
1177                 } else {
1178                         snd_hda_unlock_devices(&chip->bus);
1179                         pm_runtime_get_noresume(card->dev);
1180                         chip->disabled = false;
1181                         azx_resume(card->dev);
1182                 }
1183         }
1184 }
1185
1186 static bool azx_vs_can_switch(struct pci_dev *pci)
1187 {
1188         struct snd_card *card = pci_get_drvdata(pci);
1189         struct azx *chip = card->private_data;
1190         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1191
1192         wait_for_completion(&hda->probe_wait);
1193         if (hda->init_failed)
1194                 return false;
1195         if (chip->disabled || !hda->probe_continued)
1196                 return true;
1197         if (snd_hda_lock_devices(&chip->bus))
1198                 return false;
1199         snd_hda_unlock_devices(&chip->bus);
1200         return true;
1201 }
1202
1203 static void init_vga_switcheroo(struct azx *chip)
1204 {
1205         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1206         struct pci_dev *p = get_bound_vga(chip->pci);
1207         if (p) {
1208                 dev_info(chip->card->dev,
1209                          "Handle vga_switcheroo audio client\n");
1210                 hda->use_vga_switcheroo = 1;
1211                 pci_dev_put(p);
1212         }
1213 }
1214
1215 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1216         .set_gpu_state = azx_vs_set_state,
1217         .can_switch = azx_vs_can_switch,
1218 };
1219
1220 static int register_vga_switcheroo(struct azx *chip)
1221 {
1222         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1223         int err;
1224
1225         if (!hda->use_vga_switcheroo)
1226                 return 0;
1227         /* FIXME: currently only handling DIS controller
1228          * is there any machine with two switchable HDMI audio controllers?
1229          */
1230         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
1231                                                    VGA_SWITCHEROO_DIS);
1232         if (err < 0)
1233                 return err;
1234         hda->vga_switcheroo_registered = 1;
1235
1236         /* register as an optimus hdmi audio power domain */
1237         vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
1238                                                          &hda->hdmi_pm_domain);
1239         return 0;
1240 }
1241 #else
1242 #define init_vga_switcheroo(chip)               /* NOP */
1243 #define register_vga_switcheroo(chip)           0
1244 #define check_hdmi_disabled(pci)        false
1245 #endif /* SUPPORT_VGA_SWITCHER */
1246
1247 /*
1248  * destructor
1249  */
1250 static int azx_free(struct azx *chip)
1251 {
1252         struct pci_dev *pci = chip->pci;
1253         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1254         struct hdac_bus *bus = azx_bus(chip);
1255
1256         if (azx_has_pm_runtime(chip) && chip->running)
1257                 pm_runtime_get_noresume(&pci->dev);
1258
1259         azx_del_card_list(chip);
1260
1261         hda->init_failed = 1; /* to be sure */
1262         complete_all(&hda->probe_wait);
1263
1264         if (use_vga_switcheroo(hda)) {
1265                 if (chip->disabled && hda->probe_continued)
1266                         snd_hda_unlock_devices(&chip->bus);
1267                 if (hda->vga_switcheroo_registered) {
1268                         vga_switcheroo_unregister_client(chip->pci);
1269                         vga_switcheroo_fini_domain_pm_ops(chip->card->dev);
1270                 }
1271         }
1272
1273         if (bus->chip_init) {
1274                 azx_clear_irq_pending(chip);
1275                 azx_stop_all_streams(chip);
1276                 azx_stop_chip(chip);
1277         }
1278
1279         if (bus->irq >= 0)
1280                 free_irq(bus->irq, (void*)chip);
1281         if (chip->msi)
1282                 pci_disable_msi(chip->pci);
1283         iounmap(bus->remap_addr);
1284
1285         azx_free_stream_pages(chip);
1286         azx_free_streams(chip);
1287         snd_hdac_bus_exit(bus);
1288
1289         if (chip->region_requested)
1290                 pci_release_regions(chip->pci);
1291
1292         pci_disable_device(chip->pci);
1293 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1294         release_firmware(chip->fw);
1295 #endif
1296
1297         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1298                 if (hda->need_i915_power)
1299                         snd_hdac_display_power(bus, false);
1300                 snd_hdac_i915_exit(bus);
1301         }
1302         kfree(hda);
1303
1304         return 0;
1305 }
1306
1307 static int azx_dev_disconnect(struct snd_device *device)
1308 {
1309         struct azx *chip = device->device_data;
1310
1311         chip->bus.shutdown = 1;
1312         return 0;
1313 }
1314
1315 static int azx_dev_free(struct snd_device *device)
1316 {
1317         return azx_free(device->device_data);
1318 }
1319
1320 #ifdef SUPPORT_VGA_SWITCHEROO
1321 /*
1322  * Check of disabled HDMI controller by vga_switcheroo
1323  */
1324 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1325 {
1326         struct pci_dev *p;
1327
1328         /* check only discrete GPU */
1329         switch (pci->vendor) {
1330         case PCI_VENDOR_ID_ATI:
1331         case PCI_VENDOR_ID_AMD:
1332         case PCI_VENDOR_ID_NVIDIA:
1333                 if (pci->devfn == 1) {
1334                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1335                                                         pci->bus->number, 0);
1336                         if (p) {
1337                                 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1338                                         return p;
1339                                 pci_dev_put(p);
1340                         }
1341                 }
1342                 break;
1343         }
1344         return NULL;
1345 }
1346
1347 static bool check_hdmi_disabled(struct pci_dev *pci)
1348 {
1349         bool vga_inactive = false;
1350         struct pci_dev *p = get_bound_vga(pci);
1351
1352         if (p) {
1353                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1354                         vga_inactive = true;
1355                 pci_dev_put(p);
1356         }
1357         return vga_inactive;
1358 }
1359 #endif /* SUPPORT_VGA_SWITCHEROO */
1360
1361 /*
1362  * white/black-listing for position_fix
1363  */
1364 static struct snd_pci_quirk position_fix_list[] = {
1365         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1366         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1367         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1368         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1369         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1370         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1371         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1372         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1373         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1374         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1375         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1376         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1377         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1378         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1379         {}
1380 };
1381
1382 static int check_position_fix(struct azx *chip, int fix)
1383 {
1384         const struct snd_pci_quirk *q;
1385
1386         switch (fix) {
1387         case POS_FIX_AUTO:
1388         case POS_FIX_LPIB:
1389         case POS_FIX_POSBUF:
1390         case POS_FIX_VIACOMBO:
1391         case POS_FIX_COMBO:
1392                 return fix;
1393         }
1394
1395         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1396         if (q) {
1397                 dev_info(chip->card->dev,
1398                          "position_fix set to %d for device %04x:%04x\n",
1399                          q->value, q->subvendor, q->subdevice);
1400                 return q->value;
1401         }
1402
1403         /* Check VIA/ATI HD Audio Controller exist */
1404         if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
1405                 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1406                 return POS_FIX_VIACOMBO;
1407         }
1408         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1409                 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1410                 return POS_FIX_LPIB;
1411         }
1412         return POS_FIX_AUTO;
1413 }
1414
1415 static void assign_position_fix(struct azx *chip, int fix)
1416 {
1417         static azx_get_pos_callback_t callbacks[] = {
1418                 [POS_FIX_AUTO] = NULL,
1419                 [POS_FIX_LPIB] = azx_get_pos_lpib,
1420                 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1421                 [POS_FIX_VIACOMBO] = azx_via_get_position,
1422                 [POS_FIX_COMBO] = azx_get_pos_lpib,
1423         };
1424
1425         chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1426
1427         /* combo mode uses LPIB only for playback */
1428         if (fix == POS_FIX_COMBO)
1429                 chip->get_position[1] = NULL;
1430
1431         if (fix == POS_FIX_POSBUF &&
1432             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1433                 chip->get_delay[0] = chip->get_delay[1] =
1434                         azx_get_delay_from_lpib;
1435         }
1436
1437 }
1438
1439 /*
1440  * black-lists for probe_mask
1441  */
1442 static struct snd_pci_quirk probe_mask_list[] = {
1443         /* Thinkpad often breaks the controller communication when accessing
1444          * to the non-working (or non-existing) modem codec slot.
1445          */
1446         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1447         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1448         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1449         /* broken BIOS */
1450         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1451         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1452         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1453         /* forced codec slots */
1454         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1455         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1456         /* WinFast VP200 H (Teradici) user reported broken communication */
1457         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1458         {}
1459 };
1460
1461 #define AZX_FORCE_CODEC_MASK    0x100
1462
1463 static void check_probe_mask(struct azx *chip, int dev)
1464 {
1465         const struct snd_pci_quirk *q;
1466
1467         chip->codec_probe_mask = probe_mask[dev];
1468         if (chip->codec_probe_mask == -1) {
1469                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1470                 if (q) {
1471                         dev_info(chip->card->dev,
1472                                  "probe_mask set to 0x%x for device %04x:%04x\n",
1473                                  q->value, q->subvendor, q->subdevice);
1474                         chip->codec_probe_mask = q->value;
1475                 }
1476         }
1477
1478         /* check forced option */
1479         if (chip->codec_probe_mask != -1 &&
1480             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1481                 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1482                 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1483                          (int)azx_bus(chip)->codec_mask);
1484         }
1485 }
1486
1487 /*
1488  * white/black-list for enable_msi
1489  */
1490 static struct snd_pci_quirk msi_black_list[] = {
1491         SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1492         SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1493         SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1494         SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1495         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1496         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1497         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1498         SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1499         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1500         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1501         {}
1502 };
1503
1504 static void check_msi(struct azx *chip)
1505 {
1506         const struct snd_pci_quirk *q;
1507
1508         if (enable_msi >= 0) {
1509                 chip->msi = !!enable_msi;
1510                 return;
1511         }
1512         chip->msi = 1;  /* enable MSI as default */
1513         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1514         if (q) {
1515                 dev_info(chip->card->dev,
1516                          "msi for device %04x:%04x set to %d\n",
1517                          q->subvendor, q->subdevice, q->value);
1518                 chip->msi = q->value;
1519                 return;
1520         }
1521
1522         /* NVidia chipsets seem to cause troubles with MSI */
1523         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1524                 dev_info(chip->card->dev, "Disabling MSI\n");
1525                 chip->msi = 0;
1526         }
1527 }
1528
1529 /* check the snoop mode availability */
1530 static void azx_check_snoop_available(struct azx *chip)
1531 {
1532         int snoop = hda_snoop;
1533
1534         if (snoop >= 0) {
1535                 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1536                          snoop ? "snoop" : "non-snoop");
1537                 chip->snoop = snoop;
1538                 return;
1539         }
1540
1541         snoop = true;
1542         if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1543             chip->driver_type == AZX_DRIVER_VIA) {
1544                 /* force to non-snoop mode for a new VIA controller
1545                  * when BIOS is set
1546                  */
1547                 u8 val;
1548                 pci_read_config_byte(chip->pci, 0x42, &val);
1549                 if (!(val & 0x80) && chip->pci->revision == 0x30)
1550                         snoop = false;
1551         }
1552
1553         if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1554                 snoop = false;
1555
1556         chip->snoop = snoop;
1557         if (!snoop)
1558                 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1559 }
1560
1561 static void azx_probe_work(struct work_struct *work)
1562 {
1563         struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1564         azx_probe_continue(&hda->chip);
1565 }
1566
1567 /*
1568  * constructor
1569  */
1570 static const struct hdac_io_ops pci_hda_io_ops;
1571 static const struct hda_controller_ops pci_hda_ops;
1572
1573 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1574                       int dev, unsigned int driver_caps,
1575                       struct azx **rchip)
1576 {
1577         static struct snd_device_ops ops = {
1578                 .dev_disconnect = azx_dev_disconnect,
1579                 .dev_free = azx_dev_free,
1580         };
1581         struct hda_intel *hda;
1582         struct azx *chip;
1583         int err;
1584
1585         *rchip = NULL;
1586
1587         err = pci_enable_device(pci);
1588         if (err < 0)
1589                 return err;
1590
1591         hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1592         if (!hda) {
1593                 pci_disable_device(pci);
1594                 return -ENOMEM;
1595         }
1596
1597         chip = &hda->chip;
1598         mutex_init(&chip->open_mutex);
1599         chip->card = card;
1600         chip->pci = pci;
1601         chip->ops = &pci_hda_ops;
1602         chip->driver_caps = driver_caps;
1603         chip->driver_type = driver_caps & 0xff;
1604         check_msi(chip);
1605         chip->dev_index = dev;
1606         chip->jackpoll_ms = jackpoll_ms;
1607         INIT_LIST_HEAD(&chip->pcm_list);
1608         INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1609         INIT_LIST_HEAD(&hda->list);
1610         init_vga_switcheroo(chip);
1611         init_completion(&hda->probe_wait);
1612
1613         assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1614
1615         check_probe_mask(chip, dev);
1616
1617         chip->single_cmd = single_cmd;
1618         azx_check_snoop_available(chip);
1619
1620         if (bdl_pos_adj[dev] < 0) {
1621                 switch (chip->driver_type) {
1622                 case AZX_DRIVER_ICH:
1623                 case AZX_DRIVER_PCH:
1624                         bdl_pos_adj[dev] = 1;
1625                         break;
1626                 default:
1627                         bdl_pos_adj[dev] = 32;
1628                         break;
1629                 }
1630         }
1631         chip->bdl_pos_adj = bdl_pos_adj;
1632
1633         err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1634         if (err < 0) {
1635                 kfree(hda);
1636                 pci_disable_device(pci);
1637                 return err;
1638         }
1639
1640         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1641         if (err < 0) {
1642                 dev_err(card->dev, "Error creating device [card]!\n");
1643                 azx_free(chip);
1644                 return err;
1645         }
1646
1647         /* continue probing in work context as may trigger request module */
1648         INIT_WORK(&hda->probe_work, azx_probe_work);
1649
1650         *rchip = chip;
1651
1652         return 0;
1653 }
1654
1655 static int azx_first_init(struct azx *chip)
1656 {
1657         int dev = chip->dev_index;
1658         struct pci_dev *pci = chip->pci;
1659         struct snd_card *card = chip->card;
1660         struct hdac_bus *bus = azx_bus(chip);
1661         int err;
1662         unsigned short gcap;
1663         unsigned int dma_bits = 64;
1664
1665 #if BITS_PER_LONG != 64
1666         /* Fix up base address on ULI M5461 */
1667         if (chip->driver_type == AZX_DRIVER_ULI) {
1668                 u16 tmp3;
1669                 pci_read_config_word(pci, 0x40, &tmp3);
1670                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1671                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1672         }
1673 #endif
1674
1675         err = pci_request_regions(pci, "ICH HD audio");
1676         if (err < 0)
1677                 return err;
1678         chip->region_requested = 1;
1679
1680         bus->addr = pci_resource_start(pci, 0);
1681         bus->remap_addr = pci_ioremap_bar(pci, 0);
1682         if (bus->remap_addr == NULL) {
1683                 dev_err(card->dev, "ioremap error\n");
1684                 return -ENXIO;
1685         }
1686
1687         if (chip->msi) {
1688                 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1689                         dev_dbg(card->dev, "Disabling 64bit MSI\n");
1690                         pci->no_64bit_msi = true;
1691                 }
1692                 if (pci_enable_msi(pci) < 0)
1693                         chip->msi = 0;
1694         }
1695
1696         if (azx_acquire_irq(chip, 0) < 0)
1697                 return -EBUSY;
1698
1699         pci_set_master(pci);
1700         synchronize_irq(bus->irq);
1701
1702         gcap = azx_readw(chip, GCAP);
1703         dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1704
1705         /* AMD devices support 40 or 48bit DMA, take the safe one */
1706         if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1707                 dma_bits = 40;
1708
1709         /* disable SB600 64bit support for safety */
1710         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1711                 struct pci_dev *p_smbus;
1712                 dma_bits = 40;
1713                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1714                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1715                                          NULL);
1716                 if (p_smbus) {
1717                         if (p_smbus->revision < 0x30)
1718                                 gcap &= ~AZX_GCAP_64OK;
1719                         pci_dev_put(p_smbus);
1720                 }
1721         }
1722
1723         /* disable 64bit DMA address on some devices */
1724         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1725                 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1726                 gcap &= ~AZX_GCAP_64OK;
1727         }
1728
1729         /* disable buffer size rounding to 128-byte multiples if supported */
1730         if (align_buffer_size >= 0)
1731                 chip->align_buffer_size = !!align_buffer_size;
1732         else {
1733                 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1734                         chip->align_buffer_size = 0;
1735                 else
1736                         chip->align_buffer_size = 1;
1737         }
1738
1739         /* allow 64bit DMA address if supported by H/W */
1740         if (!(gcap & AZX_GCAP_64OK))
1741                 dma_bits = 32;
1742         if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1743                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1744         } else {
1745                 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1746                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1747         }
1748
1749         /* read number of streams from GCAP register instead of using
1750          * hardcoded value
1751          */
1752         chip->capture_streams = (gcap >> 8) & 0x0f;
1753         chip->playback_streams = (gcap >> 12) & 0x0f;
1754         if (!chip->playback_streams && !chip->capture_streams) {
1755                 /* gcap didn't give any info, switching to old method */
1756
1757                 switch (chip->driver_type) {
1758                 case AZX_DRIVER_ULI:
1759                         chip->playback_streams = ULI_NUM_PLAYBACK;
1760                         chip->capture_streams = ULI_NUM_CAPTURE;
1761                         break;
1762                 case AZX_DRIVER_ATIHDMI:
1763                 case AZX_DRIVER_ATIHDMI_NS:
1764                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1765                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1766                         break;
1767                 case AZX_DRIVER_GENERIC:
1768                 default:
1769                         chip->playback_streams = ICH6_NUM_PLAYBACK;
1770                         chip->capture_streams = ICH6_NUM_CAPTURE;
1771                         break;
1772                 }
1773         }
1774         chip->capture_index_offset = 0;
1775         chip->playback_index_offset = chip->capture_streams;
1776         chip->num_streams = chip->playback_streams + chip->capture_streams;
1777
1778         /* initialize streams */
1779         err = azx_init_streams(chip);
1780         if (err < 0)
1781                 return err;
1782
1783         err = azx_alloc_stream_pages(chip);
1784         if (err < 0)
1785                 return err;
1786
1787         /* initialize chip */
1788         azx_init_pci(chip);
1789
1790         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1791                 struct hda_intel *hda;
1792
1793                 hda = container_of(chip, struct hda_intel, chip);
1794                 haswell_set_bclk(hda);
1795         }
1796
1797         hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1798
1799         /* codec detection */
1800         if (!azx_bus(chip)->codec_mask) {
1801                 dev_err(card->dev, "no codecs found!\n");
1802                 return -ENODEV;
1803         }
1804
1805         strcpy(card->driver, "HDA-Intel");
1806         strlcpy(card->shortname, driver_short_names[chip->driver_type],
1807                 sizeof(card->shortname));
1808         snprintf(card->longname, sizeof(card->longname),
1809                  "%s at 0x%lx irq %i",
1810                  card->shortname, bus->addr, bus->irq);
1811
1812         return 0;
1813 }
1814
1815 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1816 /* callback from request_firmware_nowait() */
1817 static void azx_firmware_cb(const struct firmware *fw, void *context)
1818 {
1819         struct snd_card *card = context;
1820         struct azx *chip = card->private_data;
1821         struct pci_dev *pci = chip->pci;
1822
1823         if (!fw) {
1824                 dev_err(card->dev, "Cannot load firmware, aborting\n");
1825                 goto error;
1826         }
1827
1828         chip->fw = fw;
1829         if (!chip->disabled) {
1830                 /* continue probing */
1831                 if (azx_probe_continue(chip))
1832                         goto error;
1833         }
1834         return; /* OK */
1835
1836  error:
1837         snd_card_free(card);
1838         pci_set_drvdata(pci, NULL);
1839 }
1840 #endif
1841
1842 /*
1843  * HDA controller ops.
1844  */
1845
1846 /* PCI register access. */
1847 static void pci_azx_writel(u32 value, u32 __iomem *addr)
1848 {
1849         writel(value, addr);
1850 }
1851
1852 static u32 pci_azx_readl(u32 __iomem *addr)
1853 {
1854         return readl(addr);
1855 }
1856
1857 static void pci_azx_writew(u16 value, u16 __iomem *addr)
1858 {
1859         writew(value, addr);
1860 }
1861
1862 static u16 pci_azx_readw(u16 __iomem *addr)
1863 {
1864         return readw(addr);
1865 }
1866
1867 static void pci_azx_writeb(u8 value, u8 __iomem *addr)
1868 {
1869         writeb(value, addr);
1870 }
1871
1872 static u8 pci_azx_readb(u8 __iomem *addr)
1873 {
1874         return readb(addr);
1875 }
1876
1877 static int disable_msi_reset_irq(struct azx *chip)
1878 {
1879         struct hdac_bus *bus = azx_bus(chip);
1880         int err;
1881
1882         free_irq(bus->irq, chip);
1883         bus->irq = -1;
1884         pci_disable_msi(chip->pci);
1885         chip->msi = 0;
1886         err = azx_acquire_irq(chip, 1);
1887         if (err < 0)
1888                 return err;
1889
1890         return 0;
1891 }
1892
1893 /* DMA page allocation helpers.  */
1894 static int dma_alloc_pages(struct hdac_bus *bus,
1895                            int type,
1896                            size_t size,
1897                            struct snd_dma_buffer *buf)
1898 {
1899         struct azx *chip = bus_to_azx(bus);
1900         int err;
1901
1902         err = snd_dma_alloc_pages(type,
1903                                   bus->dev,
1904                                   size, buf);
1905         if (err < 0)
1906                 return err;
1907         mark_pages_wc(chip, buf, true);
1908         return 0;
1909 }
1910
1911 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
1912 {
1913         struct azx *chip = bus_to_azx(bus);
1914
1915         mark_pages_wc(chip, buf, false);
1916         snd_dma_free_pages(buf);
1917 }
1918
1919 static int substream_alloc_pages(struct azx *chip,
1920                                  struct snd_pcm_substream *substream,
1921                                  size_t size)
1922 {
1923         struct azx_dev *azx_dev = get_azx_dev(substream);
1924         int ret;
1925
1926         mark_runtime_wc(chip, azx_dev, substream, false);
1927         ret = snd_pcm_lib_malloc_pages(substream, size);
1928         if (ret < 0)
1929                 return ret;
1930         mark_runtime_wc(chip, azx_dev, substream, true);
1931         return 0;
1932 }
1933
1934 static int substream_free_pages(struct azx *chip,
1935                                 struct snd_pcm_substream *substream)
1936 {
1937         struct azx_dev *azx_dev = get_azx_dev(substream);
1938         mark_runtime_wc(chip, azx_dev, substream, false);
1939         return snd_pcm_lib_free_pages(substream);
1940 }
1941
1942 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1943                              struct vm_area_struct *area)
1944 {
1945 #ifdef CONFIG_X86
1946         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1947         struct azx *chip = apcm->chip;
1948         if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
1949                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1950 #endif
1951 }
1952
1953 static const struct hdac_io_ops pci_hda_io_ops = {
1954         .reg_writel = pci_azx_writel,
1955         .reg_readl = pci_azx_readl,
1956         .reg_writew = pci_azx_writew,
1957         .reg_readw = pci_azx_readw,
1958         .reg_writeb = pci_azx_writeb,
1959         .reg_readb = pci_azx_readb,
1960         .dma_alloc_pages = dma_alloc_pages,
1961         .dma_free_pages = dma_free_pages,
1962 };
1963
1964 static const struct hda_controller_ops pci_hda_ops = {
1965         .disable_msi_reset_irq = disable_msi_reset_irq,
1966         .substream_alloc_pages = substream_alloc_pages,
1967         .substream_free_pages = substream_free_pages,
1968         .pcm_mmap_prepare = pcm_mmap_prepare,
1969         .position_check = azx_position_check,
1970         .link_power = azx_intel_link_power,
1971 };
1972
1973 static int azx_probe(struct pci_dev *pci,
1974                      const struct pci_device_id *pci_id)
1975 {
1976         static int dev;
1977         struct snd_card *card;
1978         struct hda_intel *hda;
1979         struct azx *chip;
1980         bool schedule_probe;
1981         int err;
1982
1983         if (dev >= SNDRV_CARDS)
1984                 return -ENODEV;
1985         if (!enable[dev]) {
1986                 dev++;
1987                 return -ENOENT;
1988         }
1989
1990         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1991                            0, &card);
1992         if (err < 0) {
1993                 dev_err(&pci->dev, "Error creating card!\n");
1994                 return err;
1995         }
1996
1997         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
1998         if (err < 0)
1999                 goto out_free;
2000         card->private_data = chip;
2001         hda = container_of(chip, struct hda_intel, chip);
2002
2003         pci_set_drvdata(pci, card);
2004
2005         err = register_vga_switcheroo(chip);
2006         if (err < 0) {
2007                 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2008                 goto out_free;
2009         }
2010
2011         if (check_hdmi_disabled(pci)) {
2012                 dev_info(card->dev, "VGA controller is disabled\n");
2013                 dev_info(card->dev, "Delaying initialization\n");
2014                 chip->disabled = true;
2015         }
2016
2017         schedule_probe = !chip->disabled;
2018
2019 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2020         if (patch[dev] && *patch[dev]) {
2021                 dev_info(card->dev, "Applying patch firmware '%s'\n",
2022                          patch[dev]);
2023                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2024                                               &pci->dev, GFP_KERNEL, card,
2025                                               azx_firmware_cb);
2026                 if (err < 0)
2027                         goto out_free;
2028                 schedule_probe = false; /* continued in azx_firmware_cb() */
2029         }
2030 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2031
2032 #ifndef CONFIG_SND_HDA_I915
2033         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2034                 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n");
2035 #endif
2036
2037         if (schedule_probe)
2038                 schedule_work(&hda->probe_work);
2039
2040         dev++;
2041         if (chip->disabled)
2042                 complete_all(&hda->probe_wait);
2043         return 0;
2044
2045 out_free:
2046         snd_card_free(card);
2047         return err;
2048 }
2049
2050 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2051 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2052         [AZX_DRIVER_NVIDIA] = 8,
2053         [AZX_DRIVER_TERA] = 1,
2054 };
2055
2056 static int azx_probe_continue(struct azx *chip)
2057 {
2058         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2059         struct hdac_bus *bus = azx_bus(chip);
2060         struct pci_dev *pci = chip->pci;
2061         int dev = chip->dev_index;
2062         int err;
2063
2064         hda->probe_continued = 1;
2065
2066         /* Request display power well for the HDA controller or codec. For
2067          * Haswell/Broadwell, both the display HDA controller and codec need
2068          * this power. For other platforms, like Baytrail/Braswell, only the
2069          * display codec needs the power and it can be released after probe.
2070          */
2071         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
2072                 /* HSW/BDW controllers need this power */
2073                 if (CONTROLLER_IN_GPU(pci))
2074                         hda->need_i915_power = 1;
2075
2076                 err = snd_hdac_i915_init(bus);
2077                 if (err < 0) {
2078                         /* if the controller is bound only with HDMI/DP
2079                          * (for HSW and BDW), we need to abort the probe;
2080                          * for other chips, still continue probing as other
2081                          * codecs can be on the same link.
2082                          */
2083                         if (CONTROLLER_IN_GPU(pci))
2084                                 goto out_free;
2085                         else
2086                                 goto skip_i915;
2087                 }
2088
2089                 err = snd_hdac_display_power(bus, true);
2090                 if (err < 0) {
2091                         dev_err(chip->card->dev,
2092                                 "Cannot turn on display power on i915\n");
2093                         goto i915_power_fail;
2094                 }
2095         }
2096
2097  skip_i915:
2098         err = azx_first_init(chip);
2099         if (err < 0)
2100                 goto out_free;
2101
2102 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2103         chip->beep_mode = beep_mode[dev];
2104 #endif
2105
2106         /* create codec instances */
2107         err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2108         if (err < 0)
2109                 goto out_free;
2110
2111 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2112         if (chip->fw) {
2113                 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2114                                          chip->fw->data);
2115                 if (err < 0)
2116                         goto out_free;
2117 #ifndef CONFIG_PM
2118                 release_firmware(chip->fw); /* no longer needed */
2119                 chip->fw = NULL;
2120 #endif
2121         }
2122 #endif
2123         if ((probe_only[dev] & 1) == 0) {
2124                 err = azx_codec_configure(chip);
2125                 if (err < 0)
2126                         goto out_free;
2127         }
2128
2129         err = snd_card_register(chip->card);
2130         if (err < 0)
2131                 goto out_free;
2132
2133         chip->running = 1;
2134         azx_add_card_list(chip);
2135         snd_hda_set_power_save(&chip->bus, power_save * 1000);
2136         if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo)
2137                 pm_runtime_put_noidle(&pci->dev);
2138
2139 out_free:
2140         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
2141                 && !hda->need_i915_power)
2142                 snd_hdac_display_power(bus, false);
2143
2144 i915_power_fail:
2145         if (err < 0)
2146                 hda->init_failed = 1;
2147         complete_all(&hda->probe_wait);
2148         return err;
2149 }
2150
2151 static void azx_remove(struct pci_dev *pci)
2152 {
2153         struct snd_card *card = pci_get_drvdata(pci);
2154         struct azx *chip;
2155         struct hda_intel *hda;
2156
2157         if (card) {
2158                 /* cancel the pending probing work */
2159                 chip = card->private_data;
2160                 hda = container_of(chip, struct hda_intel, chip);
2161                 cancel_work_sync(&hda->probe_work);
2162
2163                 snd_card_free(card);
2164         }
2165 }
2166
2167 static void azx_shutdown(struct pci_dev *pci)
2168 {
2169         struct snd_card *card = pci_get_drvdata(pci);
2170         struct azx *chip;
2171
2172         if (!card)
2173                 return;
2174         chip = card->private_data;
2175         if (chip && chip->running)
2176                 azx_stop_chip(chip);
2177 }
2178
2179 /* PCI IDs */
2180 static const struct pci_device_id azx_ids[] = {
2181         /* CPT */
2182         { PCI_DEVICE(0x8086, 0x1c20),
2183           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2184         /* PBG */
2185         { PCI_DEVICE(0x8086, 0x1d20),
2186           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2187         /* Panther Point */
2188         { PCI_DEVICE(0x8086, 0x1e20),
2189           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2190         /* Lynx Point */
2191         { PCI_DEVICE(0x8086, 0x8c20),
2192           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2193         /* 9 Series */
2194         { PCI_DEVICE(0x8086, 0x8ca0),
2195           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2196         /* Wellsburg */
2197         { PCI_DEVICE(0x8086, 0x8d20),
2198           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2199         { PCI_DEVICE(0x8086, 0x8d21),
2200           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2201         /* Lewisburg */
2202         { PCI_DEVICE(0x8086, 0xa1f0),
2203           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2204         { PCI_DEVICE(0x8086, 0xa270),
2205           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2206         /* Lynx Point-LP */
2207         { PCI_DEVICE(0x8086, 0x9c20),
2208           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2209         /* Lynx Point-LP */
2210         { PCI_DEVICE(0x8086, 0x9c21),
2211           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2212         /* Wildcat Point-LP */
2213         { PCI_DEVICE(0x8086, 0x9ca0),
2214           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2215         /* Sunrise Point */
2216         { PCI_DEVICE(0x8086, 0xa170),
2217           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2218         /* Sunrise Point-LP */
2219         { PCI_DEVICE(0x8086, 0x9d70),
2220           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2221         /* Kabylake */
2222         { PCI_DEVICE(0x8086, 0xa171),
2223           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2224         /* Kabylake-LP */
2225         { PCI_DEVICE(0x8086, 0x9d71),
2226           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2227         /* Kabylake-H */
2228         { PCI_DEVICE(0x8086, 0xa2f0),
2229           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2230         /* Broxton-P(Apollolake) */
2231         { PCI_DEVICE(0x8086, 0x5a98),
2232           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON },
2233         /* Broxton-T */
2234         { PCI_DEVICE(0x8086, 0x1a98),
2235           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON },
2236         /* Haswell */
2237         { PCI_DEVICE(0x8086, 0x0a0c),
2238           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2239         { PCI_DEVICE(0x8086, 0x0c0c),
2240           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2241         { PCI_DEVICE(0x8086, 0x0d0c),
2242           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2243         /* Broadwell */
2244         { PCI_DEVICE(0x8086, 0x160c),
2245           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2246         /* 5 Series/3400 */
2247         { PCI_DEVICE(0x8086, 0x3b56),
2248           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2249         /* Poulsbo */
2250         { PCI_DEVICE(0x8086, 0x811b),
2251           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2252         /* Oaktrail */
2253         { PCI_DEVICE(0x8086, 0x080a),
2254           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2255         /* BayTrail */
2256         { PCI_DEVICE(0x8086, 0x0f04),
2257           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2258         /* Braswell */
2259         { PCI_DEVICE(0x8086, 0x2284),
2260           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2261         /* ICH6 */
2262         { PCI_DEVICE(0x8086, 0x2668),
2263           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2264         /* ICH7 */
2265         { PCI_DEVICE(0x8086, 0x27d8),
2266           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2267         /* ESB2 */
2268         { PCI_DEVICE(0x8086, 0x269a),
2269           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2270         /* ICH8 */
2271         { PCI_DEVICE(0x8086, 0x284b),
2272           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2273         /* ICH9 */
2274         { PCI_DEVICE(0x8086, 0x293e),
2275           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2276         /* ICH9 */
2277         { PCI_DEVICE(0x8086, 0x293f),
2278           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2279         /* ICH10 */
2280         { PCI_DEVICE(0x8086, 0x3a3e),
2281           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2282         /* ICH10 */
2283         { PCI_DEVICE(0x8086, 0x3a6e),
2284           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2285         /* Generic Intel */
2286         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2287           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2288           .class_mask = 0xffffff,
2289           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2290         /* ATI SB 450/600/700/800/900 */
2291         { PCI_DEVICE(0x1002, 0x437b),
2292           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2293         { PCI_DEVICE(0x1002, 0x4383),
2294           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2295         /* AMD Hudson */
2296         { PCI_DEVICE(0x1022, 0x780d),
2297           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2298         /* ATI HDMI */
2299         { PCI_DEVICE(0x1002, 0x0002),
2300           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2301         { PCI_DEVICE(0x1002, 0x1308),
2302           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2303         { PCI_DEVICE(0x1002, 0x157a),
2304           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2305         { PCI_DEVICE(0x1002, 0x15b3),
2306           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2307         { PCI_DEVICE(0x1002, 0x793b),
2308           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2309         { PCI_DEVICE(0x1002, 0x7919),
2310           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2311         { PCI_DEVICE(0x1002, 0x960f),
2312           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2313         { PCI_DEVICE(0x1002, 0x970f),
2314           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2315         { PCI_DEVICE(0x1002, 0x9840),
2316           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2317         { PCI_DEVICE(0x1002, 0xaa00),
2318           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2319         { PCI_DEVICE(0x1002, 0xaa08),
2320           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2321         { PCI_DEVICE(0x1002, 0xaa10),
2322           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2323         { PCI_DEVICE(0x1002, 0xaa18),
2324           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2325         { PCI_DEVICE(0x1002, 0xaa20),
2326           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2327         { PCI_DEVICE(0x1002, 0xaa28),
2328           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2329         { PCI_DEVICE(0x1002, 0xaa30),
2330           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2331         { PCI_DEVICE(0x1002, 0xaa38),
2332           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2333         { PCI_DEVICE(0x1002, 0xaa40),
2334           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2335         { PCI_DEVICE(0x1002, 0xaa48),
2336           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2337         { PCI_DEVICE(0x1002, 0xaa50),
2338           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2339         { PCI_DEVICE(0x1002, 0xaa58),
2340           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2341         { PCI_DEVICE(0x1002, 0xaa60),
2342           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2343         { PCI_DEVICE(0x1002, 0xaa68),
2344           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2345         { PCI_DEVICE(0x1002, 0xaa80),
2346           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2347         { PCI_DEVICE(0x1002, 0xaa88),
2348           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2349         { PCI_DEVICE(0x1002, 0xaa90),
2350           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2351         { PCI_DEVICE(0x1002, 0xaa98),
2352           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2353         { PCI_DEVICE(0x1002, 0x9902),
2354           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2355         { PCI_DEVICE(0x1002, 0xaaa0),
2356           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2357         { PCI_DEVICE(0x1002, 0xaaa8),
2358           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2359         { PCI_DEVICE(0x1002, 0xaab0),
2360           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2361         { PCI_DEVICE(0x1002, 0xaac0),
2362           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2363         { PCI_DEVICE(0x1002, 0xaac8),
2364           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2365         { PCI_DEVICE(0x1002, 0xaad8),
2366           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2367         { PCI_DEVICE(0x1002, 0xaae8),
2368           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2369         /* VIA VT8251/VT8237A */
2370         { PCI_DEVICE(0x1106, 0x3288),
2371           .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
2372         /* VIA GFX VT7122/VX900 */
2373         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2374         /* VIA GFX VT6122/VX11 */
2375         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2376         /* SIS966 */
2377         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2378         /* ULI M5461 */
2379         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2380         /* NVIDIA MCP */
2381         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2382           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2383           .class_mask = 0xffffff,
2384           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2385         /* Teradici */
2386         { PCI_DEVICE(0x6549, 0x1200),
2387           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2388         { PCI_DEVICE(0x6549, 0x2200),
2389           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2390         /* Creative X-Fi (CA0110-IBG) */
2391         /* CTHDA chips */
2392         { PCI_DEVICE(0x1102, 0x0010),
2393           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2394         { PCI_DEVICE(0x1102, 0x0012),
2395           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2396 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2397         /* the following entry conflicts with snd-ctxfi driver,
2398          * as ctxfi driver mutates from HD-audio to native mode with
2399          * a special command sequence.
2400          */
2401         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2402           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2403           .class_mask = 0xffffff,
2404           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2405           AZX_DCAPS_NO_64BIT |
2406           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
2407 #else
2408         /* this entry seems still valid -- i.e. without emu20kx chip */
2409         { PCI_DEVICE(0x1102, 0x0009),
2410           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2411           AZX_DCAPS_NO_64BIT |
2412           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
2413 #endif
2414         /* CM8888 */
2415         { PCI_DEVICE(0x13f6, 0x5011),
2416           .driver_data = AZX_DRIVER_CMEDIA |
2417           AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2418         /* Vortex86MX */
2419         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2420         /* VMware HDAudio */
2421         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2422         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2423         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2424           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2425           .class_mask = 0xffffff,
2426           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2427         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2428           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2429           .class_mask = 0xffffff,
2430           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2431         { 0, }
2432 };
2433 MODULE_DEVICE_TABLE(pci, azx_ids);
2434
2435 /* pci_driver definition */
2436 static struct pci_driver azx_driver = {
2437         .name = KBUILD_MODNAME,
2438         .id_table = azx_ids,
2439         .probe = azx_probe,
2440         .remove = azx_remove,
2441         .shutdown = azx_shutdown,
2442         .driver = {
2443                 .pm = AZX_PM_OPS,
2444         },
2445 };
2446
2447 module_pci_driver(azx_driver);