sound/pci/hda/hda_controller.c

   1 /*
   2  *
   3  *  Implementation of primary alsa driver code base for Intel HD Audio.
   4  *
   5  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   6  *
   7  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   8  *                     PeiSen Hou <pshou@realtek.com.tw>
   9  *
  10  *  This program is free software; you can redistribute it and/or modify it
  11  *  under the terms of the GNU General Public License as published by the Free
  12  *  Software Foundation; either version 2 of the License, or (at your option)
  13  *  any later version.
  14  *
  15  *  This program is distributed in the hope that it will be useful, but WITHOUT
  16  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  18  *  more details.
  19  *
  20  *
  21  */
  22
  23 #include <linux/clocksource.h>
  24 #include <linux/delay.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/slab.h>
  30 #include <linux/reboot.h>
  31 #include <sound/core.h>
  32 #include <sound/initval.h>
  33 #include "hda_controller.h"
  34
  35 #define CREATE_TRACE_POINTS
  36 #include "hda_intel_trace.h"
  37
  38 /* DSP lock helpers */
  39 #ifdef CONFIG_SND_HDA_DSP_LOADER
  40 #define dsp_lock_init(dev)      mutex_init(&(dev)->dsp_mutex)
  41 #define dsp_lock(dev)           mutex_lock(&(dev)->dsp_mutex)
  42 #define dsp_unlock(dev)         mutex_unlock(&(dev)->dsp_mutex)
  43 #define dsp_is_locked(dev)      ((dev)->locked)
  44 #else
  45 #define dsp_lock_init(dev)      do {} while (0)
  46 #define dsp_lock(dev)           do {} while (0)
  47 #define dsp_unlock(dev)         do {} while (0)
  48 #define dsp_is_locked(dev)      0
  49 #endif
  50
  51 /*
  52  * AZX stream operations.
  53  */
  54
  55 /* start a stream */
  56 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
  57 {
  58         /*
  59          * Before stream start, initialize parameter
  60          */
  61         azx_dev->insufficient = 1;
  62
  63         /* enable SIE */
  64         azx_writel(chip, INTCTL,
  65                    azx_readl(chip, INTCTL) | (1 << azx_dev->index));
  66         /* set DMA start and interrupt mask */
  67         azx_sd_writeb(chip, azx_dev, SD_CTL,
  68                       azx_sd_readb(chip, azx_dev, SD_CTL) |
  69                       SD_CTL_DMA_START | SD_INT_MASK);
  70 }
  71
  72 /* stop DMA */
  73 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
  74 {
  75         azx_sd_writeb(chip, azx_dev, SD_CTL,
  76                       azx_sd_readb(chip, azx_dev, SD_CTL) &
  77                       ~(SD_CTL_DMA_START | SD_INT_MASK));
  78         azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
  79 }
  80
  81 /* stop a stream */
  82 void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
  83 {
  84         azx_stream_clear(chip, azx_dev);
  85         /* disable SIE */
  86         azx_writel(chip, INTCTL,
  87                    azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
  88 }
  89 EXPORT_SYMBOL_GPL(azx_stream_stop);
  90
  91 /* reset stream */
  92 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
  93 {
  94         unsigned char val;
  95         int timeout;
  96
  97         azx_stream_clear(chip, azx_dev);
  98
  99         azx_sd_writeb(chip, azx_dev, SD_CTL,
 100                       azx_sd_readb(chip, azx_dev, SD_CTL) |
 101                       SD_CTL_STREAM_RESET);
 102         udelay(3);
 103         timeout = 300;
 104         while (!((val = azx_sd_readb(chip, azx_dev, SD_CTL)) &
 105                  SD_CTL_STREAM_RESET) && --timeout)
 106                 ;
 107         val &= ~SD_CTL_STREAM_RESET;
 108         azx_sd_writeb(chip, azx_dev, SD_CTL, val);
 109         udelay(3);
 110
 111         timeout = 300;
 112         /* waiting for hardware to report that the stream is out of reset */
 113         while (((val = azx_sd_readb(chip, azx_dev, SD_CTL)) &
 114                 SD_CTL_STREAM_RESET) && --timeout)
 115                 ;
 116
 117         /* reset first position - may not be synced with hw at this time */
 118         *azx_dev->posbuf = 0;
 119 }
 120
 121 /*
 122  * set up the SD for streaming
 123  */
 124 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
 125 {
 126         unsigned int val;
 127         /* make sure the run bit is zero for SD */
 128         azx_stream_clear(chip, azx_dev);
 129         /* program the stream_tag */
 130         val = azx_sd_readl(chip, azx_dev, SD_CTL);
 131         val = (val & ~SD_CTL_STREAM_TAG_MASK) |
 132                 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
 133         if (!azx_snoop(chip))
 134                 val |= SD_CTL_TRAFFIC_PRIO;
 135         azx_sd_writel(chip, azx_dev, SD_CTL, val);
 136
 137         /* program the length of samples in cyclic buffer */
 138         azx_sd_writel(chip, azx_dev, SD_CBL, azx_dev->bufsize);
 139
 140         /* program the stream format */
 141         /* this value needs to be the same as the one programmed */
 142         azx_sd_writew(chip, azx_dev, SD_FORMAT, azx_dev->format_val);
 143
 144         /* program the stream LVI (last valid index) of the BDL */
 145         azx_sd_writew(chip, azx_dev, SD_LVI, azx_dev->frags - 1);
 146
 147         /* program the BDL address */
 148         /* lower BDL address */
 149         azx_sd_writel(chip, azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
 150         /* upper BDL address */
 151         azx_sd_writel(chip, azx_dev, SD_BDLPU,
 152                       upper_32_bits(azx_dev->bdl.addr));
 153
 154         /* enable the position buffer */
 155         if (chip->get_position[0] != azx_get_pos_lpib ||
 156             chip->get_position[1] != azx_get_pos_lpib) {
 157                 if (!(azx_readl(chip, DPLBASE) & AZX_DPLBASE_ENABLE))
 158                         azx_writel(chip, DPLBASE,
 159                                 (u32)chip->posbuf.addr | AZX_DPLBASE_ENABLE);
 160         }
 161
 162         /* set the interrupt enable bits in the descriptor control register */
 163         azx_sd_writel(chip, azx_dev, SD_CTL,
 164                       azx_sd_readl(chip, azx_dev, SD_CTL) | SD_INT_MASK);
 165
 166         return 0;
 167 }
 168
 169 /* assign a stream for the PCM */
 170 static inline struct azx_dev *
 171 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
 172 {
 173         int dev, i, nums;
 174         struct azx_dev *res = NULL;
 175         /* make a non-zero unique key for the substream */
 176         int key = (substream->pcm->device << 16) | (substream->number << 2) |
 177                 (substream->stream + 1);
 178
 179         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 180                 dev = chip->playback_index_offset;
 181                 nums = chip->playback_streams;
 182         } else {
 183                 dev = chip->capture_index_offset;
 184                 nums = chip->capture_streams;
 185         }
 186         for (i = 0; i < nums; i++, dev++) {
 187                 struct azx_dev *azx_dev = &chip->azx_dev[dev];
 188                 dsp_lock(azx_dev);
 189                 if (!azx_dev->opened && !dsp_is_locked(azx_dev)) {
 190                         if (azx_dev->assigned_key == key) {
 191                                 azx_dev->opened = 1;
 192                                 azx_dev->assigned_key = key;
 193                                 dsp_unlock(azx_dev);
 194                                 return azx_dev;
 195                         }
 196                         if (!res ||
 197                             (chip->driver_caps & AZX_DCAPS_REVERSE_ASSIGN))
 198                                 res = azx_dev;
 199                 }
 200                 dsp_unlock(azx_dev);
 201         }
 202         if (res) {
 203                 dsp_lock(res);
 204                 res->opened = 1;
 205                 res->assigned_key = key;
 206                 dsp_unlock(res);
 207         }
 208         return res;
 209 }
 210
 211 /* release the assigned stream */
 212 static inline void azx_release_device(struct azx_dev *azx_dev)
 213 {
 214         azx_dev->opened = 0;
 215 }
 216
 217 static cycle_t azx_cc_read(const struct cyclecounter *cc)
 218 {
 219         struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc);
 220         struct snd_pcm_substream *substream = azx_dev->substream;
 221         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 222         struct azx *chip = apcm->chip;
 223
 224         return azx_readl(chip, WALLCLK);
 225 }
 226
 227 static void azx_timecounter_init(struct snd_pcm_substream *substream,
 228                                 bool force, cycle_t last)
 229 {
 230         struct azx_dev *azx_dev = get_azx_dev(substream);
 231         struct timecounter *tc = &azx_dev->azx_tc;
 232         struct cyclecounter *cc = &azx_dev->azx_cc;
 233         u64 nsec;
 234
 235         cc->read = azx_cc_read;
 236         cc->mask = CLOCKSOURCE_MASK(32);
 237
 238         /*
 239          * Converting from 24 MHz to ns means applying a 125/3 factor.
 240          * To avoid any saturation issues in intermediate operations,
 241          * the 125 factor is applied first. The division is applied
 242          * last after reading the timecounter value.
 243          * Applying the 1/3 factor as part of the multiplication
 244          * requires at least 20 bits for a decent precision, however
 245          * overflows occur after about 4 hours or less, not a option.
 246          */
 247
 248         cc->mult = 125; /* saturation after 195 years */
 249         cc->shift = 0;
 250
 251         nsec = 0; /* audio time is elapsed time since trigger */
 252         timecounter_init(tc, cc, nsec);
 253         if (force)
 254                 /*
 255                  * force timecounter to use predefined value,
 256                  * used for synchronized starts
 257                  */
 258                 tc->cycle_last = last;
 259 }
 260
 261 static inline struct hda_pcm_stream *
 262 to_hda_pcm_stream(struct snd_pcm_substream *substream)
 263 {
 264         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 265         return &apcm->info->stream[substream->stream];
 266 }
 267
 268 static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream,
 269                                 u64 nsec)
 270 {
 271         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 272         struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
 273         u64 codec_frames, codec_nsecs;
 274
 275         if (!hinfo->ops.get_delay)
 276                 return nsec;
 277
 278         codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream);
 279         codec_nsecs = div_u64(codec_frames * 1000000000LL,
 280                               substream->runtime->rate);
 281
 282         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 283                 return nsec + codec_nsecs;
 284
 285         return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
 286 }
 287
 288 /*
 289  * set up a BDL entry
 290  */
 291 static int setup_bdle(struct azx *chip,
 292                       struct snd_dma_buffer *dmab,
 293                       struct azx_dev *azx_dev, u32 **bdlp,
 294                       int ofs, int size, int with_ioc)
 295 {
 296         u32 *bdl = *bdlp;
 297
 298         while (size > 0) {
 299                 dma_addr_t addr;
 300                 int chunk;
 301
 302                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
 303                         return -EINVAL;
 304
 305                 addr = snd_sgbuf_get_addr(dmab, ofs);
 306                 /* program the address field of the BDL entry */
 307                 bdl[0] = cpu_to_le32((u32)addr);
 308                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
 309                 /* program the size field of the BDL entry */
 310                 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
 311                 /* one BDLE cannot cross 4K boundary on CTHDA chips */
 312                 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
 313                         u32 remain = 0x1000 - (ofs & 0xfff);
 314                         if (chunk > remain)
 315                                 chunk = remain;
 316                 }
 317                 bdl[2] = cpu_to_le32(chunk);
 318                 /* program the IOC to enable interrupt
 319                  * only when the whole fragment is processed
 320                  */
 321                 size -= chunk;
 322                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
 323                 bdl += 4;
 324                 azx_dev->frags++;
 325                 ofs += chunk;
 326         }
 327         *bdlp = bdl;
 328         return ofs;
 329 }
 330
 331 /*
 332  * set up BDL entries
 333  */
 334 static int azx_setup_periods(struct azx *chip,
 335                              struct snd_pcm_substream *substream,
 336                              struct azx_dev *azx_dev)
 337 {
 338         u32 *bdl;
 339         int i, ofs, periods, period_bytes;
 340         int pos_adj = 0;
 341
 342         /* reset BDL address */
 343         azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
 344         azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
 345
 346         period_bytes = azx_dev->period_bytes;
 347         periods = azx_dev->bufsize / period_bytes;
 348
 349         /* program the initial BDL entries */
 350         bdl = (u32 *)azx_dev->bdl.area;
 351         ofs = 0;
 352         azx_dev->frags = 0;
 353
 354         if (chip->bdl_pos_adj)
 355                 pos_adj = chip->bdl_pos_adj[chip->dev_index];
 356         if (!azx_dev->no_period_wakeup && pos_adj > 0) {
 357                 struct snd_pcm_runtime *runtime = substream->runtime;
 358                 int pos_align = pos_adj;
 359                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
 360                 if (!pos_adj)
 361                         pos_adj = pos_align;
 362                 else
 363                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
 364                                 pos_align;
 365                 pos_adj = frames_to_bytes(runtime, pos_adj);
 366                 if (pos_adj >= period_bytes) {
 367                         dev_warn(chip->card->dev,"Too big adjustment %d\n",
 368                                  pos_adj);
 369                         pos_adj = 0;
 370                 } else {
 371                         ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
 372                                          azx_dev,
 373                                          &bdl, ofs, pos_adj, true);
 374                         if (ofs < 0)
 375                                 goto error;
 376                 }
 377         } else
 378                 pos_adj = 0;
 379
 380         for (i = 0; i < periods; i++) {
 381                 if (i == periods - 1 && pos_adj)
 382                         ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
 383                                          azx_dev, &bdl, ofs,
 384                                          period_bytes - pos_adj, 0);
 385                 else
 386                         ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
 387                                          azx_dev, &bdl, ofs,
 388                                          period_bytes,
 389                                          !azx_dev->no_period_wakeup);
 390                 if (ofs < 0)
 391                         goto error;
 392         }
 393         return 0;
 394
 395  error:
 396         dev_err(chip->card->dev, "Too many BDL entries: buffer=%d, period=%d\n",
 397                 azx_dev->bufsize, period_bytes);
 398         return -EINVAL;
 399 }
 400
 401 /*
 402  * PCM ops
 403  */
 404
 405 static int azx_pcm_close(struct snd_pcm_substream *substream)
 406 {
 407         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 408         struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
 409         struct azx *chip = apcm->chip;
 410         struct azx_dev *azx_dev = get_azx_dev(substream);
 411         unsigned long flags;
 412
 413         mutex_lock(&chip->open_mutex);
 414         spin_lock_irqsave(&chip->reg_lock, flags);
 415         azx_dev->substream = NULL;
 416         azx_dev->running = 0;
 417         spin_unlock_irqrestore(&chip->reg_lock, flags);
 418         azx_release_device(azx_dev);
 419         hinfo->ops.close(hinfo, apcm->codec, substream);
 420         snd_hda_power_down(apcm->codec);
 421         mutex_unlock(&chip->open_mutex);
 422         return 0;
 423 }
 424
 425 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
 426                              struct snd_pcm_hw_params *hw_params)
 427 {
 428         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 429         struct azx *chip = apcm->chip;
 430         int ret;
 431
 432         dsp_lock(get_azx_dev(substream));
 433         if (dsp_is_locked(get_azx_dev(substream))) {
 434                 ret = -EBUSY;
 435                 goto unlock;
 436         }
 437
 438         ret = chip->ops->substream_alloc_pages(chip, substream,
 439                                           params_buffer_bytes(hw_params));
 440 unlock:
 441         dsp_unlock(get_azx_dev(substream));
 442         return ret;
 443 }
 444
 445 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
 446 {
 447         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 448         struct azx_dev *azx_dev = get_azx_dev(substream);
 449         struct azx *chip = apcm->chip;
 450         struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
 451         int err;
 452
 453         /* reset BDL address */
 454         dsp_lock(azx_dev);
 455         if (!dsp_is_locked(azx_dev)) {
 456                 azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
 457                 azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
 458                 azx_sd_writel(chip, azx_dev, SD_CTL, 0);
 459                 azx_dev->bufsize = 0;
 460                 azx_dev->period_bytes = 0;
 461                 azx_dev->format_val = 0;
 462         }
 463
 464         snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
 465
 466         err = chip->ops->substream_free_pages(chip, substream);
 467         azx_dev->prepared = 0;
 468         dsp_unlock(azx_dev);
 469         return err;
 470 }
 471
 472 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
 473 {
 474         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 475         struct azx *chip = apcm->chip;
 476         struct azx_dev *azx_dev = get_azx_dev(substream);
 477         struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
 478         struct snd_pcm_runtime *runtime = substream->runtime;
 479         unsigned int bufsize, period_bytes, format_val, stream_tag;
 480         int err;
 481         struct hda_spdif_out *spdif =
 482                 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
 483         unsigned short ctls = spdif ? spdif->ctls : 0;
 484
 485         dsp_lock(azx_dev);
 486         if (dsp_is_locked(azx_dev)) {
 487                 err = -EBUSY;
 488                 goto unlock;
 489         }
 490
 491         azx_stream_reset(chip, azx_dev);
 492         format_val = snd_hda_calc_stream_format(apcm->codec,
 493                                                 runtime->rate,
 494                                                 runtime->channels,
 495                                                 runtime->format,
 496                                                 hinfo->maxbps,
 497                                                 ctls);
 498         if (!format_val) {
 499                 dev_err(chip->card->dev,
 500                         "invalid format_val, rate=%d, ch=%d, format=%d\n",
 501                         runtime->rate, runtime->channels, runtime->format);
 502                 err = -EINVAL;
 503                 goto unlock;
 504         }
 505
 506         bufsize = snd_pcm_lib_buffer_bytes(substream);
 507         period_bytes = snd_pcm_lib_period_bytes(substream);
 508
 509         dev_dbg(chip->card->dev, "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
 510                 bufsize, format_val);
 511
 512         if (bufsize != azx_dev->bufsize ||
 513             period_bytes != azx_dev->period_bytes ||
 514             format_val != azx_dev->format_val ||
 515             runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
 516                 azx_dev->bufsize = bufsize;
 517                 azx_dev->period_bytes = period_bytes;
 518                 azx_dev->format_val = format_val;
 519                 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
 520                 err = azx_setup_periods(chip, substream, azx_dev);
 521                 if (err < 0)
 522                         goto unlock;
 523         }
 524
 525         /* when LPIB delay correction gives a small negative value,
 526          * we ignore it; currently set the threshold statically to
 527          * 64 frames
 528          */
 529         if (runtime->period_size > 64)
 530                 azx_dev->delay_negative_threshold = -frames_to_bytes(runtime, 64);
 531         else
 532                 azx_dev->delay_negative_threshold = 0;
 533
 534         /* wallclk has 24Mhz clock source */
 535         azx_dev->period_wallclk = (((runtime->period_size * 24000) /
 536                                                 runtime->rate) * 1000);
 537         azx_setup_controller(chip, azx_dev);
 538         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 539                 azx_dev->fifo_size =
 540                         azx_sd_readw(chip, azx_dev, SD_FIFOSIZE) + 1;
 541         else
 542                 azx_dev->fifo_size = 0;
 543
 544         stream_tag = azx_dev->stream_tag;
 545         /* CA-IBG chips need the playback stream starting from 1 */
 546         if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
 547             stream_tag > chip->capture_streams)
 548                 stream_tag -= chip->capture_streams;
 549         err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
 550                                      azx_dev->format_val, substream);
 551
 552  unlock:
 553         if (!err)
 554                 azx_dev->prepared = 1;
 555         dsp_unlock(azx_dev);
 556         return err;
 557 }
 558
 559 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
 560 {
 561         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 562         struct azx *chip = apcm->chip;
 563         struct azx_dev *azx_dev;
 564         struct snd_pcm_substream *s;
 565         int rstart = 0, start, nsync = 0, sbits = 0;
 566         int nwait, timeout;
 567
 568         azx_dev = get_azx_dev(substream);
 569         trace_azx_pcm_trigger(chip, azx_dev, cmd);
 570
 571         if (dsp_is_locked(azx_dev) || !azx_dev->prepared)
 572                 return -EPIPE;
 573
 574         switch (cmd) {
 575         case SNDRV_PCM_TRIGGER_START:
 576                 rstart = 1;
 577         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 578         case SNDRV_PCM_TRIGGER_RESUME:
 579                 start = 1;
 580                 break;
 581         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 582         case SNDRV_PCM_TRIGGER_SUSPEND:
 583         case SNDRV_PCM_TRIGGER_STOP:
 584                 start = 0;
 585                 break;
 586         default:
 587                 return -EINVAL;
 588         }
 589
 590         snd_pcm_group_for_each_entry(s, substream) {
 591                 if (s->pcm->card != substream->pcm->card)
 592                         continue;
 593                 azx_dev = get_azx_dev(s);
 594                 sbits |= 1 << azx_dev->index;
 595                 nsync++;
 596                 snd_pcm_trigger_done(s, substream);
 597         }
 598
 599         spin_lock(&chip->reg_lock);
 600
 601         /* first, set SYNC bits of corresponding streams */
 602         if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
 603                 azx_writel(chip, OLD_SSYNC,
 604                         azx_readl(chip, OLD_SSYNC) | sbits);
 605         else
 606                 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
 607
 608         snd_pcm_group_for_each_entry(s, substream) {
 609                 if (s->pcm->card != substream->pcm->card)
 610                         continue;
 611                 azx_dev = get_azx_dev(s);
 612                 if (start) {
 613                         azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
 614                         if (!rstart)
 615                                 azx_dev->start_wallclk -=
 616                                                 azx_dev->period_wallclk;
 617                         azx_stream_start(chip, azx_dev);
 618                 } else {
 619                         azx_stream_stop(chip, azx_dev);
 620                 }
 621                 azx_dev->running = start;
 622         }
 623         spin_unlock(&chip->reg_lock);
 624         if (start) {
 625                 /* wait until all FIFOs get ready */
 626                 for (timeout = 5000; timeout; timeout--) {
 627                         nwait = 0;
 628                         snd_pcm_group_for_each_entry(s, substream) {
 629                                 if (s->pcm->card != substream->pcm->card)
 630                                         continue;
 631                                 azx_dev = get_azx_dev(s);
 632                                 if (!(azx_sd_readb(chip, azx_dev, SD_STS) &
 633                                       SD_STS_FIFO_READY))
 634                                         nwait++;
 635                         }
 636                         if (!nwait)
 637                                 break;
 638                         cpu_relax();
 639                 }
 640         } else {
 641                 /* wait until all RUN bits are cleared */
 642                 for (timeout = 5000; timeout; timeout--) {
 643                         nwait = 0;
 644                         snd_pcm_group_for_each_entry(s, substream) {
 645                                 if (s->pcm->card != substream->pcm->card)
 646                                         continue;
 647                                 azx_dev = get_azx_dev(s);
 648                                 if (azx_sd_readb(chip, azx_dev, SD_CTL) &
 649                                     SD_CTL_DMA_START)
 650                                         nwait++;
 651                         }
 652                         if (!nwait)
 653                                 break;
 654                         cpu_relax();
 655                 }
 656         }
 657         spin_lock(&chip->reg_lock);
 658         /* reset SYNC bits */
 659         if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
 660                 azx_writel(chip, OLD_SSYNC,
 661                         azx_readl(chip, OLD_SSYNC) & ~sbits);
 662         else
 663                 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
 664         if (start) {
 665                 azx_timecounter_init(substream, 0, 0);
 666                 snd_pcm_gettime(substream->runtime, &substream->runtime->trigger_tstamp);
 667                 substream->runtime->trigger_tstamp_latched = true;
 668
 669                 if (nsync > 1) {
 670                         cycle_t cycle_last;
 671
 672                         /* same start cycle for master and group */
 673                         azx_dev = get_azx_dev(substream);
 674                         cycle_last = azx_dev->azx_tc.cycle_last;
 675
 676                         snd_pcm_group_for_each_entry(s, substream) {
 677                                 if (s->pcm->card != substream->pcm->card)
 678                                         continue;
 679                                 azx_timecounter_init(s, 1, cycle_last);
 680                         }
 681                 }
 682         }
 683         spin_unlock(&chip->reg_lock);
 684         return 0;
 685 }
 686
 687 unsigned int azx_get_pos_lpib(struct azx *chip, struct azx_dev *azx_dev)
 688 {
 689         return azx_sd_readl(chip, azx_dev, SD_LPIB);
 690 }
 691 EXPORT_SYMBOL_GPL(azx_get_pos_lpib);
 692
 693 unsigned int azx_get_pos_posbuf(struct azx *chip, struct azx_dev *azx_dev)
 694 {
 695         return le32_to_cpu(*azx_dev->posbuf);
 696 }
 697 EXPORT_SYMBOL_GPL(azx_get_pos_posbuf);
 698
 699 unsigned int azx_get_position(struct azx *chip,
 700                               struct azx_dev *azx_dev)
 701 {
 702         struct snd_pcm_substream *substream = azx_dev->substream;
 703         unsigned int pos;
 704         int stream = substream->stream;
 705         int delay = 0;
 706
 707         if (chip->get_position[stream])
 708                 pos = chip->get_position[stream](chip, azx_dev);
 709         else /* use the position buffer as default */
 710                 pos = azx_get_pos_posbuf(chip, azx_dev);
 711
 712         if (pos >= azx_dev->bufsize)
 713                 pos = 0;
 714
 715         if (substream->runtime) {
 716                 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 717                 struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
 718
 719                 if (chip->get_delay[stream])
 720                         delay += chip->get_delay[stream](chip, azx_dev, pos);
 721                 if (hinfo->ops.get_delay)
 722                         delay += hinfo->ops.get_delay(hinfo, apcm->codec,
 723                                                       substream);
 724                 substream->runtime->delay = delay;
 725         }
 726
 727         trace_azx_get_position(chip, azx_dev, pos, delay);
 728         return pos;
 729 }
 730 EXPORT_SYMBOL_GPL(azx_get_position);
 731
 732 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
 733 {
 734         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 735         struct azx *chip = apcm->chip;
 736         struct azx_dev *azx_dev = get_azx_dev(substream);
 737         return bytes_to_frames(substream->runtime,
 738                                azx_get_position(chip, azx_dev));
 739 }
 740
 741 static int azx_get_time_info(struct snd_pcm_substream *substream,
 742                         struct timespec *system_ts, struct timespec *audio_ts,
 743                         struct snd_pcm_audio_tstamp_config *audio_tstamp_config,
 744                         struct snd_pcm_audio_tstamp_report *audio_tstamp_report)
 745 {
 746         struct azx_dev *azx_dev = get_azx_dev(substream);
 747         u64 nsec;
 748
 749         if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) &&
 750                 (audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) {
 751
 752                 snd_pcm_gettime(substream->runtime, system_ts);
 753
 754                 nsec = timecounter_read(&azx_dev->azx_tc);
 755                 nsec = div_u64(nsec, 3); /* can be optimized */
 756                 if (audio_tstamp_config->report_delay)
 757                         nsec = azx_adjust_codec_delay(substream, nsec);
 758
 759                 *audio_ts = ns_to_timespec(nsec);
 760
 761                 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK;
 762                 audio_tstamp_report->accuracy_report = 1; /* rest of structure is valid */
 763                 audio_tstamp_report->accuracy = 42; /* 24 MHz WallClock == 42ns resolution */
 764
 765         } else
 766                 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT;
 767
 768         return 0;
 769 }
 770
 771 static struct snd_pcm_hardware azx_pcm_hw = {
 772         .info =                 (SNDRV_PCM_INFO_MMAP |
 773                                  SNDRV_PCM_INFO_INTERLEAVED |
 774                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
 775                                  SNDRV_PCM_INFO_MMAP_VALID |
 776                                  /* No full-resume yet implemented */
 777                                  /* SNDRV_PCM_INFO_RESUME |*/
 778                                  SNDRV_PCM_INFO_PAUSE |
 779                                  SNDRV_PCM_INFO_SYNC_START |
 780                                  SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */
 781                                  SNDRV_PCM_INFO_HAS_LINK_ATIME |
 782                                  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
 783         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
 784         .rates =                SNDRV_PCM_RATE_48000,
 785         .rate_min =             48000,
 786         .rate_max =             48000,
 787         .channels_min =         2,
 788         .channels_max =         2,
 789         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
 790         .period_bytes_min =     128,
 791         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
 792         .periods_min =          2,
 793         .periods_max =          AZX_MAX_FRAG,
 794         .fifo_size =            0,
 795 };
 796
 797 static int azx_pcm_open(struct snd_pcm_substream *substream)
 798 {
 799         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 800         struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
 801         struct azx *chip = apcm->chip;
 802         struct azx_dev *azx_dev;
 803         struct snd_pcm_runtime *runtime = substream->runtime;
 804         unsigned long flags;
 805         int err;
 806         int buff_step;
 807
 808         mutex_lock(&chip->open_mutex);
 809         azx_dev = azx_assign_device(chip, substream);
 810         if (azx_dev == NULL) {
 811                 mutex_unlock(&chip->open_mutex);
 812                 return -EBUSY;
 813         }
 814         runtime->hw = azx_pcm_hw;
 815         runtime->hw.channels_min = hinfo->channels_min;
 816         runtime->hw.channels_max = hinfo->channels_max;
 817         runtime->hw.formats = hinfo->formats;
 818         runtime->hw.rates = hinfo->rates;
 819         snd_pcm_limit_hw_rates(runtime);
 820         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
 821
 822         /* avoid wrap-around with wall-clock */
 823         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
 824                                      20,
 825                                      178000000);
 826
 827         if (chip->align_buffer_size)
 828                 /* constrain buffer sizes to be multiple of 128
 829                    bytes. This is more efficient in terms of memory
 830                    access but isn't required by the HDA spec and
 831                    prevents users from specifying exact period/buffer
 832                    sizes. For example for 44.1kHz, a period size set
 833                    to 20ms will be rounded to 19.59ms. */
 834                 buff_step = 128;
 835         else
 836                 /* Don't enforce steps on buffer sizes, still need to
 837                    be multiple of 4 bytes (HDA spec). Tested on Intel
 838                    HDA controllers, may not work on all devices where
 839                    option needs to be disabled */
 840                 buff_step = 4;
 841
 842         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
 843                                    buff_step);
 844         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
 845                                    buff_step);
 846         snd_hda_power_up(apcm->codec);
 847         err = hinfo->ops.open(hinfo, apcm->codec, substream);
 848         if (err < 0) {
 849                 azx_release_device(azx_dev);
 850                 snd_hda_power_down(apcm->codec);
 851                 mutex_unlock(&chip->open_mutex);
 852                 return err;
 853         }
 854         snd_pcm_limit_hw_rates(runtime);
 855         /* sanity check */
 856         if (snd_BUG_ON(!runtime->hw.channels_min) ||
 857             snd_BUG_ON(!runtime->hw.channels_max) ||
 858             snd_BUG_ON(!runtime->hw.formats) ||
 859             snd_BUG_ON(!runtime->hw.rates)) {
 860                 azx_release_device(azx_dev);
 861                 hinfo->ops.close(hinfo, apcm->codec, substream);
 862                 snd_hda_power_down(apcm->codec);
 863                 mutex_unlock(&chip->open_mutex);
 864                 return -EINVAL;
 865         }
 866
 867         /* disable LINK_ATIME timestamps for capture streams
 868            until we figure out how to handle digital inputs */
 869         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
 870                 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */
 871                 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME;
 872         }
 873
 874         spin_lock_irqsave(&chip->reg_lock, flags);
 875         azx_dev->substream = substream;
 876         azx_dev->running = 0;
 877         spin_unlock_irqrestore(&chip->reg_lock, flags);
 878
 879         runtime->private_data = azx_dev;
 880         snd_pcm_set_sync(substream);
 881         mutex_unlock(&chip->open_mutex);
 882         return 0;
 883 }
 884
 885 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
 886                         struct vm_area_struct *area)
 887 {
 888         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 889         struct azx *chip = apcm->chip;
 890         if (chip->ops->pcm_mmap_prepare)
 891                 chip->ops->pcm_mmap_prepare(substream, area);
 892         return snd_pcm_lib_default_mmap(substream, area);
 893 }
 894
 895 static struct snd_pcm_ops azx_pcm_ops = {
 896         .open = azx_pcm_open,
 897         .close = azx_pcm_close,
 898         .ioctl = snd_pcm_lib_ioctl,
 899         .hw_params = azx_pcm_hw_params,
 900         .hw_free = azx_pcm_hw_free,
 901         .prepare = azx_pcm_prepare,
 902         .trigger = azx_pcm_trigger,
 903         .pointer = azx_pcm_pointer,
 904         .get_time_info =  azx_get_time_info,
 905         .mmap = azx_pcm_mmap,
 906         .page = snd_pcm_sgbuf_ops_page,
 907 };
 908
 909 static void azx_pcm_free(struct snd_pcm *pcm)
 910 {
 911         struct azx_pcm *apcm = pcm->private_data;
 912         if (apcm) {
 913                 list_del(&apcm->list);
 914                 apcm->info->pcm = NULL;
 915                 kfree(apcm);
 916         }
 917 }
 918
 919 #define MAX_PREALLOC_SIZE       (32 * 1024 * 1024)
 920
 921 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
 922                                  struct hda_pcm *cpcm)
 923 {
 924         struct azx *chip = bus->private_data;
 925         struct snd_pcm *pcm;
 926         struct azx_pcm *apcm;
 927         int pcm_dev = cpcm->device;
 928         unsigned int size;
 929         int s, err;
 930
 931         list_for_each_entry(apcm, &chip->pcm_list, list) {
 932                 if (apcm->pcm->device == pcm_dev) {
 933                         dev_err(chip->card->dev, "PCM %d already exists\n",
 934                                 pcm_dev);
 935                         return -EBUSY;
 936                 }
 937         }
 938         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
 939                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
 940                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
 941                           &pcm);
 942         if (err < 0)
 943                 return err;
 944         strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
 945         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
 946         if (apcm == NULL)
 947                 return -ENOMEM;
 948         apcm->chip = chip;
 949         apcm->pcm = pcm;
 950         apcm->codec = codec;
 951         apcm->info = cpcm;
 952         pcm->private_data = apcm;
 953         pcm->private_free = azx_pcm_free;
 954         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
 955                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
 956         list_add_tail(&apcm->list, &chip->pcm_list);
 957         cpcm->pcm = pcm;
 958         for (s = 0; s < 2; s++) {
 959                 if (cpcm->stream[s].substreams)
 960                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
 961         }
 962         /* buffer pre-allocation */
 963         size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
 964         if (size > MAX_PREALLOC_SIZE)
 965                 size = MAX_PREALLOC_SIZE;
 966         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
 967                                               chip->card->dev,
 968                                               size, MAX_PREALLOC_SIZE);
 969         return 0;
 970 }
 971
 972 /*
 973  * CORB / RIRB interface
 974  */
 975 static int azx_alloc_cmd_io(struct azx *chip)
 976 {
 977         int err;
 978
 979         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
 980         err = chip->ops->dma_alloc_pages(chip, SNDRV_DMA_TYPE_DEV,
 981                                          PAGE_SIZE, &chip->rb);
 982         if (err < 0)
 983                 dev_err(chip->card->dev, "cannot allocate CORB/RIRB\n");
 984         return err;
 985 }
 986
 987 static void azx_init_cmd_io(struct azx *chip)
 988 {
 989         int timeout;
 990
 991         spin_lock_irq(&chip->reg_lock);
 992         /* CORB set up */
 993         chip->corb.addr = chip->rb.addr;
 994         chip->corb.buf = (u32 *)chip->rb.area;
 995         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
 996         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
 997
 998         /* set the corb size to 256 entries (ULI requires explicitly) */
 999         azx_writeb(chip, CORBSIZE, 0x02);
1000         /* set the corb write pointer to 0 */
1001         azx_writew(chip, CORBWP, 0);
1002
1003         /* reset the corb hw read pointer */
1004         azx_writew(chip, CORBRP, AZX_CORBRP_RST);
1005         if (!(chip->driver_caps & AZX_DCAPS_CORBRP_SELF_CLEAR)) {
1006                 for (timeout = 1000; timeout > 0; timeout--) {
1007                         if ((azx_readw(chip, CORBRP) & AZX_CORBRP_RST) == AZX_CORBRP_RST)
1008                                 break;
1009                         udelay(1);
1010                 }
1011                 if (timeout <= 0)
1012                         dev_err(chip->card->dev, "CORB reset timeout#1, CORBRP = %d\n",
1013                                 azx_readw(chip, CORBRP));
1014
1015                 azx_writew(chip, CORBRP, 0);
1016                 for (timeout = 1000; timeout > 0; timeout--) {
1017                         if (azx_readw(chip, CORBRP) == 0)
1018                                 break;
1019                         udelay(1);
1020                 }
1021                 if (timeout <= 0)
1022                         dev_err(chip->card->dev, "CORB reset timeout#2, CORBRP = %d\n",
1023                                 azx_readw(chip, CORBRP));
1024         }
1025
1026         /* enable corb dma */
1027         azx_writeb(chip, CORBCTL, AZX_CORBCTL_RUN);
1028
1029         /* RIRB set up */
1030         chip->rirb.addr = chip->rb.addr + 2048;
1031         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
1032         chip->rirb.wp = chip->rirb.rp = 0;
1033         memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
1034         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
1035         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
1036
1037         /* set the rirb size to 256 entries (ULI requires explicitly) */
1038         azx_writeb(chip, RIRBSIZE, 0x02);
1039         /* reset the rirb hw write pointer */
1040         azx_writew(chip, RIRBWP, AZX_RIRBWP_RST);
1041         /* set N=1, get RIRB response interrupt for new entry */
1042         if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
1043                 azx_writew(chip, RINTCNT, 0xc0);
1044         else
1045                 azx_writew(chip, RINTCNT, 1);
1046         /* enable rirb dma and response irq */
1047         azx_writeb(chip, RIRBCTL, AZX_RBCTL_DMA_EN | AZX_RBCTL_IRQ_EN);
1048         spin_unlock_irq(&chip->reg_lock);
1049 }
1050
1051 static void azx_free_cmd_io(struct azx *chip)
1052 {
1053         spin_lock_irq(&chip->reg_lock);
1054         /* disable ringbuffer DMAs */
1055         azx_writeb(chip, RIRBCTL, 0);
1056         azx_writeb(chip, CORBCTL, 0);
1057         spin_unlock_irq(&chip->reg_lock);
1058 }
1059
1060 static unsigned int azx_command_addr(u32 cmd)
1061 {
1062         unsigned int addr = cmd >> 28;
1063
1064         if (addr >= AZX_MAX_CODECS) {
1065                 snd_BUG();
1066                 addr = 0;
1067         }
1068
1069         return addr;
1070 }
1071
1072 /* send a command */
1073 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
1074 {
1075         struct azx *chip = bus->private_data;
1076         unsigned int addr = azx_command_addr(val);
1077         unsigned int wp, rp;
1078
1079         spin_lock_irq(&chip->reg_lock);
1080
1081         /* add command to corb */
1082         wp = azx_readw(chip, CORBWP);
1083         if (wp == 0xffff) {
1084                 /* something wrong, controller likely turned to D3 */
1085                 spin_unlock_irq(&chip->reg_lock);
1086                 return -EIO;
1087         }
1088         wp++;
1089         wp %= AZX_MAX_CORB_ENTRIES;
1090
1091         rp = azx_readw(chip, CORBRP);
1092         if (wp == rp) {
1093                 /* oops, it's full */
1094                 spin_unlock_irq(&chip->reg_lock);
1095                 return -EAGAIN;
1096         }
1097
1098         chip->rirb.cmds[addr]++;
1099         chip->corb.buf[wp] = cpu_to_le32(val);
1100         azx_writew(chip, CORBWP, wp);
1101
1102         spin_unlock_irq(&chip->reg_lock);
1103
1104         return 0;
1105 }
1106
1107 #define AZX_RIRB_EX_UNSOL_EV    (1<<4)
1108
1109 /* retrieve RIRB entry - called from interrupt handler */
1110 static void azx_update_rirb(struct azx *chip)
1111 {
1112         unsigned int rp, wp;
1113         unsigned int addr;
1114         u32 res, res_ex;
1115
1116         wp = azx_readw(chip, RIRBWP);
1117         if (wp == 0xffff) {
1118                 /* something wrong, controller likely turned to D3 */
1119                 return;
1120         }
1121
1122         if (wp == chip->rirb.wp)
1123                 return;
1124         chip->rirb.wp = wp;
1125
1126         while (chip->rirb.rp != wp) {
1127                 chip->rirb.rp++;
1128                 chip->rirb.rp %= AZX_MAX_RIRB_ENTRIES;
1129
1130                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
1131                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
1132                 res = le32_to_cpu(chip->rirb.buf[rp]);
1133                 addr = res_ex & 0xf;
1134                 if ((addr >= AZX_MAX_CODECS) || !(chip->codec_mask & (1 << addr))) {
1135                         dev_err(chip->card->dev, "spurious response %#x:%#x, rp = %d, wp = %d",
1136                                 res, res_ex,
1137                                 chip->rirb.rp, wp);
1138                         snd_BUG();
1139                 } else if (res_ex & AZX_RIRB_EX_UNSOL_EV)
1140                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
1141                 else if (chip->rirb.cmds[addr]) {
1142                         chip->rirb.res[addr] = res;
1143                         smp_wmb();
1144                         chip->rirb.cmds[addr]--;
1145                 } else if (printk_ratelimit()) {
1146                         dev_err(chip->card->dev, "spurious response %#x:%#x, last cmd=%#08x\n",
1147                                 res, res_ex,
1148                                 chip->last_cmd[addr]);
1149                 }
1150         }
1151 }
1152
1153 /* receive a response */
1154 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
1155                                           unsigned int addr)
1156 {
1157         struct azx *chip = bus->private_data;
1158         unsigned long timeout;
1159         unsigned long loopcounter;
1160         int do_poll = 0;
1161
1162  again:
1163         timeout = jiffies + msecs_to_jiffies(1000);
1164
1165         for (loopcounter = 0;; loopcounter++) {
1166                 if (chip->polling_mode || do_poll) {
1167                         spin_lock_irq(&chip->reg_lock);
1168                         azx_update_rirb(chip);
1169                         spin_unlock_irq(&chip->reg_lock);
1170                 }
1171                 if (!chip->rirb.cmds[addr]) {
1172                         smp_rmb();
1173                         bus->rirb_error = 0;
1174
1175                         if (!do_poll)
1176                                 chip->poll_count = 0;
1177                         return chip->rirb.res[addr]; /* the last value */
1178                 }
1179                 if (time_after(jiffies, timeout))
1180                         break;
1181                 if (bus->needs_damn_long_delay || loopcounter > 3000)
1182                         msleep(2); /* temporary workaround */
1183                 else {
1184                         udelay(10);
1185                         cond_resched();
1186                 }
1187         }
1188
1189         if (bus->no_response_fallback)
1190                 return -1;
1191
1192         if (!chip->polling_mode && chip->poll_count < 2) {
1193                 dev_dbg(chip->card->dev,
1194                         "azx_get_response timeout, polling the codec once: last cmd=0x%08x\n",
1195                         chip->last_cmd[addr]);
1196                 do_poll = 1;
1197                 chip->poll_count++;
1198                 goto again;
1199         }
1200
1201
1202         if (!chip->polling_mode) {
1203                 dev_warn(chip->card->dev,
1204                          "azx_get_response timeout, switching to polling mode: last cmd=0x%08x\n",
1205                          chip->last_cmd[addr]);
1206                 chip->polling_mode = 1;
1207                 goto again;
1208         }
1209
1210         if (chip->msi) {
1211                 dev_warn(chip->card->dev,
1212                          "No response from codec, disabling MSI: last cmd=0x%08x\n",
1213                          chip->last_cmd[addr]);
1214                 if (chip->ops->disable_msi_reset_irq(chip) &&
1215                     chip->ops->disable_msi_reset_irq(chip) < 0) {
1216                         bus->rirb_error = 1;
1217                         return -1;
1218                 }
1219                 goto again;
1220         }
1221
1222         if (chip->probing) {
1223                 /* If this critical timeout happens during the codec probing
1224                  * phase, this is likely an access to a non-existing codec
1225                  * slot.  Better to return an error and reset the system.
1226                  */
1227                 return -1;
1228         }
1229
1230         /* a fatal communication error; need either to reset or to fallback
1231          * to the single_cmd mode
1232          */
1233         bus->rirb_error = 1;
1234         if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
1235                 bus->response_reset = 1;
1236                 return -1; /* give a chance to retry */
1237         }
1238
1239         dev_err(chip->card->dev,
1240                 "azx_get_response timeout, switching to single_cmd mode: last cmd=0x%08x\n",
1241                 chip->last_cmd[addr]);
1242         chip->single_cmd = 1;
1243         bus->response_reset = 0;
1244         /* release CORB/RIRB */
1245         azx_free_cmd_io(chip);
1246         /* disable unsolicited responses */
1247         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~AZX_GCTL_UNSOL);
1248         return -1;
1249 }
1250
1251 /*
1252  * Use the single immediate command instead of CORB/RIRB for simplicity
1253  *
1254  * Note: according to Intel, this is not preferred use.  The command was
1255  *       intended for the BIOS only, and may get confused with unsolicited
1256  *       responses.  So, we shouldn't use it for normal operation from the
1257  *       driver.
1258  *       I left the codes, however, for debugging/testing purposes.
1259  */
1260
1261 /* receive a response */
1262 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
1263 {
1264         int timeout = 50;
1265
1266         while (timeout--) {
1267                 /* check IRV busy bit */
1268                 if (azx_readw(chip, IRS) & AZX_IRS_VALID) {
1269                         /* reuse rirb.res as the response return value */
1270                         chip->rirb.res[addr] = azx_readl(chip, IR);
1271                         return 0;
1272                 }
1273                 udelay(1);
1274         }
1275         if (printk_ratelimit())
1276                 dev_dbg(chip->card->dev, "get_response timeout: IRS=0x%x\n",
1277                         azx_readw(chip, IRS));
1278         chip->rirb.res[addr] = -1;
1279         return -EIO;
1280 }
1281
1282 /* send a command */
1283 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
1284 {
1285         struct azx *chip = bus->private_data;
1286         unsigned int addr = azx_command_addr(val);
1287         int timeout = 50;
1288
1289         bus->rirb_error = 0;
1290         while (timeout--) {
1291                 /* check ICB busy bit */
1292                 if (!((azx_readw(chip, IRS) & AZX_IRS_BUSY))) {
1293                         /* Clear IRV valid bit */
1294                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
1295                                    AZX_IRS_VALID);
1296                         azx_writel(chip, IC, val);
1297                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
1298                                    AZX_IRS_BUSY);
1299                         return azx_single_wait_for_response(chip, addr);
1300                 }
1301                 udelay(1);
1302         }
1303         if (printk_ratelimit())
1304                 dev_dbg(chip->card->dev,
1305                         "send_cmd timeout: IRS=0x%x, val=0x%x\n",
1306                         azx_readw(chip, IRS), val);
1307         return -EIO;
1308 }
1309
1310 /* receive a response */
1311 static unsigned int azx_single_get_response(struct hda_bus *bus,
1312                                             unsigned int addr)
1313 {
1314         struct azx *chip = bus->private_data;
1315         return chip->rirb.res[addr];
1316 }
1317
1318 /*
1319  * The below are the main callbacks from hda_codec.
1320  *
1321  * They are just the skeleton to call sub-callbacks according to the
1322  * current setting of chip->single_cmd.
1323  */
1324
1325 /* send a command */
1326 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
1327 {
1328         struct azx *chip = bus->private_data;
1329
1330         if (chip->disabled)
1331                 return 0;
1332         chip->last_cmd[azx_command_addr(val)] = val;
1333         if (chip->single_cmd)
1334                 return azx_single_send_cmd(bus, val);
1335         else
1336                 return azx_corb_send_cmd(bus, val);
1337 }
1338
1339 /* get a response */
1340 static unsigned int azx_get_response(struct hda_bus *bus,
1341                                      unsigned int addr)
1342 {
1343         struct azx *chip = bus->private_data;
1344         if (chip->disabled)
1345                 return 0;
1346         if (chip->single_cmd)
1347                 return azx_single_get_response(bus, addr);
1348         else
1349                 return azx_rirb_get_response(bus, addr);
1350 }
1351
1352 #ifdef CONFIG_SND_HDA_DSP_LOADER
1353 /*
1354  * DSP loading code (e.g. for CA0132)
1355  */
1356
1357 /* use the first stream for loading DSP */
1358 static struct azx_dev *
1359 azx_get_dsp_loader_dev(struct azx *chip)
1360 {
1361         return &chip->azx_dev[chip->playback_index_offset];
1362 }
1363
1364 static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
1365                                 unsigned int byte_size,
1366                                 struct snd_dma_buffer *bufp)
1367 {
1368         u32 *bdl;
1369         struct azx *chip = bus->private_data;
1370         struct azx_dev *azx_dev;
1371         int err;
1372
1373         azx_dev = azx_get_dsp_loader_dev(chip);
1374
1375         dsp_lock(azx_dev);
1376         spin_lock_irq(&chip->reg_lock);
1377         if (azx_dev->running || azx_dev->locked) {
1378                 spin_unlock_irq(&chip->reg_lock);
1379                 err = -EBUSY;
1380                 goto unlock;
1381         }
1382         azx_dev->prepared = 0;
1383         chip->saved_azx_dev = *azx_dev;
1384         azx_dev->locked = 1;
1385         spin_unlock_irq(&chip->reg_lock);
1386
1387         err = chip->ops->dma_alloc_pages(chip, SNDRV_DMA_TYPE_DEV_SG,
1388                                          byte_size, bufp);
1389         if (err < 0)
1390                 goto err_alloc;
1391
1392         azx_dev->bufsize = byte_size;
1393         azx_dev->period_bytes = byte_size;
1394         azx_dev->format_val = format;
1395
1396         azx_stream_reset(chip, azx_dev);
1397
1398         /* reset BDL address */
1399         azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
1400         azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
1401
1402         azx_dev->frags = 0;
1403         bdl = (u32 *)azx_dev->bdl.area;
1404         err = setup_bdle(chip, bufp, azx_dev, &bdl, 0, byte_size, 0);
1405         if (err < 0)
1406                 goto error;
1407
1408         azx_setup_controller(chip, azx_dev);
1409         dsp_unlock(azx_dev);
1410         return azx_dev->stream_tag;
1411
1412  error:
1413         chip->ops->dma_free_pages(chip, bufp);
1414  err_alloc:
1415         spin_lock_irq(&chip->reg_lock);
1416         if (azx_dev->opened)
1417                 *azx_dev = chip->saved_azx_dev;
1418         azx_dev->locked = 0;
1419         spin_unlock_irq(&chip->reg_lock);
1420  unlock:
1421         dsp_unlock(azx_dev);
1422         return err;
1423 }
1424
1425 static void azx_load_dsp_trigger(struct hda_bus *bus, bool start)
1426 {
1427         struct azx *chip = bus->private_data;
1428         struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
1429
1430         if (start)
1431                 azx_stream_start(chip, azx_dev);
1432         else
1433                 azx_stream_stop(chip, azx_dev);
1434         azx_dev->running = start;
1435 }
1436
1437 static void azx_load_dsp_cleanup(struct hda_bus *bus,
1438                                  struct snd_dma_buffer *dmab)
1439 {
1440         struct azx *chip = bus->private_data;
1441         struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
1442
1443         if (!dmab->area || !azx_dev->locked)
1444                 return;
1445
1446         dsp_lock(azx_dev);
1447         /* reset BDL address */
1448         azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
1449         azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
1450         azx_sd_writel(chip, azx_dev, SD_CTL, 0);
1451         azx_dev->bufsize = 0;
1452         azx_dev->period_bytes = 0;
1453         azx_dev->format_val = 0;
1454
1455         chip->ops->dma_free_pages(chip, dmab);
1456         dmab->area = NULL;
1457
1458         spin_lock_irq(&chip->reg_lock);
1459         if (azx_dev->opened)
1460                 *azx_dev = chip->saved_azx_dev;
1461         azx_dev->locked = 0;
1462         spin_unlock_irq(&chip->reg_lock);
1463         dsp_unlock(azx_dev);
1464 }
1465 #endif /* CONFIG_SND_HDA_DSP_LOADER */
1466
1467 int azx_alloc_stream_pages(struct azx *chip)
1468 {
1469         int i, err;
1470         struct snd_card *card = chip->card;
1471
1472         for (i = 0; i < chip->num_streams; i++) {
1473                 dsp_lock_init(&chip->azx_dev[i]);
1474                 /* allocate memory for the BDL for each stream */
1475                 err = chip->ops->dma_alloc_pages(chip, SNDRV_DMA_TYPE_DEV,
1476                                                  BDL_SIZE,
1477                                                  &chip->azx_dev[i].bdl);
1478                 if (err < 0) {
1479                         dev_err(card->dev, "cannot allocate BDL\n");
1480                         return -ENOMEM;
1481                 }
1482         }
1483         /* allocate memory for the position buffer */
1484         err = chip->ops->dma_alloc_pages(chip, SNDRV_DMA_TYPE_DEV,
1485                                          chip->num_streams * 8, &chip->posbuf);
1486         if (err < 0) {
1487                 dev_err(card->dev, "cannot allocate posbuf\n");
1488                 return -ENOMEM;
1489         }
1490
1491         /* allocate CORB/RIRB */
1492         err = azx_alloc_cmd_io(chip);
1493         if (err < 0)
1494                 return err;
1495         return 0;
1496 }
1497 EXPORT_SYMBOL_GPL(azx_alloc_stream_pages);
1498
1499 void azx_free_stream_pages(struct azx *chip)
1500 {
1501         int i;
1502         if (chip->azx_dev) {
1503                 for (i = 0; i < chip->num_streams; i++)
1504                         if (chip->azx_dev[i].bdl.area)
1505                                 chip->ops->dma_free_pages(
1506                                         chip, &chip->azx_dev[i].bdl);
1507         }
1508         if (chip->rb.area)
1509                 chip->ops->dma_free_pages(chip, &chip->rb);
1510         if (chip->posbuf.area)
1511                 chip->ops->dma_free_pages(chip, &chip->posbuf);
1512 }
1513 EXPORT_SYMBOL_GPL(azx_free_stream_pages);
1514
1515 /*
1516  * Lowlevel interface
1517  */
1518
1519 /* enter link reset */
1520 void azx_enter_link_reset(struct azx *chip)
1521 {
1522         unsigned long timeout;
1523
1524         /* reset controller */
1525         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~AZX_GCTL_RESET);
1526
1527         timeout = jiffies + msecs_to_jiffies(100);
1528         while ((azx_readb(chip, GCTL) & AZX_GCTL_RESET) &&
1529                         time_before(jiffies, timeout))
1530                 usleep_range(500, 1000);
1531 }
1532 EXPORT_SYMBOL_GPL(azx_enter_link_reset);
1533
1534 /* exit link reset */
1535 static void azx_exit_link_reset(struct azx *chip)
1536 {
1537         unsigned long timeout;
1538
1539         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | AZX_GCTL_RESET);
1540
1541         timeout = jiffies + msecs_to_jiffies(100);
1542         while (!azx_readb(chip, GCTL) &&
1543                         time_before(jiffies, timeout))
1544                 usleep_range(500, 1000);
1545 }
1546
1547 /* reset codec link */
1548 static int azx_reset(struct azx *chip, bool full_reset)
1549 {
1550         if (!full_reset)
1551                 goto __skip;
1552
1553         /* clear STATESTS */
1554         azx_writew(chip, STATESTS, STATESTS_INT_MASK);
1555
1556         /* reset controller */
1557         azx_enter_link_reset(chip);
1558
1559         /* delay for >= 100us for codec PLL to settle per spec
1560          * Rev 0.9 section 5.5.1
1561          */
1562         usleep_range(500, 1000);
1563
1564         /* Bring controller out of reset */
1565         azx_exit_link_reset(chip);
1566
1567         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1568         usleep_range(1000, 1200);
1569
1570       __skip:
1571         /* check to see if controller is ready */
1572         if (!azx_readb(chip, GCTL)) {
1573                 dev_dbg(chip->card->dev, "azx_reset: controller not ready!\n");
1574                 return -EBUSY;
1575         }
1576
1577         /* Accept unsolicited responses */
1578         if (!chip->single_cmd)
1579                 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1580                            AZX_GCTL_UNSOL);
1581
1582         /* detect codecs */
1583         if (!chip->codec_mask) {
1584                 chip->codec_mask = azx_readw(chip, STATESTS);
1585                 dev_dbg(chip->card->dev, "codec_mask = 0x%x\n",
1586                         chip->codec_mask);
1587         }
1588
1589         return 0;
1590 }
1591
1592 /* enable interrupts */
1593 static void azx_int_enable(struct azx *chip)
1594 {
1595         /* enable controller CIE and GIE */
1596         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1597                    AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN);
1598 }
1599
1600 /* disable interrupts */
1601 static void azx_int_disable(struct azx *chip)
1602 {
1603         int i;
1604
1605         /* disable interrupts in stream descriptor */
1606         for (i = 0; i < chip->num_streams; i++) {
1607                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1608                 azx_sd_writeb(chip, azx_dev, SD_CTL,
1609                               azx_sd_readb(chip, azx_dev, SD_CTL) &
1610                                         ~SD_INT_MASK);
1611         }
1612
1613         /* disable SIE for all streams */
1614         azx_writeb(chip, INTCTL, 0);
1615
1616         /* disable controller CIE and GIE */
1617         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1618                    ~(AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN));
1619 }
1620
1621 /* clear interrupts */
1622 static void azx_int_clear(struct azx *chip)
1623 {
1624         int i;
1625
1626         /* clear stream status */
1627         for (i = 0; i < chip->num_streams; i++) {
1628                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1629                 azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK);
1630         }
1631
1632         /* clear STATESTS */
1633         azx_writew(chip, STATESTS, STATESTS_INT_MASK);
1634
1635         /* clear rirb status */
1636         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1637
1638         /* clear int status */
1639         azx_writel(chip, INTSTS, AZX_INT_CTRL_EN | AZX_INT_ALL_STREAM);
1640 }
1641
1642 /*
1643  * reset and start the controller registers
1644  */
1645 void azx_init_chip(struct azx *chip, bool full_reset)
1646 {
1647         if (chip->initialized)
1648                 return;
1649
1650         /* reset controller */
1651         azx_reset(chip, full_reset);
1652
1653         /* initialize interrupts */
1654         azx_int_clear(chip);
1655         azx_int_enable(chip);
1656
1657         /* initialize the codec command I/O */
1658         if (!chip->single_cmd)
1659                 azx_init_cmd_io(chip);
1660
1661         /* program the position buffer */
1662         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1663         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1664
1665         chip->initialized = 1;
1666 }
1667 EXPORT_SYMBOL_GPL(azx_init_chip);
1668
1669 void azx_stop_chip(struct azx *chip)
1670 {
1671         if (!chip->initialized)
1672                 return;
1673
1674         /* disable interrupts */
1675         azx_int_disable(chip);
1676         azx_int_clear(chip);
1677
1678         /* disable CORB/RIRB */
1679         azx_free_cmd_io(chip);
1680
1681         /* disable position buffer */
1682         azx_writel(chip, DPLBASE, 0);
1683         azx_writel(chip, DPUBASE, 0);
1684
1685         chip->initialized = 0;
1686 }
1687 EXPORT_SYMBOL_GPL(azx_stop_chip);
1688
1689 /*
1690  * interrupt handler
1691  */
1692 irqreturn_t azx_interrupt(int irq, void *dev_id)
1693 {
1694         struct azx *chip = dev_id;
1695         struct azx_dev *azx_dev;
1696         u32 status;
1697         u8 sd_status;
1698         int i;
1699
1700 #ifdef CONFIG_PM
1701         if (azx_has_pm_runtime(chip))
1702                 if (!pm_runtime_active(chip->card->dev))
1703                         return IRQ_NONE;
1704 #endif
1705
1706         spin_lock(&chip->reg_lock);
1707
1708         if (chip->disabled) {
1709                 spin_unlock(&chip->reg_lock);
1710                 return IRQ_NONE;
1711         }
1712
1713         status = azx_readl(chip, INTSTS);
1714         if (status == 0 || status == 0xffffffff) {
1715                 spin_unlock(&chip->reg_lock);
1716                 return IRQ_NONE;
1717         }
1718
1719         for (i = 0; i < chip->num_streams; i++) {
1720                 azx_dev = &chip->azx_dev[i];
1721                 if (status & azx_dev->sd_int_sta_mask) {
1722                         sd_status = azx_sd_readb(chip, azx_dev, SD_STS);
1723                         azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK);
1724                         if (!azx_dev->substream || !azx_dev->running ||
1725                             !(sd_status & SD_INT_COMPLETE))
1726                                 continue;
1727                         /* check whether this IRQ is really acceptable */
1728                         if (!chip->ops->position_check ||
1729                             chip->ops->position_check(chip, azx_dev)) {
1730                                 spin_unlock(&chip->reg_lock);
1731                                 snd_pcm_period_elapsed(azx_dev->substream);
1732                                 spin_lock(&chip->reg_lock);
1733                         }
1734                 }
1735         }
1736
1737         /* clear rirb int */
1738         status = azx_readb(chip, RIRBSTS);
1739         if (status & RIRB_INT_MASK) {
1740                 if (status & RIRB_INT_RESPONSE) {
1741                         if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1742                                 udelay(80);
1743                         azx_update_rirb(chip);
1744                 }
1745                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1746         }
1747
1748         spin_unlock(&chip->reg_lock);
1749
1750         return IRQ_HANDLED;
1751 }
1752 EXPORT_SYMBOL_GPL(azx_interrupt);
1753
1754 /*
1755  * Codec initerface
1756  */
1757
1758 /*
1759  * Probe the given codec address
1760  */
1761 static int probe_codec(struct azx *chip, int addr)
1762 {
1763         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1764                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1765         unsigned int res;
1766
1767         mutex_lock(&chip->bus->cmd_mutex);
1768         chip->probing = 1;
1769         azx_send_cmd(chip->bus, cmd);
1770         res = azx_get_response(chip->bus, addr);
1771         chip->probing = 0;
1772         mutex_unlock(&chip->bus->cmd_mutex);
1773         if (res == -1)
1774                 return -EIO;
1775         dev_dbg(chip->card->dev, "codec #%d probed OK\n", addr);
1776         return 0;
1777 }
1778
1779 static void azx_bus_reset(struct hda_bus *bus)
1780 {
1781         struct azx *chip = bus->private_data;
1782
1783         bus->in_reset = 1;
1784         azx_stop_chip(chip);
1785         azx_init_chip(chip, true);
1786         if (chip->initialized)
1787                 snd_hda_bus_reset(chip->bus);
1788         bus->in_reset = 0;
1789 }
1790
1791 static int get_jackpoll_interval(struct azx *chip)
1792 {
1793         int i;
1794         unsigned int j;
1795
1796         if (!chip->jackpoll_ms)
1797                 return 0;
1798
1799         i = chip->jackpoll_ms[chip->dev_index];
1800         if (i == 0)
1801                 return 0;
1802         if (i < 50 || i > 60000)
1803                 j = 0;
1804         else
1805                 j = msecs_to_jiffies(i);
1806         if (j == 0)
1807                 dev_warn(chip->card->dev,
1808                          "jackpoll_ms value out of range: %d\n", i);
1809         return j;
1810 }
1811
1812 static struct hda_bus_ops bus_ops = {
1813         .command = azx_send_cmd,
1814         .get_response = azx_get_response,
1815         .attach_pcm = azx_attach_pcm_stream,
1816         .bus_reset = azx_bus_reset,
1817 #ifdef CONFIG_SND_HDA_DSP_LOADER
1818         .load_dsp_prepare = azx_load_dsp_prepare,
1819         .load_dsp_trigger = azx_load_dsp_trigger,
1820         .load_dsp_cleanup = azx_load_dsp_cleanup,
1821 #endif
1822 };
1823
1824 /* HD-audio bus initialization */
1825 int azx_bus_create(struct azx *chip, const char *model)
1826 {
1827         struct hda_bus *bus;
1828         int err;
1829
1830         err = snd_hda_bus_new(chip->card, &bus);
1831         if (err < 0)
1832                 return err;
1833
1834         chip->bus = bus;
1835         bus->private_data = chip;
1836         bus->pci = chip->pci;
1837         bus->modelname = model;
1838         bus->ops = bus_ops;
1839
1840         if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1841                 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1842                 bus->needs_damn_long_delay = 1;
1843         }
1844
1845         /* AMD chipsets often cause the communication stalls upon certain
1846          * sequence like the pin-detection.  It seems that forcing the synced
1847          * access works around the stall.  Grrr...
1848          */
1849         if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1850                 dev_dbg(chip->card->dev, "Enable sync_write for stable communication\n");
1851                 bus->sync_write = 1;
1852                 bus->allow_bus_reset = 1;
1853         }
1854
1855         return 0;
1856 }
1857 EXPORT_SYMBOL_GPL(azx_bus_create);
1858
1859 /* Probe codecs */
1860 int azx_probe_codecs(struct azx *chip, unsigned int max_slots)
1861 {
1862         struct hda_bus *bus = chip->bus;
1863         int c, codecs, err;
1864
1865         codecs = 0;
1866         if (!max_slots)
1867                 max_slots = AZX_DEFAULT_CODECS;
1868
1869         /* First try to probe all given codec slots */
1870         for (c = 0; c < max_slots; c++) {
1871                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1872                         if (probe_codec(chip, c) < 0) {
1873                                 /* Some BIOSen give you wrong codec addresses
1874                                  * that don't exist
1875                                  */
1876                                 dev_warn(chip->card->dev,
1877                                          "Codec #%d probe error; disabling it...\n", c);
1878                                 chip->codec_mask &= ~(1 << c);
1879                                 /* More badly, accessing to a non-existing
1880                                  * codec often screws up the controller chip,
1881                                  * and disturbs the further communications.
1882                                  * Thus if an error occurs during probing,
1883                                  * better to reset the controller chip to
1884                                  * get back to the sanity state.
1885                                  */
1886                                 azx_stop_chip(chip);
1887                                 azx_init_chip(chip, true);
1888                         }
1889                 }
1890         }
1891
1892         /* Then create codec instances */
1893         for (c = 0; c < max_slots; c++) {
1894                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1895                         struct hda_codec *codec;
1896                         err = snd_hda_codec_new(bus, c, &codec);
1897                         if (err < 0)
1898                                 continue;
1899                         codec->jackpoll_interval = get_jackpoll_interval(chip);
1900                         codec->beep_mode = chip->beep_mode;
1901                         codecs++;
1902                 }
1903         }
1904         if (!codecs) {
1905                 dev_err(chip->card->dev, "no codecs initialized\n");
1906                 return -ENXIO;
1907         }
1908         return 0;
1909 }
1910 EXPORT_SYMBOL_GPL(azx_probe_codecs);
1911
1912 /* configure each codec instance */
1913 int azx_codec_configure(struct azx *chip)
1914 {
1915         struct hda_codec *codec;
1916         list_for_each_entry(codec, &chip->bus->codec_list, list) {
1917                 snd_hda_codec_configure(codec);
1918         }
1919         return 0;
1920 }
1921 EXPORT_SYMBOL_GPL(azx_codec_configure);
1922
1923
1924 static bool is_input_stream(struct azx *chip, unsigned char index)
1925 {
1926         return (index >= chip->capture_index_offset &&
1927                 index < chip->capture_index_offset + chip->capture_streams);
1928 }
1929
1930 /* initialize SD streams */
1931 int azx_init_stream(struct azx *chip)
1932 {
1933         int i;
1934         int in_stream_tag = 0;
1935         int out_stream_tag = 0;
1936
1937         /* initialize each stream (aka device)
1938          * assign the starting bdl address to each stream (device)
1939          * and initialize
1940          */
1941         for (i = 0; i < chip->num_streams; i++) {
1942                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1943                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1944                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1945                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1946                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1947                 azx_dev->sd_int_sta_mask = 1 << i;
1948                 azx_dev->index = i;
1949
1950                 /* stream tag must be unique throughout
1951                  * the stream direction group,
1952                  * valid values 1...15
1953                  * use separate stream tag if the flag
1954                  * AZX_DCAPS_SEPARATE_STREAM_TAG is used
1955                  */
1956                 if (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG)
1957                         azx_dev->stream_tag =
1958                                 is_input_stream(chip, i) ?
1959                                 ++in_stream_tag :
1960                                 ++out_stream_tag;
1961                 else
1962                         azx_dev->stream_tag = i + 1;
1963         }
1964
1965         return 0;
1966 }
1967 EXPORT_SYMBOL_GPL(azx_init_stream);
1968
1969 /*
1970  * reboot notifier for hang-up problem at power-down
1971  */
1972 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
1973 {
1974         struct azx *chip = container_of(nb, struct azx, reboot_notifier);
1975         snd_hda_bus_reboot_notify(chip->bus);
1976         azx_stop_chip(chip);
1977         return NOTIFY_OK;
1978 }
1979
1980 void azx_notifier_register(struct azx *chip)
1981 {
1982         chip->reboot_notifier.notifier_call = azx_halt;
1983         register_reboot_notifier(&chip->reboot_notifier);
1984 }
1985 EXPORT_SYMBOL_GPL(azx_notifier_register);
1986
1987 void azx_notifier_unregister(struct azx *chip)
1988 {
1989         if (chip->reboot_notifier.notifier_call)
1990                 unregister_reboot_notifier(&chip->reboot_notifier);
1991 }
1992 EXPORT_SYMBOL_GPL(azx_notifier_unregister);
1993
1994 MODULE_LICENSE("GPL");
1995 MODULE_DESCRIPTION("Common HDA driver functions");