sound/pci/hda/hda_controller.c

   1 /*
   2  *
   3  *  Implementation of primary alsa driver code base for Intel HD Audio.
   4  *
   5  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   6  *
   7  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   8  *                     PeiSen Hou <pshou@realtek.com.tw>
   9  *
  10  *  This program is free software; you can redistribute it and/or modify it
  11  *  under the terms of the GNU General Public License as published by the Free
  12  *  Software Foundation; either version 2 of the License, or (at your option)
  13  *  any later version.
  14  *
  15  *  This program is distributed in the hope that it will be useful, but WITHOUT
  16  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  18  *  more details.
  19  *
  20  *
  21  */
  22
  23 #include <linux/clocksource.h>
  24 #include <linux/delay.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/slab.h>
  30 #include <sound/core.h>
  31 #include <sound/initval.h>
  32 #include "hda_controller.h"
  33
  34 /* DSP lock helpers */
  35 #define dsp_lock(dev)           snd_hdac_dsp_lock(azx_stream(dev))
  36 #define dsp_unlock(dev)         snd_hdac_dsp_unlock(azx_stream(dev))
  37 #define dsp_is_locked(dev)      snd_hdac_stream_is_locked(azx_stream(dev))
  38
  39 /* assign a stream for the PCM */
  40 static inline struct azx_dev *
  41 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
  42 {
  43         struct hdac_stream *s;
  44
  45         s = snd_hdac_stream_assign(azx_bus(chip), substream);
  46         if (!s)
  47                 return NULL;
  48         return stream_to_azx_dev(s);
  49 }
  50
  51 /* release the assigned stream */
  52 static inline void azx_release_device(struct azx_dev *azx_dev)
  53 {
  54         snd_hdac_stream_release(azx_stream(azx_dev));
  55 }
  56
  57 static inline struct hda_pcm_stream *
  58 to_hda_pcm_stream(struct snd_pcm_substream *substream)
  59 {
  60         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
  61         return &apcm->info->stream[substream->stream];
  62 }
  63
  64 static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream,
  65                                 u64 nsec)
  66 {
  67         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
  68         struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
  69         u64 codec_frames, codec_nsecs;
  70
  71         if (!hinfo->ops.get_delay)
  72                 return nsec;
  73
  74         codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream);
  75         codec_nsecs = div_u64(codec_frames * 1000000000LL,
  76                               substream->runtime->rate);
  77
  78         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
  79                 return nsec + codec_nsecs;
  80
  81         return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
  82 }
  83
  84 /*
  85  * PCM ops
  86  */
  87
  88 static int azx_pcm_close(struct snd_pcm_substream *substream)
  89 {
  90         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
  91         struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
  92         struct azx *chip = apcm->chip;
  93         struct azx_dev *azx_dev = get_azx_dev(substream);
  94
  95         mutex_lock(&chip->open_mutex);
  96         azx_release_device(azx_dev);
  97         if (hinfo->ops.close)
  98                 hinfo->ops.close(hinfo, apcm->codec, substream);
  99         snd_hda_power_down(apcm->codec);
 100         mutex_unlock(&chip->open_mutex);
 101         snd_hda_codec_pcm_put(apcm->info);
 102         return 0;
 103 }
 104
 105 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
 106                              struct snd_pcm_hw_params *hw_params)
 107 {
 108         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 109         struct azx *chip = apcm->chip;
 110         struct azx_dev *azx_dev = get_azx_dev(substream);
 111         int ret;
 112
 113         dsp_lock(azx_dev);
 114         if (dsp_is_locked(azx_dev)) {
 115                 ret = -EBUSY;
 116                 goto unlock;
 117         }
 118
 119         azx_dev->core.bufsize = 0;
 120         azx_dev->core.period_bytes = 0;
 121         azx_dev->core.format_val = 0;
 122         ret = chip->ops->substream_alloc_pages(chip, substream,
 123                                           params_buffer_bytes(hw_params));
 124 unlock:
 125         dsp_unlock(azx_dev);
 126         return ret;
 127 }
 128
 129 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
 130 {
 131         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 132         struct azx_dev *azx_dev = get_azx_dev(substream);
 133         struct azx *chip = apcm->chip;
 134         struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
 135         int err;
 136
 137         /* reset BDL address */
 138         dsp_lock(azx_dev);
 139         if (!dsp_is_locked(azx_dev))
 140                 snd_hdac_stream_cleanup(azx_stream(azx_dev));
 141
 142         snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
 143
 144         err = chip->ops->substream_free_pages(chip, substream);
 145         azx_dev->prepared = 0;
 146         dsp_unlock(azx_dev);
 147         return err;
 148 }
 149
 150 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
 151 {
 152         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 153         struct azx *chip = apcm->chip;
 154         struct azx_dev *azx_dev = get_azx_dev(substream);
 155         struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
 156         struct snd_pcm_runtime *runtime = substream->runtime;
 157         unsigned int bufsize, period_bytes, format_val, stream_tag;
 158         int err;
 159         struct hda_spdif_out *spdif =
 160                 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
 161         unsigned short ctls = spdif ? spdif->ctls : 0;
 162
 163         dsp_lock(azx_dev);
 164         if (dsp_is_locked(azx_dev)) {
 165                 err = -EBUSY;
 166                 goto unlock;
 167         }
 168
 169         snd_hdac_stream_reset(azx_stream(azx_dev));
 170         format_val = snd_hdac_calc_stream_format(runtime->rate,
 171                                                 runtime->channels,
 172                                                 runtime->format,
 173                                                 hinfo->maxbps,
 174                                                 ctls);
 175         if (!format_val) {
 176                 dev_err(chip->card->dev,
 177                         "invalid format_val, rate=%d, ch=%d, format=%d\n",
 178                         runtime->rate, runtime->channels, runtime->format);
 179                 err = -EINVAL;
 180                 goto unlock;
 181         }
 182
 183         bufsize = snd_pcm_lib_buffer_bytes(substream);
 184         period_bytes = snd_pcm_lib_period_bytes(substream);
 185
 186         dev_dbg(chip->card->dev, "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
 187                 bufsize, format_val);
 188
 189         if (bufsize != azx_dev->core.bufsize ||
 190             period_bytes != azx_dev->core.period_bytes ||
 191             format_val != azx_dev->core.format_val ||
 192             runtime->no_period_wakeup != azx_dev->core.no_period_wakeup) {
 193                 azx_dev->core.bufsize = bufsize;
 194                 azx_dev->core.period_bytes = period_bytes;
 195                 azx_dev->core.format_val = format_val;
 196                 azx_dev->core.no_period_wakeup = runtime->no_period_wakeup;
 197                 err = snd_hdac_stream_setup_periods(azx_stream(azx_dev));
 198                 if (err < 0)
 199                         goto unlock;
 200         }
 201
 202         snd_hdac_stream_setup(azx_stream(azx_dev));
 203
 204         stream_tag = azx_dev->core.stream_tag;
 205         /* CA-IBG chips need the playback stream starting from 1 */
 206         if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
 207             stream_tag > chip->capture_streams)
 208                 stream_tag -= chip->capture_streams;
 209         err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
 210                                      azx_dev->core.format_val, substream);
 211
 212  unlock:
 213         if (!err)
 214                 azx_dev->prepared = 1;
 215         dsp_unlock(azx_dev);
 216         return err;
 217 }
 218
 219 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
 220 {
 221         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 222         struct azx *chip = apcm->chip;
 223         struct hdac_bus *bus = azx_bus(chip);
 224         struct azx_dev *azx_dev;
 225         struct snd_pcm_substream *s;
 226         struct hdac_stream *hstr;
 227         bool start;
 228         int sbits = 0;
 229         int sync_reg;
 230
 231         azx_dev = get_azx_dev(substream);
 232         hstr = azx_stream(azx_dev);
 233         if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
 234                 sync_reg = AZX_REG_OLD_SSYNC;
 235         else
 236                 sync_reg = AZX_REG_SSYNC;
 237
 238         if (dsp_is_locked(azx_dev) || !azx_dev->prepared)
 239                 return -EPIPE;
 240
 241         switch (cmd) {
 242         case SNDRV_PCM_TRIGGER_START:
 243         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 244         case SNDRV_PCM_TRIGGER_RESUME:
 245                 start = true;
 246                 break;
 247         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 248         case SNDRV_PCM_TRIGGER_SUSPEND:
 249         case SNDRV_PCM_TRIGGER_STOP:
 250                 start = false;
 251                 break;
 252         default:
 253                 return -EINVAL;
 254         }
 255
 256         snd_pcm_group_for_each_entry(s, substream) {
 257                 if (s->pcm->card != substream->pcm->card)
 258                         continue;
 259                 azx_dev = get_azx_dev(s);
 260                 sbits |= 1 << azx_dev->core.index;
 261                 snd_pcm_trigger_done(s, substream);
 262         }
 263
 264         spin_lock(&bus->reg_lock);
 265
 266         /* first, set SYNC bits of corresponding streams */
 267         snd_hdac_stream_sync_trigger(hstr, true, sbits, sync_reg);
 268
 269         snd_pcm_group_for_each_entry(s, substream) {
 270                 if (s->pcm->card != substream->pcm->card)
 271                         continue;
 272                 azx_dev = get_azx_dev(s);
 273                 if (start) {
 274                         azx_dev->insufficient = 1;
 275                         snd_hdac_stream_start(azx_stream(azx_dev), true);
 276                 } else {
 277                         snd_hdac_stream_stop(azx_stream(azx_dev));
 278                 }
 279         }
 280         spin_unlock(&bus->reg_lock);
 281
 282         snd_hdac_stream_sync(hstr, start, sbits);
 283
 284         spin_lock(&bus->reg_lock);
 285         /* reset SYNC bits */
 286         snd_hdac_stream_sync_trigger(hstr, false, sbits, sync_reg);
 287         if (start)
 288                 snd_hdac_stream_timecounter_init(hstr, sbits);
 289         spin_unlock(&bus->reg_lock);
 290         return 0;
 291 }
 292
 293 unsigned int azx_get_pos_lpib(struct azx *chip, struct azx_dev *azx_dev)
 294 {
 295         return snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 296 }
 297 EXPORT_SYMBOL_GPL(azx_get_pos_lpib);
 298
 299 unsigned int azx_get_pos_posbuf(struct azx *chip, struct azx_dev *azx_dev)
 300 {
 301         return snd_hdac_stream_get_pos_posbuf(azx_stream(azx_dev));
 302 }
 303 EXPORT_SYMBOL_GPL(azx_get_pos_posbuf);
 304
 305 unsigned int azx_get_position(struct azx *chip,
 306                               struct azx_dev *azx_dev)
 307 {
 308         struct snd_pcm_substream *substream = azx_dev->core.substream;
 309         unsigned int pos;
 310         int stream = substream->stream;
 311         int delay = 0;
 312
 313         if (chip->get_position[stream])
 314                 pos = chip->get_position[stream](chip, azx_dev);
 315         else /* use the position buffer as default */
 316                 pos = azx_get_pos_posbuf(chip, azx_dev);
 317
 318         if (pos >= azx_dev->core.bufsize)
 319                 pos = 0;
 320
 321         if (substream->runtime) {
 322                 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 323                 struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
 324
 325                 if (chip->get_delay[stream])
 326                         delay += chip->get_delay[stream](chip, azx_dev, pos);
 327                 if (hinfo->ops.get_delay)
 328                         delay += hinfo->ops.get_delay(hinfo, apcm->codec,
 329                                                       substream);
 330                 substream->runtime->delay = delay;
 331         }
 332
 333         return pos;
 334 }
 335 EXPORT_SYMBOL_GPL(azx_get_position);
 336
 337 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
 338 {
 339         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 340         struct azx *chip = apcm->chip;
 341         struct azx_dev *azx_dev = get_azx_dev(substream);
 342         return bytes_to_frames(substream->runtime,
 343                                azx_get_position(chip, azx_dev));
 344 }
 345
 346 static int azx_get_time_info(struct snd_pcm_substream *substream,
 347                         struct timespec *system_ts, struct timespec *audio_ts,
 348                         struct snd_pcm_audio_tstamp_config *audio_tstamp_config,
 349                         struct snd_pcm_audio_tstamp_report *audio_tstamp_report)
 350 {
 351         struct azx_dev *azx_dev = get_azx_dev(substream);
 352         u64 nsec;
 353
 354         if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) &&
 355                 (audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) {
 356
 357                 snd_pcm_gettime(substream->runtime, system_ts);
 358
 359                 nsec = timecounter_read(&azx_dev->core.tc);
 360                 nsec = div_u64(nsec, 3); /* can be optimized */
 361                 if (audio_tstamp_config->report_delay)
 362                         nsec = azx_adjust_codec_delay(substream, nsec);
 363
 364                 *audio_ts = ns_to_timespec(nsec);
 365
 366                 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK;
 367                 audio_tstamp_report->accuracy_report = 1; /* rest of structure is valid */
 368                 audio_tstamp_report->accuracy = 42; /* 24 MHz WallClock == 42ns resolution */
 369
 370         } else
 371                 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT;
 372
 373         return 0;
 374 }
 375
 376 static struct snd_pcm_hardware azx_pcm_hw = {
 377         .info =                 (SNDRV_PCM_INFO_MMAP |
 378                                  SNDRV_PCM_INFO_INTERLEAVED |
 379                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
 380                                  SNDRV_PCM_INFO_MMAP_VALID |
 381                                  /* No full-resume yet implemented */
 382                                  /* SNDRV_PCM_INFO_RESUME |*/
 383                                  SNDRV_PCM_INFO_PAUSE |
 384                                  SNDRV_PCM_INFO_SYNC_START |
 385                                  SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */
 386                                  SNDRV_PCM_INFO_HAS_LINK_ATIME |
 387                                  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
 388         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
 389         .rates =                SNDRV_PCM_RATE_48000,
 390         .rate_min =             48000,
 391         .rate_max =             48000,
 392         .channels_min =         2,
 393         .channels_max =         2,
 394         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
 395         .period_bytes_min =     128,
 396         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
 397         .periods_min =          2,
 398         .periods_max =          AZX_MAX_FRAG,
 399         .fifo_size =            0,
 400 };
 401
 402 static int azx_pcm_open(struct snd_pcm_substream *substream)
 403 {
 404         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 405         struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
 406         struct azx *chip = apcm->chip;
 407         struct azx_dev *azx_dev;
 408         struct snd_pcm_runtime *runtime = substream->runtime;
 409         int err;
 410         int buff_step;
 411
 412         snd_hda_codec_pcm_get(apcm->info);
 413         mutex_lock(&chip->open_mutex);
 414         azx_dev = azx_assign_device(chip, substream);
 415         if (azx_dev == NULL) {
 416                 err = -EBUSY;
 417                 goto unlock;
 418         }
 419         runtime->private_data = azx_dev;
 420         runtime->hw = azx_pcm_hw;
 421         runtime->hw.channels_min = hinfo->channels_min;
 422         runtime->hw.channels_max = hinfo->channels_max;
 423         runtime->hw.formats = hinfo->formats;
 424         runtime->hw.rates = hinfo->rates;
 425         snd_pcm_limit_hw_rates(runtime);
 426         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
 427
 428         /* avoid wrap-around with wall-clock */
 429         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
 430                                      20,
 431                                      178000000);
 432
 433         if (chip->align_buffer_size)
 434                 /* constrain buffer sizes to be multiple of 128
 435                    bytes. This is more efficient in terms of memory
 436                    access but isn't required by the HDA spec and
 437                    prevents users from specifying exact period/buffer
 438                    sizes. For example for 44.1kHz, a period size set
 439                    to 20ms will be rounded to 19.59ms. */
 440                 buff_step = 128;
 441         else
 442                 /* Don't enforce steps on buffer sizes, still need to
 443                    be multiple of 4 bytes (HDA spec). Tested on Intel
 444                    HDA controllers, may not work on all devices where
 445                    option needs to be disabled */
 446                 buff_step = 4;
 447
 448         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
 449                                    buff_step);
 450         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
 451                                    buff_step);
 452         snd_hda_power_up(apcm->codec);
 453         if (hinfo->ops.open)
 454                 err = hinfo->ops.open(hinfo, apcm->codec, substream);
 455         else
 456                 err = -ENODEV;
 457         if (err < 0) {
 458                 azx_release_device(azx_dev);
 459                 goto powerdown;
 460         }
 461         snd_pcm_limit_hw_rates(runtime);
 462         /* sanity check */
 463         if (snd_BUG_ON(!runtime->hw.channels_min) ||
 464             snd_BUG_ON(!runtime->hw.channels_max) ||
 465             snd_BUG_ON(!runtime->hw.formats) ||
 466             snd_BUG_ON(!runtime->hw.rates)) {
 467                 azx_release_device(azx_dev);
 468                 if (hinfo->ops.close)
 469                         hinfo->ops.close(hinfo, apcm->codec, substream);
 470                 err = -EINVAL;
 471                 goto powerdown;
 472         }
 473
 474         /* disable LINK_ATIME timestamps for capture streams
 475            until we figure out how to handle digital inputs */
 476         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
 477                 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */
 478                 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME;
 479         }
 480
 481         snd_pcm_set_sync(substream);
 482         mutex_unlock(&chip->open_mutex);
 483         return 0;
 484
 485  powerdown:
 486         snd_hda_power_down(apcm->codec);
 487  unlock:
 488         mutex_unlock(&chip->open_mutex);
 489         snd_hda_codec_pcm_put(apcm->info);
 490         return err;
 491 }
 492
 493 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
 494                         struct vm_area_struct *area)
 495 {
 496         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 497         struct azx *chip = apcm->chip;
 498         if (chip->ops->pcm_mmap_prepare)
 499                 chip->ops->pcm_mmap_prepare(substream, area);
 500         return snd_pcm_lib_default_mmap(substream, area);
 501 }
 502
 503 static struct snd_pcm_ops azx_pcm_ops = {
 504         .open = azx_pcm_open,
 505         .close = azx_pcm_close,
 506         .ioctl = snd_pcm_lib_ioctl,
 507         .hw_params = azx_pcm_hw_params,
 508         .hw_free = azx_pcm_hw_free,
 509         .prepare = azx_pcm_prepare,
 510         .trigger = azx_pcm_trigger,
 511         .pointer = azx_pcm_pointer,
 512         .get_time_info =  azx_get_time_info,
 513         .mmap = azx_pcm_mmap,
 514         .page = snd_pcm_sgbuf_ops_page,
 515 };
 516
 517 static void azx_pcm_free(struct snd_pcm *pcm)
 518 {
 519         struct azx_pcm *apcm = pcm->private_data;
 520         if (apcm) {
 521                 list_del(&apcm->list);
 522                 apcm->info->pcm = NULL;
 523                 kfree(apcm);
 524         }
 525 }
 526
 527 #define MAX_PREALLOC_SIZE       (32 * 1024 * 1024)
 528
 529 static int azx_attach_pcm_stream(struct hda_bus *_bus, struct hda_codec *codec,
 530                                  struct hda_pcm *cpcm)
 531 {
 532         struct hdac_bus *bus = &_bus->core;
 533         struct azx *chip = bus_to_azx(bus);
 534         struct snd_pcm *pcm;
 535         struct azx_pcm *apcm;
 536         int pcm_dev = cpcm->device;
 537         unsigned int size;
 538         int s, err;
 539
 540         list_for_each_entry(apcm, &chip->pcm_list, list) {
 541                 if (apcm->pcm->device == pcm_dev) {
 542                         dev_err(chip->card->dev, "PCM %d already exists\n",
 543                                 pcm_dev);
 544                         return -EBUSY;
 545                 }
 546         }
 547         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
 548                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
 549                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
 550                           &pcm);
 551         if (err < 0)
 552                 return err;
 553         strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
 554         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
 555         if (apcm == NULL)
 556                 return -ENOMEM;
 557         apcm->chip = chip;
 558         apcm->pcm = pcm;
 559         apcm->codec = codec;
 560         apcm->info = cpcm;
 561         pcm->private_data = apcm;
 562         pcm->private_free = azx_pcm_free;
 563         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
 564                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
 565         list_add_tail(&apcm->list, &chip->pcm_list);
 566         cpcm->pcm = pcm;
 567         for (s = 0; s < 2; s++) {
 568                 if (cpcm->stream[s].substreams)
 569                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
 570         }
 571         /* buffer pre-allocation */
 572         size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
 573         if (size > MAX_PREALLOC_SIZE)
 574                 size = MAX_PREALLOC_SIZE;
 575         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
 576                                               chip->card->dev,
 577                                               size, MAX_PREALLOC_SIZE);
 578         return 0;
 579 }
 580
 581 static unsigned int azx_command_addr(u32 cmd)
 582 {
 583         unsigned int addr = cmd >> 28;
 584
 585         if (addr >= AZX_MAX_CODECS) {
 586                 snd_BUG();
 587                 addr = 0;
 588         }
 589
 590         return addr;
 591 }
 592
 593 /* receive a response */
 594 static int azx_rirb_get_response(struct hdac_bus *bus, unsigned int addr,
 595                                  unsigned int *res)
 596 {
 597         struct azx *chip = bus_to_azx(bus);
 598         struct hda_bus *hbus = &chip->bus;
 599         unsigned long timeout;
 600         unsigned long loopcounter;
 601         int do_poll = 0;
 602
 603  again:
 604         timeout = jiffies + msecs_to_jiffies(1000);
 605
 606         for (loopcounter = 0;; loopcounter++) {
 607                 spin_lock_irq(&bus->reg_lock);
 608                 if (chip->polling_mode || do_poll)
 609                         snd_hdac_bus_update_rirb(bus);
 610                 if (!bus->rirb.cmds[addr]) {
 611                         if (!do_poll)
 612                                 chip->poll_count = 0;
 613                         if (res)
 614                                 *res = bus->rirb.res[addr]; /* the last value */
 615                         spin_unlock_irq(&bus->reg_lock);
 616                         return 0;
 617                 }
 618                 spin_unlock_irq(&bus->reg_lock);
 619                 if (time_after(jiffies, timeout))
 620                         break;
 621                 if (hbus->needs_damn_long_delay || loopcounter > 3000)
 622                         msleep(2); /* temporary workaround */
 623                 else {
 624                         udelay(10);
 625                         cond_resched();
 626                 }
 627         }
 628
 629         if (hbus->no_response_fallback)
 630                 return -EIO;
 631
 632         if (!chip->polling_mode && chip->poll_count < 2) {
 633                 dev_dbg(chip->card->dev,
 634                         "azx_get_response timeout, polling the codec once: last cmd=0x%08x\n",
 635                         bus->last_cmd[addr]);
 636                 do_poll = 1;
 637                 chip->poll_count++;
 638                 goto again;
 639         }
 640
 641
 642         if (!chip->polling_mode) {
 643                 dev_warn(chip->card->dev,
 644                          "azx_get_response timeout, switching to polling mode: last cmd=0x%08x\n",
 645                          bus->last_cmd[addr]);
 646                 chip->polling_mode = 1;
 647                 goto again;
 648         }
 649
 650         if (chip->msi) {
 651                 dev_warn(chip->card->dev,
 652                          "No response from codec, disabling MSI: last cmd=0x%08x\n",
 653                          bus->last_cmd[addr]);
 654                 if (chip->ops->disable_msi_reset_irq &&
 655                     chip->ops->disable_msi_reset_irq(chip) < 0)
 656                         return -EIO;
 657                 goto again;
 658         }
 659
 660         if (chip->probing) {
 661                 /* If this critical timeout happens during the codec probing
 662                  * phase, this is likely an access to a non-existing codec
 663                  * slot.  Better to return an error and reset the system.
 664                  */
 665                 return -EIO;
 666         }
 667
 668         /* a fatal communication error; need either to reset or to fallback
 669          * to the single_cmd mode
 670          */
 671         if (hbus->allow_bus_reset && !hbus->response_reset && !hbus->in_reset) {
 672                 hbus->response_reset = 1;
 673                 return -EAGAIN; /* give a chance to retry */
 674         }
 675
 676         dev_err(chip->card->dev,
 677                 "azx_get_response timeout, switching to single_cmd mode: last cmd=0x%08x\n",
 678                 bus->last_cmd[addr]);
 679         chip->single_cmd = 1;
 680         hbus->response_reset = 0;
 681         snd_hdac_bus_stop_cmd_io(bus);
 682         return -EIO;
 683 }
 684
 685 /*
 686  * Use the single immediate command instead of CORB/RIRB for simplicity
 687  *
 688  * Note: according to Intel, this is not preferred use.  The command was
 689  *       intended for the BIOS only, and may get confused with unsolicited
 690  *       responses.  So, we shouldn't use it for normal operation from the
 691  *       driver.
 692  *       I left the codes, however, for debugging/testing purposes.
 693  */
 694
 695 /* receive a response */
 696 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
 697 {
 698         int timeout = 50;
 699
 700         while (timeout--) {
 701                 /* check IRV busy bit */
 702                 if (azx_readw(chip, IRS) & AZX_IRS_VALID) {
 703                         /* reuse rirb.res as the response return value */
 704                         azx_bus(chip)->rirb.res[addr] = azx_readl(chip, IR);
 705                         return 0;
 706                 }
 707                 udelay(1);
 708         }
 709         if (printk_ratelimit())
 710                 dev_dbg(chip->card->dev, "get_response timeout: IRS=0x%x\n",
 711                         azx_readw(chip, IRS));
 712         azx_bus(chip)->rirb.res[addr] = -1;
 713         return -EIO;
 714 }
 715
 716 /* send a command */
 717 static int azx_single_send_cmd(struct hdac_bus *bus, u32 val)
 718 {
 719         struct azx *chip = bus_to_azx(bus);
 720         unsigned int addr = azx_command_addr(val);
 721         int timeout = 50;
 722
 723         bus->last_cmd[azx_command_addr(val)] = val;
 724         while (timeout--) {
 725                 /* check ICB busy bit */
 726                 if (!((azx_readw(chip, IRS) & AZX_IRS_BUSY))) {
 727                         /* Clear IRV valid bit */
 728                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 729                                    AZX_IRS_VALID);
 730                         azx_writel(chip, IC, val);
 731                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 732                                    AZX_IRS_BUSY);
 733                         return azx_single_wait_for_response(chip, addr);
 734                 }
 735                 udelay(1);
 736         }
 737         if (printk_ratelimit())
 738                 dev_dbg(chip->card->dev,
 739                         "send_cmd timeout: IRS=0x%x, val=0x%x\n",
 740                         azx_readw(chip, IRS), val);
 741         return -EIO;
 742 }
 743
 744 /* receive a response */
 745 static int azx_single_get_response(struct hdac_bus *bus, unsigned int addr,
 746                                    unsigned int *res)
 747 {
 748         if (res)
 749                 *res = bus->rirb.res[addr];
 750         return 0;
 751 }
 752
 753 /*
 754  * The below are the main callbacks from hda_codec.
 755  *
 756  * They are just the skeleton to call sub-callbacks according to the
 757  * current setting of chip->single_cmd.
 758  */
 759
 760 /* send a command */
 761 static int azx_send_cmd(struct hdac_bus *bus, unsigned int val)
 762 {
 763         struct azx *chip = bus_to_azx(bus);
 764
 765         if (chip->disabled)
 766                 return 0;
 767         if (chip->single_cmd)
 768                 return azx_single_send_cmd(bus, val);
 769         else
 770                 return snd_hdac_bus_send_cmd(bus, val);
 771 }
 772
 773 /* get a response */
 774 static int azx_get_response(struct hdac_bus *bus, unsigned int addr,
 775                             unsigned int *res)
 776 {
 777         struct azx *chip = bus_to_azx(bus);
 778
 779         if (chip->disabled)
 780                 return 0;
 781         if (chip->single_cmd)
 782                 return azx_single_get_response(bus, addr, res);
 783         else
 784                 return azx_rirb_get_response(bus, addr, res);
 785 }
 786
 787 static const struct hdac_bus_ops bus_core_ops = {
 788         .command = azx_send_cmd,
 789         .get_response = azx_get_response,
 790 };
 791
 792 #ifdef CONFIG_SND_HDA_DSP_LOADER
 793 /*
 794  * DSP loading code (e.g. for CA0132)
 795  */
 796
 797 /* use the first stream for loading DSP */
 798 static struct azx_dev *
 799 azx_get_dsp_loader_dev(struct azx *chip)
 800 {
 801         struct hdac_bus *bus = azx_bus(chip);
 802         struct hdac_stream *s;
 803
 804         list_for_each_entry(s, &bus->stream_list, list)
 805                 if (s->index == chip->playback_index_offset)
 806                         return stream_to_azx_dev(s);
 807
 808         return NULL;
 809 }
 810
 811 static int azx_load_dsp_prepare(struct hda_bus *_bus, unsigned int format,
 812                                 unsigned int byte_size,
 813                                 struct snd_dma_buffer *bufp)
 814 {
 815         struct hdac_bus *bus = &_bus->core;
 816         struct azx *chip = bus_to_azx(bus);
 817         struct azx_dev *azx_dev;
 818         struct hdac_stream *hstr;
 819         bool saved = false;
 820         int err;
 821
 822         azx_dev = azx_get_dsp_loader_dev(chip);
 823         hstr = azx_stream(azx_dev);
 824         spin_lock_irq(&bus->reg_lock);
 825         if (hstr->opened) {
 826                 chip->saved_azx_dev = *azx_dev;
 827                 saved = true;
 828         }
 829         spin_unlock_irq(&bus->reg_lock);
 830
 831         err = snd_hdac_dsp_prepare(hstr, format, byte_size, bufp);
 832         if (err < 0) {
 833                 spin_lock_irq(&bus->reg_lock);
 834                 if (saved)
 835                         *azx_dev = chip->saved_azx_dev;
 836                 spin_unlock_irq(&bus->reg_lock);
 837                 return err;
 838         }
 839
 840         azx_dev->prepared = 0;
 841         return err;
 842 }
 843
 844 static void azx_load_dsp_trigger(struct hda_bus *_bus, bool start)
 845 {
 846         struct hdac_bus *bus = &_bus->core;
 847         struct azx *chip = bus_to_azx(bus);
 848         struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
 849
 850         snd_hdac_dsp_trigger(azx_stream(azx_dev), start);
 851 }
 852
 853 static void azx_load_dsp_cleanup(struct hda_bus *_bus,
 854                                  struct snd_dma_buffer *dmab)
 855 {
 856         struct hdac_bus *bus = &_bus->core;
 857         struct azx *chip = bus_to_azx(bus);
 858         struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
 859         struct hdac_stream *hstr = azx_stream(azx_dev);
 860
 861         if (!dmab->area || !azx_dev->core.locked)
 862                 return;
 863
 864         snd_hdac_dsp_cleanup(hstr, dmab);
 865         spin_lock_irq(&bus->reg_lock);
 866         if (hstr->opened)
 867                 *azx_dev = chip->saved_azx_dev;
 868         hstr->locked = false;
 869         spin_unlock_irq(&bus->reg_lock);
 870 }
 871 #endif /* CONFIG_SND_HDA_DSP_LOADER */
 872
 873 /*
 874  * reset and start the controller registers
 875  */
 876 void azx_init_chip(struct azx *chip, bool full_reset)
 877 {
 878         if (snd_hdac_bus_init_chip(azx_bus(chip), full_reset)) {
 879                 /* correct RINTCNT for CXT */
 880                 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
 881                         azx_writew(chip, RINTCNT, 0xc0);
 882         }
 883 }
 884 EXPORT_SYMBOL_GPL(azx_init_chip);
 885
 886 void azx_stop_all_streams(struct azx *chip)
 887 {
 888         struct hdac_bus *bus = azx_bus(chip);
 889         struct hdac_stream *s;
 890
 891         list_for_each_entry(s, &bus->stream_list, list)
 892                 snd_hdac_stream_stop(s);
 893 }
 894 EXPORT_SYMBOL_GPL(azx_stop_all_streams);
 895
 896 void azx_stop_chip(struct azx *chip)
 897 {
 898         snd_hdac_bus_stop_chip(azx_bus(chip));
 899 }
 900 EXPORT_SYMBOL_GPL(azx_stop_chip);
 901
 902 /*
 903  * interrupt handler
 904  */
 905 static void stream_update(struct hdac_bus *bus, struct hdac_stream *s)
 906 {
 907         struct azx *chip = bus_to_azx(bus);
 908         struct azx_dev *azx_dev = stream_to_azx_dev(s);
 909
 910         /* check whether this IRQ is really acceptable */
 911         if (!chip->ops->position_check ||
 912             chip->ops->position_check(chip, azx_dev)) {
 913                 spin_unlock(&bus->reg_lock);
 914                 snd_pcm_period_elapsed(azx_stream(azx_dev)->substream);
 915                 spin_lock(&bus->reg_lock);
 916         }
 917 }
 918
 919 irqreturn_t azx_interrupt(int irq, void *dev_id)
 920 {
 921         struct azx *chip = dev_id;
 922         struct hdac_bus *bus = azx_bus(chip);
 923         u32 status;
 924
 925 #ifdef CONFIG_PM
 926         if (azx_has_pm_runtime(chip))
 927                 if (!pm_runtime_active(chip->card->dev))
 928                         return IRQ_NONE;
 929 #endif
 930
 931         spin_lock(&bus->reg_lock);
 932
 933         if (chip->disabled) {
 934                 spin_unlock(&bus->reg_lock);
 935                 return IRQ_NONE;
 936         }
 937
 938         status = azx_readl(chip, INTSTS);
 939         if (status == 0 || status == 0xffffffff) {
 940                 spin_unlock(&bus->reg_lock);
 941                 return IRQ_NONE;
 942         }
 943
 944         snd_hdac_bus_handle_stream_irq(bus, status, stream_update);
 945
 946         /* clear rirb int */
 947         status = azx_readb(chip, RIRBSTS);
 948         if (status & RIRB_INT_MASK) {
 949                 if (status & RIRB_INT_RESPONSE) {
 950                         if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
 951                                 udelay(80);
 952                         snd_hdac_bus_update_rirb(bus);
 953                 }
 954                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
 955         }
 956
 957         spin_unlock(&bus->reg_lock);
 958
 959         return IRQ_HANDLED;
 960 }
 961 EXPORT_SYMBOL_GPL(azx_interrupt);
 962
 963 /*
 964  * Codec initerface
 965  */
 966
 967 /*
 968  * Probe the given codec address
 969  */
 970 static int probe_codec(struct azx *chip, int addr)
 971 {
 972         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
 973                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
 974         struct hdac_bus *bus = azx_bus(chip);
 975         int err;
 976         unsigned int res = -1;
 977
 978         mutex_lock(&bus->cmd_mutex);
 979         chip->probing = 1;
 980         azx_send_cmd(bus, cmd);
 981         err = azx_get_response(bus, addr, &res);
 982         chip->probing = 0;
 983         mutex_unlock(&bus->cmd_mutex);
 984         if (err < 0 || res == -1)
 985                 return -EIO;
 986         dev_dbg(chip->card->dev, "codec #%d probed OK\n", addr);
 987         return 0;
 988 }
 989
 990 static void azx_bus_reset(struct hda_bus *bus)
 991 {
 992         struct azx *chip = bus_to_azx(&bus->core);
 993
 994         bus->in_reset = 1;
 995         azx_stop_chip(chip);
 996         azx_init_chip(chip, true);
 997         if (bus->core.chip_init)
 998                 snd_hda_bus_reset(bus);
 999         bus->in_reset = 0;
1000 }
1001
1002 static int get_jackpoll_interval(struct azx *chip)
1003 {
1004         int i;
1005         unsigned int j;
1006
1007         if (!chip->jackpoll_ms)
1008                 return 0;
1009
1010         i = chip->jackpoll_ms[chip->dev_index];
1011         if (i == 0)
1012                 return 0;
1013         if (i < 50 || i > 60000)
1014                 j = 0;
1015         else
1016                 j = msecs_to_jiffies(i);
1017         if (j == 0)
1018                 dev_warn(chip->card->dev,
1019                          "jackpoll_ms value out of range: %d\n", i);
1020         return j;
1021 }
1022
1023 static struct hda_bus_ops bus_ops = {
1024         .attach_pcm = azx_attach_pcm_stream,
1025         .bus_reset = azx_bus_reset,
1026 #ifdef CONFIG_SND_HDA_DSP_LOADER
1027         .load_dsp_prepare = azx_load_dsp_prepare,
1028         .load_dsp_trigger = azx_load_dsp_trigger,
1029         .load_dsp_cleanup = azx_load_dsp_cleanup,
1030 #endif
1031 };
1032
1033 /* HD-audio bus initialization */
1034 int azx_bus_init(struct azx *chip, const char *model,
1035                  const struct hdac_io_ops *io_ops)
1036 {
1037         struct hda_bus *bus = &chip->bus;
1038         int err;
1039
1040         err = snd_hdac_bus_init(&bus->core, chip->card->dev, &bus_core_ops,
1041                                 io_ops);
1042         if (err < 0)
1043                 return err;
1044
1045         bus->card = chip->card;
1046         mutex_init(&bus->prepare_mutex);
1047         bus->pci = chip->pci;
1048         bus->modelname = model;
1049         bus->ops = bus_ops;
1050         bus->core.snoop = azx_snoop(chip);
1051         if (chip->get_position[0] != azx_get_pos_lpib ||
1052             chip->get_position[1] != azx_get_pos_lpib)
1053                 bus->core.use_posbuf = true;
1054         if (chip->bdl_pos_adj)
1055                 bus->core.bdl_pos_adj = chip->bdl_pos_adj[chip->dev_index];
1056         if (chip->driver_caps & AZX_DCAPS_CORBRP_SELF_CLEAR)
1057                 bus->core.corbrp_self_clear = true;
1058
1059         if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1060                 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1061                 bus->needs_damn_long_delay = 1;
1062         }
1063
1064         /* AMD chipsets often cause the communication stalls upon certain
1065          * sequence like the pin-detection.  It seems that forcing the synced
1066          * access works around the stall.  Grrr...
1067          */
1068         if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1069                 dev_dbg(chip->card->dev, "Enable sync_write for stable communication\n");
1070                 bus->core.sync_write = 1;
1071                 bus->allow_bus_reset = 1;
1072         }
1073
1074         return 0;
1075 }
1076 EXPORT_SYMBOL_GPL(azx_bus_init);
1077
1078 /* Probe codecs */
1079 int azx_probe_codecs(struct azx *chip, unsigned int max_slots)
1080 {
1081         struct hdac_bus *bus = azx_bus(chip);
1082         int c, codecs, err;
1083
1084         codecs = 0;
1085         if (!max_slots)
1086                 max_slots = AZX_DEFAULT_CODECS;
1087
1088         /* First try to probe all given codec slots */
1089         for (c = 0; c < max_slots; c++) {
1090                 if ((bus->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1091                         if (probe_codec(chip, c) < 0) {
1092                                 /* Some BIOSen give you wrong codec addresses
1093                                  * that don't exist
1094                                  */
1095                                 dev_warn(chip->card->dev,
1096                                          "Codec #%d probe error; disabling it...\n", c);
1097                                 bus->codec_mask &= ~(1 << c);
1098                                 /* More badly, accessing to a non-existing
1099                                  * codec often screws up the controller chip,
1100                                  * and disturbs the further communications.
1101                                  * Thus if an error occurs during probing,
1102                                  * better to reset the controller chip to
1103                                  * get back to the sanity state.
1104                                  */
1105                                 azx_stop_chip(chip);
1106                                 azx_init_chip(chip, true);
1107                         }
1108                 }
1109         }
1110
1111         /* Then create codec instances */
1112         for (c = 0; c < max_slots; c++) {
1113                 if ((bus->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1114                         struct hda_codec *codec;
1115                         err = snd_hda_codec_new(&chip->bus, chip->card, c, &codec);
1116                         if (err < 0)
1117                                 continue;
1118                         codec->jackpoll_interval = get_jackpoll_interval(chip);
1119                         codec->beep_mode = chip->beep_mode;
1120                         codecs++;
1121                 }
1122         }
1123         if (!codecs) {
1124                 dev_err(chip->card->dev, "no codecs initialized\n");
1125                 return -ENXIO;
1126         }
1127         return 0;
1128 }
1129 EXPORT_SYMBOL_GPL(azx_probe_codecs);
1130
1131 /* configure each codec instance */
1132 int azx_codec_configure(struct azx *chip)
1133 {
1134         struct hda_codec *codec;
1135         list_for_each_codec(codec, &chip->bus) {
1136                 snd_hda_codec_configure(codec);
1137         }
1138         return 0;
1139 }
1140 EXPORT_SYMBOL_GPL(azx_codec_configure);
1141
1142 static int stream_direction(struct azx *chip, unsigned char index)
1143 {
1144         if (index >= chip->capture_index_offset &&
1145             index < chip->capture_index_offset + chip->capture_streams)
1146                 return SNDRV_PCM_STREAM_CAPTURE;
1147         return SNDRV_PCM_STREAM_PLAYBACK;
1148 }
1149
1150 /* initialize SD streams */
1151 int azx_init_streams(struct azx *chip)
1152 {
1153         int i;
1154         int stream_tags[2] = { 0, 0 };
1155
1156         /* initialize each stream (aka device)
1157          * assign the starting bdl address to each stream (device)
1158          * and initialize
1159          */
1160         for (i = 0; i < chip->num_streams; i++) {
1161                 struct azx_dev *azx_dev = kzalloc(sizeof(*azx_dev), GFP_KERNEL);
1162                 int dir, tag;
1163
1164                 if (!azx_dev)
1165                         return -ENOMEM;
1166
1167                 dir = stream_direction(chip, i);
1168                 /* stream tag must be unique throughout
1169                  * the stream direction group,
1170                  * valid values 1...15
1171                  * use separate stream tag if the flag
1172                  * AZX_DCAPS_SEPARATE_STREAM_TAG is used
1173                  */
1174                 if (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG)
1175                         tag = ++stream_tags[dir];
1176                 else
1177                         tag = i + 1;
1178                 snd_hdac_stream_init(azx_bus(chip), azx_stream(azx_dev),
1179                                      i, dir, tag);
1180         }
1181
1182         return 0;
1183 }
1184 EXPORT_SYMBOL_GPL(azx_init_streams);
1185
1186 void azx_free_streams(struct azx *chip)
1187 {
1188         struct hdac_bus *bus = azx_bus(chip);
1189         struct hdac_stream *s;
1190
1191         while (!list_empty(&bus->stream_list)) {
1192                 s = list_first_entry(&bus->stream_list, struct hdac_stream, list);
1193                 list_del(&s->list);
1194                 kfree(stream_to_azx_dev(s));
1195         }
1196 }
1197 EXPORT_SYMBOL_GPL(azx_free_streams);