sound/firewire/dice.c

   1 /*
   2  * TC Applied Technologies Digital Interface Communications Engine driver
   3  *
   4  * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
   5  * Licensed under the terms of the GNU General Public License, version 2.
   6  */
   7
   8 #include <linux/compat.h>
   9 #include <linux/completion.h>
  10 #include <linux/delay.h>
  11 #include <linux/device.h>
  12 #include <linux/firewire.h>
  13 #include <linux/firewire-constants.h>
  14 #include <linux/jiffies.h>
  15 #include <linux/module.h>
  16 #include <linux/mod_devicetable.h>
  17 #include <linux/mutex.h>
  18 #include <linux/slab.h>
  19 #include <linux/spinlock.h>
  20 #include <linux/wait.h>
  21 #include <sound/control.h>
  22 #include <sound/core.h>
  23 #include <sound/firewire.h>
  24 #include <sound/hwdep.h>
  25 #include <sound/initval.h>
  26 #include <sound/pcm.h>
  27 #include <sound/pcm_params.h>
  28 #include "amdtp.h"
  29 #include "iso-resources.h"
  30 #include "lib.h"
  31 #include "dice-interface.h"
  32
  33
  34 struct dice {
  35         struct snd_card *card;
  36         struct fw_unit *unit;
  37         spinlock_t lock;
  38         struct mutex mutex;
  39         unsigned int global_offset;
  40         unsigned int rx_offset;
  41         unsigned int clock_caps;
  42         unsigned int rx_channels[3];
  43         unsigned int rx_midi_ports[3];
  44         struct fw_address_handler notification_handler;
  45         int owner_generation;
  46         int dev_lock_count; /* > 0 driver, < 0 userspace */
  47         bool dev_lock_changed;
  48         bool global_enabled;
  49         struct completion clock_accepted;
  50         wait_queue_head_t hwdep_wait;
  51         u32 notification_bits;
  52         struct fw_iso_resources resources;
  53         struct amdtp_out_stream stream;
  54 };
  55
  56 MODULE_DESCRIPTION("DICE driver");
  57 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
  58 MODULE_LICENSE("GPL v2");
  59
  60 static const unsigned int dice_rates[] = {
  61         /* mode 0 */
  62         [0] =  32000,
  63         [1] =  44100,
  64         [2] =  48000,
  65         /* mode 1 */
  66         [3] =  88200,
  67         [4] =  96000,
  68         /* mode 2 */
  69         [5] = 176400,
  70         [6] = 192000,
  71 };
  72
  73 static unsigned int rate_to_index(unsigned int rate)
  74 {
  75         unsigned int i;
  76
  77         for (i = 0; i < ARRAY_SIZE(dice_rates); ++i)
  78                 if (dice_rates[i] == rate)
  79                         return i;
  80
  81         return 0;
  82 }
  83
  84 static unsigned int rate_index_to_mode(unsigned int rate_index)
  85 {
  86         return ((int)rate_index - 1) / 2;
  87 }
  88
  89 static void dice_lock_changed(struct dice *dice)
  90 {
  91         dice->dev_lock_changed = true;
  92         wake_up(&dice->hwdep_wait);
  93 }
  94
  95 static int dice_try_lock(struct dice *dice)
  96 {
  97         int err;
  98
  99         spin_lock_irq(&dice->lock);
 100
 101         if (dice->dev_lock_count < 0) {
 102                 err = -EBUSY;
 103                 goto out;
 104         }
 105
 106         if (dice->dev_lock_count++ == 0)
 107                 dice_lock_changed(dice);
 108         err = 0;
 109
 110 out:
 111         spin_unlock_irq(&dice->lock);
 112
 113         return err;
 114 }
 115
 116 static void dice_unlock(struct dice *dice)
 117 {
 118         spin_lock_irq(&dice->lock);
 119
 120         if (WARN_ON(dice->dev_lock_count <= 0))
 121                 goto out;
 122
 123         if (--dice->dev_lock_count == 0)
 124                 dice_lock_changed(dice);
 125
 126 out:
 127         spin_unlock_irq(&dice->lock);
 128 }
 129
 130 static inline u64 global_address(struct dice *dice, unsigned int offset)
 131 {
 132         return DICE_PRIVATE_SPACE + dice->global_offset + offset;
 133 }
 134
 135 // TODO: rx index
 136 static inline u64 rx_address(struct dice *dice, unsigned int offset)
 137 {
 138         return DICE_PRIVATE_SPACE + dice->rx_offset + offset;
 139 }
 140
 141 static int dice_owner_set(struct dice *dice)
 142 {
 143         struct fw_device *device = fw_parent_device(dice->unit);
 144         __be64 *buffer;
 145         int err, errors = 0;
 146
 147         buffer = kmalloc(2 * 8, GFP_KERNEL);
 148         if (!buffer)
 149                 return -ENOMEM;
 150
 151         for (;;) {
 152                 buffer[0] = cpu_to_be64(OWNER_NO_OWNER);
 153                 buffer[1] = cpu_to_be64(
 154                         ((u64)device->card->node_id << OWNER_NODE_SHIFT) |
 155                         dice->notification_handler.offset);
 156
 157                 dice->owner_generation = device->generation;
 158                 smp_rmb(); /* node_id vs. generation */
 159                 err = snd_fw_transaction(dice->unit,
 160                                          TCODE_LOCK_COMPARE_SWAP,
 161                                          global_address(dice, GLOBAL_OWNER),
 162                                          buffer, 2 * 8,
 163                                          FW_FIXED_GENERATION |
 164                                                         dice->owner_generation);
 165
 166                 if (err == 0) {
 167                         if (buffer[0] != cpu_to_be64(OWNER_NO_OWNER)) {
 168                                 dev_err(&dice->unit->device,
 169                                         "device is already in use\n");
 170                                 err = -EBUSY;
 171                         }
 172                         break;
 173                 }
 174                 if (err != -EAGAIN || ++errors >= 3)
 175                         break;
 176
 177                 msleep(20);
 178         }
 179
 180         kfree(buffer);
 181
 182         return err;
 183 }
 184
 185 static int dice_owner_update(struct dice *dice)
 186 {
 187         struct fw_device *device = fw_parent_device(dice->unit);
 188         __be64 *buffer;
 189         int err;
 190
 191         if (dice->owner_generation == -1)
 192                 return 0;
 193
 194         buffer = kmalloc(2 * 8, GFP_KERNEL);
 195         if (!buffer)
 196                 return -ENOMEM;
 197
 198         buffer[0] = cpu_to_be64(OWNER_NO_OWNER);
 199         buffer[1] = cpu_to_be64(
 200                 ((u64)device->card->node_id << OWNER_NODE_SHIFT) |
 201                 dice->notification_handler.offset);
 202
 203         dice->owner_generation = device->generation;
 204         smp_rmb(); /* node_id vs. generation */
 205         err = snd_fw_transaction(dice->unit, TCODE_LOCK_COMPARE_SWAP,
 206                                  global_address(dice, GLOBAL_OWNER),
 207                                  buffer, 2 * 8,
 208                                  FW_FIXED_GENERATION | dice->owner_generation);
 209
 210         if (err == 0) {
 211                 if (buffer[0] != cpu_to_be64(OWNER_NO_OWNER)) {
 212                         dev_err(&dice->unit->device,
 213                                 "device is already in use\n");
 214                         err = -EBUSY;
 215                 }
 216         } else if (err == -EAGAIN) {
 217                 err = 0; /* try again later */
 218         }
 219
 220         kfree(buffer);
 221
 222         if (err < 0)
 223                 dice->owner_generation = -1;
 224
 225         return err;
 226 }
 227
 228 static void dice_owner_clear(struct dice *dice)
 229 {
 230         struct fw_device *device = fw_parent_device(dice->unit);
 231         __be64 *buffer;
 232
 233         buffer = kmalloc(2 * 8, GFP_KERNEL);
 234         if (!buffer)
 235                 return;
 236
 237         buffer[0] = cpu_to_be64(
 238                 ((u64)device->card->node_id << OWNER_NODE_SHIFT) |
 239                 dice->notification_handler.offset);
 240         buffer[1] = cpu_to_be64(OWNER_NO_OWNER);
 241         snd_fw_transaction(dice->unit, TCODE_LOCK_COMPARE_SWAP,
 242                            global_address(dice, GLOBAL_OWNER),
 243                            buffer, 2 * 8, FW_QUIET |
 244                            FW_FIXED_GENERATION | dice->owner_generation);
 245
 246         kfree(buffer);
 247
 248         dice->owner_generation = -1;
 249 }
 250
 251 static int dice_enable_set(struct dice *dice)
 252 {
 253         __be32 value;
 254         int err;
 255
 256         value = cpu_to_be32(1);
 257         err = snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
 258                                  global_address(dice, GLOBAL_ENABLE),
 259                                  &value, 4,
 260                                  FW_FIXED_GENERATION | dice->owner_generation);
 261         if (err < 0)
 262                 return err;
 263
 264         dice->global_enabled = true;
 265
 266         return 0;
 267 }
 268
 269 static void dice_enable_clear(struct dice *dice)
 270 {
 271         __be32 value;
 272
 273         if (!dice->global_enabled)
 274                 return;
 275
 276         value = 0;
 277         snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
 278                            global_address(dice, GLOBAL_ENABLE),
 279                            &value, 4, FW_QUIET |
 280                            FW_FIXED_GENERATION | dice->owner_generation);
 281
 282         dice->global_enabled = false;
 283 }
 284
 285 static void dice_notification(struct fw_card *card, struct fw_request *request,
 286                               int tcode, int destination, int source,
 287                               int generation, unsigned long long offset,
 288                               void *data, size_t length, void *callback_data)
 289 {
 290         struct dice *dice = callback_data;
 291         u32 bits;
 292         unsigned long flags;
 293
 294         if (tcode != TCODE_WRITE_QUADLET_REQUEST) {
 295                 fw_send_response(card, request, RCODE_TYPE_ERROR);
 296                 return;
 297         }
 298         if ((offset & 3) != 0) {
 299                 fw_send_response(card, request, RCODE_ADDRESS_ERROR);
 300                 return;
 301         }
 302
 303         bits = be32_to_cpup(data);
 304
 305         spin_lock_irqsave(&dice->lock, flags);
 306         dice->notification_bits |= bits;
 307         spin_unlock_irqrestore(&dice->lock, flags);
 308
 309         fw_send_response(card, request, RCODE_COMPLETE);
 310
 311         if (bits & NOTIFY_CLOCK_ACCEPTED)
 312                 complete(&dice->clock_accepted);
 313         wake_up(&dice->hwdep_wait);
 314 }
 315
 316 static int dice_rate_constraint(struct snd_pcm_hw_params *params,
 317                                 struct snd_pcm_hw_rule *rule)
 318 {
 319         struct dice *dice = rule->private;
 320         const struct snd_interval *channels =
 321                 hw_param_interval_c(params, SNDRV_PCM_HW_PARAM_CHANNELS);
 322         struct snd_interval *rate =
 323                 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
 324         struct snd_interval allowed_rates = {
 325                 .min = UINT_MAX, .max = 0, .integer = 1
 326         };
 327         unsigned int i, mode;
 328
 329         for (i = 0; i < ARRAY_SIZE(dice_rates); ++i) {
 330                 mode = rate_index_to_mode(i);
 331                 if ((dice->clock_caps & (1 << i)) &&
 332                     snd_interval_test(channels, dice->rx_channels[mode])) {
 333                         allowed_rates.min = min(allowed_rates.min,
 334                                                 dice_rates[i]);
 335                         allowed_rates.max = max(allowed_rates.max,
 336                                                 dice_rates[i]);
 337                 }
 338         }
 339
 340         return snd_interval_refine(rate, &allowed_rates);
 341 }
 342
 343 static int dice_channels_constraint(struct snd_pcm_hw_params *params,
 344                                     struct snd_pcm_hw_rule *rule)
 345 {
 346         struct dice *dice = rule->private;
 347         const struct snd_interval *rate =
 348                 hw_param_interval_c(params, SNDRV_PCM_HW_PARAM_RATE);
 349         struct snd_interval *channels =
 350                 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
 351         struct snd_interval allowed_channels = {
 352                 .min = UINT_MAX, .max = 0, .integer = 1
 353         };
 354         unsigned int i, mode;
 355
 356         for (i = 0; i < ARRAY_SIZE(dice_rates); ++i)
 357                 if ((dice->clock_caps & (1 << i)) &&
 358                     snd_interval_test(rate, dice_rates[i])) {
 359                         mode = rate_index_to_mode(i);
 360                         allowed_channels.min = min(allowed_channels.min,
 361                                                    dice->rx_channels[mode]);
 362                         allowed_channels.max = max(allowed_channels.max,
 363                                                    dice->rx_channels[mode]);
 364                 }
 365
 366         return snd_interval_refine(channels, &allowed_channels);
 367 }
 368
 369 static int dice_open(struct snd_pcm_substream *substream)
 370 {
 371         static const struct snd_pcm_hardware hardware = {
 372                 .info = SNDRV_PCM_INFO_MMAP |
 373                         SNDRV_PCM_INFO_MMAP_VALID |
 374                         SNDRV_PCM_INFO_BATCH |
 375                         SNDRV_PCM_INFO_INTERLEAVED |
 376                         SNDRV_PCM_INFO_BLOCK_TRANSFER,
 377                 .formats = AMDTP_OUT_PCM_FORMAT_BITS,
 378                 .channels_min = UINT_MAX,
 379                 .channels_max = 0,
 380                 .buffer_bytes_max = 16 * 1024 * 1024,
 381                 .period_bytes_min = 1,
 382                 .period_bytes_max = UINT_MAX,
 383                 .periods_min = 1,
 384                 .periods_max = UINT_MAX,
 385         };
 386         struct dice *dice = substream->private_data;
 387         struct snd_pcm_runtime *runtime = substream->runtime;
 388         unsigned int i;
 389         int err;
 390
 391         err = dice_try_lock(dice);
 392         if (err < 0)
 393                 goto error;
 394
 395         runtime->hw = hardware;
 396
 397         for (i = 0; i < ARRAY_SIZE(dice_rates); ++i)
 398                 if (dice->clock_caps & (1 << i))
 399                         runtime->hw.rates |=
 400                                 snd_pcm_rate_to_rate_bit(dice_rates[i]);
 401         snd_pcm_limit_hw_rates(runtime);
 402
 403         for (i = 0; i < 3; ++i)
 404                 if (dice->rx_channels[i]) {
 405                         runtime->hw.channels_min = min(runtime->hw.channels_min,
 406                                                        dice->rx_channels[i]);
 407                         runtime->hw.channels_max = max(runtime->hw.channels_max,
 408                                                        dice->rx_channels[i]);
 409                 }
 410
 411         err = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
 412                                   dice_rate_constraint, dice,
 413                                   SNDRV_PCM_HW_PARAM_CHANNELS, -1);
 414         if (err < 0)
 415                 goto err_lock;
 416         err = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
 417                                   dice_channels_constraint, dice,
 418                                   SNDRV_PCM_HW_PARAM_RATE, -1);
 419         if (err < 0)
 420                 goto err_lock;
 421
 422         err = snd_pcm_hw_constraint_step(runtime, 0,
 423                                          SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 32);
 424         if (err < 0)
 425                 goto err_lock;
 426         err = snd_pcm_hw_constraint_step(runtime, 0,
 427                                          SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 32);
 428         if (err < 0)
 429                 goto err_lock;
 430
 431         err = snd_pcm_hw_constraint_minmax(runtime,
 432                                            SNDRV_PCM_HW_PARAM_PERIOD_TIME,
 433                                            5000, UINT_MAX);
 434         if (err < 0)
 435                 goto err_lock;
 436
 437         err = snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
 438         if (err < 0)
 439                 goto err_lock;
 440
 441         return 0;
 442
 443 err_lock:
 444         dice_unlock(dice);
 445 error:
 446         return err;
 447 }
 448
 449 static int dice_close(struct snd_pcm_substream *substream)
 450 {
 451         struct dice *dice = substream->private_data;
 452
 453         dice_unlock(dice);
 454
 455         return 0;
 456 }
 457
 458 static int dice_stream_start_packets(struct dice *dice)
 459 {
 460         int err;
 461
 462         if (amdtp_out_stream_running(&dice->stream))
 463                 return 0;
 464
 465         err = amdtp_out_stream_start(&dice->stream, dice->resources.channel,
 466                                      fw_parent_device(dice->unit)->max_speed);
 467         if (err < 0)
 468                 return err;
 469
 470         err = dice_enable_set(dice);
 471         if (err < 0) {
 472                 amdtp_out_stream_stop(&dice->stream);
 473                 return err;
 474         }
 475
 476         return 0;
 477 }
 478
 479 static int dice_stream_start(struct dice *dice)
 480 {
 481         __be32 channel;
 482         int err;
 483
 484         if (!dice->resources.allocated) {
 485                 err = fw_iso_resources_allocate(&dice->resources,
 486                                 amdtp_out_stream_get_max_payload(&dice->stream),
 487                                 fw_parent_device(dice->unit)->max_speed);
 488                 if (err < 0)
 489                         goto error;
 490
 491                 channel = cpu_to_be32(dice->resources.channel);
 492                 err = snd_fw_transaction(dice->unit,
 493                                          TCODE_WRITE_QUADLET_REQUEST,
 494                                          rx_address(dice, RX_ISOCHRONOUS),
 495                                          &channel, 4, 0);
 496                 if (err < 0)
 497                         goto err_resources;
 498         }
 499
 500         err = dice_stream_start_packets(dice);
 501         if (err < 0)
 502                 goto err_rx_channel;
 503
 504         return 0;
 505
 506 err_rx_channel:
 507         channel = cpu_to_be32((u32)-1);
 508         snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
 509                            rx_address(dice, RX_ISOCHRONOUS), &channel, 4, 0);
 510 err_resources:
 511         fw_iso_resources_free(&dice->resources);
 512 error:
 513         return err;
 514 }
 515
 516 static void dice_stream_stop_packets(struct dice *dice)
 517 {
 518         if (amdtp_out_stream_running(&dice->stream)) {
 519                 dice_enable_clear(dice);
 520                 amdtp_out_stream_stop(&dice->stream);
 521         }
 522 }
 523
 524 static void dice_stream_stop(struct dice *dice)
 525 {
 526         __be32 channel;
 527
 528         dice_stream_stop_packets(dice);
 529
 530         if (!dice->resources.allocated)
 531                 return;
 532
 533         channel = cpu_to_be32((u32)-1);
 534         snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
 535                            rx_address(dice, RX_ISOCHRONOUS), &channel, 4, 0);
 536
 537         fw_iso_resources_free(&dice->resources);
 538 }
 539
 540 static int dice_change_rate(struct dice *dice, unsigned int clock_rate)
 541 {
 542         __be32 value;
 543         int err;
 544
 545         INIT_COMPLETION(dice->clock_accepted);
 546
 547         value = cpu_to_be32(clock_rate | CLOCK_SOURCE_ARX1);
 548         err = snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
 549                                  global_address(dice, GLOBAL_CLOCK_SELECT),
 550                                  &value, 4, 0);
 551         if (err < 0)
 552                 return err;
 553
 554         wait_for_completion_timeout(&dice->clock_accepted,
 555                                     msecs_to_jiffies(100));
 556
 557         return 0;
 558 }
 559
 560 static int dice_hw_params(struct snd_pcm_substream *substream,
 561                           struct snd_pcm_hw_params *hw_params)
 562 {
 563         struct dice *dice = substream->private_data;
 564         unsigned int rate_index, mode;
 565         int err;
 566
 567         mutex_lock(&dice->mutex);
 568         dice_stream_stop(dice);
 569         mutex_unlock(&dice->mutex);
 570
 571         err = snd_pcm_lib_alloc_vmalloc_buffer(substream,
 572                                                params_buffer_bytes(hw_params));
 573         if (err < 0)
 574                 return err;
 575
 576         rate_index = rate_to_index(params_rate(hw_params));
 577         err = dice_change_rate(dice, rate_index << CLOCK_RATE_SHIFT);
 578         if (err < 0)
 579                 return err;
 580
 581         mode = rate_index_to_mode(rate_index);
 582         amdtp_out_stream_set_parameters(&dice->stream,
 583                                         params_rate(hw_params),
 584                                         params_channels(hw_params),
 585                                         dice->rx_midi_ports[mode]);
 586         amdtp_out_stream_set_pcm_format(&dice->stream,
 587                                         params_format(hw_params));
 588
 589         return 0;
 590 }
 591
 592 static int dice_hw_free(struct snd_pcm_substream *substream)
 593 {
 594         struct dice *dice = substream->private_data;
 595
 596         mutex_lock(&dice->mutex);
 597         dice_stream_stop(dice);
 598         mutex_unlock(&dice->mutex);
 599
 600         return snd_pcm_lib_free_vmalloc_buffer(substream);
 601 }
 602
 603 static int dice_prepare(struct snd_pcm_substream *substream)
 604 {
 605         struct dice *dice = substream->private_data;
 606         int err;
 607
 608         mutex_lock(&dice->mutex);
 609
 610         if (amdtp_out_streaming_error(&dice->stream))
 611                 dice_stream_stop_packets(dice);
 612
 613         err = dice_stream_start(dice);
 614         if (err < 0) {
 615                 mutex_unlock(&dice->mutex);
 616                 return err;
 617         }
 618
 619         mutex_unlock(&dice->mutex);
 620
 621         amdtp_out_stream_pcm_prepare(&dice->stream);
 622
 623         return 0;
 624 }
 625
 626 static int dice_trigger(struct snd_pcm_substream *substream, int cmd)
 627 {
 628         struct dice *dice = substream->private_data;
 629         struct snd_pcm_substream *pcm;
 630
 631         switch (cmd) {
 632         case SNDRV_PCM_TRIGGER_START:
 633                 pcm = substream;
 634                 break;
 635         case SNDRV_PCM_TRIGGER_STOP:
 636                 pcm = NULL;
 637                 break;
 638         default:
 639                 return -EINVAL;
 640         }
 641         amdtp_out_stream_pcm_trigger(&dice->stream, pcm);
 642
 643         return 0;
 644 }
 645
 646 static snd_pcm_uframes_t dice_pointer(struct snd_pcm_substream *substream)
 647 {
 648         struct dice *dice = substream->private_data;
 649
 650         return amdtp_out_stream_pcm_pointer(&dice->stream);
 651 }
 652
 653 static int dice_create_pcm(struct dice *dice)
 654 {
 655         static struct snd_pcm_ops ops = {
 656                 .open      = dice_open,
 657                 .close     = dice_close,
 658                 .ioctl     = snd_pcm_lib_ioctl,
 659                 .hw_params = dice_hw_params,
 660                 .hw_free   = dice_hw_free,
 661                 .prepare   = dice_prepare,
 662                 .trigger   = dice_trigger,
 663                 .pointer   = dice_pointer,
 664                 .page      = snd_pcm_lib_get_vmalloc_page,
 665                 .mmap      = snd_pcm_lib_mmap_vmalloc,
 666         };
 667         struct snd_pcm *pcm;
 668         int err;
 669
 670         err = snd_pcm_new(dice->card, "DICE", 0, 1, 0, &pcm);
 671         if (err < 0)
 672                 return err;
 673         pcm->private_data = dice;
 674         strcpy(pcm->name, dice->card->shortname);
 675         pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream->ops = &ops;
 676
 677         return 0;
 678 }
 679
 680 static long dice_hwdep_read(struct snd_hwdep *hwdep, char __user *buf,
 681                             long count, loff_t *offset)
 682 {
 683         struct dice *dice = hwdep->private_data;
 684         DEFINE_WAIT(wait);
 685         union snd_firewire_event event;
 686
 687         spin_lock_irq(&dice->lock);
 688
 689         while (!dice->dev_lock_changed && dice->notification_bits == 0) {
 690                 prepare_to_wait(&dice->hwdep_wait, &wait, TASK_INTERRUPTIBLE);
 691                 spin_unlock_irq(&dice->lock);
 692                 schedule();
 693                 finish_wait(&dice->hwdep_wait, &wait);
 694                 if (signal_pending(current))
 695                         return -ERESTARTSYS;
 696                 spin_lock_irq(&dice->lock);
 697         }
 698
 699         memset(&event, 0, sizeof(event));
 700         if (dice->dev_lock_changed) {
 701                 event.lock_status.type = SNDRV_FIREWIRE_EVENT_LOCK_STATUS;
 702                 event.lock_status.status = dice->dev_lock_count > 0;
 703                 dice->dev_lock_changed = false;
 704
 705                 count = min(count, (long)sizeof(event.lock_status));
 706         } else {
 707                 event.dice_notification.type = SNDRV_FIREWIRE_EVENT_DICE_NOTIFICATION;
 708                 event.dice_notification.notification = dice->notification_bits;
 709                 dice->notification_bits = 0;
 710
 711                 count = min(count, (long)sizeof(event.dice_notification));
 712         }
 713
 714         spin_unlock_irq(&dice->lock);
 715
 716         if (copy_to_user(buf, &event, count))
 717                 return -EFAULT;
 718
 719         return count;
 720 }
 721
 722 static unsigned int dice_hwdep_poll(struct snd_hwdep *hwdep, struct file *file,
 723                                     poll_table *wait)
 724 {
 725         struct dice *dice = hwdep->private_data;
 726         unsigned int events;
 727
 728         poll_wait(file, &dice->hwdep_wait, wait);
 729
 730         spin_lock_irq(&dice->lock);
 731         if (dice->dev_lock_changed || dice->notification_bits != 0)
 732                 events = POLLIN | POLLRDNORM;
 733         else
 734                 events = 0;
 735         spin_unlock_irq(&dice->lock);
 736
 737         return events;
 738 }
 739
 740 static int dice_hwdep_get_info(struct dice *dice, void __user *arg)
 741 {
 742         struct fw_device *dev = fw_parent_device(dice->unit);
 743         struct snd_firewire_get_info info;
 744
 745         memset(&info, 0, sizeof(info));
 746         info.type = SNDRV_FIREWIRE_TYPE_DICE;
 747         info.card = dev->card->index;
 748         *(__be32 *)&info.guid[0] = cpu_to_be32(dev->config_rom[3]);
 749         *(__be32 *)&info.guid[4] = cpu_to_be32(dev->config_rom[4]);
 750         strlcpy(info.device_name, dev_name(&dev->device),
 751                 sizeof(info.device_name));
 752
 753         if (copy_to_user(arg, &info, sizeof(info)))
 754                 return -EFAULT;
 755
 756         return 0;
 757 }
 758
 759 static int dice_hwdep_lock(struct dice *dice)
 760 {
 761         int err;
 762
 763         spin_lock_irq(&dice->lock);
 764
 765         if (dice->dev_lock_count == 0) {
 766                 dice->dev_lock_count = -1;
 767                 err = 0;
 768         } else {
 769                 err = -EBUSY;
 770         }
 771
 772         spin_unlock_irq(&dice->lock);
 773
 774         return err;
 775 }
 776
 777 static int dice_hwdep_unlock(struct dice *dice)
 778 {
 779         int err;
 780
 781         spin_lock_irq(&dice->lock);
 782
 783         if (dice->dev_lock_count == -1) {
 784                 dice->dev_lock_count = 0;
 785                 err = 0;
 786         } else {
 787                 err = -EBADFD;
 788         }
 789
 790         spin_unlock_irq(&dice->lock);
 791
 792         return err;
 793 }
 794
 795 static int dice_hwdep_release(struct snd_hwdep *hwdep, struct file *file)
 796 {
 797         struct dice *dice = hwdep->private_data;
 798
 799         spin_lock_irq(&dice->lock);
 800         if (dice->dev_lock_count == -1)
 801                 dice->dev_lock_count = 0;
 802         spin_unlock_irq(&dice->lock);
 803
 804         return 0;
 805 }
 806
 807 static int dice_hwdep_ioctl(struct snd_hwdep *hwdep, struct file *file,
 808                             unsigned int cmd, unsigned long arg)
 809 {
 810         struct dice *dice = hwdep->private_data;
 811
 812         switch (cmd) {
 813         case SNDRV_FIREWIRE_IOCTL_GET_INFO:
 814                 return dice_hwdep_get_info(dice, (void __user *)arg);
 815         case SNDRV_FIREWIRE_IOCTL_LOCK:
 816                 return dice_hwdep_lock(dice);
 817         case SNDRV_FIREWIRE_IOCTL_UNLOCK:
 818                 return dice_hwdep_unlock(dice);
 819         default:
 820                 return -ENOIOCTLCMD;
 821         }
 822 }
 823
 824 #ifdef CONFIG_COMPAT
 825 static int dice_hwdep_compat_ioctl(struct snd_hwdep *hwdep, struct file *file,
 826                                    unsigned int cmd, unsigned long arg)
 827 {
 828         return dice_hwdep_ioctl(hwdep, file, cmd,
 829                                 (unsigned long)compat_ptr(arg));
 830 }
 831 #else
 832 #define dice_hwdep_compat_ioctl NULL
 833 #endif
 834
 835 static int dice_create_hwdep(struct dice *dice)
 836 {
 837         static const struct snd_hwdep_ops ops = {
 838                 .read         = dice_hwdep_read,
 839                 .release      = dice_hwdep_release,
 840                 .poll         = dice_hwdep_poll,
 841                 .ioctl        = dice_hwdep_ioctl,
 842                 .ioctl_compat = dice_hwdep_compat_ioctl,
 843         };
 844         struct snd_hwdep *hwdep;
 845         int err;
 846
 847         err = snd_hwdep_new(dice->card, "DICE", 0, &hwdep);
 848         if (err < 0)
 849                 return err;
 850         strcpy(hwdep->name, "DICE");
 851         hwdep->iface = SNDRV_HWDEP_IFACE_FW_DICE;
 852         hwdep->ops = ops;
 853         hwdep->private_data = dice;
 854         hwdep->exclusive = true;
 855
 856         return 0;
 857 }
 858
 859 static void dice_card_free(struct snd_card *card)
 860 {
 861         struct dice *dice = card->private_data;
 862
 863         amdtp_out_stream_destroy(&dice->stream);
 864         fw_core_remove_address_handler(&dice->notification_handler);
 865         mutex_destroy(&dice->mutex);
 866 }
 867
 868 #define DICE_CATEGORY_ID 0x04
 869
 870 static int dice_interface_check(struct fw_unit *unit)
 871 {
 872         static const int min_values[10] = {
 873                 10, 0x64 / 4,
 874                 10, 0x18 / 4,
 875                 10, 0x18 / 4,
 876                 0, 0,
 877                 0, 0,
 878         };
 879         struct fw_device *device = fw_parent_device(unit);
 880         struct fw_csr_iterator it;
 881         int key, value, vendor = -1, model = -1, err;
 882         unsigned int i;
 883         __be32 pointers[ARRAY_SIZE(min_values)];
 884         __be32 version;
 885
 886         /*
 887          * Check that GUID and unit directory are constructed according to DICE
 888          * rules, i.e., that the specifier ID is the GUID's OUI, and that the
 889          * GUID chip ID consists of the 8-bit DICE category ID, the 10-bit
 890          * product ID, and a 22-bit serial number.
 891          */
 892         fw_csr_iterator_init(&it, unit->directory);
 893         while (fw_csr_iterator_next(&it, &key, &value)) {
 894                 switch (key) {
 895                 case CSR_SPECIFIER_ID:
 896                         vendor = value;
 897                         break;
 898                 case CSR_MODEL:
 899                         model = value;
 900                         break;
 901                 }
 902         }
 903         if (device->config_rom[3] != ((vendor << 8) | DICE_CATEGORY_ID) ||
 904             device->config_rom[4] >> 22 != model)
 905                 return -ENODEV;
 906
 907         /*
 908          * Check that the sub address spaces exist and are located inside the
 909          * private address space.  The minimum values are chosen so that all
 910          * minimally required registers are included.
 911          */
 912         err = snd_fw_transaction(unit, TCODE_READ_BLOCK_REQUEST,
 913                                  DICE_PRIVATE_SPACE,
 914                                  pointers, sizeof(pointers), 0);
 915         if (err < 0)
 916                 return -ENODEV;
 917         for (i = 0; i < ARRAY_SIZE(pointers); ++i) {
 918                 value = be32_to_cpu(pointers[i]);
 919                 if (value < min_values[i] || value >= 0x40000)
 920                         return -ENODEV;
 921         }
 922
 923         /*
 924          * Check that the implemented DICE driver specification major version
 925          * number matches.
 926          */
 927         err = snd_fw_transaction(unit, TCODE_READ_QUADLET_REQUEST,
 928                                  DICE_PRIVATE_SPACE +
 929                                  be32_to_cpu(pointers[0]) * 4 + GLOBAL_VERSION,
 930                                  &version, 4, 0);
 931         if (err < 0)
 932                 return -ENODEV;
 933         if ((version & cpu_to_be32(0xff000000)) != cpu_to_be32(0x01000000)) {
 934                 dev_err(&unit->device,
 935                         "unknown DICE version: 0x%08x\n", be32_to_cpu(version));
 936                 return -ENODEV;
 937         }
 938
 939         return 0;
 940 }
 941
 942 static int highest_supported_mode_rate(struct dice *dice, unsigned int mode)
 943 {
 944         int i;
 945
 946         for (i = ARRAY_SIZE(dice_rates) - 1; i >= 0; --i)
 947                 if ((dice->clock_caps & (1 << i)) &&
 948                     rate_index_to_mode(i) == mode)
 949                         return i;
 950
 951         return -1;
 952 }
 953
 954 static int dice_read_mode_params(struct dice *dice, unsigned int mode)
 955 {
 956         __be32 values[2];
 957         int rate_index, err;
 958
 959         rate_index = highest_supported_mode_rate(dice, mode);
 960         if (rate_index < 0) {
 961                 dice->rx_channels[mode] = 0;
 962                 dice->rx_midi_ports[mode] = 0;
 963                 return 0;
 964         }
 965
 966         err = dice_change_rate(dice, rate_index << CLOCK_RATE_SHIFT);
 967         if (err < 0)
 968                 return err;
 969
 970         err = snd_fw_transaction(dice->unit, TCODE_READ_BLOCK_REQUEST,
 971                                  rx_address(dice, RX_NUMBER_AUDIO),
 972                                  values, 2 * 4, 0);
 973         if (err < 0)
 974                 return err;
 975
 976         dice->rx_channels[mode]   = be32_to_cpu(values[0]);
 977         dice->rx_midi_ports[mode] = be32_to_cpu(values[1]);
 978
 979         return 0;
 980 }
 981
 982 static int dice_read_params(struct dice *dice)
 983 {
 984         __be32 pointers[6];
 985         __be32 value;
 986         int mode, err;
 987
 988         err = snd_fw_transaction(dice->unit, TCODE_READ_BLOCK_REQUEST,
 989                                  DICE_PRIVATE_SPACE,
 990                                  pointers, sizeof(pointers), 0);
 991         if (err < 0)
 992                 return err;
 993
 994         dice->global_offset = be32_to_cpu(pointers[0]) * 4;
 995         dice->rx_offset = be32_to_cpu(pointers[4]) * 4;
 996
 997         /* some very old firmwares don't tell about their clock support */
 998         if (be32_to_cpu(pointers[1]) * 4 >= GLOBAL_CLOCK_CAPABILITIES + 4) {
 999                 err = snd_fw_transaction(
1000                                 dice->unit, TCODE_READ_QUADLET_REQUEST,
1001                                 global_address(dice, GLOBAL_CLOCK_CAPABILITIES),
1002                                 &value, 4, 0);
1003                 if (err < 0)
1004                         return err;
1005                 dice->clock_caps = be32_to_cpu(value);
1006         } else {
1007                 /* this should be supported by any device */
1008                 dice->clock_caps = CLOCK_CAP_RATE_44100 |
1009                                    CLOCK_CAP_RATE_48000 |
1010                                    CLOCK_CAP_SOURCE_ARX1 |
1011                                    CLOCK_CAP_SOURCE_INTERNAL;
1012         }
1013
1014         for (mode = 2; mode >= 0; --mode) {
1015                 err = dice_read_mode_params(dice, mode);
1016                 if (err < 0)
1017                         return err;
1018         }
1019
1020         return 0;
1021 }
1022
1023 static void dice_card_strings(struct dice *dice)
1024 {
1025         struct snd_card *card = dice->card;
1026         struct fw_device *dev = fw_parent_device(dice->unit);
1027         char vendor[32], model[32];
1028         unsigned int i;
1029         int err;
1030
1031         strcpy(card->driver, "DICE");
1032
1033         strcpy(card->shortname, "DICE");
1034         BUILD_BUG_ON(NICK_NAME_SIZE < sizeof(card->shortname));
1035         err = snd_fw_transaction(dice->unit, TCODE_READ_BLOCK_REQUEST,
1036                                  global_address(dice, GLOBAL_NICK_NAME),
1037                                  card->shortname, sizeof(card->shortname), 0);
1038         if (err >= 0) {
1039                 /* DICE strings are returned in "always-wrong" endianness */
1040                 BUILD_BUG_ON(sizeof(card->shortname) % 4 != 0);
1041                 for (i = 0; i < sizeof(card->shortname); i += 4)
1042                         swab32s((u32 *)&card->shortname[i]);
1043                 card->shortname[sizeof(card->shortname) - 1] = '\0';
1044         }
1045
1046         strcpy(vendor, "?");
1047         fw_csr_string(dev->config_rom + 5, CSR_VENDOR, vendor, sizeof(vendor));
1048         strcpy(model, "?");
1049         fw_csr_string(dice->unit->directory, CSR_MODEL, model, sizeof(model));
1050         snprintf(card->longname, sizeof(card->longname),
1051                  "%s %s (serial %u) at %s, S%d",
1052                  vendor, model, dev->config_rom[4] & 0x3fffff,
1053                  dev_name(&dice->unit->device), 100 << dev->max_speed);
1054
1055         strcpy(card->mixername, "DICE");
1056 }
1057
1058 static int dice_probe(struct fw_unit *unit, const struct ieee1394_device_id *id)
1059 {
1060         struct snd_card *card;
1061         struct dice *dice;
1062         __be32 clock_sel;
1063         int err;
1064
1065         err = dice_interface_check(unit);
1066         if (err < 0)
1067                 return err;
1068
1069         err = snd_card_create(-1, NULL, THIS_MODULE, sizeof(*dice), &card);
1070         if (err < 0)
1071                 return err;
1072         snd_card_set_dev(card, &unit->device);
1073
1074         dice = card->private_data;
1075         dice->card = card;
1076         spin_lock_init(&dice->lock);
1077         mutex_init(&dice->mutex);
1078         dice->unit = unit;
1079         init_completion(&dice->clock_accepted);
1080         init_waitqueue_head(&dice->hwdep_wait);
1081
1082         dice->notification_handler.length = 4;
1083         dice->notification_handler.address_callback = dice_notification;
1084         dice->notification_handler.callback_data = dice;
1085         err = fw_core_add_address_handler(&dice->notification_handler,
1086                                           &fw_high_memory_region);
1087         if (err < 0)
1088                 goto err_mutex;
1089
1090         err = dice_owner_set(dice);
1091         if (err < 0)
1092                 goto err_notification_handler;
1093
1094         err = dice_read_params(dice);
1095         if (err < 0)
1096                 goto err_owner;
1097
1098         err = fw_iso_resources_init(&dice->resources, unit);
1099         if (err < 0)
1100                 goto err_owner;
1101         dice->resources.channels_mask = 0x00000000ffffffffuLL;
1102
1103         err = amdtp_out_stream_init(&dice->stream, unit,
1104                                     CIP_BLOCKING | CIP_HI_DUALWIRE);
1105         if (err < 0)
1106                 goto err_resources;
1107
1108         card->private_free = dice_card_free;
1109
1110         dice_card_strings(dice);
1111
1112         err = snd_fw_transaction(unit, TCODE_READ_QUADLET_REQUEST,
1113                                  global_address(dice, GLOBAL_CLOCK_SELECT),
1114                                  &clock_sel, 4, 0);
1115         if (err < 0)
1116                 goto error;
1117         clock_sel &= cpu_to_be32(~CLOCK_SOURCE_MASK);
1118         clock_sel |= cpu_to_be32(CLOCK_SOURCE_ARX1);
1119         err = snd_fw_transaction(unit, TCODE_WRITE_QUADLET_REQUEST,
1120                                  global_address(dice, GLOBAL_CLOCK_SELECT),
1121                                  &clock_sel, 4, 0);
1122         if (err < 0)
1123                 goto error;
1124
1125         err = dice_create_pcm(dice);
1126         if (err < 0)
1127                 goto error;
1128
1129         err = dice_create_hwdep(dice);
1130         if (err < 0)
1131                 goto error;
1132
1133         err = snd_card_register(card);
1134         if (err < 0)
1135                 goto error;
1136
1137         dev_set_drvdata(&unit->device, dice);
1138
1139         return 0;
1140
1141 err_resources:
1142         fw_iso_resources_destroy(&dice->resources);
1143 err_owner:
1144         dice_owner_clear(dice);
1145 err_notification_handler:
1146         fw_core_remove_address_handler(&dice->notification_handler);
1147 err_mutex:
1148         mutex_destroy(&dice->mutex);
1149 error:
1150         snd_card_free(card);
1151         return err;
1152 }
1153
1154 static void dice_remove(struct fw_unit *unit)
1155 {
1156         struct dice *dice = dev_get_drvdata(&unit->device);
1157
1158         amdtp_out_stream_pcm_abort(&dice->stream);
1159
1160         snd_card_disconnect(dice->card);
1161
1162         mutex_lock(&dice->mutex);
1163
1164         dice_stream_stop(dice);
1165         dice_owner_clear(dice);
1166
1167         mutex_unlock(&dice->mutex);
1168
1169         snd_card_free_when_closed(dice->card);
1170 }
1171
1172 static void dice_bus_reset(struct fw_unit *unit)
1173 {
1174         struct dice *dice = dev_get_drvdata(&unit->device);
1175
1176         /*
1177          * On a bus reset, the DICE firmware disables streaming and then goes
1178          * off contemplating its own navel for hundreds of milliseconds before
1179          * it can react to any of our attempts to reenable streaming.  This
1180          * means that we lose synchronization anyway, so we force our streams
1181          * to stop so that the application can restart them in an orderly
1182          * manner.
1183          */
1184         amdtp_out_stream_pcm_abort(&dice->stream);
1185
1186         mutex_lock(&dice->mutex);
1187
1188         dice->global_enabled = false;
1189         dice_stream_stop_packets(dice);
1190
1191         dice_owner_update(dice);
1192
1193         fw_iso_resources_update(&dice->resources);
1194
1195         mutex_unlock(&dice->mutex);
1196 }
1197
1198 #define DICE_INTERFACE  0x000001
1199
1200 static const struct ieee1394_device_id dice_id_table[] = {
1201         {
1202                 .match_flags = IEEE1394_MATCH_VERSION,
1203                 .version     = DICE_INTERFACE,
1204         },
1205         { }
1206 };
1207 MODULE_DEVICE_TABLE(ieee1394, dice_id_table);
1208
1209 static struct fw_driver dice_driver = {
1210         .driver   = {
1211                 .owner  = THIS_MODULE,
1212                 .name   = KBUILD_MODNAME,
1213                 .bus    = &fw_bus_type,
1214         },
1215         .probe    = dice_probe,
1216         .update   = dice_bus_reset,
1217         .remove   = dice_remove,
1218         .id_table = dice_id_table,
1219 };
1220
1221 static int __init alsa_dice_init(void)
1222 {
1223         return driver_register(&dice_driver.driver);
1224 }
1225
1226 static void __exit alsa_dice_exit(void)
1227 {
1228         driver_unregister(&dice_driver.driver);
1229 }
1230
1231 module_init(alsa_dice_init);
1232 module_exit(alsa_dice_exit);