security/optee_linuxdriver/fdts/fvp-foundation-gicv2-psci.dts

   1 /*
   2  * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions are met:
   6  *
   7  * Redistributions of source code must retain the above copyright notice, this
   8  * list of conditions and the following disclaimer.
   9  *
  10  * Redistributions in binary form must reproduce the above copyright notice,
  11  * this list of conditions and the following disclaimer in the documentation
  12  * and/or other materials provided with the distribution.
  13  *
  14  * Neither the name of the ARM nor the names of its contributors may be used
  15  * to endorse or promote products derived from this software without specific
  16  * prior written permission.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  19  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  22  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  28  * POSSIBILITY OF SUCH DAMAGE.
  29  */
  30
  31 /dts-v1/;
  32
  33 /memreserve/ 0x81000000 0x00100000;
  34 /memreserve/ 0x80000000 0x00010000;
  35
  36 / {
  37 };
  38
  39 / {
  40         model = "FVP Foundation";
  41         compatible = "arm,fvp-base", "arm,vexpress";
  42         interrupt-parent = <&gic>;
  43         #address-cells = <2>;
  44         #size-cells = <2>;
  45
  46         chosen { };
  47
  48         aliases {
  49                 serial0 = &v2m_serial0;
  50                 serial1 = &v2m_serial1;
  51                 serial2 = &v2m_serial2;
  52                 serial3 = &v2m_serial3;
  53         };
  54
  55         psci {
  56                 compatible = "arm,psci";
  57                 method = "smc";
  58                 cpu_suspend = <0xc4000001>;
  59                 cpu_off = <0x84000002>;
  60                 cpu_on = <0xc4000003>;
  61         };
  62
  63         cpus {
  64                 #address-cells = <2>;
  65                 #size-cells = <0>;
  66
  67                 cpu@0 {
  68                         device_type = "cpu";
  69                         compatible = "arm,armv8";
  70                         reg = <0x0 0x0>;
  71                         enable-method = "psci";
  72                 };
  73                 cpu@1 {
  74                         device_type = "cpu";
  75                         compatible = "arm,armv8";
  76                         reg = <0x0 0x1>;
  77                         enable-method = "psci";
  78                 };
  79                 cpu@2 {
  80                         device_type = "cpu";
  81                         compatible = "arm,armv8";
  82                         reg = <0x0 0x2>;
  83                         enable-method = "psci";
  84                 };
  85                 cpu@3 {
  86                         device_type = "cpu";
  87                         compatible = "arm,armv8";
  88                         reg = <0x0 0x3>;
  89                         enable-method = "psci";
  90                 };
  91         };
  92
  93         memory@80000000 {
  94                 device_type = "memory";
  95                 reg = <0x00000000 0x80000000 0 0x7F000000>,
  96                       <0x00000008 0x80000000 0 0x80000000>;
  97         };
  98
  99         gic: interrupt-controller@2f000000 {
 100                 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
 101                 #interrupt-cells = <3>;
 102                 #address-cells = <0>;
 103                 interrupt-controller;
 104                 reg = <0x0 0x2f000000 0 0x10000>,
 105                       <0x0 0x2c000000 0 0x2000>,
 106                       <0x0 0x2c010000 0 0x2000>,
 107                       <0x0 0x2c02F000 0 0x2000>;
 108                 interrupts = <1 9 0xf04>;
 109         };
 110
 111         timer {
 112                 compatible = "arm,armv8-timer";
 113                 interrupts = <1 13 0xff01>,
 114                              <1 14 0xff01>,
 115                              <1 11 0xff01>,
 116                              <1 10 0xff01>;
 117                 clock-frequency = <100000000>;
 118         };
 119
 120         timer@2a810000 {
 121                         compatible = "arm,armv7-timer-mem";
 122                         reg = <0x0 0x2a810000 0x0 0x10000>;
 123                         clock-frequency = <100000000>;
 124                         #address-cells = <2>;
 125                         #size-cells = <2>;
 126                         ranges;
 127                         frame@2a830000 {
 128                                 frame-number = <1>;
 129                                 interrupts = <0 26 4>;
 130                                 reg = <0x0 0x2a830000 0x0 0x10000>;
 131                         };
 132         };
 133
 134         pmu {
 135                 compatible = "arm,armv8-pmuv3";
 136                 interrupts = <0 60 4>,
 137                              <0 61 4>,
 138                              <0 62 4>,
 139                              <0 63 4>;
 140         };
 141
 142         smb {
 143                 compatible = "simple-bus";
 144
 145                 #address-cells = <2>;
 146                 #size-cells = <1>;
 147                 ranges = <0 0 0 0x08000000 0x04000000>,
 148                          <1 0 0 0x14000000 0x04000000>,
 149                          <2 0 0 0x18000000 0x04000000>,
 150                          <3 0 0 0x1c000000 0x04000000>,
 151                          <4 0 0 0x0c000000 0x04000000>,
 152                          <5 0 0 0x10000000 0x04000000>;
 153
 154                 #interrupt-cells = <1>;
 155                 interrupt-map-mask = <0 0 63>;
 156                 interrupt-map = <0 0  0 &gic 0  0 4>,
 157                                 <0 0  1 &gic 0  1 4>,
 158                                 <0 0  2 &gic 0  2 4>,
 159                                 <0 0  3 &gic 0  3 4>,
 160                                 <0 0  4 &gic 0  4 4>,
 161                                 <0 0  5 &gic 0  5 4>,
 162                                 <0 0  6 &gic 0  6 4>,
 163                                 <0 0  7 &gic 0  7 4>,
 164                                 <0 0  8 &gic 0  8 4>,
 165                                 <0 0  9 &gic 0  9 4>,
 166                                 <0 0 10 &gic 0 10 4>,
 167                                 <0 0 11 &gic 0 11 4>,
 168                                 <0 0 12 &gic 0 12 4>,
 169                                 <0 0 13 &gic 0 13 4>,
 170                                 <0 0 14 &gic 0 14 4>,
 171                                 <0 0 15 &gic 0 15 4>,
 172                                 <0 0 16 &gic 0 16 4>,
 173                                 <0 0 17 &gic 0 17 4>,
 174                                 <0 0 18 &gic 0 18 4>,
 175                                 <0 0 19 &gic 0 19 4>,
 176                                 <0 0 20 &gic 0 20 4>,
 177                                 <0 0 21 &gic 0 21 4>,
 178                                 <0 0 22 &gic 0 22 4>,
 179                                 <0 0 23 &gic 0 23 4>,
 180                                 <0 0 24 &gic 0 24 4>,
 181                                 <0 0 25 &gic 0 25 4>,
 182                                 <0 0 26 &gic 0 26 4>,
 183                                 <0 0 27 &gic 0 27 4>,
 184                                 <0 0 28 &gic 0 28 4>,
 185                                 <0 0 29 &gic 0 29 4>,
 186                                 <0 0 30 &gic 0 30 4>,
 187                                 <0 0 31 &gic 0 31 4>,
 188                                 <0 0 32 &gic 0 32 4>,
 189                                 <0 0 33 &gic 0 33 4>,
 190                                 <0 0 34 &gic 0 34 4>,
 191                                 <0 0 35 &gic 0 35 4>,
 192                                 <0 0 36 &gic 0 36 4>,
 193                                 <0 0 37 &gic 0 37 4>,
 194                                 <0 0 38 &gic 0 38 4>,
 195                                 <0 0 39 &gic 0 39 4>,
 196                                 <0 0 40 &gic 0 40 4>,
 197                                 <0 0 41 &gic 0 41 4>,
 198                                 <0 0 42 &gic 0 42 4>;
 199
 200                 /include/ "fvp-foundation-motherboard.dtsi"
 201         };
 202 };