1 //===- XCoreRegisterInfo.cpp - XCore Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the XCore implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "XCoreRegisterInfo.h"
15 #include "XCoreMachineFunctionInfo.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineLocation.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/RegisterScavenging.h"
24 #include "llvm/Target/TargetFrameInfo.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Type.h"
29 #include "llvm/Function.h"
30 #include "llvm/ADT/BitVector.h"
31 #include "llvm/ADT/STLExtras.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
38 XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii)
39 : XCoreGenRegisterInfo(XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP),
44 static inline bool isImmUs(unsigned val) {
48 static inline bool isImmU6(unsigned val) {
49 return val < (1 << 6);
52 static inline bool isImmU16(unsigned val) {
53 return val < (1 << 16);
56 static const unsigned XCore_ArgRegs[] = {
57 XCore::R0, XCore::R1, XCore::R2, XCore::R3
60 const unsigned * XCoreRegisterInfo::getArgRegs(const MachineFunction *MF)
65 unsigned XCoreRegisterInfo::getNumArgRegs(const MachineFunction *MF)
67 return array_lengthof(XCore_ArgRegs);
70 bool XCoreRegisterInfo::needsFrameMoves(const MachineFunction &MF)
72 const MachineFrameInfo *MFI = MF.getFrameInfo();
73 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
74 return (MMI && MMI->hasDebugInfo()) ||
75 !MF.getFunction()->doesNotThrow() ||
76 UnwindTablesMandatory;
79 const unsigned* XCoreRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
81 static const unsigned CalleeSavedRegs[] = {
82 XCore::R4, XCore::R5, XCore::R6, XCore::R7,
83 XCore::R8, XCore::R9, XCore::R10, XCore::LR,
86 return CalleeSavedRegs;
89 const TargetRegisterClass* const*
90 XCoreRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
91 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
92 XCore::GRRegsRegisterClass, XCore::GRRegsRegisterClass,
93 XCore::GRRegsRegisterClass, XCore::GRRegsRegisterClass,
94 XCore::GRRegsRegisterClass, XCore::GRRegsRegisterClass,
95 XCore::GRRegsRegisterClass, XCore::RRegsRegisterClass,
98 return CalleeSavedRegClasses;
101 BitVector XCoreRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
102 BitVector Reserved(getNumRegs());
103 Reserved.set(XCore::CP);
104 Reserved.set(XCore::DP);
105 Reserved.set(XCore::SP);
106 Reserved.set(XCore::LR);
108 Reserved.set(XCore::R10);
114 XCoreRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
115 // TODO can we estimate stack size?
119 bool XCoreRegisterInfo::hasFP(const MachineFunction &MF) const {
120 return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
123 // This function eliminates ADJCALLSTACKDOWN,
124 // ADJCALLSTACKUP pseudo instructions
125 void XCoreRegisterInfo::
126 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
127 MachineBasicBlock::iterator I) const {
128 if (!hasReservedCallFrame(MF)) {
129 // Turn the adjcallstackdown instruction into 'extsp <amt>' and the
130 // adjcallstackup instruction into 'ldaw sp, sp[<amt>]'
131 MachineInstr *Old = I;
132 uint64_t Amount = Old->getOperand(0).getImm();
134 // We need to keep the stack aligned properly. To do this, we round the
135 // amount of space needed for the outgoing arguments up to the next
136 // alignment boundary.
137 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
138 Amount = (Amount+Align-1)/Align*Align;
140 assert(Amount%4 == 0);
143 bool isU6 = isImmU6(Amount);
145 if (!isU6 && !isImmU16(Amount)) {
146 // FIX could emit multiple instructions in this case.
148 cerr << "eliminateCallFramePseudoInstr size too big: "
155 if (Old->getOpcode() == XCore::ADJCALLSTACKDOWN) {
156 int Opcode = isU6 ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
157 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode))
160 assert(Old->getOpcode() == XCore::ADJCALLSTACKUP);
161 int Opcode = isU6 ? XCore::LDAWSP_ru6_RRegs : XCore::LDAWSP_lru6_RRegs;
162 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode), XCore::SP)
166 // Replace the pseudo instruction with a new instruction...
174 void XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
175 int SPAdj, RegScavenger *RS) const {
176 assert(SPAdj == 0 && "Unexpected");
177 MachineInstr &MI = *II;
178 DebugLoc dl = MI.getDebugLoc();
181 while (!MI.getOperand(i).isFI()) {
183 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
186 MachineOperand &FrameOp = MI.getOperand(i);
187 int FrameIndex = FrameOp.getIndex();
189 MachineFunction &MF = *MI.getParent()->getParent();
190 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
191 int StackSize = MF.getFrameInfo()->getStackSize();
194 DEBUG(errs() << "\nFunction : "
195 << MF.getFunction()->getName() << "\n");
196 DEBUG(errs() << "<--------->\n");
197 DEBUG(MI.print(errs()));
198 DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n");
199 DEBUG(errs() << "FrameOffset : " << Offset << "\n");
200 DEBUG(errs() << "StackSize : " << StackSize << "\n");
205 // fold constant into offset.
206 Offset += MI.getOperand(i + 1).getImm();
207 MI.getOperand(i + 1).ChangeToImmediate(0);
209 assert(Offset%4 == 0 && "Misaligned stack offset");
211 DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n");
217 unsigned Reg = MI.getOperand(0).getReg();
218 bool isKill = MI.getOpcode() == XCore::STWFI && MI.getOperand(0).isKill();
220 assert(XCore::GRRegsRegisterClass->contains(Reg) &&
221 "Unexpected register operand");
223 MachineBasicBlock &MBB = *MI.getParent();
226 bool isUs = isImmUs(Offset);
227 unsigned FramePtr = XCore::R10;
229 MachineInstr *New = 0;
233 raw_string_ostream Msg(msg);
234 Msg << "eliminateFrameIndex Frame size too big: " << Offset;
235 llvm_report_error(Msg.str());
237 unsigned ScratchReg = RS->scavengeRegister(XCore::GRRegsRegisterClass, II,
239 loadConstant(MBB, II, ScratchReg, Offset, dl);
240 switch (MI.getOpcode()) {
242 New = BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
244 .addReg(ScratchReg, RegState::Kill);
247 New = BuildMI(MBB, II, dl, TII.get(XCore::STW_3r))
248 .addReg(Reg, getKillRegState(isKill))
250 .addReg(ScratchReg, RegState::Kill);
253 New = BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
255 .addReg(ScratchReg, RegState::Kill);
258 llvm_unreachable("Unexpected Opcode");
261 switch (MI.getOpcode()) {
263 New = BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
268 New = BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
269 .addReg(Reg, getKillRegState(isKill))
274 New = BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
279 llvm_unreachable("Unexpected Opcode");
283 bool isU6 = isImmU6(Offset);
284 if (!isU6 && !isImmU16(Offset)) {
286 raw_string_ostream Msg(msg);
287 Msg << "eliminateFrameIndex Frame size too big: " << Offset;
288 llvm_report_error(Msg.str());
291 switch (MI.getOpcode()) {
294 NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
295 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
299 NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
300 BuildMI(MBB, II, dl, TII.get(NewOpcode))
301 .addReg(Reg, getKillRegState(isKill))
305 NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
306 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
310 llvm_unreachable("Unexpected Opcode");
313 // Erase old instruction.
318 XCoreRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
319 RegScavenger *RS) const {
320 MachineFrameInfo *MFI = MF.getFrameInfo();
321 bool LRUsed = MF.getRegInfo().isPhysRegUsed(XCore::LR);
322 const TargetRegisterClass *RC = XCore::GRRegsRegisterClass;
323 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
325 MF.getRegInfo().setPhysRegUnused(XCore::LR);
327 bool isVarArg = MF.getFunction()->isVarArg();
330 // A fixed offset of 0 allows us to save / restore LR using entsp / retsp.
331 FrameIdx = MFI->CreateFixedObject(RC->getSize(), 0);
333 FrameIdx = MFI->CreateStackObject(RC->getSize(), RC->getAlignment());
335 XFI->setUsesLR(FrameIdx);
336 XFI->setLRSpillSlot(FrameIdx);
338 if (requiresRegisterScavenging(MF)) {
339 // Reserve a slot close to SP or frame pointer.
340 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
341 RC->getAlignment()));
344 // A callee save register is used to hold the FP.
345 // This needs saving / restoring in the epilogue / prologue.
346 XFI->setFPSpillSlot(MFI->CreateStackObject(RC->getSize(),
347 RC->getAlignment()));
351 void XCoreRegisterInfo::
352 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
356 void XCoreRegisterInfo::
357 loadConstant(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
358 unsigned DstReg, int64_t Value, DebugLoc dl) const {
359 // TODO use mkmsk if possible.
360 if (!isImmU16(Value)) {
361 // TODO use constant pool.
363 raw_string_ostream Msg(msg);
364 Msg << "loadConstant value too big " << Value;
365 llvm_report_error(Msg.str());
367 int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6;
368 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg).addImm(Value);
371 void XCoreRegisterInfo::
372 storeToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
373 unsigned SrcReg, int Offset, DebugLoc dl) const {
374 assert(Offset%4 == 0 && "Misaligned stack offset");
376 bool isU6 = isImmU6(Offset);
377 if (!isU6 && !isImmU16(Offset)) {
379 raw_string_ostream Msg(msg);
380 Msg << "storeToStack offset too big " << Offset;
381 llvm_report_error(Msg.str());
383 int Opcode = isU6 ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
384 BuildMI(MBB, I, dl, TII.get(Opcode))
389 void XCoreRegisterInfo::
390 loadFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
391 unsigned DstReg, int Offset, DebugLoc dl) const {
392 assert(Offset%4 == 0 && "Misaligned stack offset");
394 bool isU6 = isImmU6(Offset);
395 if (!isU6 && !isImmU16(Offset)) {
397 raw_string_ostream Msg(msg);
398 Msg << "loadFromStack offset too big " << Offset;
399 llvm_report_error(Msg.str());
401 int Opcode = isU6 ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
402 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg)
406 void XCoreRegisterInfo::emitPrologue(MachineFunction &MF) const {
407 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
408 MachineBasicBlock::iterator MBBI = MBB.begin();
409 MachineFrameInfo *MFI = MF.getFrameInfo();
410 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
411 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
412 DebugLoc dl = (MBBI != MBB.end() ?
413 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
417 // Work out frame sizes.
418 int FrameSize = MFI->getStackSize();
420 assert(FrameSize%4 == 0 && "Misaligned frame size");
424 bool isU6 = isImmU6(FrameSize);
426 if (!isU6 && !isImmU16(FrameSize)) {
427 // FIXME could emit multiple instructions.
429 raw_string_ostream Msg(msg);
430 Msg << "emitPrologue Frame size too big: " << FrameSize;
431 llvm_report_error(Msg.str());
433 bool emitFrameMoves = needsFrameMoves(MF);
435 // Do we need to allocate space on the stack?
437 bool saveLR = XFI->getUsesLR();
438 bool LRSavedOnEntry = false;
440 if (saveLR && (MFI->getObjectOffset(XFI->getLRSpillSlot()) == 0)) {
441 Opcode = (isU6) ? XCore::ENTSP_u6 : XCore::ENTSP_lu6;
442 MBB.addLiveIn(XCore::LR);
444 LRSavedOnEntry = true;
446 Opcode = (isU6) ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
448 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize);
450 if (emitFrameMoves) {
451 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
453 // Show update of SP.
454 unsigned FrameLabelId = MMI->NextLabelID();
455 BuildMI(MBB, MBBI, dl, TII.get(XCore::DBG_LABEL)).addImm(FrameLabelId);
457 MachineLocation SPDst(MachineLocation::VirtualFP);
458 MachineLocation SPSrc(MachineLocation::VirtualFP, -FrameSize * 4);
459 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
461 if (LRSavedOnEntry) {
462 MachineLocation CSDst(MachineLocation::VirtualFP, 0);
463 MachineLocation CSSrc(XCore::LR);
464 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
468 int LRSpillOffset = MFI->getObjectOffset(XFI->getLRSpillSlot());
469 storeToStack(MBB, MBBI, XCore::LR, LRSpillOffset + FrameSize*4, dl);
470 MBB.addLiveIn(XCore::LR);
472 if (emitFrameMoves) {
473 unsigned SaveLRLabelId = MMI->NextLabelID();
474 BuildMI(MBB, MBBI, dl, TII.get(XCore::DBG_LABEL)).addImm(SaveLRLabelId);
475 MachineLocation CSDst(MachineLocation::VirtualFP, LRSpillOffset);
476 MachineLocation CSSrc(XCore::LR);
477 MMI->getFrameMoves().push_back(MachineMove(SaveLRLabelId,
484 // Save R10 to the stack.
485 int FPSpillOffset = MFI->getObjectOffset(XFI->getFPSpillSlot());
486 storeToStack(MBB, MBBI, XCore::R10, FPSpillOffset + FrameSize*4, dl);
487 // R10 is live-in. It is killed at the spill.
488 MBB.addLiveIn(XCore::R10);
489 if (emitFrameMoves) {
490 unsigned SaveR10LabelId = MMI->NextLabelID();
491 BuildMI(MBB, MBBI, dl, TII.get(XCore::DBG_LABEL)).addImm(SaveR10LabelId);
492 MachineLocation CSDst(MachineLocation::VirtualFP, FPSpillOffset);
493 MachineLocation CSSrc(XCore::R10);
494 MMI->getFrameMoves().push_back(MachineMove(SaveR10LabelId,
497 // Set the FP from the SP.
498 unsigned FramePtr = XCore::R10;
499 BuildMI(MBB, MBBI, dl, TII.get(XCore::LDAWSP_ru6), FramePtr)
501 if (emitFrameMoves) {
502 // Show FP is now valid.
503 unsigned FrameLabelId = MMI->NextLabelID();
504 BuildMI(MBB, MBBI, dl, TII.get(XCore::DBG_LABEL)).addImm(FrameLabelId);
505 MachineLocation SPDst(FramePtr);
506 MachineLocation SPSrc(MachineLocation::VirtualFP);
507 MMI->getFrameMoves().push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
511 if (emitFrameMoves) {
512 // Frame moves for callee saved.
513 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
514 std::vector<std::pair<unsigned, CalleeSavedInfo> >&SpillLabels =
515 XFI->getSpillLabels();
516 for (unsigned I = 0, E = SpillLabels.size(); I != E; ++I) {
517 unsigned SpillLabel = SpillLabels[I].first;
518 CalleeSavedInfo &CSI = SpillLabels[I].second;
519 int Offset = MFI->getObjectOffset(CSI.getFrameIdx());
520 unsigned Reg = CSI.getReg();
521 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
522 MachineLocation CSSrc(Reg);
523 Moves.push_back(MachineMove(SpillLabel, CSDst, CSSrc));
528 void XCoreRegisterInfo::emitEpilogue(MachineFunction &MF,
529 MachineBasicBlock &MBB) const {
530 MachineFrameInfo *MFI = MF.getFrameInfo();
531 MachineBasicBlock::iterator MBBI = prior(MBB.end());
532 DebugLoc dl = MBBI->getDebugLoc();
537 // Restore the stack pointer.
538 unsigned FramePtr = XCore::R10;
539 BuildMI(MBB, MBBI, dl, TII.get(XCore::SETSP_1r))
543 // Work out frame sizes.
544 int FrameSize = MFI->getStackSize();
546 assert(FrameSize%4 == 0 && "Misaligned frame size");
550 bool isU6 = isImmU6(FrameSize);
552 if (!isU6 && !isImmU16(FrameSize)) {
553 // FIXME could emit multiple instructions.
555 raw_string_ostream Msg(msg);
556 Msg << "emitEpilogue Frame size too big: " << FrameSize;
557 llvm_report_error(Msg.str());
561 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
565 int FPSpillOffset = MFI->getObjectOffset(XFI->getFPSpillSlot());
566 FPSpillOffset += FrameSize*4;
567 loadFromStack(MBB, MBBI, XCore::R10, FPSpillOffset, dl);
569 bool restoreLR = XFI->getUsesLR();
570 if (restoreLR && MFI->getObjectOffset(XFI->getLRSpillSlot()) != 0) {
571 int LRSpillOffset = MFI->getObjectOffset(XFI->getLRSpillSlot());
572 LRSpillOffset += FrameSize*4;
573 loadFromStack(MBB, MBBI, XCore::LR, LRSpillOffset, dl);
577 // Fold prologue into return instruction
578 assert(MBBI->getOpcode() == XCore::RETSP_u6
579 || MBBI->getOpcode() == XCore::RETSP_lu6);
580 int Opcode = (isU6) ? XCore::RETSP_u6 : XCore::RETSP_lu6;
581 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize);
584 int Opcode = (isU6) ? XCore::LDAWSP_ru6_RRegs : XCore::LDAWSP_lru6_RRegs;
585 BuildMI(MBB, MBBI, dl, TII.get(Opcode), XCore::SP).addImm(FrameSize);
590 int XCoreRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
591 return XCoreGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
594 unsigned XCoreRegisterInfo::getFrameRegister(MachineFunction &MF) const {
597 return FP ? XCore::R10 : XCore::SP;
600 unsigned XCoreRegisterInfo::getRARegister() const {
604 void XCoreRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
606 // Initial state of the frame pointer is SP.
607 MachineLocation Dst(MachineLocation::VirtualFP);
608 MachineLocation Src(XCore::SP, 0);
609 Moves.push_back(MachineMove(0, Dst, Src));
612 #include "XCoreGenRegisterInfo.inc"