1 //===-- XCoreInstrInfo.td - Target Description for XCore ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the XCore instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 // Uses of CP, DP are not currently reflected in the patterns, since
15 // having a physical register as an operand prevents loop hoisting and
16 // since the value of these registers never changes during the life of the
19 //===----------------------------------------------------------------------===//
20 // Instruction format superclass.
21 //===----------------------------------------------------------------------===//
23 include "XCoreInstrFormats.td"
25 //===----------------------------------------------------------------------===//
26 // XCore specific DAG Nodes.
30 def SDT_XCoreBranchLink : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
31 def XCoreBranchLink : SDNode<"XCoreISD::BL",SDT_XCoreBranchLink,
32 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
35 def XCoreRetsp : SDNode<"XCoreISD::RETSP", SDTBrind,
36 [SDNPHasChain, SDNPOptInGlue, SDNPMayLoad]>;
38 def SDT_XCoreBR_JT : SDTypeProfile<0, 2,
39 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
41 def XCoreBR_JT : SDNode<"XCoreISD::BR_JT", SDT_XCoreBR_JT,
44 def XCoreBR_JT32 : SDNode<"XCoreISD::BR_JT32", SDT_XCoreBR_JT,
47 def SDT_XCoreAddress : SDTypeProfile<1, 1,
48 [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
50 def pcrelwrapper : SDNode<"XCoreISD::PCRelativeWrapper", SDT_XCoreAddress,
53 def dprelwrapper : SDNode<"XCoreISD::DPRelativeWrapper", SDT_XCoreAddress,
56 def cprelwrapper : SDNode<"XCoreISD::CPRelativeWrapper", SDT_XCoreAddress,
59 def SDT_XCoreStwsp : SDTypeProfile<0, 2, [SDTCisInt<1>]>;
60 def XCoreStwsp : SDNode<"XCoreISD::STWSP", SDT_XCoreStwsp,
61 [SDNPHasChain, SDNPMayStore]>;
63 // These are target-independent nodes, but have target-specific formats.
64 def SDT_XCoreCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
65 def SDT_XCoreCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
68 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_XCoreCallSeqStart,
69 [SDNPHasChain, SDNPOutGlue]>;
70 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_XCoreCallSeqEnd,
71 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
73 //===----------------------------------------------------------------------===//
74 // Instruction Pattern Stuff
75 //===----------------------------------------------------------------------===//
77 def div4_xform : SDNodeXForm<imm, [{
78 // Transformation function: imm/4
79 assert(N->getZExtValue() % 4 == 0);
80 return getI32Imm(N->getZExtValue()/4);
83 def msksize_xform : SDNodeXForm<imm, [{
84 // Transformation function: get the size of a mask
85 assert(isMask_32(N->getZExtValue()));
86 // look for the first non-zero bit
87 return getI32Imm(32 - CountLeadingZeros_32(N->getZExtValue()));
90 def neg_xform : SDNodeXForm<imm, [{
91 // Transformation function: -imm
92 uint32_t value = N->getZExtValue();
93 return getI32Imm(-value);
96 def bpwsub_xform : SDNodeXForm<imm, [{
97 // Transformation function: 32-imm
98 uint32_t value = N->getZExtValue();
99 return getI32Imm(32-value);
102 def div4neg_xform : SDNodeXForm<imm, [{
103 // Transformation function: -imm/4
104 uint32_t value = N->getZExtValue();
105 assert(-value % 4 == 0);
106 return getI32Imm(-value/4);
109 def immUs4Neg : PatLeaf<(imm), [{
110 uint32_t value = (uint32_t)N->getZExtValue();
111 return (-value)%4 == 0 && (-value)/4 <= 11;
114 def immUs4 : PatLeaf<(imm), [{
115 uint32_t value = (uint32_t)N->getZExtValue();
116 return value%4 == 0 && value/4 <= 11;
119 def immUsNeg : PatLeaf<(imm), [{
120 return -((uint32_t)N->getZExtValue()) <= 11;
123 def immUs : PatLeaf<(imm), [{
124 return (uint32_t)N->getZExtValue() <= 11;
127 def immU6 : PatLeaf<(imm), [{
128 return (uint32_t)N->getZExtValue() < (1 << 6);
131 def immU10 : PatLeaf<(imm), [{
132 return (uint32_t)N->getZExtValue() < (1 << 10);
135 def immU16 : PatLeaf<(imm), [{
136 return (uint32_t)N->getZExtValue() < (1 << 16);
139 def immU20 : PatLeaf<(imm), [{
140 return (uint32_t)N->getZExtValue() < (1 << 20);
143 def immMskBitp : PatLeaf<(imm), [{ return immMskBitp(N); }]>;
145 def immBitp : PatLeaf<(imm), [{
146 uint32_t value = (uint32_t)N->getZExtValue();
147 return (value >= 1 && value <= 8)
153 def immBpwSubBitp : PatLeaf<(imm), [{
154 uint32_t value = (uint32_t)N->getZExtValue();
155 return (value >= 24 && value <= 31)
161 def lda16f : PatFrag<(ops node:$addr, node:$offset),
162 (add node:$addr, (shl node:$offset, 1))>;
163 def lda16b : PatFrag<(ops node:$addr, node:$offset),
164 (sub node:$addr, (shl node:$offset, 1))>;
165 def ldawf : PatFrag<(ops node:$addr, node:$offset),
166 (add node:$addr, (shl node:$offset, 2))>;
167 def ldawb : PatFrag<(ops node:$addr, node:$offset),
168 (sub node:$addr, (shl node:$offset, 2))>;
170 // Instruction operand types
171 def calltarget : Operand<i32>;
172 def brtarget : Operand<OtherVT>;
173 def pclabel : Operand<i32>;
176 def ADDRspii : ComplexPattern<i32, 2, "SelectADDRspii", [add, frameindex], []>;
177 def ADDRdpii : ComplexPattern<i32, 2, "SelectADDRdpii", [add, dprelwrapper],
179 def ADDRcpii : ComplexPattern<i32, 2, "SelectADDRcpii", [add, cprelwrapper],
183 def MEMii : Operand<i32> {
184 let PrintMethod = "printMemOperand";
185 let MIOperandInfo = (ops i32imm, i32imm);
189 def InlineJT : Operand<i32> {
190 let PrintMethod = "printInlineJT";
193 def InlineJT32 : Operand<i32> {
194 let PrintMethod = "printInlineJT32";
197 //===----------------------------------------------------------------------===//
198 // Instruction Class Templates
199 //===----------------------------------------------------------------------===//
201 // Three operand short
203 multiclass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> {
204 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
205 !strconcat(OpcStr, " $dst, $b, $c"),
206 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
207 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
208 !strconcat(OpcStr, " $dst, $b, $c"),
209 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
212 multiclass F3R_2RUS_np<bits<5> opc1, bits<5> opc2, string OpcStr> {
213 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
214 !strconcat(OpcStr, " $dst, $b, $c"), []>;
215 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
216 !strconcat(OpcStr, " $dst, $b, $c"), []>;
219 multiclass F3R_2RBITP<bits<5> opc1, bits<5> opc2, string OpcStr,
221 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
222 !strconcat(OpcStr, " $dst, $b, $c"),
223 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
224 def _2rus : _F2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
225 !strconcat(OpcStr, " $dst, $b, $c"),
226 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
229 class F3R<bits<5> opc, string OpcStr, SDNode OpNode> :
230 _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
231 !strconcat(OpcStr, " $dst, $b, $c"),
232 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
234 class F3R_np<bits<5> opc, string OpcStr> :
235 _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
236 !strconcat(OpcStr, " $dst, $b, $c"), []>;
237 // Three operand long
239 /// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot.
240 multiclass FL3R_L2RUS<bits<9> opc, string OpcStr, SDNode OpNode> {
241 def _l3r: _FL3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
242 !strconcat(OpcStr, " $dst, $b, $c"),
243 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
244 def _l2rus : _FL2RUS<
245 (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
246 !strconcat(OpcStr, " $dst, $b, $c"),
247 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
250 /// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot.
251 multiclass FL3R_L2RBITP<bits<9> opc, string OpcStr, SDNode OpNode> {
252 def _l3r: _FL3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
253 !strconcat(OpcStr, " $dst, $b, $c"),
254 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
255 def _l2rus : _FL2RUS<
256 (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
257 !strconcat(OpcStr, " $dst, $b, $c"),
258 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
261 class FL3R<bits<9> opc, string OpcStr, SDNode OpNode> :
262 _FL3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
263 !strconcat(OpcStr, " $dst, $b, $c"),
264 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
267 // Operand register - U6
268 multiclass FRU6_LRU6_branch<string OpcStr> {
270 (outs), (ins GRRegs:$cond, brtarget:$dest),
271 !strconcat(OpcStr, " $cond, $dest"),
274 (outs), (ins GRRegs:$cond, brtarget:$dest),
275 !strconcat(OpcStr, " $cond, $dest"),
279 multiclass FRU6_LRU6_cp<string OpcStr> {
281 (outs GRRegs:$dst), (ins i32imm:$a),
282 !strconcat(OpcStr, " $dst, cp[$a]"),
285 (outs GRRegs:$dst), (ins i32imm:$a),
286 !strconcat(OpcStr, " $dst, cp[$a]"),
291 multiclass FU6_LU6<string OpcStr, SDNode OpNode> {
293 (outs), (ins i32imm:$b),
294 !strconcat(OpcStr, " $b"),
295 [(OpNode immU6:$b)]>;
297 (outs), (ins i32imm:$b),
298 !strconcat(OpcStr, " $b"),
299 [(OpNode immU16:$b)]>;
301 multiclass FU6_LU6_int<string OpcStr, Intrinsic Int> {
303 (outs), (ins i32imm:$b),
304 !strconcat(OpcStr, " $b"),
307 (outs), (ins i32imm:$b),
308 !strconcat(OpcStr, " $b"),
312 multiclass FU6_LU6_np<string OpcStr> {
314 (outs), (ins i32imm:$b),
315 !strconcat(OpcStr, " $b"),
318 (outs), (ins i32imm:$b),
319 !strconcat(OpcStr, " $b"),
324 multiclass FU10_LU10_np<string OpcStr> {
326 (outs), (ins i32imm:$b),
327 !strconcat(OpcStr, " $b"),
330 (outs), (ins i32imm:$b),
331 !strconcat(OpcStr, " $b"),
337 class F2R_np<bits<6> opc, string OpcStr> :
338 _F2R<opc, (outs GRRegs:$dst), (ins GRRegs:$b),
339 !strconcat(OpcStr, " $dst, $b"), []>;
343 //===----------------------------------------------------------------------===//
344 // Pseudo Instructions
345 //===----------------------------------------------------------------------===//
347 let Defs = [SP], Uses = [SP] in {
348 def ADJCALLSTACKDOWN : PseudoInstXCore<(outs), (ins i32imm:$amt),
349 "# ADJCALLSTACKDOWN $amt",
350 [(callseq_start timm:$amt)]>;
351 def ADJCALLSTACKUP : PseudoInstXCore<(outs), (ins i32imm:$amt1, i32imm:$amt2),
352 "# ADJCALLSTACKUP $amt1",
353 [(callseq_end timm:$amt1, timm:$amt2)]>;
356 def LDWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr),
357 "# LDWFI $dst, $addr",
358 [(set GRRegs:$dst, (load ADDRspii:$addr))]>;
360 def LDAWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr),
361 "# LDAWFI $dst, $addr",
362 [(set GRRegs:$dst, ADDRspii:$addr)]>;
364 def STWFI : PseudoInstXCore<(outs), (ins GRRegs:$src, MEMii:$addr),
365 "# STWFI $src, $addr",
366 [(store GRRegs:$src, ADDRspii:$addr)]>;
368 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
369 // instruction selection into a branch sequence.
370 let usesCustomInserter = 1 in {
371 def SELECT_CC : PseudoInstXCore<(outs GRRegs:$dst),
372 (ins GRRegs:$cond, GRRegs:$T, GRRegs:$F),
373 "# SELECT_CC PSEUDO!",
375 (select GRRegs:$cond, GRRegs:$T, GRRegs:$F))]>;
378 //===----------------------------------------------------------------------===//
380 //===----------------------------------------------------------------------===//
382 // Three operand short
383 defm ADD : F3R_2RUS<0b00010, 0b10010, "add", add>;
384 defm SUB : F3R_2RUS<0b00011, 0b10011, "sub", sub>;
385 let neverHasSideEffects = 1 in {
386 defm EQ : F3R_2RUS_np<0b00110, 0b10110, "eq">;
387 def LSS_3r : F3R_np<0b11000, "lss">;
388 def LSU_3r : F3R_np<0b11001, "lsu">;
390 def AND_3r : F3R<0b00111, "and", and>;
391 def OR_3r : F3R<0b01000, "or", or>;
394 def LDW_3r : _F3R<0b01001, (outs GRRegs:$dst),
395 (ins GRRegs:$addr, GRRegs:$offset),
396 "ldw $dst, $addr[$offset]", []>;
398 def LDW_2rus : _F2RUS<0b00001, (outs GRRegs:$dst),
399 (ins GRRegs:$addr, i32imm:$offset),
400 "ldw $dst, $addr[$offset]", []>;
402 def LD16S_3r : _F3R<0b10000, (outs GRRegs:$dst),
403 (ins GRRegs:$addr, GRRegs:$offset),
404 "ld16s $dst, $addr[$offset]", []>;
406 def LD8U_3r : _F3R<0b10001, (outs GRRegs:$dst),
407 (ins GRRegs:$addr, GRRegs:$offset),
408 "ld8u $dst, $addr[$offset]", []>;
412 def STW_3r : _FL3R<0b000001100, (outs),
413 (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
414 "stw $val, $addr[$offset]", []>;
416 def STW_2rus : _F2RUS<0b0000, (outs),
417 (ins GRRegs:$val, GRRegs:$addr, i32imm:$offset),
418 "stw $val, $addr[$offset]", []>;
421 defm SHL : F3R_2RBITP<0b00100, 0b10100, "shl", shl>;
422 defm SHR : F3R_2RBITP<0b00101, 0b10101, "shr", srl>;
425 // Three operand long
426 def LDAWF_l3r : _FL3R<0b000111100, (outs GRRegs:$dst),
427 (ins GRRegs:$addr, GRRegs:$offset),
428 "ldaw $dst, $addr[$offset]",
430 (ldawf GRRegs:$addr, GRRegs:$offset))]>;
432 let neverHasSideEffects = 1 in
433 def LDAWF_l2rus : _FL2RUS<(outs GRRegs:$dst),
434 (ins GRRegs:$addr, i32imm:$offset),
435 "ldaw $dst, $addr[$offset]",
438 def LDAWB_l3r : _FL3R<0b001001100, (outs GRRegs:$dst),
439 (ins GRRegs:$addr, GRRegs:$offset),
440 "ldaw $dst, $addr[-$offset]",
442 (ldawb GRRegs:$addr, GRRegs:$offset))]>;
444 let neverHasSideEffects = 1 in
445 def LDAWB_l2rus : _FL2RUS<(outs GRRegs:$dst),
446 (ins GRRegs:$addr, i32imm:$offset),
447 "ldaw $dst, $addr[-$offset]",
450 def LDA16F_l3r : _FL3R<0b001011100, (outs GRRegs:$dst),
451 (ins GRRegs:$addr, GRRegs:$offset),
452 "lda16 $dst, $addr[$offset]",
454 (lda16f GRRegs:$addr, GRRegs:$offset))]>;
456 def LDA16B_l3r : _FL3R<0b001101100, (outs GRRegs:$dst),
457 (ins GRRegs:$addr, GRRegs:$offset),
458 "lda16 $dst, $addr[-$offset]",
460 (lda16b GRRegs:$addr, GRRegs:$offset))]>;
462 def MUL_l3r : FL3R<0b001111100, "mul", mul>;
463 // Instructions which may trap are marked as side effecting.
464 let hasSideEffects = 1 in {
465 def DIVS_l3r : FL3R<0b010001100, "divs", sdiv>;
466 def DIVU_l3r : FL3R<0b010011100, "divu", udiv>;
467 def REMS_l3r : FL3R<0b110001100, "rems", srem>;
468 def REMU_l3r : FL3R<0b110011100, "remu", urem>;
470 def XOR_l3r : FL3R<0b000011100, "xor", xor>;
471 defm ASHR : FL3R_L2RBITP<0b000101100, "ashr", sra>;
473 let Constraints = "$src1 = $dst" in
474 def CRC_l3r : _FL3RSrcDst<0b101011100, (outs GRRegs:$dst),
475 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
476 "crc32 $dst, $src2, $src3",
478 (int_xcore_crc32 GRRegs:$src1, GRRegs:$src2,
483 def ST16_l3r : _FL3R<0b100001100, (outs),
484 (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
485 "st16 $val, $addr[$offset]", []>;
487 def ST8_l3r : _FL3R<0b100011100, (outs),
488 (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
489 "st8 $val, $addr[$offset]", []>;
493 let Constraints = "$src1 = $dst1,$src2 = $dst2" in {
494 def MACCU_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2),
495 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3,
497 "maccu $dst1, $dst2, $src3, $src4",
500 def MACCS_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2),
501 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3,
503 "maccs $dst1, $dst2, $src3, $src4",
507 let Constraints = "$src1 = $dst1" in
508 def CRC8_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2),
509 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
510 "crc8 $dst1, $dst2, $src2, $src3",
515 def LADD_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2),
516 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
517 "ladd $dst1, $dst2, $src1, $src2, $src3",
520 def LSUB_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2),
521 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
522 "lsub $dst1, $dst2, $src1, $src2, $src3",
525 def LDIV_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2),
526 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
527 "ldiv $dst1, $dst2, $src1, $src2, $src3",
532 def LMUL_l6r : _L6R<(outs GRRegs:$dst1, GRRegs:$dst2),
533 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3,
535 "lmul $dst1, $dst2, $src1, $src2, $src3, $src4",
540 //let Uses = [DP] in ...
541 let neverHasSideEffects = 1, isReMaterializable = 1 in
542 def LDAWDP_ru6: _FRU6<(outs GRRegs:$dst), (ins MEMii:$a),
546 let isReMaterializable = 1 in
547 def LDAWDP_lru6: _FLRU6<
548 (outs GRRegs:$dst), (ins MEMii:$a),
550 [(set GRRegs:$dst, ADDRdpii:$a)]>;
553 def LDWDP_ru6: _FRU6<(outs GRRegs:$dst), (ins MEMii:$a),
557 def LDWDP_lru6: _FLRU6<
558 (outs GRRegs:$dst), (ins MEMii:$a),
560 [(set GRRegs:$dst, (load ADDRdpii:$a))]>;
563 def STWDP_ru6 : _FRU6<(outs), (ins GRRegs:$val, MEMii:$addr),
564 "stw $val, dp[$addr]",
567 def STWDP_lru6 : _FLRU6<(outs), (ins GRRegs:$val, MEMii:$addr),
568 "stw $val, dp[$addr]",
569 [(store GRRegs:$val, ADDRdpii:$addr)]>;
571 //let Uses = [CP] in ..
572 let mayLoad = 1, isReMaterializable = 1, neverHasSideEffects = 1 in
573 defm LDWCP : FRU6_LRU6_cp<"ldw">;
577 def STWSP_ru6 : _FRU6<
578 (outs), (ins GRRegs:$val, i32imm:$index),
579 "stw $val, sp[$index]",
580 [(XCoreStwsp GRRegs:$val, immU6:$index)]>;
582 def STWSP_lru6 : _FLRU6<
583 (outs), (ins GRRegs:$val, i32imm:$index),
584 "stw $val, sp[$index]",
585 [(XCoreStwsp GRRegs:$val, immU16:$index)]>;
589 def LDWSP_ru6 : _FRU6<
590 (outs GRRegs:$dst), (ins i32imm:$b),
594 def LDWSP_lru6 : _FLRU6<
595 (outs GRRegs:$dst), (ins i32imm:$b),
600 let neverHasSideEffects = 1 in {
601 def LDAWSP_ru6 : _FRU6<
602 (outs GRRegs:$dst), (ins i32imm:$b),
606 def LDAWSP_lru6 : _FLRU6<
607 (outs GRRegs:$dst), (ins i32imm:$b),
611 def LDAWSP_ru6_RRegs : _FRU6<
612 (outs RRegs:$dst), (ins i32imm:$b),
616 def LDAWSP_lru6_RRegs : _FLRU6<
617 (outs RRegs:$dst), (ins i32imm:$b),
623 let isReMaterializable = 1 in {
625 (outs GRRegs:$dst), (ins i32imm:$b),
627 [(set GRRegs:$dst, immU6:$b)]>;
629 def LDC_lru6 : _FLRU6<
630 (outs GRRegs:$dst), (ins i32imm:$b),
632 [(set GRRegs:$dst, immU16:$b)]>;
635 def SETC_ru6 : _FRU6<(outs), (ins GRRegs:$r, i32imm:$val),
636 "setc res[$r], $val",
637 [(int_xcore_setc GRRegs:$r, immU6:$val)]>;
639 def SETC_lru6 : _FLRU6<(outs), (ins GRRegs:$r, i32imm:$val),
640 "setc res[$r], $val",
641 [(int_xcore_setc GRRegs:$r, immU16:$val)]>;
643 // Operand register - U6
644 let isBranch = 1, isTerminator = 1 in {
645 defm BRFT: FRU6_LRU6_branch<"bt">;
646 defm BRBT: FRU6_LRU6_branch<"bt">;
647 defm BRFF: FRU6_LRU6_branch<"bf">;
648 defm BRBF: FRU6_LRU6_branch<"bf">;
652 let Defs = [SP], Uses = [SP] in {
653 let neverHasSideEffects = 1 in
654 defm EXTSP : FU6_LU6_np<"extsp">;
656 defm ENTSP : FU6_LU6_np<"entsp">;
658 let isReturn = 1, isTerminator = 1, mayLoad = 1, isBarrier = 1 in {
659 defm RETSP : FU6_LU6<"retsp", XCoreRetsp>;
663 // TODO extdp, kentsp, krestsp, blat
665 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
668 (ins brtarget:$target),
672 def BRBU_lu6 : _FLU6<
674 (ins brtarget:$target),
680 (ins brtarget:$target),
684 def BRFU_lu6 : _FLU6<
686 (ins brtarget:$target),
691 //let Uses = [CP] in ...
692 let Defs = [R11], neverHasSideEffects = 1, isReMaterializable = 1 in
693 def LDAWCP_u6: _FRU6<(outs), (ins MEMii:$a),
697 let Defs = [R11], isReMaterializable = 1 in
698 def LDAWCP_lu6: _FLRU6<
699 (outs), (ins MEMii:$a),
701 [(set R11, ADDRcpii:$a)]>;
703 defm SETSR : FU6_LU6_int<"setsr", int_xcore_setsr>;
705 defm CLRSR : FU6_LU6_int<"clrsr", int_xcore_clrsr>;
707 // setsr may cause a branch if it is used to enable events. clrsr may
708 // branch if it is executed while events are enabled.
709 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in {
710 defm SETSR_branch : FU6_LU6_np<"setsr">;
711 defm CLRSR_branch : FU6_LU6_np<"clrsr">;
715 // TODO ldwcpl, blacp
717 let Defs = [R11], isReMaterializable = 1, neverHasSideEffects = 1 in
718 def LDAP_u10 : _FU10<
724 let Defs = [R11], isReMaterializable = 1 in
725 def LDAP_lu10 : _FLU10<
729 [(set R11, (pcrelwrapper tglobaladdr:$addr))]>;
731 let Defs = [R11], isReMaterializable = 1 in
732 def LDAP_lu10_ba : _FLU10<(outs),
735 [(set R11, (pcrelwrapper tblockaddress:$addr))]>;
738 // All calls clobber the link register and the non-callee-saved registers:
739 Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in {
741 (outs), (ins calltarget:$target),
743 [(XCoreBranchLink immU10:$target)]>;
745 def BL_lu10 : _FLU10<
746 (outs), (ins calltarget:$target),
748 [(XCoreBranchLink immU20:$target)]>;
752 // TODO eet, eef, tsetmr
753 def NOT : _F2R<0b100010, (outs GRRegs:$dst), (ins GRRegs:$b),
754 "not $dst, $b", [(set GRRegs:$dst, (not GRRegs:$b))]>;
756 def NEG : _F2R<0b100100, (outs GRRegs:$dst), (ins GRRegs:$b),
757 "neg $dst, $b", [(set GRRegs:$dst, (ineg GRRegs:$b))]>;
759 let Constraints = "$src1 = $dst" in {
761 _FRUSSrcDstBitp<0b001101, (outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
763 [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1,
767 _F2RSrcDst<0b001100, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
769 [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1, GRRegs:$src2))]>;
772 _FRUSSrcDstBitp<0b010001, (outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
774 [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1,
778 _F2RSrcDst<0b010000, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
780 [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1, GRRegs:$src2))]>;
783 _F2RSrcDst<0b001010, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
784 "andnot $dst, $src2",
785 [(set GRRegs:$dst, (and GRRegs:$src1, (not GRRegs:$src2)))]>;
788 let isReMaterializable = 1, neverHasSideEffects = 1 in
789 def MKMSK_rus : _FRUSBitp<0b101001, (outs GRRegs:$dst), (ins i32imm:$size),
790 "mkmsk $dst, $size", []>;
792 def MKMSK_2r : _F2R<0b101000, (outs GRRegs:$dst), (ins GRRegs:$size),
794 [(set GRRegs:$dst, (add (shl 1, GRRegs:$size), -1))]>;
796 def GETR_rus : _FRUS<0b100000, (outs GRRegs:$dst), (ins i32imm:$type),
798 [(set GRRegs:$dst, (int_xcore_getr immUs:$type))]>;
800 def GETTS_2r : _F2R<0b001110, (outs GRRegs:$dst), (ins GRRegs:$r),
801 "getts $dst, res[$r]",
802 [(set GRRegs:$dst, (int_xcore_getts GRRegs:$r))]>;
804 def SETPT_2r : _FR2R<0b001111, (outs), (ins GRRegs:$r, GRRegs:$val),
805 "setpt res[$r], $val",
806 [(int_xcore_setpt GRRegs:$r, GRRegs:$val)]>;
808 def OUTCT_2r : _F2R<0b010010, (outs), (ins GRRegs:$r, GRRegs:$val),
809 "outct res[$r], $val",
810 [(int_xcore_outct GRRegs:$r, GRRegs:$val)]>;
812 def OUTCT_rus : _FRUS<0b010011, (outs), (ins GRRegs:$r, i32imm:$val),
813 "outct res[$r], $val",
814 [(int_xcore_outct GRRegs:$r, immUs:$val)]>;
816 def OUTT_2r : _FR2R<0b000011, (outs), (ins GRRegs:$r, GRRegs:$val),
817 "outt res[$r], $val",
818 [(int_xcore_outt GRRegs:$r, GRRegs:$val)]>;
820 def OUT_2r : _FR2R<0b101010, (outs), (ins GRRegs:$r, GRRegs:$val),
822 [(int_xcore_out GRRegs:$r, GRRegs:$val)]>;
824 let Constraints = "$src = $dst" in
826 _F2RSrcDst<0b101011, (outs GRRegs:$dst), (ins GRRegs:$src, GRRegs:$r),
827 "outshr res[$r], $src",
828 [(set GRRegs:$dst, (int_xcore_outshr GRRegs:$r, GRRegs:$src))]>;
830 def INCT_2r : _F2R<0b100001, (outs GRRegs:$dst), (ins GRRegs:$r),
831 "inct $dst, res[$r]",
832 [(set GRRegs:$dst, (int_xcore_inct GRRegs:$r))]>;
834 def INT_2r : _F2R<0b100011, (outs GRRegs:$dst), (ins GRRegs:$r),
836 [(set GRRegs:$dst, (int_xcore_int GRRegs:$r))]>;
838 def IN_2r : _F2R<0b101100, (outs GRRegs:$dst), (ins GRRegs:$r),
840 [(set GRRegs:$dst, (int_xcore_in GRRegs:$r))]>;
842 let Constraints = "$src = $dst" in
844 _F2RSrcDst<0b101101, (outs GRRegs:$dst), (ins GRRegs:$src, GRRegs:$r),
845 "inshr $dst, res[$r]",
846 [(set GRRegs:$dst, (int_xcore_inshr GRRegs:$r, GRRegs:$src))]>;
848 def CHKCT_2r : _F2R<0b110010, (outs), (ins GRRegs:$r, GRRegs:$val),
849 "chkct res[$r], $val",
850 [(int_xcore_chkct GRRegs:$r, GRRegs:$val)]>;
852 def CHKCT_rus : _FRUSBitp<0b110011, (outs), (ins GRRegs:$r, i32imm:$val),
853 "chkct res[$r], $val",
854 [(int_xcore_chkct GRRegs:$r, immUs:$val)]>;
856 def TESTCT_2r : _F2R<0b101111, (outs GRRegs:$dst), (ins GRRegs:$src),
857 "testct $dst, res[$src]",
858 [(set GRRegs:$dst, (int_xcore_testct GRRegs:$src))]>;
860 def TESTWCT_2r : _F2R<0b110001, (outs GRRegs:$dst), (ins GRRegs:$src),
861 "testwct $dst, res[$src]",
862 [(set GRRegs:$dst, (int_xcore_testwct GRRegs:$src))]>;
864 def SETD_2r : _FR2R<0b000101, (outs), (ins GRRegs:$r, GRRegs:$val),
865 "setd res[$r], $val",
866 [(int_xcore_setd GRRegs:$r, GRRegs:$val)]>;
868 def SETPSC_l2r : _FR2R<0b110000, (outs), (ins GRRegs:$src1, GRRegs:$src2),
869 "setpsc res[$src1], $src2",
870 [(int_xcore_setpsc GRRegs:$src1, GRRegs:$src2)]>;
872 def GETST_2r : _F2R<0b000001, (outs GRRegs:$dst), (ins GRRegs:$r),
873 "getst $dst, res[$r]",
874 [(set GRRegs:$dst, (int_xcore_getst GRRegs:$r))]>;
876 def INITSP_2r : _F2R<0b000100, (outs), (ins GRRegs:$src, GRRegs:$t),
877 "init t[$t]:sp, $src",
878 [(int_xcore_initsp GRRegs:$t, GRRegs:$src)]>;
880 def INITPC_2r : _F2R<0b000000, (outs), (ins GRRegs:$src, GRRegs:$t),
881 "init t[$t]:pc, $src",
882 [(int_xcore_initpc GRRegs:$t, GRRegs:$src)]>;
884 def INITCP_2r : _F2R<0b000110, (outs), (ins GRRegs:$src, GRRegs:$t),
885 "init t[$t]:cp, $src",
886 [(int_xcore_initcp GRRegs:$t, GRRegs:$src)]>;
888 def INITDP_2r : _F2R<0b000010, (outs), (ins GRRegs:$src, GRRegs:$t),
889 "init t[$t]:dp, $src",
890 [(int_xcore_initdp GRRegs:$t, GRRegs:$src)]>;
892 def PEEK_2r : _F2R<0b101110, (outs GRRegs:$dst), (ins GRRegs:$src),
893 "peek $dst, res[$src]",
894 [(set GRRegs:$dst, (int_xcore_peek GRRegs:$src))]>;
896 def ENDIN_2r : _F2R<0b100101, (outs GRRegs:$dst), (ins GRRegs:$src),
897 "endin $dst, res[$src]",
898 [(set GRRegs:$dst, (int_xcore_endin GRRegs:$src))]>;
902 def BITREV_l2r : _FL2R<0b0000011000, (outs GRRegs:$dst), (ins GRRegs:$src),
904 [(set GRRegs:$dst, (int_xcore_bitrev GRRegs:$src))]>;
906 def BYTEREV_l2r : _FL2R<0b0000011001, (outs GRRegs:$dst), (ins GRRegs:$src),
907 "byterev $dst, $src",
908 [(set GRRegs:$dst, (bswap GRRegs:$src))]>;
910 def CLZ_l2r : _FL2R<0b000111000, (outs GRRegs:$dst), (ins GRRegs:$src),
912 [(set GRRegs:$dst, (ctlz GRRegs:$src))]>;
914 def SETC_l2r : _FL2R<0b0010111001, (outs), (ins GRRegs:$r, GRRegs:$val),
915 "setc res[$r], $val",
916 [(int_xcore_setc GRRegs:$r, GRRegs:$val)]>;
918 def SETTW_l2r : _FLR2R<0b0010011001, (outs), (ins GRRegs:$r, GRRegs:$val),
919 "settw res[$r], $val",
920 [(int_xcore_settw GRRegs:$r, GRRegs:$val)]>;
922 def GETPS_l2r : _FL2R<0b0001011001, (outs GRRegs:$dst), (ins GRRegs:$src),
923 "get $dst, ps[$src]",
924 [(set GRRegs:$dst, (int_xcore_getps GRRegs:$src))]>;
926 def SETPS_l2r : _FLR2R<0b0001111000, (outs), (ins GRRegs:$src1, GRRegs:$src2),
927 "set ps[$src1], $src2",
928 [(int_xcore_setps GRRegs:$src1, GRRegs:$src2)]>;
930 def INITLR_l2r : _FL2R<0b0001011000, (outs), (ins GRRegs:$src, GRRegs:$t),
931 "init t[$t]:lr, $src",
932 [(int_xcore_initlr GRRegs:$t, GRRegs:$src)]>;
934 def SETCLK_l2r : _FLR2R<0b0000111001, (outs), (ins GRRegs:$src1, GRRegs:$src2),
935 "setclk res[$src1], $src2",
936 [(int_xcore_setclk GRRegs:$src1, GRRegs:$src2)]>;
938 def SETRDY_l2r : _FLR2R<0b0010111000, (outs), (ins GRRegs:$src1, GRRegs:$src2),
939 "setrdy res[$src1], $src2",
940 [(int_xcore_setrdy GRRegs:$src1, GRRegs:$src2)]>;
943 // TODO edu, eeu, waitet, waitef, tstart, clrtp
944 // setdp, setcp, setev, kcall
946 def MSYNC_1r : _F1R<0b000111, (outs), (ins GRRegs:$a),
948 [(int_xcore_msync GRRegs:$a)]>;
949 def MJOIN_1r : _F1R<0b000101, (outs), (ins GRRegs:$a),
951 [(int_xcore_mjoin GRRegs:$a)]>;
953 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
954 def BAU_1r : _F1R<0b001001, (outs), (ins GRRegs:$a),
956 [(brind GRRegs:$a)]>;
958 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
959 def BR_JT : PseudoInstXCore<(outs), (ins InlineJT:$t, GRRegs:$i),
961 [(XCoreBR_JT tjumptable:$t, GRRegs:$i)]>;
963 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
964 def BR_JT32 : PseudoInstXCore<(outs), (ins InlineJT32:$t, GRRegs:$i),
966 [(XCoreBR_JT32 tjumptable:$t, GRRegs:$i)]>;
968 let Defs=[SP], neverHasSideEffects=1 in
969 def SETSP_1r : _F1R<0b001011, (outs), (ins GRRegs:$a),
973 let hasCtrlDep = 1 in
974 def ECALLT_1r : _F1R<0b010011, (outs), (ins GRRegs:$a),
978 let hasCtrlDep = 1 in
979 def ECALLF_1r : _F1R<0b010010, (outs), (ins GRRegs:$a),
984 // All calls clobber the link register and the non-callee-saved registers:
985 Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in {
986 def BLA_1r : _F1R<0b001000, (outs), (ins GRRegs:$a),
988 [(XCoreBranchLink GRRegs:$a)]>;
991 def SYNCR_1r : _F1R<0b100001, (outs), (ins GRRegs:$a),
993 [(int_xcore_syncr GRRegs:$a)]>;
995 def FREER_1r : _F1R<0b000100, (outs), (ins GRRegs:$a),
997 [(int_xcore_freer GRRegs:$a)]>;
1000 def SETV_1r : _F1R<0b010001, (outs), (ins GRRegs:$a),
1001 "setv res[$a], r11",
1002 [(int_xcore_setv GRRegs:$a, R11)]>;
1004 def SETEV_1r : _F1R<0b001111, (outs), (ins GRRegs:$a),
1005 "setev res[$a], r11",
1006 [(int_xcore_setev GRRegs:$a, R11)]>;
1009 def EEU_1r : _F1R<0b000001, (outs), (ins GRRegs:$a),
1011 [(int_xcore_eeu GRRegs:$a)]>;
1013 // Zero operand short
1014 // TODO freet, ldspc, stspc, ldssr, stssr, ldsed, stsed,
1015 // stet, getkep, getksp, setkep, getid, kret, dcall, dret,
1018 def CLRE_0R : _F0R<0b0000001101, (outs), (ins), "clre", [(int_xcore_clre)]>;
1020 let Defs = [R11] in {
1021 def GETID_0R : _F0R<0b0001001110, (outs), (ins),
1023 [(set R11, (int_xcore_getid))]>;
1025 def GETED_0R : _F0R<0b0000111110, (outs), (ins),
1027 [(set R11, (int_xcore_geted))]>;
1029 def GETET_0R : _F0R<0b0000111111, (outs), (ins),
1031 [(set R11, (int_xcore_getet))]>;
1034 def SSYNC_0r : _F0R<0b0000001110, (outs), (ins),
1036 [(int_xcore_ssync)]>;
1038 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1,
1039 hasSideEffects = 1 in
1040 def WAITEU_0R : _F0R<0b0000001100, (outs), (ins),
1042 [(brind (int_xcore_waitevent))]>;
1044 //===----------------------------------------------------------------------===//
1045 // Non-Instruction Patterns
1046 //===----------------------------------------------------------------------===//
1048 def : Pat<(XCoreBranchLink tglobaladdr:$addr), (BL_lu10 tglobaladdr:$addr)>;
1049 def : Pat<(XCoreBranchLink texternalsym:$addr), (BL_lu10 texternalsym:$addr)>;
1052 def : Pat<(sext_inreg GRRegs:$b, i1), (SEXT_rus GRRegs:$b, 1)>;
1053 def : Pat<(sext_inreg GRRegs:$b, i8), (SEXT_rus GRRegs:$b, 8)>;
1054 def : Pat<(sext_inreg GRRegs:$b, i16), (SEXT_rus GRRegs:$b, 16)>;
1057 def : Pat<(zextloadi8 (add GRRegs:$addr, GRRegs:$offset)),
1058 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>;
1059 def : Pat<(zextloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>;
1061 def : Pat<(sextloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)),
1062 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>;
1063 def : Pat<(sextloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>;
1065 def : Pat<(load (ldawf GRRegs:$addr, GRRegs:$offset)),
1066 (LDW_3r GRRegs:$addr, GRRegs:$offset)>;
1067 def : Pat<(load (add GRRegs:$addr, immUs4:$offset)),
1068 (LDW_2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;
1069 def : Pat<(load GRRegs:$addr), (LDW_2rus GRRegs:$addr, 0)>;
1072 def : Pat<(extloadi8 (add GRRegs:$addr, GRRegs:$offset)),
1073 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>;
1074 def : Pat<(extloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>;
1075 def : Pat<(extloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)),
1076 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>;
1077 def : Pat<(extloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>;
1080 def : Pat<(truncstorei8 GRRegs:$val, (add GRRegs:$addr, GRRegs:$offset)),
1081 (ST8_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
1082 def : Pat<(truncstorei8 GRRegs:$val, GRRegs:$addr),
1083 (ST8_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>;
1085 def : Pat<(truncstorei16 GRRegs:$val, (lda16f GRRegs:$addr, GRRegs:$offset)),
1086 (ST16_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
1087 def : Pat<(truncstorei16 GRRegs:$val, GRRegs:$addr),
1088 (ST16_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>;
1090 def : Pat<(store GRRegs:$val, (ldawf GRRegs:$addr, GRRegs:$offset)),
1091 (STW_3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
1092 def : Pat<(store GRRegs:$val, (add GRRegs:$addr, immUs4:$offset)),
1093 (STW_2rus GRRegs:$val, GRRegs:$addr, (div4_xform immUs4:$offset))>;
1094 def : Pat<(store GRRegs:$val, GRRegs:$addr),
1095 (STW_2rus GRRegs:$val, GRRegs:$addr, 0)>;
1098 def : Pat<(cttz GRRegs:$src), (CLZ_l2r (BITREV_l2r GRRegs:$src))>;
1101 def : Pat<(trap), (ECALLF_1r (LDC_ru6 0))>;
1107 // unconditional branch
1108 def : Pat<(br bb:$addr), (BRFU_lu6 bb:$addr)>;
1110 // direct match equal/notequal zero brcond
1111 def : Pat<(brcond (setne GRRegs:$lhs, 0), bb:$dst),
1112 (BRFT_lru6 GRRegs:$lhs, bb:$dst)>;
1113 def : Pat<(brcond (seteq GRRegs:$lhs, 0), bb:$dst),
1114 (BRFF_lru6 GRRegs:$lhs, bb:$dst)>;
1116 def : Pat<(brcond (setle GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1117 (BRFF_lru6 (LSS_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>;
1118 def : Pat<(brcond (setule GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1119 (BRFF_lru6 (LSU_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>;
1120 def : Pat<(brcond (setge GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1121 (BRFF_lru6 (LSS_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;
1122 def : Pat<(brcond (setuge GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1123 (BRFF_lru6 (LSU_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;
1124 def : Pat<(brcond (setne GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1125 (BRFF_lru6 (EQ_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;
1126 def : Pat<(brcond (setne GRRegs:$lhs, immUs:$rhs), bb:$dst),
1127 (BRFF_lru6 (EQ_2rus GRRegs:$lhs, immUs:$rhs), bb:$dst)>;
1129 // generic brcond pattern
1130 def : Pat<(brcond GRRegs:$cond, bb:$addr), (BRFT_lru6 GRRegs:$cond, bb:$addr)>;
1137 // direct match equal/notequal zero select
1138 def : Pat<(select (setne GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
1139 (SELECT_CC GRRegs:$lhs, GRRegs:$T, GRRegs:$F)>;
1141 def : Pat<(select (seteq GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
1142 (SELECT_CC GRRegs:$lhs, GRRegs:$F, GRRegs:$T)>;
1144 def : Pat<(select (setle GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1145 (SELECT_CC (LSS_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;
1146 def : Pat<(select (setule GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1147 (SELECT_CC (LSU_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;
1148 def : Pat<(select (setge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1149 (SELECT_CC (LSS_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1150 def : Pat<(select (setuge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1151 (SELECT_CC (LSU_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1152 def : Pat<(select (setne GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1153 (SELECT_CC (EQ_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1154 def : Pat<(select (setne GRRegs:$lhs, immUs:$rhs), GRRegs:$T, GRRegs:$F),
1155 (SELECT_CC (EQ_2rus GRRegs:$lhs, immUs:$rhs), GRRegs:$F, GRRegs:$T)>;
1158 /// setcc patterns, only matched when none of the above brcond
1162 // setcc 2 register operands
1163 def : Pat<(setle GRRegs:$lhs, GRRegs:$rhs),
1164 (EQ_2rus (LSS_3r GRRegs:$rhs, GRRegs:$lhs), 0)>;
1165 def : Pat<(setule GRRegs:$lhs, GRRegs:$rhs),
1166 (EQ_2rus (LSU_3r GRRegs:$rhs, GRRegs:$lhs), 0)>;
1168 def : Pat<(setgt GRRegs:$lhs, GRRegs:$rhs),
1169 (LSS_3r GRRegs:$rhs, GRRegs:$lhs)>;
1170 def : Pat<(setugt GRRegs:$lhs, GRRegs:$rhs),
1171 (LSU_3r GRRegs:$rhs, GRRegs:$lhs)>;
1173 def : Pat<(setge GRRegs:$lhs, GRRegs:$rhs),
1174 (EQ_2rus (LSS_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;
1175 def : Pat<(setuge GRRegs:$lhs, GRRegs:$rhs),
1176 (EQ_2rus (LSU_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;
1178 def : Pat<(setlt GRRegs:$lhs, GRRegs:$rhs),
1179 (LSS_3r GRRegs:$lhs, GRRegs:$rhs)>;
1180 def : Pat<(setult GRRegs:$lhs, GRRegs:$rhs),
1181 (LSU_3r GRRegs:$lhs, GRRegs:$rhs)>;
1183 def : Pat<(setne GRRegs:$lhs, GRRegs:$rhs),
1184 (EQ_2rus (EQ_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;
1186 def : Pat<(seteq GRRegs:$lhs, GRRegs:$rhs),
1187 (EQ_3r GRRegs:$lhs, GRRegs:$rhs)>;
1189 // setcc reg/imm operands
1190 def : Pat<(seteq GRRegs:$lhs, immUs:$rhs),
1191 (EQ_2rus GRRegs:$lhs, immUs:$rhs)>;
1192 def : Pat<(setne GRRegs:$lhs, immUs:$rhs),
1193 (EQ_2rus (EQ_2rus GRRegs:$lhs, immUs:$rhs), 0)>;
1196 def : Pat<(add GRRegs:$addr, immUs4:$offset),
1197 (LDAWF_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;
1199 def : Pat<(sub GRRegs:$addr, immUs4:$offset),
1200 (LDAWB_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;
1202 def : Pat<(and GRRegs:$val, immMskBitp:$mask),
1203 (ZEXT_rus GRRegs:$val, (msksize_xform immMskBitp:$mask))>;
1205 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1206 def : Pat<(add GRRegs:$src1, immUsNeg:$src2),
1207 (SUB_2rus GRRegs:$src1, (neg_xform immUsNeg:$src2))>;
1209 def : Pat<(add GRRegs:$src1, immUs4Neg:$src2),
1210 (LDAWB_l2rus GRRegs:$src1, (div4neg_xform immUs4Neg:$src2))>;
1216 def : Pat<(mul GRRegs:$src, 3),
1217 (LDA16F_l3r GRRegs:$src, GRRegs:$src)>;
1219 def : Pat<(mul GRRegs:$src, 5),
1220 (LDAWF_l3r GRRegs:$src, GRRegs:$src)>;
1222 def : Pat<(mul GRRegs:$src, -3),
1223 (LDAWB_l3r GRRegs:$src, GRRegs:$src)>;
1225 // ashr X, 32 is equivalent to ashr X, 31 on the XCore.
1226 def : Pat<(sra GRRegs:$src, 31),
1227 (ASHR_l2rus GRRegs:$src, 32)>;
1229 def : Pat<(brcond (setlt GRRegs:$lhs, 0), bb:$dst),
1230 (BRFT_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>;
1232 // setge X, 0 is canonicalized to setgt X, -1
1233 def : Pat<(brcond (setgt GRRegs:$lhs, -1), bb:$dst),
1234 (BRFF_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>;
1236 def : Pat<(select (setlt GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
1237 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$T, GRRegs:$F)>;
1239 def : Pat<(select (setgt GRRegs:$lhs, -1), GRRegs:$T, GRRegs:$F),
1240 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$F, GRRegs:$T)>;
1242 def : Pat<(setgt GRRegs:$lhs, -1),
1243 (EQ_2rus (ASHR_l2rus GRRegs:$lhs, 32), 0)>;
1245 def : Pat<(sra (shl GRRegs:$src, immBpwSubBitp:$imm), immBpwSubBitp:$imm),
1246 (SEXT_rus GRRegs:$src, (bpwsub_xform immBpwSubBitp:$imm))>;