1 //===- XCoreInstrInfo.cpp - XCore Instruction Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the XCore implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "XCoreMachineFunctionInfo.h"
15 #include "XCoreInstrInfo.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineLocation.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "XCoreGenInstrInfo.inc"
23 #include "llvm/Support/Debug.h"
28 // XCore Condition Codes
39 XCoreInstrInfo::XCoreInstrInfo(void)
40 : TargetInstrInfoImpl(XCoreInsts, array_lengthof(XCoreInsts)),
44 static bool isZeroImm(const MachineOperand &op) {
45 return op.isImm() && op.getImm() == 0;
48 /// Return true if the instruction is a register to register move and
49 /// leave the source and dest operands in the passed parameters.
51 bool XCoreInstrInfo::isMoveInstr(const MachineInstr &MI,
52 unsigned &SrcReg, unsigned &DstReg,
53 unsigned &SrcSR, unsigned &DstSR) const {
54 SrcSR = DstSR = 0; // No sub-registers.
56 // We look for 4 kinds of patterns here:
61 if ((MI.getOpcode() == XCore::ADD_2rus || MI.getOpcode() == XCore::SUB_2rus)
62 && isZeroImm(MI.getOperand(2))) {
63 DstReg = MI.getOperand(0).getReg();
64 SrcReg = MI.getOperand(1).getReg();
66 } else if ((MI.getOpcode() == XCore::OR_3r || MI.getOpcode() == XCore::AND_3r)
67 && MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
68 DstReg = MI.getOperand(0).getReg();
69 SrcReg = MI.getOperand(1).getReg();
75 /// isLoadFromStackSlot - If the specified machine instruction is a direct
76 /// load from a stack slot, return the virtual or physical register number of
77 /// the destination along with the FrameIndex of the loaded stack slot. If
78 /// not, return 0. This predicate must return 0 if the instruction has
79 /// any side effects other than loading from the stack slot.
81 XCoreInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const{
82 int Opcode = MI->getOpcode();
83 if (Opcode == XCore::LDWFI)
85 if ((MI->getOperand(1).isFI()) && // is a stack slot
86 (MI->getOperand(2).isImm()) && // the imm is zero
87 (isZeroImm(MI->getOperand(2))))
89 FrameIndex = MI->getOperand(1).getIndex();
90 return MI->getOperand(0).getReg();
96 /// isStoreToStackSlot - If the specified machine instruction is a direct
97 /// store to a stack slot, return the virtual or physical register number of
98 /// the source reg along with the FrameIndex of the loaded stack slot. If
99 /// not, return 0. This predicate must return 0 if the instruction has
100 /// any side effects other than storing to the stack slot.
102 XCoreInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
103 int &FrameIndex) const {
104 int Opcode = MI->getOpcode();
105 if (Opcode == XCore::STWFI)
107 if ((MI->getOperand(1).isFI()) && // is a stack slot
108 (MI->getOperand(2).isImm()) && // the imm is zero
109 (isZeroImm(MI->getOperand(2))))
111 FrameIndex = MI->getOperand(1).getIndex();
112 return MI->getOperand(0).getReg();
118 /// isInvariantLoad - Return true if the specified instruction (which is marked
119 /// mayLoad) is loading from a location whose value is invariant across the
120 /// function. For example, loading a value from the constant pool or from
121 /// from the argument area of a function if it does not change. This should
122 /// only return true of *all* loads the instruction does are invariant (if it
123 /// does multiple loads).
125 XCoreInstrInfo::isInvariantLoad(const MachineInstr *MI) const {
126 // Loads from constants pools and loads from invariant argument slots are
128 int Opcode = MI->getOpcode();
129 if (Opcode == XCore::LDWCP_ru6 || Opcode == XCore::LDWCP_lru6) {
130 return MI->getOperand(1).isCPI();
133 if (isLoadFromStackSlot(MI, FrameIndex)) {
134 const MachineFrameInfo &MFI =
135 *MI->getParent()->getParent()->getFrameInfo();
136 return MFI.isFixedObjectIndex(FrameIndex) &&
137 MFI.isImmutableObjectIndex(FrameIndex);
142 //===----------------------------------------------------------------------===//
144 //===----------------------------------------------------------------------===//
146 static inline bool IsBRU(unsigned BrOpc) {
147 return BrOpc == XCore::BRFU_u6
148 || BrOpc == XCore::BRFU_lu6
149 || BrOpc == XCore::BRBU_u6
150 || BrOpc == XCore::BRBU_lu6;
153 static inline bool IsBRT(unsigned BrOpc) {
154 return BrOpc == XCore::BRFT_ru6
155 || BrOpc == XCore::BRFT_lru6
156 || BrOpc == XCore::BRBT_ru6
157 || BrOpc == XCore::BRBT_lru6;
160 static inline bool IsBRF(unsigned BrOpc) {
161 return BrOpc == XCore::BRFF_ru6
162 || BrOpc == XCore::BRFF_lru6
163 || BrOpc == XCore::BRBF_ru6
164 || BrOpc == XCore::BRBF_lru6;
167 static inline bool IsCondBranch(unsigned BrOpc) {
168 return IsBRF(BrOpc) || IsBRT(BrOpc);
171 /// GetCondFromBranchOpc - Return the XCore CC that matches
172 /// the correspondent Branch instruction opcode.
173 static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc)
176 return XCore::COND_TRUE;
177 } else if (IsBRF(BrOpc)) {
178 return XCore::COND_FALSE;
180 return XCore::COND_INVALID;
184 /// GetCondBranchFromCond - Return the Branch instruction
185 /// opcode that matches the cc.
186 static inline unsigned GetCondBranchFromCond(XCore::CondCode CC)
189 default: assert(0 && "Illegal condition code!");
190 case XCore::COND_TRUE : return XCore::BRFT_lru6;
191 case XCore::COND_FALSE : return XCore::BRFF_lru6;
195 /// GetOppositeBranchCondition - Return the inverse of the specified
196 /// condition, e.g. turning COND_E to COND_NE.
197 static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC)
200 default: assert(0 && "Illegal condition code!");
201 case XCore::COND_TRUE : return XCore::COND_FALSE;
202 case XCore::COND_FALSE : return XCore::COND_TRUE;
206 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
207 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
208 /// implemented for a target). Upon success, this returns false and returns
209 /// with the following information in various cases:
211 /// 1. If this block ends with no branches (it just falls through to its succ)
212 /// just return false, leaving TBB/FBB null.
213 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
214 /// the destination block.
215 /// 3. If this block ends with an conditional branch and it falls through to
216 /// an successor block, it sets TBB to be the branch destination block and a
217 /// list of operands that evaluate the condition. These
218 /// operands can be passed to other TargetInstrInfo methods to create new
220 /// 4. If this block ends with an conditional branch and an unconditional
221 /// block, it returns the 'true' destination in TBB, the 'false' destination
222 /// in FBB, and a list of operands that evaluate the condition. These
223 /// operands can be passed to other TargetInstrInfo methods to create new
226 /// Note that RemoveBranch and InsertBranch must be implemented to support
227 /// cases where this method returns success.
230 XCoreInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
231 MachineBasicBlock *&FBB,
232 SmallVectorImpl<MachineOperand> &Cond) const {
233 // If the block has no terminators, it just falls into the block after it.
234 MachineBasicBlock::iterator I = MBB.end();
235 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
238 // Get the last instruction in the block.
239 MachineInstr *LastInst = I;
241 // If there is only one terminator instruction, process it.
242 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
243 if (IsBRU(LastInst->getOpcode())) {
244 TBB = LastInst->getOperand(0).getMBB();
248 XCore::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
249 if (BranchCode == XCore::COND_INVALID)
250 return true; // Can't handle indirect branch.
252 // Conditional branch
253 // Block ends with fall-through condbranch.
255 TBB = LastInst->getOperand(1).getMBB();
256 Cond.push_back(MachineOperand::CreateImm(BranchCode));
257 Cond.push_back(LastInst->getOperand(0));
261 // Get the instruction before it if it's a terminator.
262 MachineInstr *SecondLastInst = I;
264 // If there are three terminators, we don't know what sort of block this is.
265 if (SecondLastInst && I != MBB.begin() &&
266 isUnpredicatedTerminator(--I))
269 unsigned SecondLastOpc = SecondLastInst->getOpcode();
270 XCore::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc);
272 // If the block ends with conditional branch followed by unconditional,
274 if (BranchCode != XCore::COND_INVALID
275 && IsBRU(LastInst->getOpcode())) {
277 TBB = SecondLastInst->getOperand(1).getMBB();
278 Cond.push_back(MachineOperand::CreateImm(BranchCode));
279 Cond.push_back(SecondLastInst->getOperand(0));
281 FBB = LastInst->getOperand(0).getMBB();
285 // If the block ends with two unconditional branches, handle it. The second
286 // one is not executed, so remove it.
287 if (IsBRU(SecondLastInst->getOpcode()) &&
288 IsBRU(LastInst->getOpcode())) {
289 TBB = SecondLastInst->getOperand(0).getMBB();
291 I->eraseFromParent();
295 // Otherwise, can't handle this.
300 XCoreInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
301 MachineBasicBlock *FBB,
302 const SmallVectorImpl<MachineOperand> &Cond)const{
303 // Shouldn't be a fall through.
304 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
305 assert((Cond.size() == 2 || Cond.size() == 0) &&
306 "Unexpected number of components!");
308 if (FBB == 0) { // One way branch.
310 // Unconditional branch
311 BuildMI(&MBB, get(XCore::BRFU_lu6)).addMBB(TBB);
313 // Conditional branch.
314 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
315 BuildMI(&MBB, get(Opc)).addReg(Cond[1].getReg())
321 // Two-way Conditional branch.
322 assert(Cond.size() == 2 && "Unexpected number of components!");
323 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
324 BuildMI(&MBB, get(Opc)).addReg(Cond[1].getReg())
326 BuildMI(&MBB, get(XCore::BRFU_lu6)).addMBB(FBB);
331 XCoreInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
332 MachineBasicBlock::iterator I = MBB.end();
333 if (I == MBB.begin()) return 0;
335 if (!IsBRU(I->getOpcode()) && !IsCondBranch(I->getOpcode()))
338 // Remove the branch.
339 I->eraseFromParent();
343 if (I == MBB.begin()) return 1;
345 if (!IsCondBranch(I->getOpcode()))
348 // Remove the branch.
349 I->eraseFromParent();
353 bool XCoreInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
354 MachineBasicBlock::iterator I,
355 unsigned DestReg, unsigned SrcReg,
356 const TargetRegisterClass *DestRC,
357 const TargetRegisterClass *SrcRC) const {
358 if (DestRC == SrcRC) {
359 if (DestRC == XCore::GRRegsRegisterClass) {
360 BuildMI(MBB, I, get(XCore::ADD_2rus), DestReg).addReg(SrcReg).addImm(0);
367 if (SrcRC == XCore::RRegsRegisterClass && SrcReg == XCore::SP &&
368 DestRC == XCore::GRRegsRegisterClass) {
369 BuildMI(MBB, I, get(XCore::LDAWSP_ru6), DestReg).addImm(0);
372 if (DestRC == XCore::RRegsRegisterClass && DestReg == XCore::SP &&
373 SrcRC == XCore::GRRegsRegisterClass) {
374 BuildMI(MBB, I, get(XCore::SETSP_1r)).addReg(SrcReg);
380 void XCoreInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
381 MachineBasicBlock::iterator I,
382 unsigned SrcReg, bool isKill, int FrameIndex,
383 const TargetRegisterClass *RC) const
385 BuildMI(MBB, I, get(XCore::STWFI)).addReg(SrcReg, false, false, isKill)
386 .addFrameIndex(FrameIndex).addImm(0);
389 void XCoreInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
390 bool isKill, SmallVectorImpl<MachineOperand> &Addr,
391 const TargetRegisterClass *RC,
392 SmallVectorImpl<MachineInstr*> &NewMIs) const
394 assert(0 && "unimplemented\n");
397 void XCoreInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
398 MachineBasicBlock::iterator I,
399 unsigned DestReg, int FrameIndex,
400 const TargetRegisterClass *RC) const
402 BuildMI(MBB, I, get(XCore::LDWFI), DestReg).addFrameIndex(FrameIndex)
406 void XCoreInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
407 SmallVectorImpl<MachineOperand> &Addr,
408 const TargetRegisterClass *RC,
409 SmallVectorImpl<MachineInstr*> &NewMIs) const
411 assert(0 && "unimplemented\n");
414 bool XCoreInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
415 MachineBasicBlock::iterator MI,
416 const std::vector<CalleeSavedInfo> &CSI) const
421 MachineFunction *MF = MBB.getParent();
422 const MachineFrameInfo *MFI = MF->getFrameInfo();
423 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
424 XCoreFunctionInfo *XFI = MF->getInfo<XCoreFunctionInfo>();
426 bool emitFrameMoves = XCoreRegisterInfo::needsFrameMoves(*MF);
428 for (std::vector<CalleeSavedInfo>::const_iterator it = CSI.begin();
429 it != CSI.end(); ++it) {
430 // Add the callee-saved register as live-in. It's killed at the spill.
431 MBB.addLiveIn(it->getReg());
433 storeRegToStackSlot(MBB, MI, it->getReg(), true,
434 it->getFrameIdx(), it->getRegClass());
435 if (emitFrameMoves) {
436 unsigned SaveLabelId = MMI->NextLabelID();
437 BuildMI(MBB, MI, get(XCore::DBG_LABEL)).addImm(SaveLabelId);
438 XFI->getSpillLabels().push_back(
439 std::pair<unsigned, CalleeSavedInfo>(SaveLabelId, *it));
445 bool XCoreInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
446 MachineBasicBlock::iterator MI,
447 const std::vector<CalleeSavedInfo> &CSI) const
449 bool AtStart = MI == MBB.begin();
450 MachineBasicBlock::iterator BeforeI = MI;
453 for (std::vector<CalleeSavedInfo>::const_iterator it = CSI.begin();
454 it != CSI.end(); ++it) {
456 loadRegFromStackSlot(MBB, MI, it->getReg(),
459 assert(MI != MBB.begin() &&
460 "loadRegFromStackSlot didn't insert any code!");
461 // Insert in reverse order. loadRegFromStackSlot can insert multiple
473 /// BlockHasNoFallThrough - Analyse if MachineBasicBlock does not
474 /// fall-through into its successor block.
475 bool XCoreInstrInfo::
476 BlockHasNoFallThrough(const MachineBasicBlock &MBB) const
478 if (MBB.empty()) return false;
480 switch (MBB.back().getOpcode()) {
481 case XCore::RETSP_u6: // Return.
482 case XCore::RETSP_lu6:
483 case XCore::BAU_1r: // Indirect branch.
484 case XCore::BRFU_u6: // Uncond branch.
485 case XCore::BRFU_lu6:
487 case XCore::BRBU_lu6:
489 default: return false;
493 /// ReverseBranchCondition - Return the inverse opcode of the
494 /// specified Branch instruction.
495 bool XCoreInstrInfo::
496 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
498 assert((Cond.size() == 2) &&
499 "Invalid XCore branch condition!");
500 Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Cond[0].getImm()));