lib/Target/XCore/Disassembler/XCoreDisassembler.cpp

   1 //===- XCoreDisassembler.cpp - Disassembler for XCore -----------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 ///
  10 /// \file
  11 /// \brief This file is part of the XCore Disassembler.
  12 ///
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "XCore.h"
  16 #include "XCoreRegisterInfo.h"
  17 #include "llvm/MC/MCDisassembler.h"
  18 #include "llvm/MC/MCFixedLenDisassembler.h"
  19 #include "llvm/MC/MCInst.h"
  20 #include "llvm/MC/MCSubtargetInfo.h"
  21 #include "llvm/Support/MemoryObject.h"
  22 #include "llvm/Support/TargetRegistry.h"
  23
  24 using namespace llvm;
  25
  26 typedef MCDisassembler::DecodeStatus DecodeStatus;
  27
  28 namespace {
  29
  30 /// \brief A disassembler class for XCore.
  31 class XCoreDisassembler : public MCDisassembler {
  32   const MCRegisterInfo *RegInfo;
  33 public:
  34   XCoreDisassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info) :
  35     MCDisassembler(STI), RegInfo(Info) {}
  36
  37   /// \brief See MCDisassembler.
  38   virtual DecodeStatus getInstruction(MCInst &instr,
  39                                       uint64_t &size,
  40                                       const MemoryObject &region,
  41                                       uint64_t address,
  42                                       raw_ostream &vStream,
  43                                       raw_ostream &cStream) const;
  44
  45   const MCRegisterInfo *getRegInfo() const { return RegInfo; }
  46 };
  47 }
  48
  49 static bool readInstruction16(const MemoryObject &region,
  50                               uint64_t address,
  51                               uint64_t &size,
  52                               uint16_t &insn) {
  53   uint8_t Bytes[4];
  54
  55   // We want to read exactly 2 Bytes of data.
  56   if (region.readBytes(address, 2, Bytes, NULL) == -1) {
  57     size = 0;
  58     return false;
  59   }
  60   // Encoded as a little-endian 16-bit word in the stream.
  61   insn = (Bytes[0] <<  0) | (Bytes[1] <<  8);
  62   return true;
  63 }
  64
  65 static bool readInstruction32(const MemoryObject &region,
  66                               uint64_t address,
  67                               uint64_t &size,
  68                               uint32_t &insn) {
  69   uint8_t Bytes[4];
  70
  71   // We want to read exactly 4 Bytes of data.
  72   if (region.readBytes(address, 4, Bytes, NULL) == -1) {
  73     size = 0;
  74     return false;
  75   }
  76   // Encoded as a little-endian 32-bit word in the stream.
  77   insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
  78          (Bytes[3] << 24);
  79   return true;
  80 }
  81
  82 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
  83   const XCoreDisassembler *Dis = static_cast<const XCoreDisassembler*>(D);
  84   return *(Dis->getRegInfo()->getRegClass(RC).begin() + RegNo);
  85 }
  86
  87 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
  88                                               unsigned RegNo,
  89                                               uint64_t Address,
  90                                               const void *Decoder);
  91
  92 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
  93                                       uint64_t Address, const void *Decoder);
  94
  95 static DecodeStatus Decode2RInstruction(MCInst &Inst,
  96                                         unsigned Insn,
  97                                         uint64_t Address,
  98                                         const void *Decoder);
  99
 100 static DecodeStatus DecodeR2RInstruction(MCInst &Inst,
 101                                          unsigned Insn,
 102                                          uint64_t Address,
 103                                          const void *Decoder);
 104
 105 static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst,
 106                                               unsigned Insn,
 107                                               uint64_t Address,
 108                                               const void *Decoder);
 109
 110 static DecodeStatus DecodeRUSInstruction(MCInst &Inst,
 111                                          unsigned Insn,
 112                                          uint64_t Address,
 113                                          const void *Decoder);
 114
 115 static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst,
 116                                              unsigned Insn,
 117                                              uint64_t Address,
 118                                              const void *Decoder);
 119
 120 static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst &Inst,
 121                                                    unsigned Insn,
 122                                                    uint64_t Address,
 123                                                    const void *Decoder);
 124
 125 static DecodeStatus DecodeL2RInstruction(MCInst &Inst,
 126                                          unsigned Insn,
 127                                          uint64_t Address,
 128                                          const void *Decoder);
 129
 130 static DecodeStatus DecodeLR2RInstruction(MCInst &Inst,
 131                                           unsigned Insn,
 132                                           uint64_t Address,
 133                                           const void *Decoder);
 134
 135 static DecodeStatus Decode3RInstruction(MCInst &Inst,
 136                                         unsigned Insn,
 137                                         uint64_t Address,
 138                                         const void *Decoder);
 139
 140 #include "XCoreGenDisassemblerTables.inc"
 141
 142 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
 143                                               unsigned RegNo,
 144                                               uint64_t Address,
 145                                               const void *Decoder)
 146 {
 147   if (RegNo > 11)
 148     return MCDisassembler::Fail;
 149   unsigned Reg = getReg(Decoder, XCore::GRRegsRegClassID, RegNo);
 150   Inst.addOperand(MCOperand::CreateReg(Reg));
 151   return MCDisassembler::Success;
 152 }
 153
 154 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
 155                                       uint64_t Address, const void *Decoder) {
 156   if (Val > 11)
 157     return MCDisassembler::Fail;
 158   static unsigned Values[] = {
 159     32 /*bpw*/, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32
 160   };
 161   Inst.addOperand(MCOperand::CreateImm(Values[Val]));
 162   return MCDisassembler::Success;
 163 }
 164
 165 static DecodeStatus
 166 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) {
 167   unsigned Combined = fieldFromInstruction(Insn, 6, 5);
 168   if (Combined < 27)
 169     return MCDisassembler::Fail;
 170   if (fieldFromInstruction(Insn, 5, 1)) {
 171     if (Combined == 31)
 172       return MCDisassembler::Fail;
 173     Combined += 5;
 174   }
 175   Combined -= 27;
 176   unsigned Op1High = Combined % 3;
 177   unsigned Op2High = Combined / 3;
 178   Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2);
 179   Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2);
 180   return MCDisassembler::Success;
 181 }
 182
 183 static DecodeStatus
 184 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2,
 185                      unsigned &Op3) {
 186   unsigned Combined = fieldFromInstruction(Insn, 6, 5);
 187   if (Combined >= 27)
 188     return MCDisassembler::Fail;
 189
 190   unsigned Op1High = Combined % 3;
 191   unsigned Op2High = (Combined / 3) % 3;
 192   unsigned Op3High = Combined / 9;
 193   Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 4, 2);
 194   Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2);
 195   Op3 = (Op3High << 2) | fieldFromInstruction(Insn, 0, 2);
 196   return MCDisassembler::Success;
 197 }
 198
 199 static DecodeStatus
 200 Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
 201                          const void *Decoder) {
 202   // Try and decode as a 3R instruction.
 203   unsigned Opcode = fieldFromInstruction(Insn, 11, 5);
 204   switch (Opcode) {
 205   case 0x2:
 206     Inst.setOpcode(XCore::ADD_3r);
 207     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 208   case 0x3:
 209     Inst.setOpcode(XCore::SUB_3r);
 210     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 211   case 0x4:
 212     Inst.setOpcode(XCore::SHL_3r);
 213     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 214   case 0x5:
 215     Inst.setOpcode(XCore::SHR_3r);
 216     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 217   case 0x6:
 218     Inst.setOpcode(XCore::EQ_3r);
 219     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 220   case 0x7:
 221     Inst.setOpcode(XCore::AND_3r);
 222     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 223   case 0x8:
 224     Inst.setOpcode(XCore::OR_3r);
 225     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 226   case 0x9:
 227     Inst.setOpcode(XCore::LDW_3r);
 228     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 229   case 0x10:
 230     Inst.setOpcode(XCore::LD16S_3r);
 231     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 232   case 0x11:
 233     Inst.setOpcode(XCore::LD8U_3r);
 234     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 235   case 0x18:
 236     Inst.setOpcode(XCore::LSS_3r);
 237     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 238   case 0x19:
 239     Inst.setOpcode(XCore::LSU_3r);
 240     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 241   }
 242   return MCDisassembler::Fail;
 243 }
 244
 245 static DecodeStatus
 246 Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 247                     const void *Decoder) {
 248   unsigned Op1, Op2;
 249   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
 250   if (S != MCDisassembler::Success)
 251     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 252
 253   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 254   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 255   return S;
 256 }
 257
 258 static DecodeStatus
 259 DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 260                      const void *Decoder) {
 261   unsigned Op1, Op2;
 262   DecodeStatus S = Decode2OpInstruction(Insn, Op2, Op1);
 263   if (S != MCDisassembler::Success)
 264     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 265
 266   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 267   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 268   return S;
 269 }
 270
 271 static DecodeStatus
 272 Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 273                           const void *Decoder) {
 274   unsigned Op1, Op2;
 275   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
 276   if (S != MCDisassembler::Success)
 277     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 278
 279   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 280   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 281   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 282   return S;
 283 }
 284
 285 static DecodeStatus
 286 DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 287                      const void *Decoder) {
 288   unsigned Op1, Op2;
 289   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
 290   if (S != MCDisassembler::Success)
 291     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 292
 293   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 294   Inst.addOperand(MCOperand::CreateImm(Op2));
 295   return S;
 296 }
 297
 298 static DecodeStatus
 299 DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 300                          const void *Decoder) {
 301   unsigned Op1, Op2;
 302   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
 303   if (S != MCDisassembler::Success)
 304     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 305
 306   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 307   DecodeBitpOperand(Inst, Op2, Address, Decoder);
 308   return S;
 309 }
 310
 311 static DecodeStatus
 312 DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 313                                const void *Decoder) {
 314   unsigned Op1, Op2;
 315   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
 316   if (S != MCDisassembler::Success)
 317     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 318
 319   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 320   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 321   DecodeBitpOperand(Inst, Op2, Address, Decoder);
 322   return S;
 323 }
 324
 325 static DecodeStatus
 326 DecodeL2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 327                                const void *Decoder) {
 328   unsigned Op1, Op2;
 329   DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),
 330                                         Op1, Op2);
 331   if (S == MCDisassembler::Success) {
 332     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 333     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 334   }
 335   return S;
 336 }
 337
 338 static DecodeStatus
 339 DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 340                                const void *Decoder) {
 341   unsigned Op1, Op2;
 342   DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),
 343                                         Op1, Op2);
 344   if (S == MCDisassembler::Success) {
 345     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 346     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 347   }
 348   return S;
 349 }
 350
 351 static DecodeStatus
 352 Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 353                     const void *Decoder) {
 354   unsigned Op1, Op2, Op3;
 355   DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
 356   if (S == MCDisassembler::Success) {
 357     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 358     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 359     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
 360   }
 361   return S;
 362 }
 363
 364 MCDisassembler::DecodeStatus
 365 XCoreDisassembler::getInstruction(MCInst &instr,
 366                                   uint64_t &Size,
 367                                   const MemoryObject &Region,
 368                                   uint64_t Address,
 369                                   raw_ostream &vStream,
 370                                   raw_ostream &cStream) const {
 371   uint16_t insn16;
 372
 373   if (!readInstruction16(Region, Address, Size, insn16)) {
 374     return Fail;
 375   }
 376
 377   // Calling the auto-generated decoder function.
 378   DecodeStatus Result = decodeInstruction(DecoderTable16, instr, insn16,
 379                                           Address, this, STI);
 380   if (Result != Fail) {
 381     Size = 2;
 382     return Result;
 383   }
 384
 385   uint32_t insn32;
 386
 387   if (!readInstruction32(Region, Address, Size, insn32)) {
 388     return Fail;
 389   }
 390
 391   // Calling the auto-generated decoder function.
 392   Result = decodeInstruction(DecoderTable32, instr, insn32, Address, this, STI);
 393   if (Result != Fail) {
 394     Size = 4;
 395     return Result;
 396   }
 397
 398   return Fail;
 399 }
 400
 401 namespace llvm {
 402   extern Target TheXCoreTarget;
 403 }
 404
 405 static MCDisassembler *createXCoreDisassembler(const Target &T,
 406                                                const MCSubtargetInfo &STI) {
 407   return new XCoreDisassembler(STI, T.createMCRegInfo(""));
 408 }
 409
 410 extern "C" void LLVMInitializeXCoreDisassembler() {
 411   // Register the disassembler.
 412   TargetRegistry::RegisterMCDisassembler(TheXCoreTarget,
 413                                          createXCoreDisassembler);
 414 }