lib/Target/XCore/Disassembler/XCoreDisassembler.cpp

   1 //===- XCoreDisassembler.cpp - Disassembler for XCore -----------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 ///
  10 /// \file
  11 /// \brief This file is part of the XCore Disassembler.
  12 ///
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "XCore.h"
  16 #include "XCoreRegisterInfo.h"
  17 #include "llvm/MC/MCDisassembler.h"
  18 #include "llvm/MC/MCFixedLenDisassembler.h"
  19 #include "llvm/MC/MCInst.h"
  20 #include "llvm/MC/MCSubtargetInfo.h"
  21 #include "llvm/Support/MemoryObject.h"
  22 #include "llvm/Support/TargetRegistry.h"
  23
  24 using namespace llvm;
  25
  26 typedef MCDisassembler::DecodeStatus DecodeStatus;
  27
  28 namespace {
  29
  30 /// \brief A disassembler class for XCore.
  31 class XCoreDisassembler : public MCDisassembler {
  32   const MCRegisterInfo *RegInfo;
  33 public:
  34   XCoreDisassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info) :
  35     MCDisassembler(STI), RegInfo(Info) {}
  36
  37   /// \brief See MCDisassembler.
  38   virtual DecodeStatus getInstruction(MCInst &instr,
  39                                       uint64_t &size,
  40                                       const MemoryObject &region,
  41                                       uint64_t address,
  42                                       raw_ostream &vStream,
  43                                       raw_ostream &cStream) const;
  44
  45   const MCRegisterInfo *getRegInfo() const { return RegInfo; }
  46 };
  47 }
  48
  49 static bool readInstruction16(const MemoryObject &region,
  50                               uint64_t address,
  51                               uint64_t &size,
  52                               uint16_t &insn) {
  53   uint8_t Bytes[4];
  54
  55   // We want to read exactly 2 Bytes of data.
  56   if (region.readBytes(address, 2, Bytes, NULL) == -1) {
  57     size = 0;
  58     return false;
  59   }
  60   // Encoded as a little-endian 16-bit word in the stream.
  61   insn = (Bytes[0] <<  0) | (Bytes[1] <<  8);
  62   return true;
  63 }
  64
  65 static bool readInstruction32(const MemoryObject &region,
  66                               uint64_t address,
  67                               uint64_t &size,
  68                               uint32_t &insn) {
  69   uint8_t Bytes[4];
  70
  71   // We want to read exactly 4 Bytes of data.
  72   if (region.readBytes(address, 4, Bytes, NULL) == -1) {
  73     size = 0;
  74     return false;
  75   }
  76   // Encoded as a little-endian 32-bit word in the stream.
  77   insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
  78          (Bytes[3] << 24);
  79   return true;
  80 }
  81
  82 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
  83   const XCoreDisassembler *Dis = static_cast<const XCoreDisassembler*>(D);
  84   return *(Dis->getRegInfo()->getRegClass(RC).begin() + RegNo);
  85 }
  86
  87 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
  88                                               unsigned RegNo,
  89                                               uint64_t Address,
  90                                               const void *Decoder);
  91
  92 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
  93                                       uint64_t Address, const void *Decoder);
  94
  95 static DecodeStatus DecodeMEMiiOperand(MCInst &Inst, unsigned Val,
  96                                        uint64_t Address, const void *Decoder);
  97
  98 static DecodeStatus Decode2RInstruction(MCInst &Inst,
  99                                         unsigned Insn,
 100                                         uint64_t Address,
 101                                         const void *Decoder);
 102
 103 static DecodeStatus DecodeR2RInstruction(MCInst &Inst,
 104                                          unsigned Insn,
 105                                          uint64_t Address,
 106                                          const void *Decoder);
 107
 108 static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst,
 109                                               unsigned Insn,
 110                                               uint64_t Address,
 111                                               const void *Decoder);
 112
 113 static DecodeStatus DecodeRUSInstruction(MCInst &Inst,
 114                                          unsigned Insn,
 115                                          uint64_t Address,
 116                                          const void *Decoder);
 117
 118 static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst,
 119                                              unsigned Insn,
 120                                              uint64_t Address,
 121                                              const void *Decoder);
 122
 123 static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst &Inst,
 124                                                    unsigned Insn,
 125                                                    uint64_t Address,
 126                                                    const void *Decoder);
 127
 128 static DecodeStatus DecodeL2RInstruction(MCInst &Inst,
 129                                          unsigned Insn,
 130                                          uint64_t Address,
 131                                          const void *Decoder);
 132
 133 static DecodeStatus DecodeLR2RInstruction(MCInst &Inst,
 134                                           unsigned Insn,
 135                                           uint64_t Address,
 136                                           const void *Decoder);
 137
 138 static DecodeStatus Decode3RInstruction(MCInst &Inst,
 139                                         unsigned Insn,
 140                                         uint64_t Address,
 141                                         const void *Decoder);
 142
 143 static DecodeStatus Decode2RUSInstruction(MCInst &Inst,
 144                                           unsigned Insn,
 145                                           uint64_t Address,
 146                                           const void *Decoder);
 147
 148 static DecodeStatus Decode2RUSBitpInstruction(MCInst &Inst,
 149                                               unsigned Insn,
 150                                               uint64_t Address,
 151                                               const void *Decoder);
 152
 153 static DecodeStatus DecodeL3RInstruction(MCInst &Inst,
 154                                          unsigned Insn,
 155                                          uint64_t Address,
 156                                          const void *Decoder);
 157
 158 static DecodeStatus DecodeL3RSrcDstInstruction(MCInst &Inst,
 159                                                unsigned Insn,
 160                                                uint64_t Address,
 161                                                const void *Decoder);
 162
 163 static DecodeStatus DecodeL2RUSInstruction(MCInst &Inst,
 164                                            unsigned Insn,
 165                                            uint64_t Address,
 166                                            const void *Decoder);
 167
 168 static DecodeStatus DecodeL2RUSBitpInstruction(MCInst &Inst,
 169                                                unsigned Insn,
 170                                                uint64_t Address,
 171                                                const void *Decoder);
 172
 173 static DecodeStatus DecodeL6RInstruction(MCInst &Inst,
 174                                          unsigned Insn,
 175                                          uint64_t Address,
 176                                          const void *Decoder);
 177
 178 static DecodeStatus DecodeL5RInstruction(MCInst &Inst,
 179                                          unsigned Insn,
 180                                          uint64_t Address,
 181                                          const void *Decoder);
 182
 183 #include "XCoreGenDisassemblerTables.inc"
 184
 185 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
 186                                               unsigned RegNo,
 187                                               uint64_t Address,
 188                                               const void *Decoder)
 189 {
 190   if (RegNo > 11)
 191     return MCDisassembler::Fail;
 192   unsigned Reg = getReg(Decoder, XCore::GRRegsRegClassID, RegNo);
 193   Inst.addOperand(MCOperand::CreateReg(Reg));
 194   return MCDisassembler::Success;
 195 }
 196
 197 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
 198                                       uint64_t Address, const void *Decoder) {
 199   if (Val > 11)
 200     return MCDisassembler::Fail;
 201   static unsigned Values[] = {
 202     32 /*bpw*/, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32
 203   };
 204   Inst.addOperand(MCOperand::CreateImm(Values[Val]));
 205   return MCDisassembler::Success;
 206 }
 207
 208 static DecodeStatus DecodeMEMiiOperand(MCInst &Inst, unsigned Val,
 209                                        uint64_t Address, const void *Decoder) {
 210   Inst.addOperand(MCOperand::CreateImm(Val));
 211   Inst.addOperand(MCOperand::CreateImm(0));
 212   return MCDisassembler::Success;
 213 }
 214
 215 static DecodeStatus
 216 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) {
 217   unsigned Combined = fieldFromInstruction(Insn, 6, 5);
 218   if (Combined < 27)
 219     return MCDisassembler::Fail;
 220   if (fieldFromInstruction(Insn, 5, 1)) {
 221     if (Combined == 31)
 222       return MCDisassembler::Fail;
 223     Combined += 5;
 224   }
 225   Combined -= 27;
 226   unsigned Op1High = Combined % 3;
 227   unsigned Op2High = Combined / 3;
 228   Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2);
 229   Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2);
 230   return MCDisassembler::Success;
 231 }
 232
 233 static DecodeStatus
 234 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2,
 235                      unsigned &Op3) {
 236   unsigned Combined = fieldFromInstruction(Insn, 6, 5);
 237   if (Combined >= 27)
 238     return MCDisassembler::Fail;
 239
 240   unsigned Op1High = Combined % 3;
 241   unsigned Op2High = (Combined / 3) % 3;
 242   unsigned Op3High = Combined / 9;
 243   Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 4, 2);
 244   Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2);
 245   Op3 = (Op3High << 2) | fieldFromInstruction(Insn, 0, 2);
 246   return MCDisassembler::Success;
 247 }
 248
 249 static DecodeStatus
 250 Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
 251                          const void *Decoder) {
 252   // Try and decode as a 3R instruction.
 253   unsigned Opcode = fieldFromInstruction(Insn, 11, 5);
 254   switch (Opcode) {
 255   case 0x0:
 256     Inst.setOpcode(XCore::STW_2rus);
 257     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
 258   case 0x1:
 259     Inst.setOpcode(XCore::LDW_2rus);
 260     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
 261   case 0x2:
 262     Inst.setOpcode(XCore::ADD_3r);
 263     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 264   case 0x3:
 265     Inst.setOpcode(XCore::SUB_3r);
 266     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 267   case 0x4:
 268     Inst.setOpcode(XCore::SHL_3r);
 269     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 270   case 0x5:
 271     Inst.setOpcode(XCore::SHR_3r);
 272     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 273   case 0x6:
 274     Inst.setOpcode(XCore::EQ_3r);
 275     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 276   case 0x7:
 277     Inst.setOpcode(XCore::AND_3r);
 278     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 279   case 0x8:
 280     Inst.setOpcode(XCore::OR_3r);
 281     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 282   case 0x9:
 283     Inst.setOpcode(XCore::LDW_3r);
 284     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 285   case 0x10:
 286     Inst.setOpcode(XCore::LD16S_3r);
 287     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 288   case 0x11:
 289     Inst.setOpcode(XCore::LD8U_3r);
 290     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 291   case 0x12:
 292     Inst.setOpcode(XCore::ADD_2rus);
 293     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
 294   case 0x13:
 295     Inst.setOpcode(XCore::SUB_2rus);
 296     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
 297   case 0x14:
 298     Inst.setOpcode(XCore::SHL_2rus);
 299     return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
 300   case 0x15:
 301     Inst.setOpcode(XCore::SHR_2rus);
 302     return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
 303   case 0x16:
 304     Inst.setOpcode(XCore::EQ_2rus);
 305     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
 306   case 0x18:
 307     Inst.setOpcode(XCore::LSS_3r);
 308     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 309   case 0x19:
 310     Inst.setOpcode(XCore::LSU_3r);
 311     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 312   }
 313   return MCDisassembler::Fail;
 314 }
 315
 316 static DecodeStatus
 317 Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 318                     const void *Decoder) {
 319   unsigned Op1, Op2;
 320   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
 321   if (S != MCDisassembler::Success)
 322     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 323
 324   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 325   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 326   return S;
 327 }
 328
 329 static DecodeStatus
 330 DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 331                      const void *Decoder) {
 332   unsigned Op1, Op2;
 333   DecodeStatus S = Decode2OpInstruction(Insn, Op2, Op1);
 334   if (S != MCDisassembler::Success)
 335     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 336
 337   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 338   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 339   return S;
 340 }
 341
 342 static DecodeStatus
 343 Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 344                           const void *Decoder) {
 345   unsigned Op1, Op2;
 346   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
 347   if (S != MCDisassembler::Success)
 348     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 349
 350   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 351   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 352   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 353   return S;
 354 }
 355
 356 static DecodeStatus
 357 DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 358                      const void *Decoder) {
 359   unsigned Op1, Op2;
 360   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
 361   if (S != MCDisassembler::Success)
 362     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 363
 364   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 365   Inst.addOperand(MCOperand::CreateImm(Op2));
 366   return S;
 367 }
 368
 369 static DecodeStatus
 370 DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 371                          const void *Decoder) {
 372   unsigned Op1, Op2;
 373   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
 374   if (S != MCDisassembler::Success)
 375     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 376
 377   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 378   DecodeBitpOperand(Inst, Op2, Address, Decoder);
 379   return S;
 380 }
 381
 382 static DecodeStatus
 383 DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 384                                const void *Decoder) {
 385   unsigned Op1, Op2;
 386   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
 387   if (S != MCDisassembler::Success)
 388     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 389
 390   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 391   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 392   DecodeBitpOperand(Inst, Op2, Address, Decoder);
 393   return S;
 394 }
 395
 396 static DecodeStatus
 397 DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
 398                           const void *Decoder) {
 399   // Try and decode as a L3R / L2RUS instruction.
 400   unsigned Opcode = fieldFromInstruction(Insn, 16, 4) |
 401                     fieldFromInstruction(Insn, 27, 5) << 4;
 402   switch (Opcode) {
 403   case 0x0c:
 404     Inst.setOpcode(XCore::STW_l3r);
 405     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 406   case 0x1c:
 407     Inst.setOpcode(XCore::XOR_l3r);
 408     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 409   case 0x2c:
 410     Inst.setOpcode(XCore::ASHR_l3r);
 411     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 412   case 0x3c:
 413     Inst.setOpcode(XCore::LDAWF_l3r);
 414     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 415   case 0x4c:
 416     Inst.setOpcode(XCore::LDAWB_l3r);
 417     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 418   case 0x5c:
 419     Inst.setOpcode(XCore::LDA16F_l3r);
 420     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 421   case 0x6c:
 422     Inst.setOpcode(XCore::LDA16B_l3r);
 423     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 424   case 0x7c:
 425     Inst.setOpcode(XCore::MUL_l3r);
 426     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 427   case 0x8c:
 428     Inst.setOpcode(XCore::DIVS_l3r);
 429     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 430   case 0x9c:
 431     Inst.setOpcode(XCore::DIVU_l3r);
 432     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 433   case 0x10c:
 434     Inst.setOpcode(XCore::ST16_l3r);
 435     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 436   case 0x11c:
 437     Inst.setOpcode(XCore::ST8_l3r);
 438     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 439   case 0x12c:
 440     Inst.setOpcode(XCore::ASHR_l2rus);
 441     return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
 442   case 0x13c:
 443     Inst.setOpcode(XCore::LDAWF_l2rus);
 444     return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
 445   case 0x14c:
 446     Inst.setOpcode(XCore::LDAWB_l2rus);
 447     return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
 448   case 0x15c:
 449     Inst.setOpcode(XCore::CRC_l3r);
 450     return DecodeL3RSrcDstInstruction(Inst, Insn, Address, Decoder);
 451   case 0x18c:
 452     Inst.setOpcode(XCore::REMS_l3r);
 453     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 454   case 0x19c:
 455     Inst.setOpcode(XCore::REMU_l3r);
 456     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 457   }
 458   return MCDisassembler::Fail;
 459 }
 460
 461 static DecodeStatus
 462 DecodeL2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 463                                const void *Decoder) {
 464   unsigned Op1, Op2;
 465   DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),
 466                                         Op1, Op2);
 467   if (S != MCDisassembler::Success)
 468     return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
 469
 470   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 471   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 472   return S;
 473 }
 474
 475 static DecodeStatus
 476 DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 477                                const void *Decoder) {
 478   unsigned Op1, Op2;
 479   DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),
 480                                         Op1, Op2);
 481   if (S != MCDisassembler::Success)
 482     return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
 483
 484   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 485   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 486   return S;
 487 }
 488
 489 static DecodeStatus
 490 Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 491                     const void *Decoder) {
 492   unsigned Op1, Op2, Op3;
 493   DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
 494   if (S == MCDisassembler::Success) {
 495     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 496     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 497     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
 498   }
 499   return S;
 500 }
 501
 502 static DecodeStatus
 503 Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 504                       const void *Decoder) {
 505   unsigned Op1, Op2, Op3;
 506   DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
 507   if (S == MCDisassembler::Success) {
 508     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 509     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 510     Inst.addOperand(MCOperand::CreateImm(Op3));
 511   }
 512   return S;
 513 }
 514
 515 static DecodeStatus
 516 Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 517                       const void *Decoder) {
 518   unsigned Op1, Op2, Op3;
 519   DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
 520   if (S == MCDisassembler::Success) {
 521     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 522     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 523     DecodeBitpOperand(Inst, Op3, Address, Decoder);
 524   }
 525   return S;
 526 }
 527
 528 static DecodeStatus
 529 DecodeL3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 530                      const void *Decoder) {
 531   unsigned Op1, Op2, Op3;
 532   DecodeStatus S =
 533     Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
 534   if (S == MCDisassembler::Success) {
 535     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 536     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 537     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
 538   }
 539   return S;
 540 }
 541
 542 static DecodeStatus
 543 DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 544                            const void *Decoder) {
 545   unsigned Op1, Op2, Op3;
 546   DecodeStatus S =
 547   Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
 548   if (S == MCDisassembler::Success) {
 549     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 550     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 551     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 552     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
 553   }
 554   return S;
 555 }
 556
 557 static DecodeStatus
 558 DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 559                        const void *Decoder) {
 560   unsigned Op1, Op2, Op3;
 561   DecodeStatus S =
 562   Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
 563   if (S == MCDisassembler::Success) {
 564     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 565     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 566     Inst.addOperand(MCOperand::CreateImm(Op3));
 567   }
 568   return S;
 569 }
 570
 571 static DecodeStatus
 572 DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 573                            const void *Decoder) {
 574   unsigned Op1, Op2, Op3;
 575   DecodeStatus S =
 576   Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
 577   if (S == MCDisassembler::Success) {
 578     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 579     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 580     DecodeBitpOperand(Inst, Op3, Address, Decoder);
 581   }
 582   return S;
 583 }
 584
 585 static DecodeStatus
 586 DecodeL6RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 587                      const void *Decoder) {
 588   unsigned Op1, Op2, Op3, Op4, Op5, Op6;
 589   DecodeStatus S =
 590     Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
 591   if (S != MCDisassembler::Success)
 592     return S;
 593   S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6);
 594   if (S != MCDisassembler::Success)
 595     return S;
 596   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 597   DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
 598   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 599   DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
 600   DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
 601   DecodeGRRegsRegisterClass(Inst, Op6, Address, Decoder);
 602   return S;
 603 }
 604
 605 static DecodeStatus
 606 DecodeL5RInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
 607                      const void *Decoder) {
 608   // Try and decode as a L6R instruction.
 609   Inst.clear();
 610   unsigned Opcode = fieldFromInstruction(Insn, 27, 5);
 611   switch (Opcode) {
 612   case 0x00:
 613     Inst.setOpcode(XCore::LMUL_l6r);
 614     return DecodeL6RInstruction(Inst, Insn, Address, Decoder);
 615   }
 616   return MCDisassembler::Fail;
 617 }
 618
 619 static DecodeStatus
 620 DecodeL5RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 621                      const void *Decoder) {
 622   unsigned Op1, Op2, Op3, Op4, Op5;
 623   DecodeStatus S =
 624     Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
 625   if (S != MCDisassembler::Success)
 626     return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
 627   S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5);
 628   if (S != MCDisassembler::Success)
 629     return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
 630
 631   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 632   DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
 633   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 634   DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
 635   DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
 636   return S;
 637 }
 638
 639 MCDisassembler::DecodeStatus
 640 XCoreDisassembler::getInstruction(MCInst &instr,
 641                                   uint64_t &Size,
 642                                   const MemoryObject &Region,
 643                                   uint64_t Address,
 644                                   raw_ostream &vStream,
 645                                   raw_ostream &cStream) const {
 646   uint16_t insn16;
 647
 648   if (!readInstruction16(Region, Address, Size, insn16)) {
 649     return Fail;
 650   }
 651
 652   // Calling the auto-generated decoder function.
 653   DecodeStatus Result = decodeInstruction(DecoderTable16, instr, insn16,
 654                                           Address, this, STI);
 655   if (Result != Fail) {
 656     Size = 2;
 657     return Result;
 658   }
 659
 660   uint32_t insn32;
 661
 662   if (!readInstruction32(Region, Address, Size, insn32)) {
 663     return Fail;
 664   }
 665
 666   // Calling the auto-generated decoder function.
 667   Result = decodeInstruction(DecoderTable32, instr, insn32, Address, this, STI);
 668   if (Result != Fail) {
 669     Size = 4;
 670     return Result;
 671   }
 672
 673   return Fail;
 674 }
 675
 676 namespace llvm {
 677   extern Target TheXCoreTarget;
 678 }
 679
 680 static MCDisassembler *createXCoreDisassembler(const Target &T,
 681                                                const MCSubtargetInfo &STI) {
 682   return new XCoreDisassembler(STI, T.createMCRegInfo(""));
 683 }
 684
 685 extern "C" void LLVMInitializeXCoreDisassembler() {
 686   // Register the disassembler.
 687   TargetRegistry::RegisterMCDisassembler(TheXCoreTarget,
 688                                          createXCoreDisassembler);
 689 }