1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// This file implements a TargetTransformInfo analysis pass specific to the
11 /// X86 target machine. It uses the target's detailed information to provide
12 /// more precise answers to certain TTI queries, while letting the target
13 /// independent and default TTI implementations handle the rest.
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "x86tti"
19 #include "X86TargetMachine.h"
20 #include "llvm/Analysis/TargetTransformInfo.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Target/TargetLowering.h"
23 #include "llvm/Target/CostTable.h"
26 // Declare the pass initialization routine locally as target-specific passes
27 // don't havve a target-wide initialization entry point, and so we rely on the
28 // pass constructor initialization.
30 void initializeX86TTIPass(PassRegistry &);
35 class X86TTI : public ImmutablePass, public TargetTransformInfo {
36 const X86TargetMachine *TM;
37 const X86Subtarget *ST;
38 const X86TargetLowering *TLI;
40 /// Estimate the overhead of scalarizing an instruction. Insert and Extract
41 /// are set if the result needs to be inserted and/or extracted from vectors.
42 unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const;
45 X86TTI() : ImmutablePass(ID), TM(0), ST(0), TLI(0) {
46 llvm_unreachable("This pass cannot be directly constructed");
49 X86TTI(const X86TargetMachine *TM)
50 : ImmutablePass(ID), TM(TM), ST(TM->getSubtargetImpl()),
51 TLI(TM->getTargetLowering()) {
52 initializeX86TTIPass(*PassRegistry::getPassRegistry());
55 virtual void initializePass() {
59 virtual void finalizePass() {
63 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
64 TargetTransformInfo::getAnalysisUsage(AU);
67 /// Pass identification.
70 /// Provide necessary pointer adjustments for the two base classes.
71 virtual void *getAdjustedAnalysisPointer(const void *ID) {
72 if (ID == &TargetTransformInfo::ID)
73 return (TargetTransformInfo*)this;
77 /// \name Scalar TTI Implementations
79 virtual PopcntSupportKind getPopcntSupport(unsigned TyWidth) const;
83 /// \name Vector TTI Implementations
86 virtual unsigned getNumberOfRegisters(bool Vector) const;
87 virtual unsigned getRegisterBitWidth(bool Vector) const;
88 virtual unsigned getMaximumUnrollFactor() const;
89 virtual unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty,
91 OperandValueKind) const;
92 virtual unsigned getShuffleCost(ShuffleKind Kind, Type *Tp,
93 int Index, Type *SubTp) const;
94 virtual unsigned getCastInstrCost(unsigned Opcode, Type *Dst,
96 virtual unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
98 virtual unsigned getVectorInstrCost(unsigned Opcode, Type *Val,
99 unsigned Index) const;
100 virtual unsigned getMemoryOpCost(unsigned Opcode, Type *Src,
102 unsigned AddressSpace) const;
107 } // end anonymous namespace
109 INITIALIZE_AG_PASS(X86TTI, TargetTransformInfo, "x86tti",
110 "X86 Target Transform Info", true, true, false)
114 llvm::createX86TargetTransformInfoPass(const X86TargetMachine *TM) {
115 return new X86TTI(TM);
119 //===----------------------------------------------------------------------===//
123 //===----------------------------------------------------------------------===//
125 X86TTI::PopcntSupportKind X86TTI::getPopcntSupport(unsigned TyWidth) const {
126 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
127 // TODO: Currently the __builtin_popcount() implementation using SSE3
128 // instructions is inefficient. Once the problem is fixed, we should
129 // call ST->hasSSE3() instead of ST->hasSSE4().
130 return ST->hasSSE41() ? PSK_FastHardware : PSK_Software;
133 unsigned X86TTI::getNumberOfRegisters(bool Vector) const {
134 if (Vector && !ST->hasSSE1())
142 unsigned X86TTI::getRegisterBitWidth(bool Vector) const {
144 if (ST->hasAVX()) return 256;
145 if (ST->hasSSE1()) return 128;
155 unsigned X86TTI::getMaximumUnrollFactor() const {
159 // Sandybridge and Haswell have multiple execution ports and pipelined
167 unsigned X86TTI::getArithmeticInstrCost(unsigned Opcode, Type *Ty,
168 OperandValueKind Op1Info,
169 OperandValueKind Op2Info) const {
170 // Legalize the type.
171 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Ty);
173 int ISD = TLI->InstructionOpcodeToISD(Opcode);
174 assert(ISD && "Invalid opcode");
176 static const CostTblEntry<MVT> AVX2CostTable[] = {
177 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to
178 // customize them to detect the cases where shift amount is a scalar one.
179 { ISD::SHL, MVT::v4i32, 1 },
180 { ISD::SRL, MVT::v4i32, 1 },
181 { ISD::SRA, MVT::v4i32, 1 },
182 { ISD::SHL, MVT::v8i32, 1 },
183 { ISD::SRL, MVT::v8i32, 1 },
184 { ISD::SRA, MVT::v8i32, 1 },
185 { ISD::SHL, MVT::v2i64, 1 },
186 { ISD::SRL, MVT::v2i64, 1 },
187 { ISD::SHL, MVT::v4i64, 1 },
188 { ISD::SRL, MVT::v4i64, 1 },
190 { ISD::SHL, MVT::v32i8, 42 }, // cmpeqb sequence.
191 { ISD::SHL, MVT::v16i16, 16*10 }, // Scalarized.
193 { ISD::SRL, MVT::v32i8, 32*10 }, // Scalarized.
194 { ISD::SRL, MVT::v16i16, 8*10 }, // Scalarized.
196 { ISD::SRA, MVT::v32i8, 32*10 }, // Scalarized.
197 { ISD::SRA, MVT::v16i16, 16*10 }, // Scalarized.
198 { ISD::SRA, MVT::v4i64, 4*10 }, // Scalarized.
201 // Look for AVX2 lowering tricks.
203 int Idx = CostTableLookup<MVT>(AVX2CostTable, array_lengthof(AVX2CostTable),
206 return LT.first * AVX2CostTable[Idx].Cost;
209 static const CostTblEntry<MVT> SSE2CostTable[] = {
210 // We don't correctly identify costs of casts because they are marked as
212 // For some cases, where the shift amount is a scalar we would be able
213 // to generate better code. Unfortunately, when this is the case the value
214 // (the splat) will get hoisted out of the loop, thereby making it invisible
215 // to ISel. The cost model must return worst case assumptions because it is
216 // used for vectorization and we don't want to make vectorized code worse
218 { ISD::SHL, MVT::v16i8, 30 }, // cmpeqb sequence.
219 { ISD::SHL, MVT::v8i16, 8*10 }, // Scalarized.
220 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul.
221 { ISD::SHL, MVT::v2i64, 2*10 }, // Scalarized.
223 { ISD::SRL, MVT::v16i8, 16*10 }, // Scalarized.
224 { ISD::SRL, MVT::v8i16, 8*10 }, // Scalarized.
225 { ISD::SRL, MVT::v4i32, 4*10 }, // Scalarized.
226 { ISD::SRL, MVT::v2i64, 2*10 }, // Scalarized.
228 { ISD::SRA, MVT::v16i8, 16*10 }, // Scalarized.
229 { ISD::SRA, MVT::v8i16, 8*10 }, // Scalarized.
230 { ISD::SRA, MVT::v4i32, 4*10 }, // Scalarized.
231 { ISD::SRA, MVT::v2i64, 2*10 }, // Scalarized.
235 int Idx = CostTableLookup<MVT>(SSE2CostTable, array_lengthof(SSE2CostTable),
238 return LT.first * SSE2CostTable[Idx].Cost;
241 static const CostTblEntry<MVT> AVX1CostTable[] = {
242 // We don't have to scalarize unsupported ops. We can issue two half-sized
243 // operations and we only need to extract the upper YMM half.
244 // Two ops + 1 extract + 1 insert = 4.
245 { ISD::MUL, MVT::v8i32, 4 },
246 { ISD::SUB, MVT::v8i32, 4 },
247 { ISD::ADD, MVT::v8i32, 4 },
248 { ISD::SUB, MVT::v4i64, 4 },
249 { ISD::ADD, MVT::v4i64, 4 },
250 // A v4i64 multiply is custom lowered as two split v2i64 vectors that then
251 // are lowered as a series of long multiplies(3), shifts(4) and adds(2)
252 // Because we believe v4i64 to be a legal type, we must also include the
253 // split factor of two in the cost table. Therefore, the cost here is 18
255 { ISD::MUL, MVT::v4i64, 18 },
258 // Look for AVX1 lowering tricks.
259 if (ST->hasAVX() && !ST->hasAVX2()) {
260 int Idx = CostTableLookup<MVT>(AVX1CostTable, array_lengthof(AVX1CostTable),
263 return LT.first * AVX1CostTable[Idx].Cost;
266 // Custom lowering of vectors.
267 static const CostTblEntry<MVT> CustomLowered[] = {
268 // A v2i64/v4i64 and multiply is custom lowered as a series of long
269 // multiplies(3), shifts(4) and adds(2).
270 { ISD::MUL, MVT::v2i64, 9 },
271 { ISD::MUL, MVT::v4i64, 9 },
273 int Idx = CostTableLookup<MVT>(CustomLowered, array_lengthof(CustomLowered),
276 return LT.first * CustomLowered[Idx].Cost;
278 // Special lowering of v4i32 mul on sse2, sse3: Lower v4i32 mul as 2x shuffle,
279 // 2x pmuludq, 2x shuffle.
280 if (ISD == ISD::MUL && LT.second == MVT::v4i32 && ST->hasSSE2() &&
284 // Fallback to the default implementation.
285 return TargetTransformInfo::getArithmeticInstrCost(Opcode, Ty, Op1Info,
289 unsigned X86TTI::getShuffleCost(ShuffleKind Kind, Type *Tp, int Index,
291 // We only estimate the cost of reverse shuffles.
292 if (Kind != SK_Reverse)
293 return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp);
295 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Tp);
297 if (LT.second.getSizeInBits() > 128)
298 Cost = 3; // Extract + insert + copy.
300 // Multiple by the number of parts.
301 return Cost * LT.first;
304 unsigned X86TTI::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) const {
305 int ISD = TLI->InstructionOpcodeToISD(Opcode);
306 assert(ISD && "Invalid opcode");
308 EVT SrcTy = TLI->getValueType(Src);
309 EVT DstTy = TLI->getValueType(Dst);
311 if (!SrcTy.isSimple() || !DstTy.isSimple())
312 return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
314 static const TypeConversionCostTblEntry<MVT> AVXConversionTbl[] = {
315 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
316 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
317 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
318 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
319 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 },
320 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 1 },
322 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 },
323 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 },
324 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 },
325 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 },
326 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
327 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
328 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 },
329 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
330 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 },
331 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 },
332 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 },
333 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 },
335 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 },
336 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 5 },
337 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 },
338 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 9 },
339 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 },
340 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 },
341 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
342 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 6 },
343 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 },
344 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 },
345 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 },
346 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 },
348 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 1 },
349 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 },
350 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 6 },
351 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 9 },
352 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 8 },
353 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 6 },
354 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 6 },
355 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 3 },
359 int Idx = ConvertCostTableLookup<MVT>(AVXConversionTbl,
360 array_lengthof(AVXConversionTbl),
361 ISD, DstTy.getSimpleVT(), SrcTy.getSimpleVT());
363 return AVXConversionTbl[Idx].Cost;
366 return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
369 unsigned X86TTI::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
370 Type *CondTy) const {
371 // Legalize the type.
372 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(ValTy);
376 int ISD = TLI->InstructionOpcodeToISD(Opcode);
377 assert(ISD && "Invalid opcode");
379 static const CostTblEntry<MVT> SSE42CostTbl[] = {
380 { ISD::SETCC, MVT::v2f64, 1 },
381 { ISD::SETCC, MVT::v4f32, 1 },
382 { ISD::SETCC, MVT::v2i64, 1 },
383 { ISD::SETCC, MVT::v4i32, 1 },
384 { ISD::SETCC, MVT::v8i16, 1 },
385 { ISD::SETCC, MVT::v16i8, 1 },
388 static const CostTblEntry<MVT> AVX1CostTbl[] = {
389 { ISD::SETCC, MVT::v4f64, 1 },
390 { ISD::SETCC, MVT::v8f32, 1 },
391 // AVX1 does not support 8-wide integer compare.
392 { ISD::SETCC, MVT::v4i64, 4 },
393 { ISD::SETCC, MVT::v8i32, 4 },
394 { ISD::SETCC, MVT::v16i16, 4 },
395 { ISD::SETCC, MVT::v32i8, 4 },
398 static const CostTblEntry<MVT> AVX2CostTbl[] = {
399 { ISD::SETCC, MVT::v4i64, 1 },
400 { ISD::SETCC, MVT::v8i32, 1 },
401 { ISD::SETCC, MVT::v16i16, 1 },
402 { ISD::SETCC, MVT::v32i8, 1 },
406 int Idx = CostTableLookup<MVT>(AVX2CostTbl, array_lengthof(AVX2CostTbl), ISD, MTy);
408 return LT.first * AVX2CostTbl[Idx].Cost;
412 int Idx = CostTableLookup<MVT>(AVX1CostTbl, array_lengthof(AVX1CostTbl), ISD, MTy);
414 return LT.first * AVX1CostTbl[Idx].Cost;
417 if (ST->hasSSE42()) {
418 int Idx = CostTableLookup<MVT>(SSE42CostTbl, array_lengthof(SSE42CostTbl), ISD, MTy);
420 return LT.first * SSE42CostTbl[Idx].Cost;
423 return TargetTransformInfo::getCmpSelInstrCost(Opcode, ValTy, CondTy);
426 unsigned X86TTI::getVectorInstrCost(unsigned Opcode, Type *Val,
427 unsigned Index) const {
428 assert(Val->isVectorTy() && "This must be a vector type");
431 // Legalize the type.
432 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Val);
434 // This type is legalized to a scalar type.
435 if (!LT.second.isVector())
438 // The type may be split. Normalize the index to the new type.
439 unsigned Width = LT.second.getVectorNumElements();
440 Index = Index % Width;
442 // Floating point scalars are already located in index #0.
443 if (Val->getScalarType()->isFloatingPointTy() && Index == 0)
447 return TargetTransformInfo::getVectorInstrCost(Opcode, Val, Index);
450 unsigned X86TTI::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
451 unsigned AddressSpace) const {
452 // Legalize the type.
453 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Src);
454 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) &&
457 // Each load/store unit costs 1.
458 unsigned Cost = LT.first * 1;
460 // On Sandybridge 256bit load/stores are double pumped
461 // (but not on Haswell).
462 if (LT.second.getSizeInBits() > 128 && !ST->hasAVX2())