1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// This file implements a TargetTransformInfo analysis pass specific to the
11 /// X86 target machine. It uses the target's detailed information to provide
12 /// more precise answers to certain TTI queries, while letting the target
13 /// independent and default TTI implementations handle the rest.
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "x86tti"
19 #include "X86TargetMachine.h"
20 #include "llvm/Analysis/TargetTransformInfo.h"
21 #include "llvm/IR/IntrinsicInst.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Target/CostTable.h"
24 #include "llvm/Target/TargetLowering.h"
27 // Declare the pass initialization routine locally as target-specific passes
28 // don't havve a target-wide initialization entry point, and so we rely on the
29 // pass constructor initialization.
31 void initializeX86TTIPass(PassRegistry &);
36 class X86TTI LLVM_FINAL : public ImmutablePass, public TargetTransformInfo {
37 const X86Subtarget *ST;
38 const X86TargetLowering *TLI;
40 /// Estimate the overhead of scalarizing an instruction. Insert and Extract
41 /// are set if the result needs to be inserted and/or extracted from vectors.
42 unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const;
45 X86TTI() : ImmutablePass(ID), ST(0), TLI(0) {
46 llvm_unreachable("This pass cannot be directly constructed");
49 X86TTI(const X86TargetMachine *TM)
50 : ImmutablePass(ID), ST(TM->getSubtargetImpl()),
51 TLI(TM->getTargetLowering()) {
52 initializeX86TTIPass(*PassRegistry::getPassRegistry());
55 virtual void initializePass() LLVM_OVERRIDE {
59 virtual void finalizePass() {
63 virtual void getAnalysisUsage(AnalysisUsage &AU) const LLVM_OVERRIDE {
64 TargetTransformInfo::getAnalysisUsage(AU);
67 /// Pass identification.
70 /// Provide necessary pointer adjustments for the two base classes.
71 virtual void *getAdjustedAnalysisPointer(const void *ID) LLVM_OVERRIDE {
72 if (ID == &TargetTransformInfo::ID)
73 return (TargetTransformInfo*)this;
77 /// \name Scalar TTI Implementations
79 virtual PopcntSupportKind
80 getPopcntSupport(unsigned TyWidth) const LLVM_OVERRIDE;
84 /// \name Vector TTI Implementations
87 virtual unsigned getNumberOfRegisters(bool Vector) const LLVM_OVERRIDE;
88 virtual unsigned getRegisterBitWidth(bool Vector) const LLVM_OVERRIDE;
89 virtual unsigned getMaximumUnrollFactor() const LLVM_OVERRIDE;
90 virtual unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty,
92 OperandValueKind) const LLVM_OVERRIDE;
93 virtual unsigned getShuffleCost(ShuffleKind Kind, Type *Tp,
94 int Index, Type *SubTp) const LLVM_OVERRIDE;
95 virtual unsigned getCastInstrCost(unsigned Opcode, Type *Dst,
96 Type *Src) const LLVM_OVERRIDE;
97 virtual unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
98 Type *CondTy) const LLVM_OVERRIDE;
99 virtual unsigned getVectorInstrCost(unsigned Opcode, Type *Val,
100 unsigned Index) const LLVM_OVERRIDE;
101 virtual unsigned getMemoryOpCost(unsigned Opcode, Type *Src,
103 unsigned AddressSpace) const LLVM_OVERRIDE;
106 getAddressComputationCost(Type *PtrTy, bool IsComplex) const LLVM_OVERRIDE;
108 virtual unsigned getReductionCost(unsigned Opcode, Type *Ty,
109 bool IsPairwiseForm) const LLVM_OVERRIDE;
111 virtual unsigned getIntImmCost(const APInt &Imm,
112 Type *Ty) const LLVM_OVERRIDE;
114 virtual unsigned getIntImmCost(unsigned Opcode, const APInt &Imm,
115 Type *Ty) const LLVM_OVERRIDE;
116 virtual unsigned getIntImmCost(Intrinsic::ID IID, const APInt &Imm,
117 Type *Ty) const LLVM_OVERRIDE;
122 } // end anonymous namespace
124 INITIALIZE_AG_PASS(X86TTI, TargetTransformInfo, "x86tti",
125 "X86 Target Transform Info", true, true, false)
129 llvm::createX86TargetTransformInfoPass(const X86TargetMachine *TM) {
130 return new X86TTI(TM);
134 //===----------------------------------------------------------------------===//
138 //===----------------------------------------------------------------------===//
140 X86TTI::PopcntSupportKind X86TTI::getPopcntSupport(unsigned TyWidth) const {
141 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
142 // TODO: Currently the __builtin_popcount() implementation using SSE3
143 // instructions is inefficient. Once the problem is fixed, we should
144 // call ST->hasSSE3() instead of ST->hasPOPCNT().
145 return ST->hasPOPCNT() ? PSK_FastHardware : PSK_Software;
148 unsigned X86TTI::getNumberOfRegisters(bool Vector) const {
149 if (Vector && !ST->hasSSE1())
157 unsigned X86TTI::getRegisterBitWidth(bool Vector) const {
159 if (ST->hasAVX()) return 256;
160 if (ST->hasSSE1()) return 128;
170 unsigned X86TTI::getMaximumUnrollFactor() const {
174 // Sandybridge and Haswell have multiple execution ports and pipelined
182 unsigned X86TTI::getArithmeticInstrCost(unsigned Opcode, Type *Ty,
183 OperandValueKind Op1Info,
184 OperandValueKind Op2Info) const {
185 // Legalize the type.
186 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Ty);
188 int ISD = TLI->InstructionOpcodeToISD(Opcode);
189 assert(ISD && "Invalid opcode");
191 static const CostTblEntry<MVT::SimpleValueType> AVX2CostTable[] = {
192 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to
193 // customize them to detect the cases where shift amount is a scalar one.
194 { ISD::SHL, MVT::v4i32, 1 },
195 { ISD::SRL, MVT::v4i32, 1 },
196 { ISD::SRA, MVT::v4i32, 1 },
197 { ISD::SHL, MVT::v8i32, 1 },
198 { ISD::SRL, MVT::v8i32, 1 },
199 { ISD::SRA, MVT::v8i32, 1 },
200 { ISD::SHL, MVT::v2i64, 1 },
201 { ISD::SRL, MVT::v2i64, 1 },
202 { ISD::SHL, MVT::v4i64, 1 },
203 { ISD::SRL, MVT::v4i64, 1 },
205 { ISD::SHL, MVT::v32i8, 42 }, // cmpeqb sequence.
206 { ISD::SHL, MVT::v16i16, 16*10 }, // Scalarized.
208 { ISD::SRL, MVT::v32i8, 32*10 }, // Scalarized.
209 { ISD::SRL, MVT::v16i16, 8*10 }, // Scalarized.
211 { ISD::SRA, MVT::v32i8, 32*10 }, // Scalarized.
212 { ISD::SRA, MVT::v16i16, 16*10 }, // Scalarized.
213 { ISD::SRA, MVT::v4i64, 4*10 }, // Scalarized.
215 // Vectorizing division is a bad idea. See the SSE2 table for more comments.
216 { ISD::SDIV, MVT::v32i8, 32*20 },
217 { ISD::SDIV, MVT::v16i16, 16*20 },
218 { ISD::SDIV, MVT::v8i32, 8*20 },
219 { ISD::SDIV, MVT::v4i64, 4*20 },
220 { ISD::UDIV, MVT::v32i8, 32*20 },
221 { ISD::UDIV, MVT::v16i16, 16*20 },
222 { ISD::UDIV, MVT::v8i32, 8*20 },
223 { ISD::UDIV, MVT::v4i64, 4*20 },
226 // Look for AVX2 lowering tricks.
228 if (ISD == ISD::SHL && LT.second == MVT::v16i16 &&
229 (Op2Info == TargetTransformInfo::OK_UniformConstantValue ||
230 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue))
231 // On AVX2, a packed v16i16 shift left by a constant build_vector
232 // is lowered into a vector multiply (vpmullw).
235 int Idx = CostTableLookup(AVX2CostTable, ISD, LT.second);
237 return LT.first * AVX2CostTable[Idx].Cost;
240 static const CostTblEntry<MVT::SimpleValueType>
241 SSE2UniformConstCostTable[] = {
242 // We don't correctly identify costs of casts because they are marked as
244 // Constant splats are cheaper for the following instructions.
245 { ISD::SHL, MVT::v16i8, 1 }, // psllw.
246 { ISD::SHL, MVT::v8i16, 1 }, // psllw.
247 { ISD::SHL, MVT::v4i32, 1 }, // pslld
248 { ISD::SHL, MVT::v2i64, 1 }, // psllq.
250 { ISD::SRL, MVT::v16i8, 1 }, // psrlw.
251 { ISD::SRL, MVT::v8i16, 1 }, // psrlw.
252 { ISD::SRL, MVT::v4i32, 1 }, // psrld.
253 { ISD::SRL, MVT::v2i64, 1 }, // psrlq.
255 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb.
256 { ISD::SRA, MVT::v8i16, 1 }, // psraw.
257 { ISD::SRA, MVT::v4i32, 1 }, // psrad.
260 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue &&
262 int Idx = CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second);
264 return LT.first * SSE2UniformConstCostTable[Idx].Cost;
267 if (ISD == ISD::SHL &&
268 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) {
270 if ((VT == MVT::v8i16 && ST->hasSSE2()) ||
271 (VT == MVT::v4i32 && ST->hasSSE41()))
272 // Vector shift left by non uniform constant can be lowered
273 // into vector multiply (pmullw/pmulld).
275 if (VT == MVT::v4i32 && ST->hasSSE2())
276 // A vector shift left by non uniform constant is converted
277 // into a vector multiply; the new multiply is eventually
278 // lowered into a sequence of shuffles and 2 x pmuludq.
282 static const CostTblEntry<MVT::SimpleValueType> SSE2CostTable[] = {
283 // We don't correctly identify costs of casts because they are marked as
285 // For some cases, where the shift amount is a scalar we would be able
286 // to generate better code. Unfortunately, when this is the case the value
287 // (the splat) will get hoisted out of the loop, thereby making it invisible
288 // to ISel. The cost model must return worst case assumptions because it is
289 // used for vectorization and we don't want to make vectorized code worse
291 { ISD::SHL, MVT::v16i8, 30 }, // cmpeqb sequence.
292 { ISD::SHL, MVT::v8i16, 8*10 }, // Scalarized.
293 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul.
294 { ISD::SHL, MVT::v2i64, 2*10 }, // Scalarized.
295 { ISD::SHL, MVT::v4i64, 4*10 }, // Scalarized.
297 { ISD::SRL, MVT::v16i8, 16*10 }, // Scalarized.
298 { ISD::SRL, MVT::v8i16, 8*10 }, // Scalarized.
299 { ISD::SRL, MVT::v4i32, 4*10 }, // Scalarized.
300 { ISD::SRL, MVT::v2i64, 2*10 }, // Scalarized.
302 { ISD::SRA, MVT::v16i8, 16*10 }, // Scalarized.
303 { ISD::SRA, MVT::v8i16, 8*10 }, // Scalarized.
304 { ISD::SRA, MVT::v4i32, 4*10 }, // Scalarized.
305 { ISD::SRA, MVT::v2i64, 2*10 }, // Scalarized.
307 // It is not a good idea to vectorize division. We have to scalarize it and
308 // in the process we will often end up having to spilling regular
309 // registers. The overhead of division is going to dominate most kernels
310 // anyways so try hard to prevent vectorization of division - it is
311 // generally a bad idea. Assume somewhat arbitrarily that we have to be able
312 // to hide "20 cycles" for each lane.
313 { ISD::SDIV, MVT::v16i8, 16*20 },
314 { ISD::SDIV, MVT::v8i16, 8*20 },
315 { ISD::SDIV, MVT::v4i32, 4*20 },
316 { ISD::SDIV, MVT::v2i64, 2*20 },
317 { ISD::UDIV, MVT::v16i8, 16*20 },
318 { ISD::UDIV, MVT::v8i16, 8*20 },
319 { ISD::UDIV, MVT::v4i32, 4*20 },
320 { ISD::UDIV, MVT::v2i64, 2*20 },
324 int Idx = CostTableLookup(SSE2CostTable, ISD, LT.second);
326 return LT.first * SSE2CostTable[Idx].Cost;
329 static const CostTblEntry<MVT::SimpleValueType> AVX1CostTable[] = {
330 // We don't have to scalarize unsupported ops. We can issue two half-sized
331 // operations and we only need to extract the upper YMM half.
332 // Two ops + 1 extract + 1 insert = 4.
333 { ISD::MUL, MVT::v16i16, 4 },
334 { ISD::MUL, MVT::v8i32, 4 },
335 { ISD::SUB, MVT::v8i32, 4 },
336 { ISD::ADD, MVT::v8i32, 4 },
337 { ISD::SUB, MVT::v4i64, 4 },
338 { ISD::ADD, MVT::v4i64, 4 },
339 // A v4i64 multiply is custom lowered as two split v2i64 vectors that then
340 // are lowered as a series of long multiplies(3), shifts(4) and adds(2)
341 // Because we believe v4i64 to be a legal type, we must also include the
342 // split factor of two in the cost table. Therefore, the cost here is 18
344 { ISD::MUL, MVT::v4i64, 18 },
347 // Look for AVX1 lowering tricks.
348 if (ST->hasAVX() && !ST->hasAVX2()) {
351 // v16i16 and v8i32 shifts by non-uniform constants are lowered into a
352 // sequence of extract + two vector multiply + insert.
353 if (ISD == ISD::SHL && (VT == MVT::v8i32 || VT == MVT::v16i16) &&
354 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)
357 int Idx = CostTableLookup(AVX1CostTable, ISD, VT);
359 return LT.first * AVX1CostTable[Idx].Cost;
362 // Custom lowering of vectors.
363 static const CostTblEntry<MVT::SimpleValueType> CustomLowered[] = {
364 // A v2i64/v4i64 and multiply is custom lowered as a series of long
365 // multiplies(3), shifts(4) and adds(2).
366 { ISD::MUL, MVT::v2i64, 9 },
367 { ISD::MUL, MVT::v4i64, 9 },
369 int Idx = CostTableLookup(CustomLowered, ISD, LT.second);
371 return LT.first * CustomLowered[Idx].Cost;
373 // Special lowering of v4i32 mul on sse2, sse3: Lower v4i32 mul as 2x shuffle,
374 // 2x pmuludq, 2x shuffle.
375 if (ISD == ISD::MUL && LT.second == MVT::v4i32 && ST->hasSSE2() &&
379 // Fallback to the default implementation.
380 return TargetTransformInfo::getArithmeticInstrCost(Opcode, Ty, Op1Info,
384 unsigned X86TTI::getShuffleCost(ShuffleKind Kind, Type *Tp, int Index,
386 // We only estimate the cost of reverse shuffles.
387 if (Kind != SK_Reverse)
388 return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp);
390 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Tp);
392 if (LT.second.getSizeInBits() > 128)
393 Cost = 3; // Extract + insert + copy.
395 // Multiple by the number of parts.
396 return Cost * LT.first;
399 unsigned X86TTI::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) const {
400 int ISD = TLI->InstructionOpcodeToISD(Opcode);
401 assert(ISD && "Invalid opcode");
403 std::pair<unsigned, MVT> LTSrc = TLI->getTypeLegalizationCost(Src);
404 std::pair<unsigned, MVT> LTDest = TLI->getTypeLegalizationCost(Dst);
406 static const TypeConversionCostTblEntry<MVT::SimpleValueType>
408 // These are somewhat magic numbers justified by looking at the output of
409 // Intel's IACA, running some kernels and making sure when we take
410 // legalization into account the throughput will be overestimated.
411 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 },
412 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 },
413 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 },
414 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 },
415 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 },
416 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 },
417 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 },
418 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 },
419 // There are faster sequences for float conversions.
420 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 },
421 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 15 },
422 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 },
423 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 },
424 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 },
425 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 15 },
426 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 },
427 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 },
430 if (ST->hasSSE2() && !ST->hasAVX()) {
432 ConvertCostTableLookup(SSE2ConvTbl, ISD, LTDest.second, LTSrc.second);
434 return LTSrc.first * SSE2ConvTbl[Idx].Cost;
437 EVT SrcTy = TLI->getValueType(Src);
438 EVT DstTy = TLI->getValueType(Dst);
440 // The function getSimpleVT only handles simple value types.
441 if (!SrcTy.isSimple() || !DstTy.isSimple())
442 return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
444 static const TypeConversionCostTblEntry<MVT::SimpleValueType>
445 AVX2ConversionTbl[] = {
446 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 },
447 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 },
448 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 },
449 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 },
450 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
451 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
452 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
453 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
454 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 },
455 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 },
456 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 3 },
457 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 3 },
458 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
459 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
460 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
461 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
463 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 },
464 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 },
465 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 },
466 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 },
467 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 },
468 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 4 },
471 static const TypeConversionCostTblEntry<MVT::SimpleValueType>
472 AVXConversionTbl[] = {
473 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 },
474 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 4 },
475 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 },
476 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 },
477 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 7 },
478 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 4 },
479 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 },
480 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 4 },
481 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 },
482 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 },
483 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 6 },
484 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 },
485 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 6 },
486 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
487 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 4 },
488 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 4 },
490 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 4 },
491 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 4 },
492 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 4 },
493 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 },
494 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 },
495 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 4 },
496 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 9 },
498 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 },
499 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 },
500 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 },
501 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 },
502 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
503 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
504 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 },
505 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
506 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 },
507 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 },
508 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 },
509 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 },
511 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 },
512 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 5 },
513 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 },
514 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 9 },
515 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 },
516 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 },
517 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
518 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 6 },
519 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 },
520 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 },
521 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 },
522 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 },
524 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 1 },
525 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 },
529 int Idx = ConvertCostTableLookup(AVX2ConversionTbl, ISD,
530 DstTy.getSimpleVT(), SrcTy.getSimpleVT());
532 return AVX2ConversionTbl[Idx].Cost;
536 int Idx = ConvertCostTableLookup(AVXConversionTbl, ISD, DstTy.getSimpleVT(),
537 SrcTy.getSimpleVT());
539 return AVXConversionTbl[Idx].Cost;
542 return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
545 unsigned X86TTI::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
546 Type *CondTy) const {
547 // Legalize the type.
548 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(ValTy);
552 int ISD = TLI->InstructionOpcodeToISD(Opcode);
553 assert(ISD && "Invalid opcode");
555 static const CostTblEntry<MVT::SimpleValueType> SSE42CostTbl[] = {
556 { ISD::SETCC, MVT::v2f64, 1 },
557 { ISD::SETCC, MVT::v4f32, 1 },
558 { ISD::SETCC, MVT::v2i64, 1 },
559 { ISD::SETCC, MVT::v4i32, 1 },
560 { ISD::SETCC, MVT::v8i16, 1 },
561 { ISD::SETCC, MVT::v16i8, 1 },
564 static const CostTblEntry<MVT::SimpleValueType> AVX1CostTbl[] = {
565 { ISD::SETCC, MVT::v4f64, 1 },
566 { ISD::SETCC, MVT::v8f32, 1 },
567 // AVX1 does not support 8-wide integer compare.
568 { ISD::SETCC, MVT::v4i64, 4 },
569 { ISD::SETCC, MVT::v8i32, 4 },
570 { ISD::SETCC, MVT::v16i16, 4 },
571 { ISD::SETCC, MVT::v32i8, 4 },
574 static const CostTblEntry<MVT::SimpleValueType> AVX2CostTbl[] = {
575 { ISD::SETCC, MVT::v4i64, 1 },
576 { ISD::SETCC, MVT::v8i32, 1 },
577 { ISD::SETCC, MVT::v16i16, 1 },
578 { ISD::SETCC, MVT::v32i8, 1 },
582 int Idx = CostTableLookup(AVX2CostTbl, ISD, MTy);
584 return LT.first * AVX2CostTbl[Idx].Cost;
588 int Idx = CostTableLookup(AVX1CostTbl, ISD, MTy);
590 return LT.first * AVX1CostTbl[Idx].Cost;
593 if (ST->hasSSE42()) {
594 int Idx = CostTableLookup(SSE42CostTbl, ISD, MTy);
596 return LT.first * SSE42CostTbl[Idx].Cost;
599 return TargetTransformInfo::getCmpSelInstrCost(Opcode, ValTy, CondTy);
602 unsigned X86TTI::getVectorInstrCost(unsigned Opcode, Type *Val,
603 unsigned Index) const {
604 assert(Val->isVectorTy() && "This must be a vector type");
607 // Legalize the type.
608 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Val);
610 // This type is legalized to a scalar type.
611 if (!LT.second.isVector())
614 // The type may be split. Normalize the index to the new type.
615 unsigned Width = LT.second.getVectorNumElements();
616 Index = Index % Width;
618 // Floating point scalars are already located in index #0.
619 if (Val->getScalarType()->isFloatingPointTy() && Index == 0)
623 return TargetTransformInfo::getVectorInstrCost(Opcode, Val, Index);
626 unsigned X86TTI::getScalarizationOverhead(Type *Ty, bool Insert,
627 bool Extract) const {
628 assert (Ty->isVectorTy() && "Can only scalarize vectors");
631 for (int i = 0, e = Ty->getVectorNumElements(); i < e; ++i) {
633 Cost += TopTTI->getVectorInstrCost(Instruction::InsertElement, Ty, i);
635 Cost += TopTTI->getVectorInstrCost(Instruction::ExtractElement, Ty, i);
641 unsigned X86TTI::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
642 unsigned AddressSpace) const {
643 // Handle non-power-of-two vectors such as <3 x float>
644 if (VectorType *VTy = dyn_cast<VectorType>(Src)) {
645 unsigned NumElem = VTy->getVectorNumElements();
647 // Handle a few common cases:
649 if (NumElem == 3 && VTy->getScalarSizeInBits() == 32)
650 // Cost = 64 bit store + extract + 32 bit store.
654 if (NumElem == 3 && VTy->getScalarSizeInBits() == 64)
655 // Cost = 128 bit store + unpack + 64 bit store.
658 // Assume that all other non-power-of-two numbers are scalarized.
659 if (!isPowerOf2_32(NumElem)) {
660 unsigned Cost = TargetTransformInfo::getMemoryOpCost(Opcode,
661 VTy->getScalarType(),
664 unsigned SplitCost = getScalarizationOverhead(Src,
665 Opcode == Instruction::Load,
666 Opcode==Instruction::Store);
667 return NumElem * Cost + SplitCost;
671 // Legalize the type.
672 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Src);
673 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) &&
676 // Each load/store unit costs 1.
677 unsigned Cost = LT.first * 1;
679 // On Sandybridge 256bit load/stores are double pumped
680 // (but not on Haswell).
681 if (LT.second.getSizeInBits() > 128 && !ST->hasAVX2())
687 unsigned X86TTI::getAddressComputationCost(Type *Ty, bool IsComplex) const {
688 // Address computations in vectorized code with non-consecutive addresses will
689 // likely result in more instructions compared to scalar code where the
690 // computation can more often be merged into the index mode. The resulting
691 // extra micro-ops can significantly decrease throughput.
692 unsigned NumVectorInstToHideOverhead = 10;
694 if (Ty->isVectorTy() && IsComplex)
695 return NumVectorInstToHideOverhead;
697 return TargetTransformInfo::getAddressComputationCost(Ty, IsComplex);
700 unsigned X86TTI::getReductionCost(unsigned Opcode, Type *ValTy,
701 bool IsPairwise) const {
703 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(ValTy);
707 int ISD = TLI->InstructionOpcodeToISD(Opcode);
708 assert(ISD && "Invalid opcode");
710 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput
711 // and make it as the cost.
713 static const CostTblEntry<MVT::SimpleValueType> SSE42CostTblPairWise[] = {
714 { ISD::FADD, MVT::v2f64, 2 },
715 { ISD::FADD, MVT::v4f32, 4 },
716 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6".
717 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.5".
718 { ISD::ADD, MVT::v8i16, 5 },
721 static const CostTblEntry<MVT::SimpleValueType> AVX1CostTblPairWise[] = {
722 { ISD::FADD, MVT::v4f32, 4 },
723 { ISD::FADD, MVT::v4f64, 5 },
724 { ISD::FADD, MVT::v8f32, 7 },
725 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5".
726 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.5".
727 { ISD::ADD, MVT::v4i64, 5 }, // The data reported by the IACA tool is "4.8".
728 { ISD::ADD, MVT::v8i16, 5 },
729 { ISD::ADD, MVT::v8i32, 5 },
732 static const CostTblEntry<MVT::SimpleValueType> SSE42CostTblNoPairWise[] = {
733 { ISD::FADD, MVT::v2f64, 2 },
734 { ISD::FADD, MVT::v4f32, 4 },
735 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6".
736 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3".
737 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3".
740 static const CostTblEntry<MVT::SimpleValueType> AVX1CostTblNoPairWise[] = {
741 { ISD::FADD, MVT::v4f32, 3 },
742 { ISD::FADD, MVT::v4f64, 3 },
743 { ISD::FADD, MVT::v8f32, 4 },
744 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5".
745 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "2.8".
746 { ISD::ADD, MVT::v4i64, 3 },
747 { ISD::ADD, MVT::v8i16, 4 },
748 { ISD::ADD, MVT::v8i32, 5 },
753 int Idx = CostTableLookup(AVX1CostTblPairWise, ISD, MTy);
755 return LT.first * AVX1CostTblPairWise[Idx].Cost;
758 if (ST->hasSSE42()) {
759 int Idx = CostTableLookup(SSE42CostTblPairWise, ISD, MTy);
761 return LT.first * SSE42CostTblPairWise[Idx].Cost;
765 int Idx = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy);
767 return LT.first * AVX1CostTblNoPairWise[Idx].Cost;
770 if (ST->hasSSE42()) {
771 int Idx = CostTableLookup(SSE42CostTblNoPairWise, ISD, MTy);
773 return LT.first * SSE42CostTblNoPairWise[Idx].Cost;
777 return TargetTransformInfo::getReductionCost(Opcode, ValTy, IsPairwise);
780 unsigned X86TTI::getIntImmCost(const APInt &Imm, Type *Ty) const {
781 assert(Ty->isIntegerTy());
783 unsigned BitSize = Ty->getPrimitiveSizeInBits();
787 if (Imm.getBitWidth() <= 64 &&
788 (isInt<32>(Imm.getSExtValue()) || isUInt<32>(Imm.getZExtValue())))
791 return 2 * TCC_Basic;
794 unsigned X86TTI::getIntImmCost(unsigned Opcode, const APInt &Imm,
796 assert(Ty->isIntegerTy());
798 unsigned BitSize = Ty->getPrimitiveSizeInBits();
803 case Instruction::Add:
804 case Instruction::Sub:
805 case Instruction::Mul:
806 case Instruction::UDiv:
807 case Instruction::SDiv:
808 case Instruction::URem:
809 case Instruction::SRem:
810 case Instruction::Shl:
811 case Instruction::LShr:
812 case Instruction::AShr:
813 case Instruction::And:
814 case Instruction::Or:
815 case Instruction::Xor:
816 case Instruction::ICmp:
817 if (Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue()))
820 return X86TTI::getIntImmCost(Imm, Ty);
821 case Instruction::Trunc:
822 case Instruction::ZExt:
823 case Instruction::SExt:
824 case Instruction::IntToPtr:
825 case Instruction::PtrToInt:
826 case Instruction::BitCast:
827 case Instruction::Call:
828 case Instruction::Select:
829 case Instruction::Ret:
830 case Instruction::Load:
831 case Instruction::Store:
832 return X86TTI::getIntImmCost(Imm, Ty);
834 return TargetTransformInfo::getIntImmCost(Opcode, Imm, Ty);
837 unsigned X86TTI::getIntImmCost(Intrinsic::ID IID, const APInt &Imm,
839 assert(Ty->isIntegerTy());
841 unsigned BitSize = Ty->getPrimitiveSizeInBits();
846 default: return TargetTransformInfo::getIntImmCost(IID, Imm, Ty);
847 case Intrinsic::sadd_with_overflow:
848 case Intrinsic::uadd_with_overflow:
849 case Intrinsic::ssub_with_overflow:
850 case Intrinsic::usub_with_overflow:
851 case Intrinsic::smul_with_overflow:
852 case Intrinsic::umul_with_overflow:
853 if (Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue()))
856 return X86TTI::getIntImmCost(Imm, Ty);
857 case Intrinsic::experimental_stackmap:
858 case Intrinsic::experimental_patchpoint_void:
859 case Intrinsic::experimental_patchpoint_i64:
860 if (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))
863 return X86TTI::getIntImmCost(Imm, Ty);