1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86 specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #include "X86TargetMachine.h"
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/PassManager.h"
18 #include "llvm/Support/CommandLine.h"
19 #include "llvm/Support/FormattedStream.h"
20 #include "llvm/Support/TargetRegistry.h"
21 #include "llvm/Target/TargetOptions.h"
24 extern "C" void LLVMInitializeX86Target() {
25 // Register the target.
26 RegisterTargetMachine<X86TargetMachine> X(TheX86_32Target);
27 RegisterTargetMachine<X86TargetMachine> Y(TheX86_64Target);
30 void X86TargetMachine::anchor() { }
32 static std::string computeDataLayout(const X86Subtarget &ST) {
33 // X86 is little endian
34 std::string Ret = "e";
36 Ret += DataLayout::getManglingComponent(ST.getTargetTriple());
37 // X86 and x32 have 32 bit pointers.
38 if (ST.isTarget64BitILP32() || !ST.is64Bit())
41 // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
42 if (ST.is64Bit() || ST.isOSWindows() || ST.isTargetNaCl())
47 // Some ABIs align long double to 128 bits, others to 32.
48 if (ST.isTargetNaCl())
50 else if (ST.is64Bit() || ST.isTargetDarwin())
55 // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
57 Ret += "-n8:16:32:64";
61 // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
62 if (!ST.is64Bit() && ST.isOSWindows())
70 /// X86TargetMachine ctor - Create an X86 target.
72 X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT, StringRef CPU,
73 StringRef FS, const TargetOptions &Options,
74 Reloc::Model RM, CodeModel::Model CM,
76 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
77 Subtarget(TT, CPU, FS, Options.StackAlignmentOverride),
78 FrameLowering(TargetFrameLowering::StackGrowsDown,
79 Subtarget.getStackAlignment(),
80 Subtarget.is64Bit() ? -8 : -4),
81 DL(computeDataLayout(*getSubtargetImpl())), InstrInfo(*this),
82 TLInfo(*this), TSInfo(DL), JITInfo(Subtarget.hasSSE1()) {
83 // Determine the PICStyle based on the target selected.
84 if (getRelocationModel() == Reloc::Static) {
85 // Unless we're in PIC or DynamicNoPIC mode, set the PIC style to None.
86 Subtarget.setPICStyle(PICStyles::None);
87 } else if (Subtarget.is64Bit()) {
88 // PIC in 64 bit mode is always rip-rel.
89 Subtarget.setPICStyle(PICStyles::RIPRel);
90 } else if (Subtarget.isTargetCOFF()) {
91 Subtarget.setPICStyle(PICStyles::None);
92 } else if (Subtarget.isTargetDarwin()) {
93 if (getRelocationModel() == Reloc::PIC_)
94 Subtarget.setPICStyle(PICStyles::StubPIC);
96 assert(getRelocationModel() == Reloc::DynamicNoPIC);
97 Subtarget.setPICStyle(PICStyles::StubDynamicNoPIC);
99 } else if (Subtarget.isTargetELF()) {
100 Subtarget.setPICStyle(PICStyles::GOT);
103 // default to hard float ABI
104 if (Options.FloatABIType == FloatABI::Default)
105 this->Options.FloatABIType = FloatABI::Hard;
107 // Windows stack unwinder gets confused when execution flow "falls through"
108 // after a call to 'noreturn' function.
109 // To prevent that, we emit a trap for 'unreachable' IR instructions.
110 // (which on X86, happens to be the 'ud2' instruction)
111 if (Subtarget.isTargetWin64())
112 this->Options.TrapUnreachable = true;
117 //===----------------------------------------------------------------------===//
118 // Command line options for x86
119 //===----------------------------------------------------------------------===//
121 UseVZeroUpper("x86-use-vzeroupper", cl::Hidden,
122 cl::desc("Minimize AVX to SSE transition penalty"),
125 //===----------------------------------------------------------------------===//
126 // X86 Analysis Pass Setup
127 //===----------------------------------------------------------------------===//
129 void X86TargetMachine::addAnalysisPasses(PassManagerBase &PM) {
130 // Add first the target-independent BasicTTI pass, then our X86 pass. This
131 // allows the X86 pass to delegate to the target independent layer when
133 PM.add(createBasicTargetTransformInfoPass(this));
134 PM.add(createX86TargetTransformInfoPass(this));
138 //===----------------------------------------------------------------------===//
139 // Pass Pipeline Configuration
140 //===----------------------------------------------------------------------===//
143 /// X86 Code Generator Pass Configuration Options.
144 class X86PassConfig : public TargetPassConfig {
146 X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM)
147 : TargetPassConfig(TM, PM) {}
149 X86TargetMachine &getX86TargetMachine() const {
150 return getTM<X86TargetMachine>();
153 const X86Subtarget &getX86Subtarget() const {
154 return *getX86TargetMachine().getSubtargetImpl();
157 bool addInstSelector() override;
158 bool addILPOpts() override;
159 bool addPreRegAlloc() override;
160 bool addPostRegAlloc() override;
161 bool addPreEmitPass() override;
165 TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
166 return new X86PassConfig(this, PM);
169 bool X86PassConfig::addInstSelector() {
170 // Install an instruction selector.
171 addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
173 // For ELF, cleanup any local-dynamic TLS accesses.
174 if (getX86Subtarget().isTargetELF() && getOptLevel() != CodeGenOpt::None)
175 addPass(createCleanupLocalDynamicTLSPass());
177 addPass(createX86GlobalBaseRegPass());
182 bool X86PassConfig::addILPOpts() {
183 addPass(&EarlyIfConverterID);
187 bool X86PassConfig::addPreRegAlloc() {
188 return false; // -print-machineinstr shouldn't print after this.
191 bool X86PassConfig::addPostRegAlloc() {
192 addPass(createX86FloatingPointStackifierPass());
193 return true; // -print-machineinstr should print after this.
196 bool X86PassConfig::addPreEmitPass() {
197 bool ShouldPrint = false;
198 if (getOptLevel() != CodeGenOpt::None && getX86Subtarget().hasSSE2()) {
199 addPass(createExecutionDependencyFixPass(&X86::VR128RegClass));
204 addPass(createX86IssueVZeroUpperPass());
208 if (getOptLevel() != CodeGenOpt::None) {
209 addPass(createX86PadShortFunctions());
210 addPass(createX86FixupLEAs());
217 bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM,
218 JITCodeEmitter &JCE) {
219 PM.add(createX86JITCodeEmitterPass(*this, JCE));