1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86 specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #include "X86TargetMachine.h"
16 #include "llvm/IntrinsicLowering.h"
17 #include "llvm/Module.h"
18 #include "llvm/PassManager.h"
19 #include "llvm/Target/TargetMachineImpls.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/Passes.h"
22 #include "llvm/Transforms/Scalar.h"
23 #include "Support/CommandLine.h"
24 #include "Support/Statistic.h"
28 cl::opt<bool> PrintCode("print-machineinstrs",
29 cl::desc("Print generated machine code"));
30 cl::opt<bool> NoPatternISel("disable-pattern-isel", cl::init(true),
31 cl::desc("Use the 'simple' X86 instruction selector"));
32 cl::opt<bool> NoSSAPeephole("disable-ssa-peephole", cl::init(true),
33 cl::desc("Disable the ssa-based peephole optimizer "
34 "(defaults to disabled)"));
35 cl::opt<bool> DisableOutput("disable-x86-llc-output", cl::Hidden,
36 cl::desc("Disable the X86 asm printer, for use "
37 "when profiling the code generator."));
40 // allocateX86TargetMachine - Allocate and return a subclass of TargetMachine
41 // that implements the X86 backend.
43 TargetMachine *llvm::allocateX86TargetMachine(const Module &M,
44 IntrinsicLowering *IL) {
45 return new X86TargetMachine(M, IL);
49 /// X86TargetMachine ctor - Create an ILP32 architecture model
51 X86TargetMachine::X86TargetMachine(const Module &M, IntrinsicLowering *IL)
52 : TargetMachine("X86", IL, true, 4, 4, 4, 4, 4),
53 FrameInfo(TargetFrameInfo::StackGrowsDown, 8/*16 for SSE*/, 4),
58 // addPassesToEmitAssembly - We currently use all of the same passes as the JIT
59 // does to emit statically compiled machine code.
60 bool X86TargetMachine::addPassesToEmitAssembly(PassManager &PM,
62 // FIXME: Implement the switch instruction in the instruction selector!
63 PM.add(createLowerSwitchPass());
65 // FIXME: Implement the invoke/unwind instructions!
66 PM.add(createLowerInvokePass());
68 // FIXME: The code generator does not properly handle functions with
69 // unreachable basic blocks.
70 PM.add(createCFGSimplificationPass());
73 PM.add(createX86SimpleInstructionSelector(*this));
75 PM.add(createX86PatternInstructionSelector(*this));
77 // Run optional SSA-based machine code optimizations next...
79 PM.add(createX86SSAPeepholeOptimizerPass());
81 // Print the instruction selected machine code...
83 PM.add(createMachineFunctionPrinterPass(&std::cerr));
85 // Perform register allocation to convert to a concrete x86 representation
86 PM.add(createRegisterAllocator());
89 PM.add(createMachineFunctionPrinterPass(&std::cerr));
91 PM.add(createX86FloatingPointStackifierPass());
94 PM.add(createMachineFunctionPrinterPass(&std::cerr));
96 // Insert prolog/epilog code. Eliminate abstract frame index references...
97 PM.add(createPrologEpilogCodeInserter());
99 PM.add(createX86PeepholeOptimizerPass());
101 if (PrintCode) // Print the register-allocated code
102 PM.add(createX86CodePrinterPass(std::cerr, *this));
105 PM.add(createX86CodePrinterPass(Out, *this));
107 // Delete machine code for this function
108 PM.add(createMachineCodeDeleter());
110 return false; // success!
113 /// addPassesToJITCompile - Add passes to the specified pass manager to
114 /// implement a fast dynamic compiler for this target. Return true if this is
115 /// not supported for this target.
117 void X86JITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
118 // FIXME: Implement the switch instruction in the instruction selector!
119 PM.add(createLowerSwitchPass());
121 // FIXME: Implement the invoke/unwind instructions!
122 PM.add(createLowerInvokePass());
124 // FIXME: The code generator does not properly handle functions with
125 // unreachable basic blocks.
126 PM.add(createCFGSimplificationPass());
129 PM.add(createX86SimpleInstructionSelector(TM));
131 PM.add(createX86PatternInstructionSelector(TM));
133 // Run optional SSA-based machine code optimizations next...
135 PM.add(createX86SSAPeepholeOptimizerPass());
137 // FIXME: Add SSA based peephole optimizer here.
139 // Print the instruction selected machine code...
141 PM.add(createMachineFunctionPrinterPass(&std::cerr));
143 // Perform register allocation to convert to a concrete x86 representation
144 PM.add(createRegisterAllocator());
147 PM.add(createMachineFunctionPrinterPass(&std::cerr));
149 PM.add(createX86FloatingPointStackifierPass());
152 PM.add(createMachineFunctionPrinterPass(&std::cerr));
154 // Insert prolog/epilog code. Eliminate abstract frame index references...
155 PM.add(createPrologEpilogCodeInserter());
157 PM.add(createX86PeepholeOptimizerPass());
159 if (PrintCode) // Print the register-allocated code
160 PM.add(createX86CodePrinterPass(std::cerr, TM));