1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86 specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #include "X86TargetMachine.h"
16 #include "llvm/CodeGen/MachineFunction.h"
17 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/PassManager.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/FormattedStream.h"
21 #include "llvm/Support/TargetRegistry.h"
22 #include "llvm/Target/TargetOptions.h"
25 extern "C" void LLVMInitializeX86Target() {
26 // Register the target.
27 RegisterTargetMachine<X86_32TargetMachine> X(TheX86_32Target);
28 RegisterTargetMachine<X86_64TargetMachine> Y(TheX86_64Target);
31 void X86_32TargetMachine::anchor() { }
33 static std::string computeDataLayout(const X86Subtarget &ST) {
34 // X86 is little endian
35 std::string Ret = "e";
37 // X86 and x32 have 32 bit pointers.
38 if (ST.isTarget64BitILP32() || !ST.is64Bit())
41 // Objects on the stack ore aligned to 64 bits.
42 // FIXME: of any size?
46 // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
47 if (ST.is64Bit() || ST.isTargetCygMing() || ST.isTargetWindows())
52 // Some ABIs align long double to 128 bits, others to 32.
53 if (ST.is64Bit() || ST.isTargetDarwin())
58 // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
60 Ret += "-n8:16:32:64";
64 // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
65 if (!ST.is64Bit() && (ST.isTargetCygMing() || ST.isTargetWindows()))
73 X86_32TargetMachine::X86_32TargetMachine(const Target &T, StringRef TT,
74 StringRef CPU, StringRef FS,
75 const TargetOptions &Options,
76 Reloc::Model RM, CodeModel::Model CM,
78 : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false),
79 DL(computeDataLayout(*getSubtargetImpl())),
87 void X86_64TargetMachine::anchor() { }
89 X86_64TargetMachine::X86_64TargetMachine(const Target &T, StringRef TT,
90 StringRef CPU, StringRef FS,
91 const TargetOptions &Options,
92 Reloc::Model RM, CodeModel::Model CM,
94 : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true),
95 // The x32 ABI dictates the ILP32 programming model for x64.
96 DL(computeDataLayout(*getSubtargetImpl())),
104 /// X86TargetMachine ctor - Create an X86 target.
106 X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT,
107 StringRef CPU, StringRef FS,
108 const TargetOptions &Options,
109 Reloc::Model RM, CodeModel::Model CM,
110 CodeGenOpt::Level OL,
112 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
113 Subtarget(TT, CPU, FS, Options.StackAlignmentOverride, is64Bit),
114 FrameLowering(*this, Subtarget),
115 InstrItins(Subtarget.getInstrItineraryData()){
116 // Determine the PICStyle based on the target selected.
117 if (getRelocationModel() == Reloc::Static) {
118 // Unless we're in PIC or DynamicNoPIC mode, set the PIC style to None.
119 Subtarget.setPICStyle(PICStyles::None);
120 } else if (Subtarget.is64Bit()) {
121 // PIC in 64 bit mode is always rip-rel.
122 Subtarget.setPICStyle(PICStyles::RIPRel);
123 } else if (Subtarget.isTargetCOFF()) {
124 Subtarget.setPICStyle(PICStyles::None);
125 } else if (Subtarget.isTargetDarwin()) {
126 if (getRelocationModel() == Reloc::PIC_)
127 Subtarget.setPICStyle(PICStyles::StubPIC);
129 assert(getRelocationModel() == Reloc::DynamicNoPIC);
130 Subtarget.setPICStyle(PICStyles::StubDynamicNoPIC);
132 } else if (Subtarget.isTargetELF()) {
133 Subtarget.setPICStyle(PICStyles::GOT);
136 // default to hard float ABI
137 if (Options.FloatABIType == FloatABI::Default)
138 this->Options.FloatABIType = FloatABI::Hard;
141 //===----------------------------------------------------------------------===//
142 // Command line options for x86
143 //===----------------------------------------------------------------------===//
145 UseVZeroUpper("x86-use-vzeroupper", cl::Hidden,
146 cl::desc("Minimize AVX to SSE transition penalty"),
149 // Temporary option to control early if-conversion for x86 while adding machine
152 X86EarlyIfConv("x86-early-ifcvt", cl::Hidden,
153 cl::desc("Enable early if-conversion on X86"));
155 //===----------------------------------------------------------------------===//
156 // X86 Analysis Pass Setup
157 //===----------------------------------------------------------------------===//
159 void X86TargetMachine::addAnalysisPasses(PassManagerBase &PM) {
160 // Add first the target-independent BasicTTI pass, then our X86 pass. This
161 // allows the X86 pass to delegate to the target independent layer when
163 PM.add(createBasicTargetTransformInfoPass(this));
164 PM.add(createX86TargetTransformInfoPass(this));
168 //===----------------------------------------------------------------------===//
169 // Pass Pipeline Configuration
170 //===----------------------------------------------------------------------===//
173 /// X86 Code Generator Pass Configuration Options.
174 class X86PassConfig : public TargetPassConfig {
176 X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM)
177 : TargetPassConfig(TM, PM) {}
179 X86TargetMachine &getX86TargetMachine() const {
180 return getTM<X86TargetMachine>();
183 const X86Subtarget &getX86Subtarget() const {
184 return *getX86TargetMachine().getSubtargetImpl();
187 virtual bool addInstSelector();
188 virtual bool addILPOpts();
189 virtual bool addPreRegAlloc();
190 virtual bool addPostRegAlloc();
191 virtual bool addPreEmitPass();
195 TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
196 return new X86PassConfig(this, PM);
199 bool X86PassConfig::addInstSelector() {
200 // Install an instruction selector.
201 addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
203 // For ELF, cleanup any local-dynamic TLS accesses.
204 if (getX86Subtarget().isTargetELF() && getOptLevel() != CodeGenOpt::None)
205 addPass(createCleanupLocalDynamicTLSPass());
207 // For 32-bit, prepend instructions to set the "global base reg" for PIC.
208 if (!getX86Subtarget().is64Bit())
209 addPass(createGlobalBaseRegPass());
214 bool X86PassConfig::addILPOpts() {
215 if (X86EarlyIfConv && getX86Subtarget().hasCMov()) {
216 addPass(&EarlyIfConverterID);
222 bool X86PassConfig::addPreRegAlloc() {
223 return false; // -print-machineinstr shouldn't print after this.
226 bool X86PassConfig::addPostRegAlloc() {
227 addPass(createX86FloatingPointStackifierPass());
228 return true; // -print-machineinstr should print after this.
231 bool X86PassConfig::addPreEmitPass() {
232 bool ShouldPrint = false;
233 if (getOptLevel() != CodeGenOpt::None && getX86Subtarget().hasSSE2()) {
234 addPass(createExecutionDependencyFixPass(&X86::VR128RegClass));
238 if (getX86Subtarget().hasAVX() && UseVZeroUpper) {
239 addPass(createX86IssueVZeroUpperPass());
243 if (getOptLevel() != CodeGenOpt::None &&
244 getX86Subtarget().padShortFunctions()) {
245 addPass(createX86PadShortFunctions());
248 if (getOptLevel() != CodeGenOpt::None &&
249 getX86Subtarget().LEAusesAG()){
250 addPass(createX86FixupLEAs());
257 bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM,
258 JITCodeEmitter &JCE) {
259 PM.add(createX86JITCodeEmitterPass(*this, JCE));