1 //===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the X86 specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_X86_X86SUBTARGET_H
15 #define LLVM_LIB_TARGET_X86_X86SUBTARGET_H
17 #include "X86FrameLowering.h"
18 #include "X86ISelLowering.h"
19 #include "X86InstrInfo.h"
20 #include "X86SelectionDAGInfo.h"
21 #include "llvm/ADT/Triple.h"
22 #include "llvm/IR/CallingConv.h"
23 #include "llvm/Target/TargetSubtargetInfo.h"
26 #define GET_SUBTARGETINFO_HEADER
27 #include "X86GenSubtargetInfo.inc"
34 /// The X86 backend supports a number of different styles of PIC.
38 StubPIC, // Used on i386-darwin in -fPIC mode.
39 StubDynamicNoPIC, // Used on i386-darwin in -mdynamic-no-pic mode.
40 GOT, // Used on many 32-bit unices in -fPIC mode.
41 RIPRel, // Used on X86-64 when not in -static mode.
42 None // Set when in -static mode (not PIC or DynamicNoPIC mode).
46 class X86Subtarget final : public X86GenSubtargetInfo {
50 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
54 NoThreeDNow, ThreeDNow, ThreeDNowA
57 enum X86ProcFamilyEnum {
58 Others, IntelAtom, IntelSLM
61 /// X86 processor family: Intel Atom, and others
62 X86ProcFamilyEnum X86ProcFamily;
64 /// Which PIC style to use
65 PICStyles::Style PICStyle;
67 /// SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.
68 X86SSEEnum X86SSELevel;
70 /// 3DNow, 3DNow Athlon, or none supported.
71 X863DNowEnum X863DNowLevel;
73 /// True if this processor has conditional move instructions
74 /// (generally pentium pro+).
77 /// True if this processor supports MMX instructions.
80 /// True if the processor supports X86-64 instructions.
83 /// True if the processor supports POPCNT.
86 /// True if the processor supports SSE4A instructions.
89 /// Target has AES instructions
92 /// Target has carry-less multiplication
95 /// Target has 3-operand fused multiply-add
98 /// Target has 4-operand fused multiply-add
101 /// Target has XOP instructions
104 /// Target has TBM instructions.
107 /// True if the processor has the MOVBE instruction.
110 /// True if the processor has the RDRAND instruction.
113 /// Processor has 16-bit floating point conversion instructions.
116 /// Processor has FS/GS base insturctions.
119 /// Processor has LZCNT instruction.
122 /// Processor has BMI1 instructions.
125 /// Processor has BMI2 instructions.
128 /// Processor has RTM instructions.
131 /// Processor has HLE.
134 /// Processor has ADX instructions.
137 /// Processor has SHA instructions.
140 /// Processor has PRFCHW instructions.
143 /// Processor has RDSEED instructions.
146 /// True if BT (bit test) of memory instructions are slow.
149 /// True if SHLD instructions are slow.
152 /// True if unaligned memory accesses of 16-bytes are slow.
155 /// True if unaligned memory accesses of 32-bytes are slow.
158 /// True if SSE operations can have unaligned memory operands.
159 /// This may require setting a configuration bit in the processor.
160 bool HasSSEUnalignedMem;
162 /// True if this processor has the CMPXCHG16B instruction;
163 /// this is true for most x86-64 chips, but not the first AMD chips.
166 /// True if the LEA instruction should be used for adjusting
167 /// the stack pointer. This is an optimization for Intel Atom processors.
170 /// True if 8-bit divisions are significantly faster than
171 /// 32-bit divisions and should be used when possible.
172 bool HasSlowDivide32;
174 /// True if 16-bit divides are significantly faster than
175 /// 64-bit divisions and should be used when possible.
176 bool HasSlowDivide64;
178 /// True if the short functions should be padded to prevent
179 /// a stall when returning too early.
180 bool PadShortFunctions;
182 /// True if the Calls with memory reference should be converted
183 /// to a register-based indirect call.
184 bool CallRegIndirect;
186 /// True if the LEA instruction inputs have to be ready at address generation
190 /// True if the LEA instruction with certain arguments is slow
193 /// True if INC and DEC instructions are slow when writing to flags
196 /// Processor has AVX-512 PreFetch Instructions
199 /// Processor has AVX-512 Exponential and Reciprocal Instructions
202 /// Processor has AVX-512 Conflict Detection Instructions
205 /// Processor has AVX-512 Doubleword and Quadword instructions
208 /// Processor has AVX-512 Byte and Word instructions
211 /// Processor has AVX-512 Vector Length eXtenstions
214 /// Processot supports MPX - Memory Protection Extensions
217 /// Use software floating point for code generation.
220 /// The minimum alignment known to hold of the stack frame on
221 /// entry to the function and which must be maintained by every function.
222 unsigned stackAlignment;
224 /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
226 unsigned MaxInlineSizeThreshold;
228 /// What processor and OS we're targeting.
231 /// Instruction itineraries for scheduling
232 InstrItineraryData InstrItins;
236 /// Override the stack alignment.
237 unsigned StackAlignOverride;
239 /// True if compiling for 64-bit, false for 16-bit or 32-bit.
242 /// True if compiling for 32-bit, false for 16-bit or 64-bit.
245 /// True if compiling for 16-bit, false for 32-bit or 64-bit.
248 X86SelectionDAGInfo TSInfo;
249 // Ordering here is important. X86InstrInfo initializes X86RegisterInfo which
250 // X86TargetLowering needs.
251 X86InstrInfo InstrInfo;
252 X86TargetLowering TLInfo;
253 X86FrameLowering FrameLowering;
256 /// This constructor initializes the data members to match that
257 /// of the specified triple.
259 X86Subtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
260 const X86TargetMachine &TM, unsigned StackAlignOverride);
262 const X86TargetLowering *getTargetLowering() const override {
265 const X86InstrInfo *getInstrInfo() const override { return &InstrInfo; }
266 const X86FrameLowering *getFrameLowering() const override {
267 return &FrameLowering;
269 const X86SelectionDAGInfo *getSelectionDAGInfo() const override {
272 const X86RegisterInfo *getRegisterInfo() const override {
273 return &getInstrInfo()->getRegisterInfo();
276 /// Returns the minimum alignment known to hold of the
277 /// stack frame on entry to the function and which must be maintained by every
278 /// function for this subtarget.
279 unsigned getStackAlignment() const { return stackAlignment; }
281 /// Returns the maximum memset / memcpy size
282 /// that still makes it profitable to inline the call.
283 unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
285 /// ParseSubtargetFeatures - Parses features string setting specified
286 /// subtarget options. Definition of function is auto generated by tblgen.
287 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
290 /// Initialize the full set of dependencies so we can use an initializer
291 /// list for X86Subtarget.
292 X86Subtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
293 void initializeEnvironment();
294 void initSubtargetFeatures(StringRef CPU, StringRef FS);
296 /// Is this x86_64? (disregarding specific ABI / programming model)
297 bool is64Bit() const {
301 bool is32Bit() const {
305 bool is16Bit() const {
309 /// Is this x86_64 with the ILP32 programming model (x32 ABI)?
310 bool isTarget64BitILP32() const {
311 return In64BitMode && (TargetTriple.getEnvironment() == Triple::GNUX32 ||
312 TargetTriple.isOSNaCl());
315 /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
316 bool isTarget64BitLP64() const {
317 return In64BitMode && (TargetTriple.getEnvironment() != Triple::GNUX32 &&
318 !TargetTriple.isOSNaCl());
321 PICStyles::Style getPICStyle() const { return PICStyle; }
322 void setPICStyle(PICStyles::Style Style) { PICStyle = Style; }
324 bool hasCMov() const { return HasCMov; }
325 bool hasMMX() const { return HasMMX; }
326 bool hasSSE1() const { return X86SSELevel >= SSE1; }
327 bool hasSSE2() const { return X86SSELevel >= SSE2; }
328 bool hasSSE3() const { return X86SSELevel >= SSE3; }
329 bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
330 bool hasSSE41() const { return X86SSELevel >= SSE41; }
331 bool hasSSE42() const { return X86SSELevel >= SSE42; }
332 bool hasAVX() const { return X86SSELevel >= AVX; }
333 bool hasAVX2() const { return X86SSELevel >= AVX2; }
334 bool hasAVX512() const { return X86SSELevel >= AVX512F; }
335 bool hasFp256() const { return hasAVX(); }
336 bool hasInt256() const { return hasAVX2(); }
337 bool hasSSE4A() const { return HasSSE4A; }
338 bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
339 bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
340 bool hasPOPCNT() const { return HasPOPCNT; }
341 bool hasAES() const { return HasAES; }
342 bool hasPCLMUL() const { return HasPCLMUL; }
343 bool hasFMA() const { return HasFMA; }
344 // FIXME: Favor FMA when both are enabled. Is this the right thing to do?
345 bool hasFMA4() const { return HasFMA4 && !HasFMA; }
346 bool hasXOP() const { return HasXOP; }
347 bool hasTBM() const { return HasTBM; }
348 bool hasMOVBE() const { return HasMOVBE; }
349 bool hasRDRAND() const { return HasRDRAND; }
350 bool hasF16C() const { return HasF16C; }
351 bool hasFSGSBase() const { return HasFSGSBase; }
352 bool hasLZCNT() const { return HasLZCNT; }
353 bool hasBMI() const { return HasBMI; }
354 bool hasBMI2() const { return HasBMI2; }
355 bool hasRTM() const { return HasRTM; }
356 bool hasHLE() const { return HasHLE; }
357 bool hasADX() const { return HasADX; }
358 bool hasSHA() const { return HasSHA; }
359 bool hasPRFCHW() const { return HasPRFCHW; }
360 bool hasRDSEED() const { return HasRDSEED; }
361 bool isBTMemSlow() const { return IsBTMemSlow; }
362 bool isSHLDSlow() const { return IsSHLDSlow; }
363 bool isUnalignedMem16Slow() const { return IsUAMem16Slow; }
364 bool isUnalignedMem32Slow() const { return IsUAMem32Slow; }
365 bool hasSSEUnalignedMem() const { return HasSSEUnalignedMem; }
366 bool hasCmpxchg16b() const { return HasCmpxchg16b; }
367 bool useLeaForSP() const { return UseLeaForSP; }
368 bool hasSlowDivide32() const { return HasSlowDivide32; }
369 bool hasSlowDivide64() const { return HasSlowDivide64; }
370 bool padShortFunctions() const { return PadShortFunctions; }
371 bool callRegIndirect() const { return CallRegIndirect; }
372 bool LEAusesAG() const { return LEAUsesAG; }
373 bool slowLEA() const { return SlowLEA; }
374 bool slowIncDec() const { return SlowIncDec; }
375 bool hasCDI() const { return HasCDI; }
376 bool hasPFI() const { return HasPFI; }
377 bool hasERI() const { return HasERI; }
378 bool hasDQI() const { return HasDQI; }
379 bool hasBWI() const { return HasBWI; }
380 bool hasVLX() const { return HasVLX; }
381 bool hasMPX() const { return HasMPX; }
383 bool isAtom() const { return X86ProcFamily == IntelAtom; }
384 bool isSLM() const { return X86ProcFamily == IntelSLM; }
385 bool useSoftFloat() const { return UseSoftFloat; }
387 const Triple &getTargetTriple() const { return TargetTriple; }
389 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
390 bool isTargetFreeBSD() const { return TargetTriple.isOSFreeBSD(); }
391 bool isTargetDragonFly() const { return TargetTriple.isOSDragonFly(); }
392 bool isTargetSolaris() const { return TargetTriple.isOSSolaris(); }
393 bool isTargetPS4() const { return TargetTriple.isPS4(); }
395 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
396 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
397 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
399 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
400 bool isTargetAndroid() const {
401 return TargetTriple.getEnvironment() == Triple::Android;
403 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
404 bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
405 bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
407 bool isTargetWindowsMSVC() const {
408 return TargetTriple.isWindowsMSVCEnvironment();
411 bool isTargetKnownWindowsMSVC() const {
412 return TargetTriple.isKnownWindowsMSVCEnvironment();
415 bool isTargetWindowsCoreCLR() const {
416 return TargetTriple.isWindowsCoreCLREnvironment();
419 bool isTargetWindowsCygwin() const {
420 return TargetTriple.isWindowsCygwinEnvironment();
423 bool isTargetWindowsGNU() const {
424 return TargetTriple.isWindowsGNUEnvironment();
427 bool isTargetWindowsItanium() const {
428 return TargetTriple.isWindowsItaniumEnvironment();
431 bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); }
433 bool isOSWindows() const { return TargetTriple.isOSWindows(); }
435 bool isTargetWin64() const {
436 return In64BitMode && TargetTriple.isOSWindows();
439 bool isTargetWin32() const {
440 return !In64BitMode && (isTargetCygMing() || isTargetKnownWindowsMSVC());
443 bool isPICStyleSet() const { return PICStyle != PICStyles::None; }
444 bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; }
445 bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; }
447 bool isPICStyleStubPIC() const {
448 return PICStyle == PICStyles::StubPIC;
451 bool isPICStyleStubNoDynamic() const {
452 return PICStyle == PICStyles::StubDynamicNoPIC;
454 bool isPICStyleStubAny() const {
455 return PICStyle == PICStyles::StubDynamicNoPIC ||
456 PICStyle == PICStyles::StubPIC;
459 bool isCallingConvWin64(CallingConv::ID CC) const {
461 // On Win64, all these conventions just use the default convention.
463 case CallingConv::Fast:
464 case CallingConv::X86_FastCall:
465 case CallingConv::X86_StdCall:
466 case CallingConv::X86_ThisCall:
467 case CallingConv::X86_VectorCall:
468 case CallingConv::Intel_OCL_BI:
469 return isTargetWin64();
470 // This convention allows using the Win64 convention on other targets.
471 case CallingConv::X86_64_Win64:
473 // This convention allows using the SysV convention on Windows targets.
474 case CallingConv::X86_64_SysV:
476 // Otherwise, who knows what this is.
482 /// ClassifyGlobalReference - Classify a global variable reference for the
483 /// current subtarget according to how we should reference it in a non-pcrel
485 unsigned char ClassifyGlobalReference(const GlobalValue *GV,
486 const TargetMachine &TM)const;
488 /// Classify a blockaddress reference for the current subtarget according to
489 /// how we should reference it in a non-pcrel context.
490 unsigned char ClassifyBlockAddressReference() const;
492 /// Return true if the subtarget allows calls to immediate address.
493 bool IsLegalToCallImmediateAddr(const TargetMachine &TM) const;
495 /// This function returns the name of a function which has an interface
496 /// like the non-standard bzero function, if such a function exists on
497 /// the current subtarget and it is considered prefereable over
498 /// memset with zero passed as the second argument. Otherwise it
500 const char *getBZeroEntry() const;
502 /// This function returns true if the target has sincos() routine in its
503 /// compiler runtime or math libraries.
504 bool hasSinCos() const;
506 /// Enable the MachineScheduler pass for all X86 subtargets.
507 bool enableMachineScheduler() const override { return true; }
509 bool enableEarlyIfConversion() const override;
511 /// Return the instruction itineraries based on the subtarget selection.
512 const InstrItineraryData *getInstrItineraryData() const override {
516 AntiDepBreakMode getAntiDepBreakMode() const override {
517 return TargetSubtargetInfo::ANTIDEP_CRITICAL;
521 } // End llvm namespace