1 //=====---- X86Subtarget.h - Define Subtarget for the X86 -----*- C++ -*--====//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the X86 specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef X86SUBTARGET_H
15 #define X86SUBTARGET_H
17 #include "llvm/ADT/Triple.h"
18 #include "llvm/Target/TargetSubtargetInfo.h"
19 #include "llvm/CallingConv.h"
22 #define GET_SUBTARGETINFO_HEADER
23 #include "X86GenSubtargetInfo.inc"
30 /// PICStyles - The X86 backend supports a number of different styles of PIC.
34 StubPIC, // Used on i386-darwin in -fPIC mode.
35 StubDynamicNoPIC, // Used on i386-darwin in -mdynamic-no-pic mode.
36 GOT, // Used on many 32-bit unices in -fPIC mode.
37 RIPRel, // Used on X86-64 when not in -static mode.
38 None // Set when in -static mode (not PIC or DynamicNoPIC mode).
42 class X86Subtarget : public X86GenSubtargetInfo {
45 NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2
49 NoThreeDNow, ThreeDNow, ThreeDNowA
52 /// PICStyle - Which PIC style to use
54 PICStyles::Style PICStyle;
56 /// X86SSELevel - MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or
58 X86SSEEnum X86SSELevel;
60 /// X863DNowLevel - 3DNow or 3DNow Athlon, or none supported.
62 X863DNowEnum X863DNowLevel;
64 /// HasCMov - True if this processor has conditional move instructions
65 /// (generally pentium pro+).
68 /// HasX86_64 - True if the processor supports X86-64 instructions.
72 /// HasPOPCNT - True if the processor supports POPCNT.
75 /// HasSSE4A - True if the processor supports SSE4A instructions.
78 /// HasAES - Target has AES instructions
81 /// HasCLMUL - Target has carry-less multiplication
84 /// HasFMA3 - Target has 3-operand fused multiply-add
87 /// HasFMA4 - Target has 4-operand fused multiply-add
90 /// HasXOP - Target has XOP instructions
93 /// HasMOVBE - True if the processor has the MOVBE instruction.
96 /// HasRDRAND - True if the processor has the RDRAND instruction.
99 /// HasF16C - Processor has 16-bit floating point conversion instructions.
102 /// HasFSGSBase - Processor has FS/GS base insturctions.
105 /// HasLZCNT - Processor has LZCNT instruction.
108 /// HasBMI - Processor has BMI1 instructions.
111 /// HasBMI2 - Processor has BMI2 instructions.
114 /// IsBTMemSlow - True if BT (bit test) of memory instructions are slow.
117 /// IsUAMemFast - True if unaligned memory access is fast.
120 /// HasVectorUAMem - True if SIMD operations can have unaligned memory
121 /// operands. This may require setting a feature bit in the processor.
124 /// HasCmpxchg16b - True if this processor has the CMPXCHG16B instruction;
125 /// this is true for most x86-64 chips, but not the first AMD chips.
128 /// stackAlignment - The minimum alignment known to hold of the stack frame on
129 /// entry to the function and which must be maintained by every function.
130 unsigned stackAlignment;
132 /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
134 unsigned MaxInlineSizeThreshold;
136 /// TargetTriple - What processor and OS we're targeting.
140 /// In64BitMode - True if compiling for 64-bit, false for 32-bit.
145 /// This constructor initializes the data members to match that
146 /// of the specified triple.
148 X86Subtarget(const std::string &TT, const std::string &CPU,
149 const std::string &FS,
150 unsigned StackAlignOverride, bool is64Bit);
152 /// getStackAlignment - Returns the minimum alignment known to hold of the
153 /// stack frame on entry to the function and which must be maintained by every
154 /// function for this subtarget.
155 unsigned getStackAlignment() const { return stackAlignment; }
157 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
158 /// that still makes it profitable to inline the call.
159 unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
161 /// ParseSubtargetFeatures - Parses features string setting specified
162 /// subtarget options. Definition of function is auto generated by tblgen.
163 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
165 /// AutoDetectSubtargetFeatures - Auto-detect CPU features using CPUID
167 void AutoDetectSubtargetFeatures();
169 bool is64Bit() const { return In64BitMode; }
171 PICStyles::Style getPICStyle() const { return PICStyle; }
172 void setPICStyle(PICStyles::Style Style) { PICStyle = Style; }
174 bool hasCMov() const { return HasCMov; }
175 bool hasMMX() const { return X86SSELevel >= MMX; }
176 bool hasSSE1() const { return X86SSELevel >= SSE1 && !hasAVX(); }
177 bool hasSSE2() const { return X86SSELevel >= SSE2 && !hasAVX(); }
178 bool hasSSE3() const { return X86SSELevel >= SSE3 && !hasAVX(); }
179 bool hasSSSE3() const { return X86SSELevel >= SSSE3 && !hasAVX(); }
180 bool hasSSE41() const { return X86SSELevel >= SSE41 && !hasAVX(); }
181 bool hasSSE42() const { return X86SSELevel >= SSE42 && !hasAVX(); }
182 bool hasSSE4A() const { return HasSSE4A; }
183 bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
184 bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
185 bool hasPOPCNT() const { return HasPOPCNT; }
186 bool hasAVX() const { return X86SSELevel >= AVX; }
187 bool hasAVX2() const { return X86SSELevel >= AVX2; }
188 bool hasXMM() const { return X86SSELevel >= SSE1; }
189 bool hasXMMInt() const { return X86SSELevel >= SSE2; }
190 bool hasSSE3orAVX() const { return X86SSELevel >= SSE3; }
191 bool hasSSSE3orAVX() const { return X86SSELevel >= SSSE3; }
192 bool hasSSE41orAVX() const { return X86SSELevel >= SSE41; }
193 bool hasSSE42orAVX() const { return X86SSELevel >= SSE42; }
194 bool hasAES() const { return HasAES; }
195 bool hasCLMUL() const { return HasCLMUL; }
196 bool hasFMA3() const { return HasFMA3; }
197 bool hasFMA4() const { return HasFMA4; }
198 bool hasXOP() const { return HasXOP; }
199 bool hasMOVBE() const { return HasMOVBE; }
200 bool hasRDRAND() const { return HasRDRAND; }
201 bool hasF16C() const { return HasF16C; }
202 bool hasFSGSBase() const { return HasFSGSBase; }
203 bool hasLZCNT() const { return HasLZCNT; }
204 bool hasBMI() const { return HasBMI; }
205 bool hasBMI2() const { return HasBMI2; }
206 bool isBTMemSlow() const { return IsBTMemSlow; }
207 bool isUnalignedMemAccessFast() const { return IsUAMemFast; }
208 bool hasVectorUAMem() const { return HasVectorUAMem; }
209 bool hasCmpxchg16b() const { return HasCmpxchg16b; }
211 const Triple &getTargetTriple() const { return TargetTriple; }
213 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
214 bool isTargetFreeBSD() const {
215 return TargetTriple.getOS() == Triple::FreeBSD;
217 bool isTargetSolaris() const {
218 return TargetTriple.getOS() == Triple::Solaris;
221 // ELF is a reasonably sane default and the only other X86 targets we
222 // support are Darwin and Windows. Just use "not those".
223 bool isTargetELF() const {
224 return !isTargetDarwin() && !isTargetWindows() && !isTargetCygMing();
226 bool isTargetLinux() const { return TargetTriple.getOS() == Triple::Linux; }
227 bool isTargetNaCl() const {
228 return TargetTriple.getOS() == Triple::NativeClient;
230 bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
231 bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
233 bool isTargetWindows() const { return TargetTriple.getOS() == Triple::Win32; }
234 bool isTargetMingw() const { return TargetTriple.getOS() == Triple::MinGW32; }
235 bool isTargetCygwin() const { return TargetTriple.getOS() == Triple::Cygwin; }
236 bool isTargetCygMing() const {
237 return isTargetMingw() || isTargetCygwin();
240 /// isTargetCOFF - Return true if this is any COFF/Windows target variant.
241 bool isTargetCOFF() const {
242 return isTargetMingw() || isTargetCygwin() || isTargetWindows();
245 bool isTargetWin64() const {
246 // FIXME: x86_64-cygwin has not been released yet.
247 return In64BitMode && (isTargetCygMing() || isTargetWindows());
250 bool isTargetEnvMacho() const {
251 return isTargetDarwin() || (TargetTriple.getEnvironment() == Triple::MachO);
254 bool isTargetWin32() const {
255 return !In64BitMode && (isTargetMingw() || isTargetWindows());
258 bool isPICStyleSet() const { return PICStyle != PICStyles::None; }
259 bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; }
260 bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; }
262 bool isPICStyleStubPIC() const {
263 return PICStyle == PICStyles::StubPIC;
266 bool isPICStyleStubNoDynamic() const {
267 return PICStyle == PICStyles::StubDynamicNoPIC;
269 bool isPICStyleStubAny() const {
270 return PICStyle == PICStyles::StubDynamicNoPIC ||
271 PICStyle == PICStyles::StubPIC; }
273 /// ClassifyGlobalReference - Classify a global variable reference for the
274 /// current subtarget according to how we should reference it in a non-pcrel
276 unsigned char ClassifyGlobalReference(const GlobalValue *GV,
277 const TargetMachine &TM)const;
279 /// ClassifyBlockAddressReference - Classify a blockaddress reference for the
280 /// current subtarget according to how we should reference it in a non-pcrel
282 unsigned char ClassifyBlockAddressReference() const;
284 /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
285 /// to immediate address.
286 bool IsLegalToCallImmediateAddr(const TargetMachine &TM) const;
288 /// This function returns the name of a function which has an interface
289 /// like the non-standard bzero function, if such a function exists on
290 /// the current subtarget and it is considered prefereable over
291 /// memset with zero passed as the second argument. Otherwise it
293 const char *getBZeroEntry() const;
295 /// getSpecialAddressLatency - For targets where it is beneficial to
296 /// backschedule instructions that compute addresses, return a value
297 /// indicating the number of scheduling cycles of backscheduling that
298 /// should be attempted.
299 unsigned getSpecialAddressLatency() const;
302 } // End llvm namespace