1 //=- X86SchedHaswell.td - X86 Haswell Scheduling -------------*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the machine model for Haswell to support instruction
11 // scheduling and other instruction cost heuristics.
13 //===----------------------------------------------------------------------===//
15 def HaswellModel : SchedMachineModel {
16 // All x86 instructions are modeled as a single micro-op, and HW can decode 4
17 // instructions per cycle.
19 let MicroOpBufferSize = 192; // Based on the reorder buffer.
21 let MispredictPenalty = 16;
23 // Based on the LSD (loop-stream detector) queue size and benchmarking data.
24 let LoopMicroOpBufferSize = 50;
26 // FIXME: SSE4 and AVX are unimplemented. This flag is set to allow
27 // the scheduler to assign a default model to unrecognized opcodes.
28 let CompleteModel = 0;
31 let SchedModel = HaswellModel in {
33 // Haswell can issue micro-ops to 8 different ports in one cycle.
35 // Ports 0, 1, 5, and 6 handle all computation.
36 // Port 4 gets the data half of stores. Store data can be available later than
37 // the store address, but since we don't model the latency of stores, we can
39 // Ports 2 and 3 are identical. They handle loads and the address half of
40 // stores. Port 7 can handle address calculations.
41 def HWPort0 : ProcResource<1>;
42 def HWPort1 : ProcResource<1>;
43 def HWPort2 : ProcResource<1>;
44 def HWPort3 : ProcResource<1>;
45 def HWPort4 : ProcResource<1>;
46 def HWPort5 : ProcResource<1>;
47 def HWPort6 : ProcResource<1>;
48 def HWPort7 : ProcResource<1>;
50 // Many micro-ops are capable of issuing on multiple ports.
51 def HWPort01 : ProcResGroup<[HWPort0, HWPort1]>;
52 def HWPort23 : ProcResGroup<[HWPort2, HWPort3]>;
53 def HWPort237 : ProcResGroup<[HWPort2, HWPort3, HWPort7]>;
54 def HWPort05 : ProcResGroup<[HWPort0, HWPort5]>;
55 def HWPort06 : ProcResGroup<[HWPort0, HWPort6]>;
56 def HWPort15 : ProcResGroup<[HWPort1, HWPort5]>;
57 def HWPort16 : ProcResGroup<[HWPort1, HWPort6]>;
58 def HWPort015 : ProcResGroup<[HWPort0, HWPort1, HWPort5]>;
59 def HWPort056: ProcResGroup<[HWPort0, HWPort5, HWPort6]>;
60 def HWPort0156: ProcResGroup<[HWPort0, HWPort1, HWPort5, HWPort6]>;
62 // 60 Entry Unified Scheduler
63 def HWPortAny : ProcResGroup<[HWPort0, HWPort1, HWPort2, HWPort3, HWPort4,
64 HWPort5, HWPort6, HWPort7]> {
68 // Integer division issued on port 0.
69 def HWDivider : ProcResource<1>;
71 // Loads are 4 cycles, so ReadAfterLd registers needn't be available until 4
72 // cycles after the memory operand.
73 def : ReadAdvance<ReadAfterLd, 4>;
75 // Many SchedWrites are defined in pairs with and without a folded load.
76 // Instructions with folded loads are usually micro-fused, so they only appear
77 // as two micro-ops when queued in the reservation station.
78 // This multiclass defines the resource usage for variants with and without
80 multiclass HWWriteResPair<X86FoldableSchedWrite SchedRW,
81 ProcResourceKind ExePort,
83 // Register variant is using a single cycle on ExePort.
84 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
86 // Memory variant also uses a cycle on port 2/3 and adds 4 cycles to the
88 def : WriteRes<SchedRW.Folded, [HWPort23, ExePort]> {
89 let Latency = !add(Lat, 4);
93 // A folded store needs a cycle on port 4 for the store data, but it does not
94 // need an extra port 2/3 cycle to recompute the address.
95 def : WriteRes<WriteRMW, [HWPort4]>;
99 def : WriteRes<WriteStore, [HWPort237, HWPort4]>;
100 def : WriteRes<WriteLoad, [HWPort23]> { let Latency = 4; }
101 def : WriteRes<WriteMove, [HWPort0156]>;
102 def : WriteRes<WriteZero, []>;
104 defm : HWWriteResPair<WriteALU, HWPort0156, 1>;
105 defm : HWWriteResPair<WriteIMul, HWPort1, 3>;
106 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
107 defm : HWWriteResPair<WriteShift, HWPort06, 1>;
108 defm : HWWriteResPair<WriteJump, HWPort06, 1>;
110 // This is for simple LEAs with one or two input operands.
111 // The complex ones can only execute on port 1, and they require two cycles on
112 // the port to read all inputs. We don't model that.
113 def : WriteRes<WriteLEA, [HWPort15]>;
115 // This is quite rough, latency depends on the dividend.
116 def : WriteRes<WriteIDiv, [HWPort0, HWDivider]> {
118 let ResourceCycles = [1, 10];
120 def : WriteRes<WriteIDivLd, [HWPort23, HWPort0, HWDivider]> {
122 let ResourceCycles = [1, 1, 10];
125 // Scalar and vector floating point.
126 defm : HWWriteResPair<WriteFAdd, HWPort1, 3>;
127 defm : HWWriteResPair<WriteFMul, HWPort0, 5>;
128 defm : HWWriteResPair<WriteFDiv, HWPort0, 12>; // 10-14 cycles.
129 defm : HWWriteResPair<WriteFRcp, HWPort0, 5>;
130 defm : HWWriteResPair<WriteFSqrt, HWPort0, 15>;
131 defm : HWWriteResPair<WriteCvtF2I, HWPort1, 3>;
132 defm : HWWriteResPair<WriteCvtI2F, HWPort1, 4>;
133 defm : HWWriteResPair<WriteCvtF2F, HWPort1, 3>;
134 defm : HWWriteResPair<WriteFShuffle, HWPort5, 1>;
135 defm : HWWriteResPair<WriteFBlend, HWPort015, 1>;
136 defm : HWWriteResPair<WriteFShuffle256, HWPort5, 3>;
138 def : WriteRes<WriteFVarBlend, [HWPort5]> {
140 let ResourceCycles = [2];
142 def : WriteRes<WriteFVarBlendLd, [HWPort5, HWPort23]> {
144 let ResourceCycles = [2, 1];
147 // Vector integer operations.
148 defm : HWWriteResPair<WriteVecShift, HWPort0, 1>;
149 defm : HWWriteResPair<WriteVecLogic, HWPort015, 1>;
150 defm : HWWriteResPair<WriteVecALU, HWPort15, 1>;
151 defm : HWWriteResPair<WriteVecIMul, HWPort0, 5>;
152 defm : HWWriteResPair<WriteShuffle, HWPort5, 1>;
153 defm : HWWriteResPair<WriteBlend, HWPort15, 1>;
154 defm : HWWriteResPair<WriteShuffle256, HWPort5, 3>;
156 def : WriteRes<WriteVarBlend, [HWPort5]> {
158 let ResourceCycles = [2];
160 def : WriteRes<WriteVarBlendLd, [HWPort5, HWPort23]> {
162 let ResourceCycles = [2, 1];
165 def : WriteRes<WriteVarVecShift, [HWPort0, HWPort5]> {
167 let ResourceCycles = [2, 1];
169 def : WriteRes<WriteVarVecShiftLd, [HWPort0, HWPort5, HWPort23]> {
171 let ResourceCycles = [2, 1, 1];
174 def : WriteRes<WriteMPSAD, [HWPort0, HWPort5]> {
176 let ResourceCycles = [1, 2];
178 def : WriteRes<WriteMPSADLd, [HWPort23, HWPort0, HWPort5]> {
180 let ResourceCycles = [1, 1, 2];
183 // String instructions.
184 // Packed Compare Implicit Length Strings, Return Mask
185 def : WriteRes<WritePCmpIStrM, [HWPort0]> {
187 let ResourceCycles = [3];
189 def : WriteRes<WritePCmpIStrMLd, [HWPort0, HWPort23]> {
191 let ResourceCycles = [3, 1];
194 // Packed Compare Explicit Length Strings, Return Mask
195 def : WriteRes<WritePCmpEStrM, [HWPort0, HWPort16, HWPort5]> {
197 let ResourceCycles = [3, 2, 4];
199 def : WriteRes<WritePCmpEStrMLd, [HWPort05, HWPort16, HWPort23]> {
201 let ResourceCycles = [6, 2, 1];
204 // Packed Compare Implicit Length Strings, Return Index
205 def : WriteRes<WritePCmpIStrI, [HWPort0]> {
207 let ResourceCycles = [3];
209 def : WriteRes<WritePCmpIStrILd, [HWPort0, HWPort23]> {
211 let ResourceCycles = [3, 1];
214 // Packed Compare Explicit Length Strings, Return Index
215 def : WriteRes<WritePCmpEStrI, [HWPort05, HWPort16]> {
217 let ResourceCycles = [6, 2];
219 def : WriteRes<WritePCmpEStrILd, [HWPort0, HWPort16, HWPort5, HWPort23]> {
221 let ResourceCycles = [3, 2, 2, 1];
225 def : WriteRes<WriteAESDecEnc, [HWPort5]> {
227 let ResourceCycles = [1];
229 def : WriteRes<WriteAESDecEncLd, [HWPort5, HWPort23]> {
231 let ResourceCycles = [1, 1];
234 def : WriteRes<WriteAESIMC, [HWPort5]> {
236 let ResourceCycles = [2];
238 def : WriteRes<WriteAESIMCLd, [HWPort5, HWPort23]> {
240 let ResourceCycles = [2, 1];
243 def : WriteRes<WriteAESKeyGen, [HWPort0, HWPort5]> {
245 let ResourceCycles = [2, 8];
247 def : WriteRes<WriteAESKeyGenLd, [HWPort0, HWPort5, HWPort23]> {
249 let ResourceCycles = [2, 7, 1];
252 // Carry-less multiplication instructions.
253 def : WriteRes<WriteCLMul, [HWPort0, HWPort5]> {
255 let ResourceCycles = [2, 1];
257 def : WriteRes<WriteCLMulLd, [HWPort0, HWPort5, HWPort23]> {
259 let ResourceCycles = [2, 1, 1];
262 def : WriteRes<WriteSystem, [HWPort0156]> { let Latency = 100; }
263 def : WriteRes<WriteMicrocoded, [HWPort0156]> { let Latency = 100; }
264 def : WriteRes<WriteFence, [HWPort23, HWPort4]>;
265 def : WriteRes<WriteNop, []>;
267 //================ Exceptions ================//
269 //-- Specific Scheduling Models --//
270 def WriteP0 : SchedWriteRes<[HWPort0]>;
271 def WriteP1 : SchedWriteRes<[HWPort1]>;
272 def WriteP1_P23 : SchedWriteRes<[HWPort1, HWPort23]> {
275 def WriteP1_Lat3 : SchedWriteRes<[HWPort1]> {
278 def WriteP1_Lat3Ld : SchedWriteRes<[HWPort1, HWPort23]> {
282 def Write2P0156_Lat2 : SchedWriteRes<[HWPort0156]> {
284 let ResourceCycles = [2];
286 def Write2P0156_Lat2Ld : SchedWriteRes<[HWPort0156, HWPort23]> {
288 let ResourceCycles = [2, 1];
291 def Write2P237_P4 : SchedWriteRes<[HWPort237, HWPort4]> {
293 let ResourceCycles = [2, 1];
296 def WriteP01 : SchedWriteRes<[HWPort01]>;
298 def Write2P01 : SchedWriteRes<[HWPort01]> {
301 def Write3P01 : SchedWriteRes<[HWPort01]> {
305 def WriteP06 : SchedWriteRes<[HWPort06]>;
307 def Write2P06 : SchedWriteRes<[HWPort06]> {
310 let ResourceCycles = [2];
313 def Write2P1 : SchedWriteRes<[HWPort1]> {
315 let ResourceCycles = [2];
317 def Write2P1_P23 : SchedWriteRes<[HWPort1, HWPort23]> {
319 let ResourceCycles = [2, 1];
321 def WriteP15 : SchedWriteRes<[HWPort15]>;
322 def WriteP15Ld : SchedWriteRes<[HWPort15, HWPort23]> {
326 def Write3P06_Lat2 : SchedWriteRes<[HWPort06]> {
329 let ResourceCycles = [3];
332 def WriteP0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> {
336 def WriteP0156_2P237_P4 : SchedWriteRes<[HWPort0156, HWPort237, HWPort4]> {
338 let ResourceCycles = [1, 2, 1];
341 def Write2P0156_2P237_P4 : SchedWriteRes<[HWPort0156, HWPort237, HWPort4]> {
343 let ResourceCycles = [2, 2, 1];
346 def Write2P0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> {
348 let ResourceCycles = [2, 1];
351 def Write3P0156_2P237_P4 : SchedWriteRes<[HWPort0156, HWPort237, HWPort4]> {
353 let ResourceCycles = [3, 2, 1];
358 // - mm: 64 bit mmx register.
359 // - x = 128 bit xmm register.
360 // - (x)mm = mmx or xmm register.
361 // - y = 256 bit ymm register.
362 // - v = any vector register.
365 //=== Integer Instructions ===//
366 //-- Move instructions --//
370 def : InstRW<[WriteALULd], (instregex "MOV16rm")>;
374 def : InstRW<[WriteLoad], (instregex "MOV(S|Z)X32rm(8|16)")>;
378 def : InstRW<[Write2P0156_Lat2],
379 (instregex "CMOV(O|NO|B|AE|E|NE|BE|A|S|NS|P|NP|L|GE|LE|G)(16|32|64)rr")>;
381 def : InstRW<[Write2P0156_Lat2Ld, ReadAfterLd],
382 (instregex "CMOV(O|NO|B|AE|E|NE|BE|A|S|NS|P|NP|L|GE|LE|G)(16|32|64)rm")>;
386 def WriteXCHG : SchedWriteRes<[HWPort0156]> {
388 let ResourceCycles = [3];
391 def : InstRW<[WriteXCHG], (instregex "XCHG(8|16|32|64)rr", "XCHG(16|32|64)ar")>;
394 def WriteXCHGrm : SchedWriteRes<[]> {
398 def : InstRW<[WriteXCHGrm], (instregex "XCHG(8|16|32|64)rm")>;
401 def WriteXLAT : SchedWriteRes<[]> {
405 def : InstRW<[WriteXLAT], (instregex "XLAT")>;
409 def : InstRW<[Write2P237_P4], (instregex "PUSH(16|32)rmm")>;
412 def WritePushF : SchedWriteRes<[HWPort1, HWPort4, HWPort237, HWPort06]> {
415 def : InstRW<[WritePushF], (instregex "PUSHF(16|32)")>;
418 def WritePushA : SchedWriteRes<[]> {
419 let NumMicroOps = 19;
421 def : InstRW<[WritePushA], (instregex "PUSHA(16|32)")>;
425 def : InstRW<[Write2P237_P4], (instregex "POP(16|32)rmm")>;
428 def WritePopF : SchedWriteRes<[]> {
431 def : InstRW<[WritePopF], (instregex "POPF(16|32)")>;
434 def WritePopA : SchedWriteRes<[]> {
435 let NumMicroOps = 18;
437 def : InstRW<[WritePopA], (instregex "POPA(16|32)")>;
440 def : InstRW<[WriteP06], (instregex "(S|L)AHF")>;
444 def WriteBSwap32 : SchedWriteRes<[HWPort15]>;
445 def : InstRW<[WriteBSwap32], (instregex "BSWAP32r")>;
448 def WriteBSwap64 : SchedWriteRes<[HWPort06, HWPort15]> {
451 def : InstRW<[WriteBSwap64], (instregex "BSWAP64r")>;
454 // r16,m16 / r64,m64.
455 def : InstRW<[Write2P0156_Lat2Ld], (instregex "MOVBE(16|64)rm")>;
458 def WriteMoveBE32rm : SchedWriteRes<[HWPort15, HWPort23]> {
461 def : InstRW<[WriteMoveBE32rm], (instregex "MOVBE32rm")>;
464 def WriteMoveBE16mr : SchedWriteRes<[HWPort06, HWPort237, HWPort4]> {
467 def : InstRW<[WriteMoveBE16mr], (instregex "MOVBE16mr")>;
470 def WriteMoveBE32mr : SchedWriteRes<[HWPort15, HWPort237, HWPort4]> {
473 def : InstRW<[WriteMoveBE32mr], (instregex "MOVBE32mr")>;
476 def WriteMoveBE64mr : SchedWriteRes<[HWPort06, HWPort15, HWPort237, HWPort4]> {
479 def : InstRW<[WriteMoveBE64mr], (instregex "MOVBE64mr")>;
481 //-- Arithmetic instructions --//
485 def : InstRW<[Write2P0156_2P237_P4],
486 (instregex "(ADD|SUB)(8|16|32|64)m(r|i)",
487 "(ADD|SUB)(8|16|32|64)mi8", "(ADD|SUB)64mi32")>;
491 def : InstRW<[Write2P0156_Lat2], (instregex "(ADC|SBB)(8|16|32|64)r(r|i)",
492 "(ADC|SBB)(16|32|64)ri8",
494 "(ADC|SBB)(8|16|32|64)rr_REV")>;
497 def : InstRW<[Write2P0156_Lat2Ld, ReadAfterLd], (instregex "(ADC|SBB)(8|16|32|64)rm")>;
500 def : InstRW<[Write3P0156_2P237_P4],
501 (instregex "(ADC|SBB)(8|16|32|64)m(r|i)",
502 "(ADC|SBB)(16|32|64)mi8",
507 def : InstRW<[WriteP0156_2P237_P4],
508 (instregex "(INC|DEC|NOT|NEG)(8|16|32|64)m",
509 "(INC|DEC)64(16|32)m")>;
513 def WriteMul16 : SchedWriteRes<[HWPort1, HWPort0156]> {
517 def : InstRW<[WriteMul16], (instregex "IMUL16r", "MUL16r")>;
520 def WriteMul16Ld : SchedWriteRes<[HWPort1, HWPort0156, HWPort23]> {
524 def : InstRW<[WriteMul16Ld], (instregex "IMUL16m", "MUL16m")>;
527 def WriteMul32 : SchedWriteRes<[HWPort1, HWPort0156]> {
531 def : InstRW<[WriteMul32], (instregex "IMUL32r", "MUL32r")>;
534 def WriteMul32Ld : SchedWriteRes<[HWPort1, HWPort0156, HWPort23]> {
538 def : InstRW<[WriteMul32Ld], (instregex "IMUL32m", "MUL32m")>;
541 def WriteMul64 : SchedWriteRes<[HWPort1, HWPort6]> {
545 def : InstRW<[WriteMul64], (instregex "IMUL64r", "MUL64r")>;
548 def WriteMul64Ld : SchedWriteRes<[HWPort1, HWPort6, HWPort23]> {
552 def : InstRW<[WriteMul64Ld], (instregex "IMUL64m", "MUL64m")>;
555 def WriteMul16rri : SchedWriteRes<[HWPort1, HWPort0156]> {
559 def : InstRW<[WriteMul16rri], (instregex "IMUL16rri", "IMUL16rri8")>;
562 def WriteMul16rmi : SchedWriteRes<[HWPort1, HWPort0156, HWPort23]> {
566 def : InstRW<[WriteMul16rmi], (instregex "IMUL16rmi", "IMUL16rmi8")>;
570 def WriteMulX32 : SchedWriteRes<[HWPort1, HWPort056]> {
573 let ResourceCycles = [1, 2];
575 def : InstRW<[WriteMulX32], (instregex "MULX32rr")>;
578 def WriteMulX32Ld : SchedWriteRes<[HWPort1, HWPort056, HWPort23]> {
581 let ResourceCycles = [1, 2, 1];
583 def : InstRW<[WriteMulX32Ld], (instregex "MULX32rm")>;
586 def WriteMulX64 : SchedWriteRes<[HWPort1, HWPort6]> {
590 def : InstRW<[WriteMulX64], (instregex "MULX64rr")>;
593 def WriteMulX64Ld : SchedWriteRes<[HWPort1, HWPort6, HWPort23]> {
597 def : InstRW<[WriteMulX64Ld], (instregex "MULX64rm")>;
601 def WriteDiv8 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
605 def : InstRW<[WriteDiv8], (instregex "DIV8r")>;
608 def WriteDiv16 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
610 let NumMicroOps = 10;
612 def : InstRW<[WriteDiv16], (instregex "DIV16r")>;
615 def WriteDiv32 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
617 let NumMicroOps = 10;
619 def : InstRW<[WriteDiv32], (instregex "DIV32r")>;
622 def WriteDiv64 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
624 let NumMicroOps = 36;
626 def : InstRW<[WriteDiv64], (instregex "DIV64r")>;
630 def WriteIDiv8 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
634 def : InstRW<[WriteIDiv8], (instregex "IDIV8r")>;
637 def WriteIDiv16 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
639 let NumMicroOps = 10;
641 def : InstRW<[WriteIDiv16], (instregex "IDIV16r")>;
644 def WriteIDiv32 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
648 def : InstRW<[WriteIDiv32], (instregex "IDIV32r")>;
651 def WriteIDiv64 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
653 let NumMicroOps = 59;
655 def : InstRW<[WriteIDiv64], (instregex "IDIV64r")>;
657 //-- Logic instructions --//
661 def : InstRW<[Write2P0156_2P237_P4],
662 (instregex "(AND|OR|XOR)(8|16|32|64)m(r|i)",
663 "(AND|OR|XOR)(8|16|32|64)mi8", "(AND|OR|XOR)64mi32")>;
667 def WriteShiftRMW : SchedWriteRes<[HWPort06, HWPort237, HWPort4]> {
669 let ResourceCycles = [2, 1, 1];
671 def : InstRW<[WriteShiftRMW], (instregex "S(A|H)(R|L)(8|16|32|64)m(i|1)")>;
674 def : InstRW<[Write3P06_Lat2], (instregex "S(A|H)(R|L)(8|16|32|64)rCL")>;
677 def WriteShiftClLdRMW : SchedWriteRes<[HWPort06, HWPort23, HWPort4]> {
679 let ResourceCycles = [3, 2, 1];
681 def : InstRW<[WriteShiftClLdRMW], (instregex "S(A|H)(R|L)(8|16|32|64)mCL")>;
685 def : InstRW<[Write2P06], (instregex "RO(R|L)(8|16|32|64)r1")>;
688 def WriteRotateRMW : SchedWriteRes<[HWPort06, HWPort237, HWPort4]> {
690 let ResourceCycles = [2, 2, 1];
692 def : InstRW<[WriteRotateRMW], (instregex "RO(R|L)(8|16|32|64)mi")>;
695 def : InstRW<[Write3P06_Lat2], (instregex "RO(R|L)(8|16|32|64)rCL")>;
698 def WriteRotateRMWCL : SchedWriteRes<[]> {
701 def : InstRW<[WriteRotateRMWCL], (instregex "RO(R|L)(8|16|32|64)mCL")>;
705 def WriteRCr1 : SchedWriteRes<[HWPort06, HWPort0156]> {
708 let ResourceCycles = [2, 1];
710 def : InstRW<[WriteRCr1], (instregex "RC(R|L)(8|16|32|64)r1")>;
713 def WriteRCm1 : SchedWriteRes<[]> {
716 def : InstRW<[WriteRCm1], (instregex "RC(R|L)(8|16|32|64)m1")>;
719 def WriteRCri : SchedWriteRes<[HWPort0156]> {
723 def : InstRW<[WriteRCri], (instregex "RC(R|L)(8|16|32|64)r(i|CL)")>;
726 def WriteRCmi : SchedWriteRes<[]> {
727 let NumMicroOps = 11;
729 def : InstRW<[WriteRCmi], (instregex "RC(R|L)(8|16|32|64)m(i|CL)")>;
733 def WriteShDrr : SchedWriteRes<[HWPort1]> {
736 def : InstRW<[WriteShDrr], (instregex "SH(R|L)D(16|32|64)rri8")>;
739 def WriteShDmr : SchedWriteRes<[]> {
742 def : InstRW<[WriteShDmr], (instregex "SH(R|L)D(16|32|64)mri8")>;
745 def WriteShlDCL : SchedWriteRes<[HWPort0156]> {
749 def : InstRW<[WriteShlDCL], (instregex "SHLD(16|32|64)rrCL")>;
752 def WriteShrDCL : SchedWriteRes<[HWPort0156]> {
756 def : InstRW<[WriteShrDCL], (instregex "SHRD(16|32|64)rrCL")>;
759 def WriteShDmrCL : SchedWriteRes<[]> {
762 def : InstRW<[WriteShDmrCL], (instregex "SH(R|L)D(16|32|64)mrCL")>;
766 def : InstRW<[WriteShift], (instregex "BT(16|32|64)r(r|i8)")>;
769 def WriteBTmr : SchedWriteRes<[]> {
770 let NumMicroOps = 10;
772 def : InstRW<[WriteBTmr], (instregex "BT(16|32|64)mr")>;
775 def : InstRW<[WriteShiftLd], (instregex "BT(16|32|64)mi8")>;
779 def : InstRW<[WriteShift], (instregex "BT(R|S|C)(16|32|64)r(r|i8)")>;
782 def WriteBTRSCmr : SchedWriteRes<[]> {
783 let NumMicroOps = 11;
785 def : InstRW<[WriteBTRSCmr], (instregex "BT(R|S|C)(16|32|64)mr")>;
788 def : InstRW<[WriteShiftLd], (instregex "BT(R|S|C)(16|32|64)mi8")>;
792 def : InstRW<[WriteP1_Lat3], (instregex "BS(R|F)(16|32|64)rr")>;
794 def : InstRW<[WriteP1_Lat3Ld], (instregex "BS(R|F)(16|32|64)rm")>;
798 def : InstRW<[WriteShift],
799 (instregex "SET(O|NO|B|AE|E|NE|BE|A|S|NS|P|NP|L|GE|LE|G)r")>;
801 def WriteSetCCm : SchedWriteRes<[HWPort06, HWPort237, HWPort4]> {
804 def : InstRW<[WriteSetCCm],
805 (instregex "SET(O|NO|B|AE|E|NE|BE|A|S|NS|P|NP|L|GE|LE|G)m")>;
808 def WriteCldStd : SchedWriteRes<[HWPort15, HWPort6]> {
811 def : InstRW<[WriteCldStd], (instregex "STD", "CLD")>;
815 def : InstRW<[WriteP1_Lat3], (instregex "(L|TZCNT)(16|32|64)rr")>;
817 def : InstRW<[WriteP1_Lat3Ld], (instregex "(L|TZCNT)(16|32|64)rm")>;
821 def : InstRW<[WriteP15], (instregex "ANDN(32|64)rr")>;
823 def : InstRW<[WriteP15Ld], (instregex "ANDN(32|64)rm")>;
827 def : InstRW<[WriteP15], (instregex "BLS(I|MSK|R)(32|64)rr")>;
829 def : InstRW<[WriteP15Ld], (instregex "BLS(I|MSK|R)(32|64)rm")>;
833 def : InstRW<[Write2P0156_Lat2], (instregex "BEXTR(32|64)rr")>;
835 def : InstRW<[Write2P0156_Lat2Ld], (instregex "BEXTR(32|64)rm")>;
839 def : InstRW<[WriteP15], (instregex "BZHI(32|64)rr")>;
841 def : InstRW<[WriteP15Ld], (instregex "BZHI(32|64)rm")>;
845 def : InstRW<[WriteP1_Lat3], (instregex "PDEP(32|64)rr", "PEXT(32|64)rr")>;
847 def : InstRW<[WriteP1_Lat3Ld], (instregex "PDEP(32|64)rm", "PEXT(32|64)rm")>;
849 //-- Control transfer instructions --//
852 def WriteJCXZ : SchedWriteRes<[HWPort0156, HWPort6]> {
855 def : InstRW<[WriteJCXZ], (instregex "JCXZ", "JECXZ_(32|64)", "JRCXZ")>;
858 def WriteLOOP : SchedWriteRes<[]> {
861 def : InstRW<[WriteLOOP], (instregex "LOOP")>;
864 def WriteLOOPE : SchedWriteRes<[]> {
865 let NumMicroOps = 11;
867 def : InstRW<[WriteLOOPE], (instregex "LOOPE", "LOOPNE")>;
871 def WriteCALLr : SchedWriteRes<[HWPort237, HWPort4, HWPort6]> {
874 def : InstRW<[WriteCALLr], (instregex "CALL(16|32)r")>;
877 def WriteCALLm : SchedWriteRes<[HWPort237, HWPort4, HWPort6]> {
879 let ResourceCycles = [2, 1, 1];
881 def : InstRW<[WriteCALLm], (instregex "CALL(16|32)m")>;
884 def WriteRET : SchedWriteRes<[HWPort237, HWPort6]> {
887 def : InstRW<[WriteRET], (instregex "RET(L|Q|W)", "LRET(L|Q|W)")>;
890 def WriteRETI : SchedWriteRes<[HWPort23, HWPort6, HWPort015]> {
892 let ResourceCycles = [1, 2, 1];
894 def : InstRW<[WriteRETI], (instregex "RETI(L|Q|W)", "LRETI(L|Q|W)")>;
898 def WriteBOUND : SchedWriteRes<[]> {
899 let NumMicroOps = 15;
901 def : InstRW<[WriteBOUND], (instregex "BOUNDS(16|32)rm")>;
904 def WriteINTO : SchedWriteRes<[]> {
907 def : InstRW<[WriteINTO], (instregex "INTO")>;
909 //-- String instructions --//
912 def : InstRW<[Write2P0156_P23], (instregex "LODS(B|W)")>;
915 def : InstRW<[WriteP0156_P23], (instregex "LODS(L|Q)")>;
918 def WriteSTOS : SchedWriteRes<[HWPort23, HWPort0156, HWPort4]> {
921 def : InstRW<[WriteSTOS], (instregex "STOS(B|L|Q|W)")>;
924 def WriteMOVS : SchedWriteRes<[HWPort23, HWPort4, HWPort0156]> {
927 let ResourceCycles = [2, 1, 2];
929 def : InstRW<[WriteMOVS], (instregex "MOVS(B|L|Q|W)")>;
932 def : InstRW<[Write2P0156_P23], (instregex "SCAS(B|W|L|Q)")>;
935 def WriteCMPS : SchedWriteRes<[HWPort23, HWPort0156]> {
938 let ResourceCycles = [2, 3];
940 def : InstRW<[WriteCMPS], (instregex "CMPS(B|L|Q|W)")>;
942 //-- Synchronization instructions --//
945 def WriteXADD : SchedWriteRes<[]> {
948 def : InstRW<[WriteXADD], (instregex "XADD(8|16|32|64)rm")>;
951 def WriteCMPXCHG : SchedWriteRes<[]> {
954 def : InstRW<[WriteCMPXCHG], (instregex "CMPXCHG(8|16|32|64)rm")>;
957 def WriteCMPXCHG8B : SchedWriteRes<[]> {
958 let NumMicroOps = 15;
960 def : InstRW<[WriteCMPXCHG8B], (instregex "CMPXCHG8B")>;
963 def WriteCMPXCHG16B : SchedWriteRes<[]> {
964 let NumMicroOps = 22;
966 def : InstRW<[WriteCMPXCHG16B], (instregex "CMPXCHG16B")>;
971 def WritePAUSE : SchedWriteRes<[HWPort05, HWPort6]> {
973 let ResourceCycles = [1, 3];
975 def : InstRW<[WritePAUSE], (instregex "PAUSE")>;
978 def : InstRW<[Write2P0156_P23], (instregex "LEAVE")>;
981 def WriteXGETBV : SchedWriteRes<[]> {
984 def : InstRW<[WriteXGETBV], (instregex "XGETBV")>;
987 def WriteRDTSC : SchedWriteRes<[]> {
988 let NumMicroOps = 15;
990 def : InstRW<[WriteRDTSC], (instregex "RDTSC")>;
993 def WriteRDPMC : SchedWriteRes<[]> {
994 let NumMicroOps = 34;
996 def : InstRW<[WriteRDPMC], (instregex "RDPMC")>;
999 def WriteRDRAND : SchedWriteRes<[HWPort23, HWPort015]> {
1000 let NumMicroOps = 17;
1001 let ResourceCycles = [1, 16];
1003 def : InstRW<[WriteRDRAND], (instregex "RDRAND(16|32|64)r")>;
1005 //=== Floating Point x87 Instructions ===//
1006 //-- Move instructions --//
1010 def : InstRW<[WriteP01], (instregex "LD_Frr")>;
1012 def WriteLD_F80m : SchedWriteRes<[HWPort01, HWPort23]> {
1014 let NumMicroOps = 4;
1015 let ResourceCycles = [2, 2];
1017 def : InstRW<[WriteLD_F80m], (instregex "LD_F80m")>;
1021 def WriteFBLD : SchedWriteRes<[]> {
1023 let NumMicroOps = 43;
1025 def : InstRW<[WriteFBLD], (instregex "FBLDm")>;
1029 def : InstRW<[WriteP01], (instregex "ST_(F|FP)rr")>;
1032 def WriteST_FP80m : SchedWriteRes<[HWPort0156, HWPort23, HWPort4]> {
1033 let NumMicroOps = 7;
1034 let ResourceCycles = [3, 2, 2];
1036 def : InstRW<[WriteST_FP80m], (instregex "ST_FP80m")>;
1040 def WriteFBSTP : SchedWriteRes<[]> {
1041 let NumMicroOps = 226;
1043 def : InstRW<[WriteFBSTP], (instregex "FBSTPm")>;
1046 def : InstRW<[WriteNop], (instregex "XCH_F")>;
1049 def WriteFILD : SchedWriteRes<[HWPort01, HWPort23]> {
1051 let NumMicroOps = 2;
1053 def : InstRW<[WriteFILD], (instregex "ILD_F(16|32|64)m")>;
1056 def WriteFIST : SchedWriteRes<[HWPort1, HWPort23, HWPort4]> {
1058 let NumMicroOps = 3;
1060 def : InstRW<[WriteFIST], (instregex "IST_(F|FP)(16|32)m")>;
1063 def : InstRW<[WriteP01], (instregex "LD_F0")>;
1066 def : InstRW<[Write2P01], (instregex "LD_F1")>;
1068 // FLDPI FLDL2E etc.
1069 def : InstRW<[Write2P01], (instregex "FLDPI", "FLDL2(T|E)" "FLDL(G|N)2")>;
1072 def WriteFCMOVcc : SchedWriteRes<[HWPort0, HWPort5]> {
1074 let NumMicroOps = 3;
1075 let ResourceCycles = [2, 1];
1077 def : InstRW<[WriteFCMOVcc], (instregex "CMOV(B|BE|P|NB|NBE|NE|NP)_F")>;
1081 def WriteFNSTSW : SchedWriteRes<[HWPort0, HWPort0156]> {
1082 let NumMicroOps = 2;
1084 def : InstRW<[WriteFNSTSW], (instregex "FNSTSW16r")>;
1087 def WriteFNSTSWm : SchedWriteRes<[HWPort0, HWPort4, HWPort237]> {
1089 let NumMicroOps = 3;
1091 def : InstRW<[WriteFNSTSWm], (instregex "FNSTSWm")>;
1094 def WriteFLDCW : SchedWriteRes<[HWPort01, HWPort23, HWPort6]> {
1096 let NumMicroOps = 3;
1098 def : InstRW<[WriteFLDCW], (instregex "FLDCW16m")>;
1101 def WriteFNSTCW : SchedWriteRes<[HWPort237, HWPort4, HWPort6]> {
1102 let NumMicroOps = 3;
1104 def : InstRW<[WriteFNSTCW], (instregex "FNSTCW16m")>;
1107 def : InstRW<[WriteP01], (instregex "FINCSTP", "FDECSTP")>;
1110 def : InstRW<[WriteP01], (instregex "FFREE")>;
1113 def WriteFNSAVE : SchedWriteRes<[]> {
1114 let NumMicroOps = 147;
1116 def : InstRW<[WriteFNSAVE], (instregex "FSAVEm")>;
1119 def WriteFRSTOR : SchedWriteRes<[]> {
1120 let NumMicroOps = 90;
1122 def : InstRW<[WriteFRSTOR], (instregex "FRSTORm")>;
1124 //-- Arithmetic instructions --//
1127 def : InstRW<[WriteP0], (instregex "ABS_F")>;
1130 def : InstRW<[WriteP0], (instregex "CHS_F")>;
1132 // FCOM(P) FUCOM(P).
1134 def : InstRW<[WriteP1], (instregex "COM_FST0r", "COMP_FST0r", "UCOM_Fr",
1137 def : InstRW<[WriteP1_P23], (instregex "FCOM(32|64)m", "FCOMP(32|64)m")>;
1141 def : InstRW<[Write2P01], (instregex "FCOMPP", "UCOM_FPPr")>;
1143 // FCOMI(P) FUCOMI(P).
1145 def : InstRW<[Write3P01], (instregex "COM_FIr", "COM_FIPr", "UCOM_FIr",
1149 def : InstRW<[Write2P1_P23], (instregex "FICOM(16|32)m", "FICOMP(16|32)m")>;
1152 def : InstRW<[WriteP1], (instregex "TST_F")>;
1155 def : InstRW<[Write2P1], (instregex "FXAM")>;
1158 def WriteFPREM : SchedWriteRes<[]> {
1160 let NumMicroOps = 28;
1162 def : InstRW<[WriteFPREM], (instregex "FPREM")>;
1165 def WriteFPREM1 : SchedWriteRes<[]> {
1167 let NumMicroOps = 41;
1169 def : InstRW<[WriteFPREM1], (instregex "FPREM1")>;
1172 def WriteFRNDINT : SchedWriteRes<[]> {
1174 let NumMicroOps = 17;
1176 def : InstRW<[WriteFRNDINT], (instregex "FRNDINT")>;
1178 //-- Math instructions --//
1181 def WriteFSCALE : SchedWriteRes<[]> {
1182 let Latency = 75; // 49-125
1183 let NumMicroOps = 50; // 25-75
1185 def : InstRW<[WriteFSCALE], (instregex "FSCALE")>;
1188 def WriteFXTRACT : SchedWriteRes<[]> {
1190 let NumMicroOps = 17;
1192 def : InstRW<[WriteFXTRACT], (instregex "FXTRACT")>;