1 //===- X86RegisterInfo.td - Describe the X86 Register File --*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 Register file, defining the registers themselves,
11 // aliases between the registers, and the register classes built out of the
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // Register definitions...
19 let Namespace = "X86" in {
21 // Subregister indices.
22 def sub_8bit : SubRegIndex { let NumberHack = 1; }
23 def sub_8bit_hi : SubRegIndex { let NumberHack = 2; }
24 def sub_16bit : SubRegIndex { let NumberHack = 3; }
25 def sub_32bit : SubRegIndex { let NumberHack = 4; }
27 def sub_ss : SubRegIndex { let NumberHack = 1; }
28 def sub_sd : SubRegIndex { let NumberHack = 2; }
29 def sub_xmm : SubRegIndex { let NumberHack = 3; }
32 // In the register alias definitions below, we define which registers alias
33 // which others. We only specify which registers the small registers alias,
34 // because the register file generator is smart enough to figure out that
35 // AL aliases AX if we tell it that AX aliased AL (for example).
37 // Dwarf numbering is different for 32-bit and 64-bit, and there are
38 // variations by target as well. Currently the first entry is for X86-64,
39 // second - for EH on X86-32/Darwin and third is 'generic' one (X86-32/Linux
40 // and debug information on X86-32/Darwin)
44 def AL : Register<"al">, DwarfRegNum<[0, 0, 0]>;
45 def DL : Register<"dl">, DwarfRegNum<[1, 2, 2]>;
46 def CL : Register<"cl">, DwarfRegNum<[2, 1, 1]>;
47 def BL : Register<"bl">, DwarfRegNum<[3, 3, 3]>;
50 def SIL : Register<"sil">, DwarfRegNum<[4, 6, 6]>;
51 def DIL : Register<"dil">, DwarfRegNum<[5, 7, 7]>;
52 def BPL : Register<"bpl">, DwarfRegNum<[6, 4, 5]>;
53 def SPL : Register<"spl">, DwarfRegNum<[7, 5, 4]>;
54 def R8B : Register<"r8b">, DwarfRegNum<[8, -2, -2]>;
55 def R9B : Register<"r9b">, DwarfRegNum<[9, -2, -2]>;
56 def R10B : Register<"r10b">, DwarfRegNum<[10, -2, -2]>;
57 def R11B : Register<"r11b">, DwarfRegNum<[11, -2, -2]>;
58 def R12B : Register<"r12b">, DwarfRegNum<[12, -2, -2]>;
59 def R13B : Register<"r13b">, DwarfRegNum<[13, -2, -2]>;
60 def R14B : Register<"r14b">, DwarfRegNum<[14, -2, -2]>;
61 def R15B : Register<"r15b">, DwarfRegNum<[15, -2, -2]>;
63 // High registers. On x86-64, these cannot be used in any instruction
65 def AH : Register<"ah">, DwarfRegNum<[0, 0, 0]>;
66 def DH : Register<"dh">, DwarfRegNum<[1, 2, 2]>;
67 def CH : Register<"ch">, DwarfRegNum<[2, 1, 1]>;
68 def BH : Register<"bh">, DwarfRegNum<[3, 3, 3]>;
71 def AX : RegisterWithSubRegs<"ax", [AL,AH]>, DwarfRegNum<[0, 0, 0]>;
72 def DX : RegisterWithSubRegs<"dx", [DL,DH]>, DwarfRegNum<[1, 2, 2]>;
73 def CX : RegisterWithSubRegs<"cx", [CL,CH]>, DwarfRegNum<[2, 1, 1]>;
74 def BX : RegisterWithSubRegs<"bx", [BL,BH]>, DwarfRegNum<[3, 3, 3]>;
75 def SI : RegisterWithSubRegs<"si", [SIL]>, DwarfRegNum<[4, 6, 6]>;
76 def DI : RegisterWithSubRegs<"di", [DIL]>, DwarfRegNum<[5, 7, 7]>;
77 def BP : RegisterWithSubRegs<"bp", [BPL]>, DwarfRegNum<[6, 4, 5]>;
78 def SP : RegisterWithSubRegs<"sp", [SPL]>, DwarfRegNum<[7, 5, 4]>;
79 def IP : Register<"ip">, DwarfRegNum<[16]>;
82 def R8W : RegisterWithSubRegs<"r8w", [R8B]>, DwarfRegNum<[8, -2, -2]>;
83 def R9W : RegisterWithSubRegs<"r9w", [R9B]>, DwarfRegNum<[9, -2, -2]>;
84 def R10W : RegisterWithSubRegs<"r10w", [R10B]>, DwarfRegNum<[10, -2, -2]>;
85 def R11W : RegisterWithSubRegs<"r11w", [R11B]>, DwarfRegNum<[11, -2, -2]>;
86 def R12W : RegisterWithSubRegs<"r12w", [R12B]>, DwarfRegNum<[12, -2, -2]>;
87 def R13W : RegisterWithSubRegs<"r13w", [R13B]>, DwarfRegNum<[13, -2, -2]>;
88 def R14W : RegisterWithSubRegs<"r14w", [R14B]>, DwarfRegNum<[14, -2, -2]>;
89 def R15W : RegisterWithSubRegs<"r15w", [R15B]>, DwarfRegNum<[15, -2, -2]>;
92 def EAX : RegisterWithSubRegs<"eax", [AX]>, DwarfRegNum<[0, 0, 0]>;
93 def EDX : RegisterWithSubRegs<"edx", [DX]>, DwarfRegNum<[1, 2, 2]>;
94 def ECX : RegisterWithSubRegs<"ecx", [CX]>, DwarfRegNum<[2, 1, 1]>;
95 def EBX : RegisterWithSubRegs<"ebx", [BX]>, DwarfRegNum<[3, 3, 3]>;
96 def ESI : RegisterWithSubRegs<"esi", [SI]>, DwarfRegNum<[4, 6, 6]>;
97 def EDI : RegisterWithSubRegs<"edi", [DI]>, DwarfRegNum<[5, 7, 7]>;
98 def EBP : RegisterWithSubRegs<"ebp", [BP]>, DwarfRegNum<[6, 4, 5]>;
99 def ESP : RegisterWithSubRegs<"esp", [SP]>, DwarfRegNum<[7, 5, 4]>;
100 def EIP : RegisterWithSubRegs<"eip", [IP]>, DwarfRegNum<[16, 8, 8]>;
103 def R8D : RegisterWithSubRegs<"r8d", [R8W]>, DwarfRegNum<[8, -2, -2]>;
104 def R9D : RegisterWithSubRegs<"r9d", [R9W]>, DwarfRegNum<[9, -2, -2]>;
105 def R10D : RegisterWithSubRegs<"r10d", [R10W]>, DwarfRegNum<[10, -2, -2]>;
106 def R11D : RegisterWithSubRegs<"r11d", [R11W]>, DwarfRegNum<[11, -2, -2]>;
107 def R12D : RegisterWithSubRegs<"r12d", [R12W]>, DwarfRegNum<[12, -2, -2]>;
108 def R13D : RegisterWithSubRegs<"r13d", [R13W]>, DwarfRegNum<[13, -2, -2]>;
109 def R14D : RegisterWithSubRegs<"r14d", [R14W]>, DwarfRegNum<[14, -2, -2]>;
110 def R15D : RegisterWithSubRegs<"r15d", [R15W]>, DwarfRegNum<[15, -2, -2]>;
112 // 64-bit registers, X86-64 only
113 def RAX : RegisterWithSubRegs<"rax", [EAX]>, DwarfRegNum<[0, -2, -2]>;
114 def RDX : RegisterWithSubRegs<"rdx", [EDX]>, DwarfRegNum<[1, -2, -2]>;
115 def RCX : RegisterWithSubRegs<"rcx", [ECX]>, DwarfRegNum<[2, -2, -2]>;
116 def RBX : RegisterWithSubRegs<"rbx", [EBX]>, DwarfRegNum<[3, -2, -2]>;
117 def RSI : RegisterWithSubRegs<"rsi", [ESI]>, DwarfRegNum<[4, -2, -2]>;
118 def RDI : RegisterWithSubRegs<"rdi", [EDI]>, DwarfRegNum<[5, -2, -2]>;
119 def RBP : RegisterWithSubRegs<"rbp", [EBP]>, DwarfRegNum<[6, -2, -2]>;
120 def RSP : RegisterWithSubRegs<"rsp", [ESP]>, DwarfRegNum<[7, -2, -2]>;
122 def R8 : RegisterWithSubRegs<"r8", [R8D]>, DwarfRegNum<[8, -2, -2]>;
123 def R9 : RegisterWithSubRegs<"r9", [R9D]>, DwarfRegNum<[9, -2, -2]>;
124 def R10 : RegisterWithSubRegs<"r10", [R10D]>, DwarfRegNum<[10, -2, -2]>;
125 def R11 : RegisterWithSubRegs<"r11", [R11D]>, DwarfRegNum<[11, -2, -2]>;
126 def R12 : RegisterWithSubRegs<"r12", [R12D]>, DwarfRegNum<[12, -2, -2]>;
127 def R13 : RegisterWithSubRegs<"r13", [R13D]>, DwarfRegNum<[13, -2, -2]>;
128 def R14 : RegisterWithSubRegs<"r14", [R14D]>, DwarfRegNum<[14, -2, -2]>;
129 def R15 : RegisterWithSubRegs<"r15", [R15D]>, DwarfRegNum<[15, -2, -2]>;
130 def RIP : RegisterWithSubRegs<"rip", [EIP]>, DwarfRegNum<[16, -2, -2]>;
132 // MMX Registers. These are actually aliased to ST0 .. ST7
133 def MM0 : Register<"mm0">, DwarfRegNum<[41, 29, 29]>;
134 def MM1 : Register<"mm1">, DwarfRegNum<[42, 30, 30]>;
135 def MM2 : Register<"mm2">, DwarfRegNum<[43, 31, 31]>;
136 def MM3 : Register<"mm3">, DwarfRegNum<[44, 32, 32]>;
137 def MM4 : Register<"mm4">, DwarfRegNum<[45, 33, 33]>;
138 def MM5 : Register<"mm5">, DwarfRegNum<[46, 34, 34]>;
139 def MM6 : Register<"mm6">, DwarfRegNum<[47, 35, 35]>;
140 def MM7 : Register<"mm7">, DwarfRegNum<[48, 36, 36]>;
142 // Pseudo Floating Point registers
143 def FP0 : Register<"fp0">;
144 def FP1 : Register<"fp1">;
145 def FP2 : Register<"fp2">;
146 def FP3 : Register<"fp3">;
147 def FP4 : Register<"fp4">;
148 def FP5 : Register<"fp5">;
149 def FP6 : Register<"fp6">;
151 // XMM Registers, used by the various SSE instruction set extensions
152 def XMM0: Register<"xmm0">, DwarfRegNum<[17, 21, 21]>;
153 def XMM1: Register<"xmm1">, DwarfRegNum<[18, 22, 22]>;
154 def XMM2: Register<"xmm2">, DwarfRegNum<[19, 23, 23]>;
155 def XMM3: Register<"xmm3">, DwarfRegNum<[20, 24, 24]>;
156 def XMM4: Register<"xmm4">, DwarfRegNum<[21, 25, 25]>;
157 def XMM5: Register<"xmm5">, DwarfRegNum<[22, 26, 26]>;
158 def XMM6: Register<"xmm6">, DwarfRegNum<[23, 27, 27]>;
159 def XMM7: Register<"xmm7">, DwarfRegNum<[24, 28, 28]>;
162 def XMM8: Register<"xmm8">, DwarfRegNum<[25, -2, -2]>;
163 def XMM9: Register<"xmm9">, DwarfRegNum<[26, -2, -2]>;
164 def XMM10: Register<"xmm10">, DwarfRegNum<[27, -2, -2]>;
165 def XMM11: Register<"xmm11">, DwarfRegNum<[28, -2, -2]>;
166 def XMM12: Register<"xmm12">, DwarfRegNum<[29, -2, -2]>;
167 def XMM13: Register<"xmm13">, DwarfRegNum<[30, -2, -2]>;
168 def XMM14: Register<"xmm14">, DwarfRegNum<[31, -2, -2]>;
169 def XMM15: Register<"xmm15">, DwarfRegNum<[32, -2, -2]>;
171 // YMM Registers, used by AVX instructions
172 def YMM0: RegisterWithSubRegs<"ymm0", [XMM0]>, DwarfRegNum<[17, 21, 21]>;
173 def YMM1: RegisterWithSubRegs<"ymm1", [XMM1]>, DwarfRegNum<[18, 22, 22]>;
174 def YMM2: RegisterWithSubRegs<"ymm2", [XMM2]>, DwarfRegNum<[19, 23, 23]>;
175 def YMM3: RegisterWithSubRegs<"ymm3", [XMM3]>, DwarfRegNum<[20, 24, 24]>;
176 def YMM4: RegisterWithSubRegs<"ymm4", [XMM4]>, DwarfRegNum<[21, 25, 25]>;
177 def YMM5: RegisterWithSubRegs<"ymm5", [XMM5]>, DwarfRegNum<[22, 26, 26]>;
178 def YMM6: RegisterWithSubRegs<"ymm6", [XMM6]>, DwarfRegNum<[23, 27, 27]>;
179 def YMM7: RegisterWithSubRegs<"ymm7", [XMM7]>, DwarfRegNum<[24, 28, 28]>;
180 def YMM8: RegisterWithSubRegs<"ymm8", [XMM8]>, DwarfRegNum<[25, -2, -2]>;
181 def YMM9: RegisterWithSubRegs<"ymm9", [XMM9]>, DwarfRegNum<[26, -2, -2]>;
182 def YMM10: RegisterWithSubRegs<"ymm10", [XMM10]>, DwarfRegNum<[27, -2, -2]>;
183 def YMM11: RegisterWithSubRegs<"ymm11", [XMM11]>, DwarfRegNum<[28, -2, -2]>;
184 def YMM12: RegisterWithSubRegs<"ymm12", [XMM12]>, DwarfRegNum<[29, -2, -2]>;
185 def YMM13: RegisterWithSubRegs<"ymm13", [XMM13]>, DwarfRegNum<[30, -2, -2]>;
186 def YMM14: RegisterWithSubRegs<"ymm14", [XMM14]>, DwarfRegNum<[31, -2, -2]>;
187 def YMM15: RegisterWithSubRegs<"ymm15", [XMM15]>, DwarfRegNum<[32, -2, -2]>;
189 // Floating point stack registers
190 def ST0 : Register<"st(0)">, DwarfRegNum<[33, 12, 11]>;
191 def ST1 : Register<"st(1)">, DwarfRegNum<[34, 13, 12]>;
192 def ST2 : Register<"st(2)">, DwarfRegNum<[35, 14, 13]>;
193 def ST3 : Register<"st(3)">, DwarfRegNum<[36, 15, 14]>;
194 def ST4 : Register<"st(4)">, DwarfRegNum<[37, 16, 15]>;
195 def ST5 : Register<"st(5)">, DwarfRegNum<[38, 17, 16]>;
196 def ST6 : Register<"st(6)">, DwarfRegNum<[39, 18, 17]>;
197 def ST7 : Register<"st(7)">, DwarfRegNum<[40, 19, 18]>;
199 // Status flags register
200 def EFLAGS : Register<"flags">;
203 def CS : Register<"cs">;
204 def DS : Register<"ds">;
205 def SS : Register<"ss">;
206 def ES : Register<"es">;
207 def FS : Register<"fs">;
208 def GS : Register<"gs">;
211 def DR0 : Register<"dr0">;
212 def DR1 : Register<"dr1">;
213 def DR2 : Register<"dr2">;
214 def DR3 : Register<"dr3">;
215 def DR4 : Register<"dr4">;
216 def DR5 : Register<"dr5">;
217 def DR6 : Register<"dr6">;
218 def DR7 : Register<"dr7">;
220 // Condition registers
221 def CR0 : Register<"cr0">;
222 def CR1 : Register<"cr1">;
223 def CR2 : Register<"cr2">;
224 def CR3 : Register<"cr3">;
225 def CR4 : Register<"cr4">;
226 def CR5 : Register<"cr5">;
227 def CR6 : Register<"cr6">;
228 def CR7 : Register<"cr7">;
229 def CR8 : Register<"cr8">;
233 //===----------------------------------------------------------------------===//
234 // Subregister Set Definitions... now that we have all of the pieces, define the
235 // sub registers for each register.
238 def : SubRegSet<1, [AX, CX, DX, BX, SP, BP, SI, DI,
239 R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W],
240 [AL, CL, DL, BL, SPL, BPL, SIL, DIL,
241 R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
243 def : SubRegSet<2, [AX, CX, DX, BX],
246 def : SubRegSet<1, [EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI,
247 R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D],
248 [AL, CL, DL, BL, SPL, BPL, SIL, DIL,
249 R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
251 def : SubRegSet<2, [EAX, ECX, EDX, EBX],
254 def : SubRegSet<3, [EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI,
255 R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D],
256 [AX, CX, DX, BX, SP, BP, SI, DI,
257 R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]>;
259 def : SubRegSet<1, [RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI,
260 R8, R9, R10, R11, R12, R13, R14, R15],
261 [AL, CL, DL, BL, SPL, BPL, SIL, DIL,
262 R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
264 def : SubRegSet<2, [RAX, RCX, RDX, RBX],
267 def : SubRegSet<3, [RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI,
268 R8, R9, R10, R11, R12, R13, R14, R15],
269 [AX, CX, DX, BX, SP, BP, SI, DI,
270 R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]>;
272 def : SubRegSet<4, [RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI,
273 R8, R9, R10, R11, R12, R13, R14, R15],
274 [EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI,
275 R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D]>;
277 def : SubRegSet<1, [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
278 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15],
279 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
280 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15]>;
282 def : SubRegSet<2, [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
283 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15],
284 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
285 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15]>;
287 def : SubRegSet<3, [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
288 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15],
289 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
290 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15]>;
292 def : SubRegSet<1, [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
293 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15],
294 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
295 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15]>;
297 def : SubRegSet<2, [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
298 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15],
299 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
300 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15]>;
302 //===----------------------------------------------------------------------===//
303 // Register Class Definitions... now that we have all of the pieces, define the
304 // top-level register classes. The order specified in the register list is
305 // implicitly defined to be the register allocation order.
308 // List call-clobbered registers before callee-save registers. RBX, RBP, (and
309 // R12, R13, R14, and R15 for X86-64) are callee-save registers.
310 // In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and
312 // Allocate R12 and R13 last, as these require an extra byte when
313 // encoded in x86_64 instructions.
314 // FIXME: Allow AH, CH, DH, BH to be used as general-purpose registers in
315 // 64-bit mode. The main complication is that they cannot be encoded in an
316 // instruction requiring a REX prefix, while SIL, DIL, BPL, R8D, etc.
317 // require a REX prefix. For example, "addb %ah, %dil" and "movzbl %ah, %r8d"
318 // cannot be encoded.
319 def GR8 : RegisterClass<"X86", [i8], 8,
320 [AL, CL, DL, AH, CH, DH, BL, BH, SIL, DIL, BPL, SPL,
321 R8B, R9B, R10B, R11B, R14B, R15B, R12B, R13B]> {
322 let MethodProtos = [{
323 iterator allocation_order_begin(const MachineFunction &MF) const;
324 iterator allocation_order_end(const MachineFunction &MF) const;
326 let MethodBodies = [{
327 static const unsigned X86_GR8_AO_64[] = {
328 X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL,
329 X86::R8B, X86::R9B, X86::R10B, X86::R11B,
330 X86::BL, X86::R14B, X86::R15B, X86::R12B, X86::R13B, X86::BPL
334 GR8Class::allocation_order_begin(const MachineFunction &MF) const {
335 const TargetMachine &TM = MF.getTarget();
336 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
337 if (Subtarget.is64Bit())
338 return X86_GR8_AO_64;
344 GR8Class::allocation_order_end(const MachineFunction &MF) const {
345 const TargetMachine &TM = MF.getTarget();
346 const TargetRegisterInfo *RI = TM.getRegisterInfo();
347 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
348 const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
349 // Does the function dedicate RBP / EBP to being a frame ptr?
350 if (!Subtarget.is64Bit())
351 // In 32-mode, none of the 8-bit registers aliases EBP or ESP.
353 else if (RI->hasFP(MF) || MFI->getReserveFP())
354 // If so, don't allocate SPL or BPL.
355 return array_endof(X86_GR8_AO_64) - 1;
357 // If not, just don't allocate SPL.
358 return array_endof(X86_GR8_AO_64);
363 def GR16 : RegisterClass<"X86", [i16], 16,
364 [AX, CX, DX, SI, DI, BX, BP, SP,
365 R8W, R9W, R10W, R11W, R14W, R15W, R12W, R13W]> {
366 let SubRegClassList = [GR8, GR8];
367 let MethodProtos = [{
368 iterator allocation_order_begin(const MachineFunction &MF) const;
369 iterator allocation_order_end(const MachineFunction &MF) const;
371 let MethodBodies = [{
372 static const unsigned X86_GR16_AO_64[] = {
373 X86::AX, X86::CX, X86::DX, X86::SI, X86::DI,
374 X86::R8W, X86::R9W, X86::R10W, X86::R11W,
375 X86::BX, X86::R14W, X86::R15W, X86::R12W, X86::R13W, X86::BP
379 GR16Class::allocation_order_begin(const MachineFunction &MF) const {
380 const TargetMachine &TM = MF.getTarget();
381 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
382 if (Subtarget.is64Bit())
383 return X86_GR16_AO_64;
389 GR16Class::allocation_order_end(const MachineFunction &MF) const {
390 const TargetMachine &TM = MF.getTarget();
391 const TargetRegisterInfo *RI = TM.getRegisterInfo();
392 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
393 const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
394 if (Subtarget.is64Bit()) {
395 // Does the function dedicate RBP to being a frame ptr?
396 if (RI->hasFP(MF) || MFI->getReserveFP())
397 // If so, don't allocate SP or BP.
398 return array_endof(X86_GR16_AO_64) - 1;
400 // If not, just don't allocate SP.
401 return array_endof(X86_GR16_AO_64);
403 // Does the function dedicate EBP to being a frame ptr?
404 if (RI->hasFP(MF) || MFI->getReserveFP())
405 // If so, don't allocate SP or BP.
408 // If not, just don't allocate SP.
415 def GR32 : RegisterClass<"X86", [i32], 32,
416 [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP,
417 R8D, R9D, R10D, R11D, R14D, R15D, R12D, R13D]> {
418 let SubRegClassList = [GR8, GR8, GR16];
419 let MethodProtos = [{
420 iterator allocation_order_begin(const MachineFunction &MF) const;
421 iterator allocation_order_end(const MachineFunction &MF) const;
423 let MethodBodies = [{
424 static const unsigned X86_GR32_AO_64[] = {
425 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI,
426 X86::R8D, X86::R9D, X86::R10D, X86::R11D,
427 X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::EBP
431 GR32Class::allocation_order_begin(const MachineFunction &MF) const {
432 const TargetMachine &TM = MF.getTarget();
433 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
434 if (Subtarget.is64Bit())
435 return X86_GR32_AO_64;
441 GR32Class::allocation_order_end(const MachineFunction &MF) const {
442 const TargetMachine &TM = MF.getTarget();
443 const TargetRegisterInfo *RI = TM.getRegisterInfo();
444 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
445 const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
446 if (Subtarget.is64Bit()) {
447 // Does the function dedicate RBP to being a frame ptr?
448 if (RI->hasFP(MF) || MFI->getReserveFP())
449 // If so, don't allocate ESP or EBP.
450 return array_endof(X86_GR32_AO_64) - 1;
452 // If not, just don't allocate ESP.
453 return array_endof(X86_GR32_AO_64);
455 // Does the function dedicate EBP to being a frame ptr?
456 if (RI->hasFP(MF) || MFI->getReserveFP())
457 // If so, don't allocate ESP or EBP.
460 // If not, just don't allocate ESP.
467 // GR64 - 64-bit GPRs. This oddly includes RIP, which isn't accurate, since
468 // RIP isn't really a register and it can't be used anywhere except in an
469 // address, but it doesn't cause trouble.
470 def GR64 : RegisterClass<"X86", [i64], 64,
471 [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
472 RBX, R14, R15, R12, R13, RBP, RSP, RIP]> {
473 let SubRegClassList = [GR8, GR8, GR16, GR32];
474 let MethodProtos = [{
475 iterator allocation_order_end(const MachineFunction &MF) const;
477 let MethodBodies = [{
479 GR64Class::allocation_order_end(const MachineFunction &MF) const {
480 const TargetMachine &TM = MF.getTarget();
481 const TargetRegisterInfo *RI = TM.getRegisterInfo();
482 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
483 const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
484 if (!Subtarget.is64Bit())
485 return begin(); // None of these are allocatable in 32-bit.
486 // Does the function dedicate RBP to being a frame ptr?
487 if (RI->hasFP(MF) || MFI->getReserveFP())
488 return end()-3; // If so, don't allocate RIP, RSP or RBP
490 return end()-2; // If not, just don't allocate RIP or RSP
495 // Segment registers for use by MOV instructions (and others) that have a
496 // segment register as one operand. Always contain a 16-bit segment
498 def SEGMENT_REG : RegisterClass<"X86", [i16], 16, [CS, DS, SS, ES, FS, GS]> {
502 def DEBUG_REG : RegisterClass<"X86", [i32], 32,
503 [DR0, DR1, DR2, DR3, DR4, DR5, DR6, DR7]> {
506 // Control registers.
507 def CONTROL_REG : RegisterClass<"X86", [i64], 64,
508 [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7, CR8]> {
511 // GR8_ABCD_L, GR8_ABCD_H, GR16_ABCD, GR32_ABCD, GR64_ABCD - Subclasses of
512 // GR8, GR16, GR32, and GR64 which contain just the "a" "b", "c", and "d"
513 // registers. On x86-32, GR16_ABCD and GR32_ABCD are classes for registers
514 // that support 8-bit subreg operations. On x86-64, GR16_ABCD, GR32_ABCD,
515 // and GR64_ABCD are classes for registers that support 8-bit h-register
517 def GR8_ABCD_L : RegisterClass<"X86", [i8], 8, [AL, CL, DL, BL]> {
519 def GR8_ABCD_H : RegisterClass<"X86", [i8], 8, [AH, CH, DH, BH]> {
521 def GR16_ABCD : RegisterClass<"X86", [i16], 16, [AX, CX, DX, BX]> {
522 let SubRegClassList = [GR8_ABCD_L, GR8_ABCD_H];
524 def GR32_ABCD : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, EBX]> {
525 let SubRegClassList = [GR8_ABCD_L, GR8_ABCD_H, GR16_ABCD];
527 def GR64_ABCD : RegisterClass<"X86", [i64], 64, [RAX, RCX, RDX, RBX]> {
528 let SubRegClassList = [GR8_ABCD_L, GR8_ABCD_H, GR16_ABCD, GR32_ABCD];
530 def GR32_TC : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX]> {
531 let SubRegClassList = [GR8, GR8, GR16];
533 def GR64_TC : RegisterClass<"X86", [i64], 64, [RAX, RCX, RDX, RSI, RDI,
535 let SubRegClassList = [GR8, GR8, GR16, GR32_TC];
538 // GR8_NOREX - GR8 registers which do not require a REX prefix.
539 def GR8_NOREX : RegisterClass<"X86", [i8], 8,
540 [AL, CL, DL, AH, CH, DH, BL, BH]> {
541 let MethodProtos = [{
542 iterator allocation_order_begin(const MachineFunction &MF) const;
543 iterator allocation_order_end(const MachineFunction &MF) const;
545 let MethodBodies = [{
546 // In 64-bit mode, it's not safe to blindly allocate H registers.
547 static const unsigned X86_GR8_NOREX_AO_64[] = {
548 X86::AL, X86::CL, X86::DL, X86::BL
551 GR8_NOREXClass::iterator
552 GR8_NOREXClass::allocation_order_begin(const MachineFunction &MF) const {
553 const TargetMachine &TM = MF.getTarget();
554 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
555 if (Subtarget.is64Bit())
556 return X86_GR8_NOREX_AO_64;
561 GR8_NOREXClass::iterator
562 GR8_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
563 const TargetMachine &TM = MF.getTarget();
564 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
565 if (Subtarget.is64Bit())
566 return array_endof(X86_GR8_NOREX_AO_64);
572 // GR16_NOREX - GR16 registers which do not require a REX prefix.
573 def GR16_NOREX : RegisterClass<"X86", [i16], 16,
574 [AX, CX, DX, SI, DI, BX, BP, SP]> {
575 let SubRegClassList = [GR8_NOREX, GR8_NOREX];
576 let MethodProtos = [{
577 iterator allocation_order_end(const MachineFunction &MF) const;
579 let MethodBodies = [{
580 GR16_NOREXClass::iterator
581 GR16_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
582 const TargetMachine &TM = MF.getTarget();
583 const TargetRegisterInfo *RI = TM.getRegisterInfo();
584 const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
585 // Does the function dedicate RBP / EBP to being a frame ptr?
586 if (RI->hasFP(MF) || MFI->getReserveFP())
587 // If so, don't allocate SP or BP.
590 // If not, just don't allocate SP.
595 // GR32_NOREX - GR32 registers which do not require a REX prefix.
596 def GR32_NOREX : RegisterClass<"X86", [i32], 32,
597 [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP]> {
598 let SubRegClassList = [GR8_NOREX, GR8_NOREX, GR16_NOREX];
599 let MethodProtos = [{
600 iterator allocation_order_end(const MachineFunction &MF) const;
602 let MethodBodies = [{
603 GR32_NOREXClass::iterator
604 GR32_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
605 const TargetMachine &TM = MF.getTarget();
606 const TargetRegisterInfo *RI = TM.getRegisterInfo();
607 const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
608 // Does the function dedicate RBP / EBP to being a frame ptr?
609 if (RI->hasFP(MF) || MFI->getReserveFP())
610 // If so, don't allocate ESP or EBP.
613 // If not, just don't allocate ESP.
618 // GR64_NOREX - GR64 registers which do not require a REX prefix.
619 def GR64_NOREX : RegisterClass<"X86", [i64], 64,
620 [RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP]> {
621 let SubRegClassList = [GR8_NOREX, GR8_NOREX, GR16_NOREX, GR32_NOREX];
622 let MethodProtos = [{
623 iterator allocation_order_end(const MachineFunction &MF) const;
625 let MethodBodies = [{
626 GR64_NOREXClass::iterator
627 GR64_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
628 const TargetMachine &TM = MF.getTarget();
629 const TargetRegisterInfo *RI = TM.getRegisterInfo();
630 const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
631 // Does the function dedicate RBP to being a frame ptr?
632 if (RI->hasFP(MF) || MFI->getReserveFP())
633 // If so, don't allocate RIP, RSP or RBP.
636 // If not, just don't allocate RIP or RSP.
642 // GR32_NOSP - GR32 registers except ESP.
643 def GR32_NOSP : RegisterClass<"X86", [i32], 32,
644 [EAX, ECX, EDX, ESI, EDI, EBX, EBP,
645 R8D, R9D, R10D, R11D, R14D, R15D, R12D, R13D]> {
646 let SubRegClassList = [GR8, GR8, GR16];
647 let MethodProtos = [{
648 iterator allocation_order_begin(const MachineFunction &MF) const;
649 iterator allocation_order_end(const MachineFunction &MF) const;
651 let MethodBodies = [{
652 static const unsigned X86_GR32_NOSP_AO_64[] = {
653 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI,
654 X86::R8D, X86::R9D, X86::R10D, X86::R11D,
655 X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::EBP
658 GR32_NOSPClass::iterator
659 GR32_NOSPClass::allocation_order_begin(const MachineFunction &MF) const {
660 const TargetMachine &TM = MF.getTarget();
661 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
662 if (Subtarget.is64Bit())
663 return X86_GR32_NOSP_AO_64;
668 GR32_NOSPClass::iterator
669 GR32_NOSPClass::allocation_order_end(const MachineFunction &MF) const {
670 const TargetMachine &TM = MF.getTarget();
671 const TargetRegisterInfo *RI = TM.getRegisterInfo();
672 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
673 const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
674 if (Subtarget.is64Bit()) {
675 // Does the function dedicate RBP to being a frame ptr?
676 if (RI->hasFP(MF) || MFI->getReserveFP())
677 // If so, don't allocate EBP.
678 return array_endof(X86_GR32_NOSP_AO_64) - 1;
680 // If not, any reg in this class is ok.
681 return array_endof(X86_GR32_NOSP_AO_64);
683 // Does the function dedicate EBP to being a frame ptr?
684 if (RI->hasFP(MF) || MFI->getReserveFP())
685 // If so, don't allocate EBP.
688 // If not, any reg in this class is ok.
695 // GR64_NOSP - GR64 registers except RSP (and RIP).
696 def GR64_NOSP : RegisterClass<"X86", [i64], 64,
697 [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
698 RBX, R14, R15, R12, R13, RBP]> {
699 let SubRegClassList = [GR8, GR8, GR16, GR32_NOSP];
700 let MethodProtos = [{
701 iterator allocation_order_end(const MachineFunction &MF) const;
703 let MethodBodies = [{
704 GR64_NOSPClass::iterator
705 GR64_NOSPClass::allocation_order_end(const MachineFunction &MF) const {
706 const TargetMachine &TM = MF.getTarget();
707 const TargetRegisterInfo *RI = TM.getRegisterInfo();
708 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
709 const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
710 if (!Subtarget.is64Bit())
711 return begin(); // None of these are allocatable in 32-bit.
712 // Does the function dedicate RBP to being a frame ptr?
713 if (RI->hasFP(MF) || MFI->getReserveFP())
714 return end()-1; // If so, don't allocate RBP
716 return end(); // If not, any reg in this class is ok.
721 // GR64_NOREX_NOSP - GR64_NOREX registers except RSP.
722 def GR64_NOREX_NOSP : RegisterClass<"X86", [i64], 64,
723 [RAX, RCX, RDX, RSI, RDI, RBX, RBP]> {
724 let SubRegClassList = [GR8_NOREX, GR8_NOREX, GR16_NOREX, GR32_NOREX];
725 let MethodProtos = [{
726 iterator allocation_order_end(const MachineFunction &MF) const;
728 let MethodBodies = [{
729 GR64_NOREX_NOSPClass::iterator
730 GR64_NOREX_NOSPClass::allocation_order_end(const MachineFunction &MF) const
732 const TargetMachine &TM = MF.getTarget();
733 const TargetRegisterInfo *RI = TM.getRegisterInfo();
734 const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
735 // Does the function dedicate RBP to being a frame ptr?
736 if (RI->hasFP(MF) || MFI->getReserveFP())
737 // If so, don't allocate RBP.
740 // If not, any reg in this class is ok.
746 // A class to support the 'A' assembler constraint: EAX then EDX.
747 def GR32_AD : RegisterClass<"X86", [i32], 32, [EAX, EDX]> {
748 let SubRegClassList = [GR8_ABCD_L, GR8_ABCD_H, GR16_ABCD];
751 // Scalar SSE2 floating point registers.
752 def FR32 : RegisterClass<"X86", [f32], 32,
753 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
754 XMM8, XMM9, XMM10, XMM11,
755 XMM12, XMM13, XMM14, XMM15]> {
756 let MethodProtos = [{
757 iterator allocation_order_end(const MachineFunction &MF) const;
759 let MethodBodies = [{
761 FR32Class::allocation_order_end(const MachineFunction &MF) const {
762 const TargetMachine &TM = MF.getTarget();
763 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
764 if (!Subtarget.is64Bit())
765 return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.
772 def FR64 : RegisterClass<"X86", [f64], 64,
773 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
774 XMM8, XMM9, XMM10, XMM11,
775 XMM12, XMM13, XMM14, XMM15]> {
776 let MethodProtos = [{
777 iterator allocation_order_end(const MachineFunction &MF) const;
779 let MethodBodies = [{
781 FR64Class::allocation_order_end(const MachineFunction &MF) const {
782 const TargetMachine &TM = MF.getTarget();
783 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
784 if (!Subtarget.is64Bit())
785 return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.
793 // FIXME: This sets up the floating point register files as though they are f64
794 // values, though they really are f80 values. This will cause us to spill
795 // values as 64-bit quantities instead of 80-bit quantities, which is much much
796 // faster on common hardware. In reality, this should be controlled by a
797 // command line option or something.
799 def RFP32 : RegisterClass<"X86",[f32], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
800 def RFP64 : RegisterClass<"X86",[f64], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
801 def RFP80 : RegisterClass<"X86",[f80], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
803 // Floating point stack registers (these are not allocatable by the
804 // register allocator - the floating point stackifier is responsible
805 // for transforming FPn allocations to STn registers)
806 def RST : RegisterClass<"X86", [f80, f64, f32], 32,
807 [ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]> {
808 let MethodProtos = [{
809 iterator allocation_order_end(const MachineFunction &MF) const;
811 let MethodBodies = [{
813 RSTClass::allocation_order_end(const MachineFunction &MF) const {
819 // Generic vector registers: VR64 and VR128.
820 def VR64 : RegisterClass<"X86", [v8i8, v4i16, v2i32, v1i64, v2f32], 64,
821 [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7]>;
822 def VR128 : RegisterClass<"X86", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],128,
823 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
824 XMM8, XMM9, XMM10, XMM11,
825 XMM12, XMM13, XMM14, XMM15]> {
826 let SubRegClassList = [FR32, FR64];
827 let MethodProtos = [{
828 iterator allocation_order_end(const MachineFunction &MF) const;
830 let MethodBodies = [{
832 VR128Class::allocation_order_end(const MachineFunction &MF) const {
833 const TargetMachine &TM = MF.getTarget();
834 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
835 if (!Subtarget.is64Bit())
836 return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.
842 def VR256 : RegisterClass<"X86", [ v8i32, v4i64, v8f32, v4f64],256,
843 [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
844 YMM8, YMM9, YMM10, YMM11,
845 YMM12, YMM13, YMM14, YMM15]> {
846 let SubRegClassList = [FR32, FR64, VR128];
849 // Status flags registers.
850 def CCR : RegisterClass<"X86", [i32], 32, [EFLAGS]> {
851 let CopyCost = -1; // Don't allow copying of status registers.