1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineLocation.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/Target/TargetFrameLowering.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/STLExtras.h"
40 #include "llvm/Support/ErrorHandling.h"
41 #include "llvm/Support/CommandLine.h"
45 ForceStackAlign("force-align-stack",
46 cl::desc("Force align the stack to the minimum alignment"
47 " needed for the function."),
48 cl::init(false), cl::Hidden);
50 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
51 const TargetInstrInfo &tii)
52 : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() ?
53 X86::ADJCALLSTACKDOWN64 :
54 X86::ADJCALLSTACKDOWN32,
55 tm.getSubtarget<X86Subtarget>().is64Bit() ?
56 X86::ADJCALLSTACKUP64 :
57 X86::ADJCALLSTACKUP32),
59 // Cache some information.
60 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
61 Is64Bit = Subtarget->is64Bit();
62 IsWin64 = Subtarget->isTargetWin64();
63 StackAlign = TM.getFrameLowering()->getStackAlignment();
76 /// getDwarfRegNum - This function maps LLVM register identifiers to the DWARF
77 /// specific numbering, used in debug info and exception tables.
78 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
79 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
80 unsigned Flavour = DWARFFlavour::X86_64;
82 if (!Subtarget->is64Bit()) {
83 if (Subtarget->isTargetDarwin()) {
85 Flavour = DWARFFlavour::X86_32_DarwinEH;
87 Flavour = DWARFFlavour::X86_32_Generic;
88 } else if (Subtarget->isTargetCygMing()) {
89 // Unsupported by now, just quick fallback
90 Flavour = DWARFFlavour::X86_32_Generic;
92 Flavour = DWARFFlavour::X86_32_Generic;
96 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
100 X86RegisterInfo::getSEHRegNum(unsigned i) const {
101 int reg = getX86RegNum(i);
103 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
104 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
105 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
106 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
107 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
108 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
109 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
110 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
111 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
112 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
113 case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11:
114 case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15:
120 /// getX86RegNum - This function maps LLVM register identifiers to their X86
121 /// specific numbering, which is used in various places encoding instructions.
122 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
124 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
125 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
126 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
127 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
128 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
130 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
132 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
134 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
137 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
139 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
141 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
143 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
145 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
147 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
149 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
151 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
154 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
155 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
156 return RegNo-X86::ST0;
158 case X86::XMM0: case X86::XMM8:
159 case X86::YMM0: case X86::YMM8: case X86::MM0:
161 case X86::XMM1: case X86::XMM9:
162 case X86::YMM1: case X86::YMM9: case X86::MM1:
164 case X86::XMM2: case X86::XMM10:
165 case X86::YMM2: case X86::YMM10: case X86::MM2:
167 case X86::XMM3: case X86::XMM11:
168 case X86::YMM3: case X86::YMM11: case X86::MM3:
170 case X86::XMM4: case X86::XMM12:
171 case X86::YMM4: case X86::YMM12: case X86::MM4:
173 case X86::XMM5: case X86::XMM13:
174 case X86::YMM5: case X86::YMM13: case X86::MM5:
176 case X86::XMM6: case X86::XMM14:
177 case X86::YMM6: case X86::YMM14: case X86::MM6:
179 case X86::XMM7: case X86::XMM15:
180 case X86::YMM7: case X86::YMM15: case X86::MM7:
183 case X86::ES: return 0;
184 case X86::CS: return 1;
185 case X86::SS: return 2;
186 case X86::DS: return 3;
187 case X86::FS: return 4;
188 case X86::GS: return 5;
190 case X86::CR0: case X86::CR8 : case X86::DR0: return 0;
191 case X86::CR1: case X86::CR9 : case X86::DR1: return 1;
192 case X86::CR2: case X86::CR10: case X86::DR2: return 2;
193 case X86::CR3: case X86::CR11: case X86::DR3: return 3;
194 case X86::CR4: case X86::CR12: case X86::DR4: return 4;
195 case X86::CR5: case X86::CR13: case X86::DR5: return 5;
196 case X86::CR6: case X86::CR14: case X86::DR6: return 6;
197 case X86::CR7: case X86::CR15: case X86::DR7: return 7;
199 // Pseudo index registers are equivalent to a "none"
200 // scaled index (See Intel Manual 2A, table 2-3)
206 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
207 llvm_unreachable("Register allocator hasn't allocated reg correctly yet!");
212 const TargetRegisterClass *
213 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
214 const TargetRegisterClass *B,
215 unsigned SubIdx) const {
219 if (B == &X86::GR8RegClass) {
220 if (A->getSize() == 2 || A->getSize() == 4 || A->getSize() == 8)
222 } else if (B == &X86::GR8_ABCD_LRegClass || B == &X86::GR8_ABCD_HRegClass) {
223 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
224 A == &X86::GR64_NOREXRegClass ||
225 A == &X86::GR64_NOSPRegClass ||
226 A == &X86::GR64_NOREX_NOSPRegClass)
227 return &X86::GR64_ABCDRegClass;
228 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
229 A == &X86::GR32_NOREXRegClass ||
230 A == &X86::GR32_NOSPRegClass)
231 return &X86::GR32_ABCDRegClass;
232 else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
233 A == &X86::GR16_NOREXRegClass)
234 return &X86::GR16_ABCDRegClass;
235 } else if (B == &X86::GR8_NOREXRegClass) {
236 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
237 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
238 return &X86::GR64_NOREXRegClass;
239 else if (A == &X86::GR64_ABCDRegClass)
240 return &X86::GR64_ABCDRegClass;
241 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
242 A == &X86::GR32_NOSPRegClass)
243 return &X86::GR32_NOREXRegClass;
244 else if (A == &X86::GR32_ABCDRegClass)
245 return &X86::GR32_ABCDRegClass;
246 else if (A == &X86::GR16RegClass || A == &X86::GR16_NOREXRegClass)
247 return &X86::GR16_NOREXRegClass;
248 else if (A == &X86::GR16_ABCDRegClass)
249 return &X86::GR16_ABCDRegClass;
252 case X86::sub_8bit_hi:
253 if (B == &X86::GR8_ABCD_HRegClass ||
254 B->hasSubClass(&X86::GR8_ABCD_HRegClass))
255 switch (A->getSize()) {
256 case 2: return getCommonSubClass(A, &X86::GR16_ABCDRegClass);
257 case 4: return getCommonSubClass(A, &X86::GR32_ABCDRegClass);
258 case 8: return getCommonSubClass(A, &X86::GR64_ABCDRegClass);
263 if (B == &X86::GR16RegClass) {
264 if (A->getSize() == 4 || A->getSize() == 8)
266 } else if (B == &X86::GR16_ABCDRegClass) {
267 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
268 A == &X86::GR64_NOREXRegClass ||
269 A == &X86::GR64_NOSPRegClass ||
270 A == &X86::GR64_NOREX_NOSPRegClass)
271 return &X86::GR64_ABCDRegClass;
272 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
273 A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
274 return &X86::GR32_ABCDRegClass;
275 } else if (B == &X86::GR16_NOREXRegClass) {
276 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
277 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
278 return &X86::GR64_NOREXRegClass;
279 else if (A == &X86::GR64_ABCDRegClass)
280 return &X86::GR64_ABCDRegClass;
281 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
282 A == &X86::GR32_NOSPRegClass)
283 return &X86::GR32_NOREXRegClass;
284 else if (A == &X86::GR32_ABCDRegClass)
285 return &X86::GR64_ABCDRegClass;
289 if (B == &X86::GR32RegClass) {
290 if (A->getSize() == 8)
292 } else if (B == &X86::GR32_NOSPRegClass) {
293 if (A == &X86::GR64RegClass || A == &X86::GR64_NOSPRegClass)
294 return &X86::GR64_NOSPRegClass;
295 if (A->getSize() == 8)
296 return getCommonSubClass(A, &X86::GR64_NOSPRegClass);
297 } else if (B == &X86::GR32_ABCDRegClass) {
298 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
299 A == &X86::GR64_NOREXRegClass ||
300 A == &X86::GR64_NOSPRegClass ||
301 A == &X86::GR64_NOREX_NOSPRegClass)
302 return &X86::GR64_ABCDRegClass;
303 } else if (B == &X86::GR32_NOREXRegClass) {
304 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass)
305 return &X86::GR64_NOREXRegClass;
306 else if (A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
307 return &X86::GR64_NOREX_NOSPRegClass;
308 else if (A == &X86::GR64_ABCDRegClass)
309 return &X86::GR64_ABCDRegClass;
310 } else if (B == &X86::GR32_NOREX_NOSPRegClass) {
311 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
312 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
313 return &X86::GR64_NOREX_NOSPRegClass;
314 else if (A == &X86::GR64_ABCDRegClass)
315 return &X86::GR64_ABCDRegClass;
319 if (B == &X86::FR32RegClass)
323 if (B == &X86::FR64RegClass)
327 if (B == &X86::VR128RegClass)
334 const TargetRegisterClass*
335 X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) const{
336 const TargetRegisterClass *Super = RC;
337 TargetRegisterClass::sc_iterator I = RC->superclasses_begin();
339 switch (Super->getID()) {
340 case X86::GR8RegClassID:
341 case X86::GR16RegClassID:
342 case X86::GR32RegClassID:
343 case X86::GR64RegClassID:
344 case X86::FR32RegClassID:
345 case X86::FR64RegClassID:
346 case X86::RFP32RegClassID:
347 case X86::RFP64RegClassID:
348 case X86::RFP80RegClassID:
349 case X86::VR128RegClassID:
350 case X86::VR256RegClassID:
351 // Don't return a super-class that would shrink the spill size.
352 // That can happen with the vector and float classes.
353 if (Super->getSize() == RC->getSize())
361 const TargetRegisterClass *
362 X86RegisterInfo::getPointerRegClass(unsigned Kind) const {
364 default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
365 case 0: // Normal GPRs.
366 if (TM.getSubtarget<X86Subtarget>().is64Bit())
367 return &X86::GR64RegClass;
368 return &X86::GR32RegClass;
369 case 1: // Normal GPRs except the stack pointer (for encoding reasons).
370 if (TM.getSubtarget<X86Subtarget>().is64Bit())
371 return &X86::GR64_NOSPRegClass;
372 return &X86::GR32_NOSPRegClass;
373 case 2: // Available for tailcall (not callee-saved GPRs).
374 if (TM.getSubtarget<X86Subtarget>().isTargetWin64())
375 return &X86::GR64_TCW64RegClass;
376 if (TM.getSubtarget<X86Subtarget>().is64Bit())
377 return &X86::GR64_TCRegClass;
378 return &X86::GR32_TCRegClass;
382 const TargetRegisterClass *
383 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
384 if (RC == &X86::CCRRegClass) {
386 return &X86::GR64RegClass;
388 return &X86::GR32RegClass;
394 X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
395 MachineFunction &MF) const {
396 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
398 unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
399 switch (RC->getID()) {
402 case X86::GR32RegClassID:
404 case X86::GR64RegClassID:
406 case X86::VR128RegClassID:
407 return TM.getSubtarget<X86Subtarget>().is64Bit() ? 10 : 4;
408 case X86::VR64RegClassID:
414 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
415 bool callsEHReturn = false;
416 bool ghcCall = false;
419 callsEHReturn = MF->getMMI().callsEHReturn();
420 const Function *F = MF->getFunction();
421 ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false);
424 static const unsigned GhcCalleeSavedRegs[] = {
428 static const unsigned CalleeSavedRegs32Bit[] = {
429 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
432 static const unsigned CalleeSavedRegs32EHRet[] = {
433 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
436 static const unsigned CalleeSavedRegs64Bit[] = {
437 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
440 static const unsigned CalleeSavedRegs64EHRet[] = {
441 X86::RAX, X86::RDX, X86::RBX, X86::R12,
442 X86::R13, X86::R14, X86::R15, X86::RBP, 0
445 static const unsigned CalleeSavedRegsWin64[] = {
446 X86::RBX, X86::RBP, X86::RDI, X86::RSI,
447 X86::R12, X86::R13, X86::R14, X86::R15,
448 X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9,
449 X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13,
450 X86::XMM14, X86::XMM15, 0
454 return GhcCalleeSavedRegs;
455 } else if (Is64Bit) {
457 return CalleeSavedRegsWin64;
459 return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit);
461 return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit);
465 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
466 BitVector Reserved(getNumRegs());
467 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
469 // Set the stack-pointer register and its aliases as reserved.
470 Reserved.set(X86::RSP);
471 Reserved.set(X86::ESP);
472 Reserved.set(X86::SP);
473 Reserved.set(X86::SPL);
475 // Set the instruction pointer register and its aliases as reserved.
476 Reserved.set(X86::RIP);
477 Reserved.set(X86::EIP);
478 Reserved.set(X86::IP);
480 // Set the frame-pointer register and its aliases as reserved if needed.
481 if (TFI->hasFP(MF)) {
482 Reserved.set(X86::RBP);
483 Reserved.set(X86::EBP);
484 Reserved.set(X86::BP);
485 Reserved.set(X86::BPL);
488 // Mark the x87 stack registers as reserved, since they don't behave normally
489 // with respect to liveness. We don't fully model the effects of x87 stack
490 // pushes and pops after stackification.
491 Reserved.set(X86::ST0);
492 Reserved.set(X86::ST1);
493 Reserved.set(X86::ST2);
494 Reserved.set(X86::ST3);
495 Reserved.set(X86::ST4);
496 Reserved.set(X86::ST5);
497 Reserved.set(X86::ST6);
498 Reserved.set(X86::ST7);
500 // Mark the segment registers as reserved.
501 Reserved.set(X86::CS);
502 Reserved.set(X86::SS);
503 Reserved.set(X86::DS);
504 Reserved.set(X86::ES);
505 Reserved.set(X86::FS);
506 Reserved.set(X86::GS);
511 //===----------------------------------------------------------------------===//
512 // Stack Frame Processing methods
513 //===----------------------------------------------------------------------===//
515 bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
516 const MachineFrameInfo *MFI = MF.getFrameInfo();
517 return (RealignStack &&
518 !MFI->hasVarSizedObjects());
521 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
522 const MachineFrameInfo *MFI = MF.getFrameInfo();
523 const Function *F = MF.getFunction();
524 bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
525 F->hasFnAttr(Attribute::StackAlignment));
527 // FIXME: Currently we don't support stack realignment for functions with
528 // variable-sized allocas.
529 // FIXME: It's more complicated than this...
530 if (0 && requiresRealignment && MFI->hasVarSizedObjects())
532 "Stack realignment in presence of dynamic allocas is not supported");
534 // If we've requested that we force align the stack do so now.
536 return canRealignStack(MF);
538 return requiresRealignment && canRealignStack(MF);
541 bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
542 unsigned Reg, int &FrameIdx) const {
543 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
545 if (Reg == FramePtr && TFI->hasFP(MF)) {
546 FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
552 static unsigned getSUBriOpcode(unsigned is64Bit, int64_t Imm) {
555 return X86::SUB64ri8;
556 return X86::SUB64ri32;
559 return X86::SUB32ri8;
564 static unsigned getADDriOpcode(unsigned is64Bit, int64_t Imm) {
567 return X86::ADD64ri8;
568 return X86::ADD64ri32;
571 return X86::ADD32ri8;
576 void X86RegisterInfo::
577 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
578 MachineBasicBlock::iterator I) const {
579 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
580 bool reseveCallFrame = TFI->hasReservedCallFrame(MF);
581 int Opcode = I->getOpcode();
582 bool isDestroy = Opcode == getCallFrameDestroyOpcode();
583 DebugLoc DL = I->getDebugLoc();
584 uint64_t Amount = !reseveCallFrame ? I->getOperand(0).getImm() : 0;
585 uint64_t CalleeAmt = isDestroy ? I->getOperand(1).getImm() : 0;
588 if (!reseveCallFrame) {
589 // If the stack pointer can be changed after prologue, turn the
590 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
591 // adjcallstackdown instruction into 'add ESP, <amt>'
592 // TODO: consider using push / pop instead of sub + store / add
596 // We need to keep the stack aligned properly. To do this, we round the
597 // amount of space needed for the outgoing arguments up to the next
598 // alignment boundary.
599 Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
601 MachineInstr *New = 0;
602 if (Opcode == getCallFrameSetupOpcode()) {
603 New = BuildMI(MF, DL, TII.get(getSUBriOpcode(Is64Bit, Amount)),
608 assert(Opcode == getCallFrameDestroyOpcode());
610 // Factor out the amount the callee already popped.
614 unsigned Opc = getADDriOpcode(Is64Bit, Amount);
615 New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
616 .addReg(StackPtr).addImm(Amount);
621 // The EFLAGS implicit def is dead.
622 New->getOperand(3).setIsDead();
624 // Replace the pseudo instruction with a new instruction.
631 if (Opcode == getCallFrameDestroyOpcode() && CalleeAmt) {
632 // If we are performing frame pointer elimination and if the callee pops
633 // something off the stack pointer, add it back. We do this until we have
634 // more advanced stack pointer tracking ability.
635 unsigned Opc = getSUBriOpcode(Is64Bit, CalleeAmt);
636 MachineInstr *New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
637 .addReg(StackPtr).addImm(CalleeAmt);
639 // The EFLAGS implicit def is dead.
640 New->getOperand(3).setIsDead();
646 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
647 int SPAdj, RegScavenger *RS) const{
648 assert(SPAdj == 0 && "Unexpected");
651 MachineInstr &MI = *II;
652 MachineFunction &MF = *MI.getParent()->getParent();
653 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
655 while (!MI.getOperand(i).isFI()) {
657 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
660 int FrameIndex = MI.getOperand(i).getIndex();
663 unsigned Opc = MI.getOpcode();
664 bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm;
665 if (needsStackRealignment(MF))
666 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
670 BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr);
672 // This must be part of a four operand memory reference. Replace the
673 // FrameIndex with base register with EBP. Add an offset to the offset.
674 MI.getOperand(i).ChangeToRegister(BasePtr, false);
676 // Now add the frame object offset to the offset from EBP.
679 // Tail call jmp happens after FP is popped.
680 const MachineFrameInfo *MFI = MF.getFrameInfo();
681 FIOffset = MFI->getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea();
683 FIOffset = TFI->getFrameIndexOffset(MF, FrameIndex);
685 if (MI.getOperand(i+3).isImm()) {
686 // Offset is a 32-bit integer.
687 int Offset = FIOffset + (int)(MI.getOperand(i + 3).getImm());
688 MI.getOperand(i + 3).ChangeToImmediate(Offset);
690 // Offset is symbolic. This is extremely rare.
691 uint64_t Offset = FIOffset + (uint64_t)MI.getOperand(i+3).getOffset();
692 MI.getOperand(i+3).setOffset(Offset);
696 unsigned X86RegisterInfo::getRARegister() const {
697 return Is64Bit ? X86::RIP // Should have dwarf #16.
698 : X86::EIP; // Should have dwarf #8.
701 unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
702 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
703 return TFI->hasFP(MF) ? FramePtr : StackPtr;
706 unsigned X86RegisterInfo::getEHExceptionRegister() const {
707 llvm_unreachable("What is the exception register");
711 unsigned X86RegisterInfo::getEHHandlerRegister() const {
712 llvm_unreachable("What is the exception handler register");
717 unsigned getX86SubSuperRegister(unsigned Reg, EVT VT, bool High) {
718 switch (VT.getSimpleVT().SimpleTy) {
724 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
726 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
728 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
730 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
736 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
738 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
740 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
742 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
744 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
746 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
748 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
750 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
752 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
754 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
756 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
758 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
760 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
762 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
764 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
766 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
773 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
775 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
777 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
779 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
781 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
783 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
785 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
787 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
789 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
791 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
793 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
795 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
797 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
799 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
801 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
803 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
809 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
811 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
813 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
815 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
817 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
819 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
821 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
823 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
825 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
827 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
829 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
831 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
833 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
835 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
837 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
839 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
845 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
847 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
849 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
851 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
853 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
855 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
857 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
859 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
861 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
863 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
865 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
867 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
869 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
871 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
873 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
875 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
884 #include "X86GenRegisterInfo.inc"
887 struct MSAH : public MachineFunctionPass {
889 MSAH() : MachineFunctionPass(ID) {}
891 virtual bool runOnMachineFunction(MachineFunction &MF) {
892 const X86TargetMachine *TM =
893 static_cast<const X86TargetMachine *>(&MF.getTarget());
894 const X86RegisterInfo *X86RI = TM->getRegisterInfo();
895 MachineRegisterInfo &RI = MF.getRegInfo();
896 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
897 unsigned StackAlignment = X86RI->getStackAlignment();
899 // Be over-conservative: scan over all vreg defs and find whether vector
900 // registers are used. If yes, there is a possibility that vector register
901 // will be spilled and thus require dynamic stack realignment.
902 for (unsigned i = 0, e = RI.getNumVirtRegs(); i != e; ++i) {
903 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
904 if (RI.getRegClass(Reg)->getAlignment() > StackAlignment) {
905 FuncInfo->setReserveFP(true);
913 virtual const char *getPassName() const {
914 return "X86 Maximal Stack Alignment Check";
917 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
918 AU.setPreservesCFG();
919 MachineFunctionPass::getAnalysisUsage(AU);
927 llvm::createX86MaxStackAlignmentHeuristicPass() { return new MSAH(); }