1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineLocation.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/Target/TargetFrameLowering.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/STLExtras.h"
40 #include "llvm/Support/ErrorHandling.h"
41 #include "llvm/Support/CommandLine.h"
43 #define GET_REGINFO_MC_DESC
44 #define GET_REGINFO_TARGET_DESC
45 #include "X86GenRegisterInfo.inc"
50 ForceStackAlign("force-align-stack",
51 cl::desc("Force align the stack to the minimum alignment"
52 " needed for the function."),
53 cl::init(false), cl::Hidden);
55 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
56 const TargetInstrInfo &tii)
57 : X86GenRegisterInfo(X86RegDesc, X86RegInfoDesc,
58 tm.getSubtarget<X86Subtarget>().is64Bit() ?
59 X86::ADJCALLSTACKDOWN64 :
60 X86::ADJCALLSTACKDOWN32,
61 tm.getSubtarget<X86Subtarget>().is64Bit() ?
62 X86::ADJCALLSTACKUP64 :
63 X86::ADJCALLSTACKUP32),
65 // Cache some information.
66 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
67 Is64Bit = Subtarget->is64Bit();
68 IsWin64 = Subtarget->isTargetWin64();
81 static unsigned getFlavour(const X86Subtarget *Subtarget, bool isEH) {
82 if (!Subtarget->is64Bit()) {
83 if (Subtarget->isTargetDarwin()) {
85 return DWARFFlavour::X86_32_DarwinEH;
87 return DWARFFlavour::X86_32_Generic;
88 } else if (Subtarget->isTargetCygMing()) {
89 // Unsupported by now, just quick fallback
90 return DWARFFlavour::X86_32_Generic;
92 return DWARFFlavour::X86_32_Generic;
95 return DWARFFlavour::X86_64;
98 /// getDwarfRegNum - This function maps LLVM register identifiers to the DWARF
99 /// specific numbering, used in debug info and exception tables.
100 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
101 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
102 unsigned Flavour = getFlavour(Subtarget, isEH);
104 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
107 /// getLLVMRegNum - This function maps DWARF register numbers to LLVM register.
108 int X86RegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
109 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
110 unsigned Flavour = getFlavour(Subtarget, isEH);
112 return X86GenRegisterInfo::getLLVMRegNumFull(DwarfRegNo, Flavour);
116 X86RegisterInfo::getSEHRegNum(unsigned i) const {
117 int reg = getX86RegNum(i);
119 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
120 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
121 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
122 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
123 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
124 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
125 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
126 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
127 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
128 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
129 case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11:
130 case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15:
136 /// getX86RegNum - This function maps LLVM register identifiers to their X86
137 /// specific numbering, which is used in various places encoding instructions.
138 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
140 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
141 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
142 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
143 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
144 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
146 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
148 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
150 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
153 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
155 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
157 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
159 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
161 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
163 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
165 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
167 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
170 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
171 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
172 return RegNo-X86::ST0;
174 case X86::XMM0: case X86::XMM8:
175 case X86::YMM0: case X86::YMM8: case X86::MM0:
177 case X86::XMM1: case X86::XMM9:
178 case X86::YMM1: case X86::YMM9: case X86::MM1:
180 case X86::XMM2: case X86::XMM10:
181 case X86::YMM2: case X86::YMM10: case X86::MM2:
183 case X86::XMM3: case X86::XMM11:
184 case X86::YMM3: case X86::YMM11: case X86::MM3:
186 case X86::XMM4: case X86::XMM12:
187 case X86::YMM4: case X86::YMM12: case X86::MM4:
189 case X86::XMM5: case X86::XMM13:
190 case X86::YMM5: case X86::YMM13: case X86::MM5:
192 case X86::XMM6: case X86::XMM14:
193 case X86::YMM6: case X86::YMM14: case X86::MM6:
195 case X86::XMM7: case X86::XMM15:
196 case X86::YMM7: case X86::YMM15: case X86::MM7:
199 case X86::ES: return 0;
200 case X86::CS: return 1;
201 case X86::SS: return 2;
202 case X86::DS: return 3;
203 case X86::FS: return 4;
204 case X86::GS: return 5;
206 case X86::CR0: case X86::CR8 : case X86::DR0: return 0;
207 case X86::CR1: case X86::CR9 : case X86::DR1: return 1;
208 case X86::CR2: case X86::CR10: case X86::DR2: return 2;
209 case X86::CR3: case X86::CR11: case X86::DR3: return 3;
210 case X86::CR4: case X86::CR12: case X86::DR4: return 4;
211 case X86::CR5: case X86::CR13: case X86::DR5: return 5;
212 case X86::CR6: case X86::CR14: case X86::DR6: return 6;
213 case X86::CR7: case X86::CR15: case X86::DR7: return 7;
215 // Pseudo index registers are equivalent to a "none"
216 // scaled index (See Intel Manual 2A, table 2-3)
222 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
223 llvm_unreachable("Register allocator hasn't allocated reg correctly yet!");
228 const TargetRegisterClass *
229 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
230 const TargetRegisterClass *B,
231 unsigned SubIdx) const {
235 if (B == &X86::GR8RegClass) {
236 if (A->getSize() == 2 || A->getSize() == 4 || A->getSize() == 8)
238 } else if (B == &X86::GR8_ABCD_LRegClass || B == &X86::GR8_ABCD_HRegClass) {
239 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
240 A == &X86::GR64_NOREXRegClass ||
241 A == &X86::GR64_NOSPRegClass ||
242 A == &X86::GR64_NOREX_NOSPRegClass)
243 return &X86::GR64_ABCDRegClass;
244 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
245 A == &X86::GR32_NOREXRegClass ||
246 A == &X86::GR32_NOSPRegClass)
247 return &X86::GR32_ABCDRegClass;
248 else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
249 A == &X86::GR16_NOREXRegClass)
250 return &X86::GR16_ABCDRegClass;
251 } else if (B == &X86::GR8_NOREXRegClass) {
252 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
253 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
254 return &X86::GR64_NOREXRegClass;
255 else if (A == &X86::GR64_ABCDRegClass)
256 return &X86::GR64_ABCDRegClass;
257 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
258 A == &X86::GR32_NOSPRegClass)
259 return &X86::GR32_NOREXRegClass;
260 else if (A == &X86::GR32_ABCDRegClass)
261 return &X86::GR32_ABCDRegClass;
262 else if (A == &X86::GR16RegClass || A == &X86::GR16_NOREXRegClass)
263 return &X86::GR16_NOREXRegClass;
264 else if (A == &X86::GR16_ABCDRegClass)
265 return &X86::GR16_ABCDRegClass;
268 case X86::sub_8bit_hi:
269 if (B->hasSubClassEq(&X86::GR8_ABCD_HRegClass))
270 switch (A->getSize()) {
271 case 2: return getCommonSubClass(A, &X86::GR16_ABCDRegClass);
272 case 4: return getCommonSubClass(A, &X86::GR32_ABCDRegClass);
273 case 8: return getCommonSubClass(A, &X86::GR64_ABCDRegClass);
278 if (B == &X86::GR16RegClass) {
279 if (A->getSize() == 4 || A->getSize() == 8)
281 } else if (B == &X86::GR16_ABCDRegClass) {
282 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
283 A == &X86::GR64_NOREXRegClass ||
284 A == &X86::GR64_NOSPRegClass ||
285 A == &X86::GR64_NOREX_NOSPRegClass)
286 return &X86::GR64_ABCDRegClass;
287 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
288 A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
289 return &X86::GR32_ABCDRegClass;
290 } else if (B == &X86::GR16_NOREXRegClass) {
291 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
292 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
293 return &X86::GR64_NOREXRegClass;
294 else if (A == &X86::GR64_ABCDRegClass)
295 return &X86::GR64_ABCDRegClass;
296 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
297 A == &X86::GR32_NOSPRegClass)
298 return &X86::GR32_NOREXRegClass;
299 else if (A == &X86::GR32_ABCDRegClass)
300 return &X86::GR64_ABCDRegClass;
304 if (B == &X86::GR32RegClass) {
305 if (A->getSize() == 8)
307 } else if (B == &X86::GR32_NOSPRegClass) {
308 if (A == &X86::GR64RegClass || A == &X86::GR64_NOSPRegClass)
309 return &X86::GR64_NOSPRegClass;
310 if (A->getSize() == 8)
311 return getCommonSubClass(A, &X86::GR64_NOSPRegClass);
312 } else if (B == &X86::GR32_ABCDRegClass) {
313 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
314 A == &X86::GR64_NOREXRegClass ||
315 A == &X86::GR64_NOSPRegClass ||
316 A == &X86::GR64_NOREX_NOSPRegClass)
317 return &X86::GR64_ABCDRegClass;
318 } else if (B == &X86::GR32_NOREXRegClass) {
319 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass)
320 return &X86::GR64_NOREXRegClass;
321 else if (A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
322 return &X86::GR64_NOREX_NOSPRegClass;
323 else if (A == &X86::GR64_ABCDRegClass)
324 return &X86::GR64_ABCDRegClass;
325 } else if (B == &X86::GR32_NOREX_NOSPRegClass) {
326 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
327 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
328 return &X86::GR64_NOREX_NOSPRegClass;
329 else if (A == &X86::GR64_ABCDRegClass)
330 return &X86::GR64_ABCDRegClass;
334 if (B == &X86::FR32RegClass)
338 if (B == &X86::FR64RegClass)
342 if (B == &X86::VR128RegClass)
349 const TargetRegisterClass*
350 X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) const{
351 const TargetRegisterClass *Super = RC;
352 TargetRegisterClass::sc_iterator I = RC->superclasses_begin();
354 switch (Super->getID()) {
355 case X86::GR8RegClassID:
356 case X86::GR16RegClassID:
357 case X86::GR32RegClassID:
358 case X86::GR64RegClassID:
359 case X86::FR32RegClassID:
360 case X86::FR64RegClassID:
361 case X86::RFP32RegClassID:
362 case X86::RFP64RegClassID:
363 case X86::RFP80RegClassID:
364 case X86::VR128RegClassID:
365 case X86::VR256RegClassID:
366 // Don't return a super-class that would shrink the spill size.
367 // That can happen with the vector and float classes.
368 if (Super->getSize() == RC->getSize())
376 const TargetRegisterClass *
377 X86RegisterInfo::getPointerRegClass(unsigned Kind) const {
379 default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
380 case 0: // Normal GPRs.
381 if (TM.getSubtarget<X86Subtarget>().is64Bit())
382 return &X86::GR64RegClass;
383 return &X86::GR32RegClass;
384 case 1: // Normal GPRs except the stack pointer (for encoding reasons).
385 if (TM.getSubtarget<X86Subtarget>().is64Bit())
386 return &X86::GR64_NOSPRegClass;
387 return &X86::GR32_NOSPRegClass;
388 case 2: // Available for tailcall (not callee-saved GPRs).
389 if (TM.getSubtarget<X86Subtarget>().isTargetWin64())
390 return &X86::GR64_TCW64RegClass;
391 if (TM.getSubtarget<X86Subtarget>().is64Bit())
392 return &X86::GR64_TCRegClass;
393 return &X86::GR32_TCRegClass;
397 const TargetRegisterClass *
398 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
399 if (RC == &X86::CCRRegClass) {
401 return &X86::GR64RegClass;
403 return &X86::GR32RegClass;
409 X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
410 MachineFunction &MF) const {
411 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
413 unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
414 switch (RC->getID()) {
417 case X86::GR32RegClassID:
419 case X86::GR64RegClassID:
421 case X86::VR128RegClassID:
422 return TM.getSubtarget<X86Subtarget>().is64Bit() ? 10 : 4;
423 case X86::VR64RegClassID:
429 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
430 bool callsEHReturn = false;
431 bool ghcCall = false;
434 callsEHReturn = MF->getMMI().callsEHReturn();
435 const Function *F = MF->getFunction();
436 ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false);
439 static const unsigned GhcCalleeSavedRegs[] = {
443 static const unsigned CalleeSavedRegs32Bit[] = {
444 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
447 static const unsigned CalleeSavedRegs32EHRet[] = {
448 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
451 static const unsigned CalleeSavedRegs64Bit[] = {
452 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
455 static const unsigned CalleeSavedRegs64EHRet[] = {
456 X86::RAX, X86::RDX, X86::RBX, X86::R12,
457 X86::R13, X86::R14, X86::R15, X86::RBP, 0
460 static const unsigned CalleeSavedRegsWin64[] = {
461 X86::RBX, X86::RBP, X86::RDI, X86::RSI,
462 X86::R12, X86::R13, X86::R14, X86::R15,
463 X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9,
464 X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13,
465 X86::XMM14, X86::XMM15, 0
469 return GhcCalleeSavedRegs;
470 } else if (Is64Bit) {
472 return CalleeSavedRegsWin64;
474 return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit);
476 return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit);
480 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
481 BitVector Reserved(getNumRegs());
482 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
484 // Set the stack-pointer register and its aliases as reserved.
485 Reserved.set(X86::RSP);
486 Reserved.set(X86::ESP);
487 Reserved.set(X86::SP);
488 Reserved.set(X86::SPL);
490 // Set the instruction pointer register and its aliases as reserved.
491 Reserved.set(X86::RIP);
492 Reserved.set(X86::EIP);
493 Reserved.set(X86::IP);
495 // Set the frame-pointer register and its aliases as reserved if needed.
496 if (TFI->hasFP(MF)) {
497 Reserved.set(X86::RBP);
498 Reserved.set(X86::EBP);
499 Reserved.set(X86::BP);
500 Reserved.set(X86::BPL);
503 // Mark the segment registers as reserved.
504 Reserved.set(X86::CS);
505 Reserved.set(X86::SS);
506 Reserved.set(X86::DS);
507 Reserved.set(X86::ES);
508 Reserved.set(X86::FS);
509 Reserved.set(X86::GS);
511 // Reserve the registers that only exist in 64-bit mode.
513 // These 8-bit registers are part of the x86-64 extension even though their
514 // super-registers are old 32-bits.
515 Reserved.set(X86::SIL);
516 Reserved.set(X86::DIL);
517 Reserved.set(X86::BPL);
518 Reserved.set(X86::SPL);
520 for (unsigned n = 0; n != 8; ++n) {
522 const unsigned GPR64[] = {
523 X86::R8, X86::R9, X86::R10, X86::R11,
524 X86::R12, X86::R13, X86::R14, X86::R15
526 for (const unsigned *AI = getOverlaps(GPR64[n]); unsigned Reg = *AI; ++AI)
530 assert(X86::XMM15 == X86::XMM8+7);
531 for (const unsigned *AI = getOverlaps(X86::XMM8 + n); unsigned Reg = *AI;
540 //===----------------------------------------------------------------------===//
541 // Stack Frame Processing methods
542 //===----------------------------------------------------------------------===//
544 bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
545 const MachineFrameInfo *MFI = MF.getFrameInfo();
546 return (RealignStack &&
547 !MFI->hasVarSizedObjects());
550 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
551 const MachineFrameInfo *MFI = MF.getFrameInfo();
552 const Function *F = MF.getFunction();
553 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
554 bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
555 F->hasFnAttr(Attribute::StackAlignment));
557 // FIXME: Currently we don't support stack realignment for functions with
558 // variable-sized allocas.
559 // FIXME: It's more complicated than this...
560 if (0 && requiresRealignment && MFI->hasVarSizedObjects())
562 "Stack realignment in presence of dynamic allocas is not supported");
564 // If we've requested that we force align the stack do so now.
566 return canRealignStack(MF);
568 return requiresRealignment && canRealignStack(MF);
571 bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
572 unsigned Reg, int &FrameIdx) const {
573 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
575 if (Reg == FramePtr && TFI->hasFP(MF)) {
576 FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
582 static unsigned getSUBriOpcode(unsigned is64Bit, int64_t Imm) {
585 return X86::SUB64ri8;
586 return X86::SUB64ri32;
589 return X86::SUB32ri8;
594 static unsigned getADDriOpcode(unsigned is64Bit, int64_t Imm) {
597 return X86::ADD64ri8;
598 return X86::ADD64ri32;
601 return X86::ADD32ri8;
606 void X86RegisterInfo::
607 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
608 MachineBasicBlock::iterator I) const {
609 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
610 bool reseveCallFrame = TFI->hasReservedCallFrame(MF);
611 int Opcode = I->getOpcode();
612 bool isDestroy = Opcode == getCallFrameDestroyOpcode();
613 DebugLoc DL = I->getDebugLoc();
614 uint64_t Amount = !reseveCallFrame ? I->getOperand(0).getImm() : 0;
615 uint64_t CalleeAmt = isDestroy ? I->getOperand(1).getImm() : 0;
618 if (!reseveCallFrame) {
619 // If the stack pointer can be changed after prologue, turn the
620 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
621 // adjcallstackdown instruction into 'add ESP, <amt>'
622 // TODO: consider using push / pop instead of sub + store / add
626 // We need to keep the stack aligned properly. To do this, we round the
627 // amount of space needed for the outgoing arguments up to the next
628 // alignment boundary.
629 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
630 Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
632 MachineInstr *New = 0;
633 if (Opcode == getCallFrameSetupOpcode()) {
634 New = BuildMI(MF, DL, TII.get(getSUBriOpcode(Is64Bit, Amount)),
639 assert(Opcode == getCallFrameDestroyOpcode());
641 // Factor out the amount the callee already popped.
645 unsigned Opc = getADDriOpcode(Is64Bit, Amount);
646 New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
647 .addReg(StackPtr).addImm(Amount);
652 // The EFLAGS implicit def is dead.
653 New->getOperand(3).setIsDead();
655 // Replace the pseudo instruction with a new instruction.
662 if (Opcode == getCallFrameDestroyOpcode() && CalleeAmt) {
663 // If we are performing frame pointer elimination and if the callee pops
664 // something off the stack pointer, add it back. We do this until we have
665 // more advanced stack pointer tracking ability.
666 unsigned Opc = getSUBriOpcode(Is64Bit, CalleeAmt);
667 MachineInstr *New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
668 .addReg(StackPtr).addImm(CalleeAmt);
670 // The EFLAGS implicit def is dead.
671 New->getOperand(3).setIsDead();
677 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
678 int SPAdj, RegScavenger *RS) const{
679 assert(SPAdj == 0 && "Unexpected");
682 MachineInstr &MI = *II;
683 MachineFunction &MF = *MI.getParent()->getParent();
684 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
686 while (!MI.getOperand(i).isFI()) {
688 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
691 int FrameIndex = MI.getOperand(i).getIndex();
694 unsigned Opc = MI.getOpcode();
695 bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm;
696 if (needsStackRealignment(MF))
697 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
701 BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr);
703 // This must be part of a four operand memory reference. Replace the
704 // FrameIndex with base register with EBP. Add an offset to the offset.
705 MI.getOperand(i).ChangeToRegister(BasePtr, false);
707 // Now add the frame object offset to the offset from EBP.
710 // Tail call jmp happens after FP is popped.
711 const MachineFrameInfo *MFI = MF.getFrameInfo();
712 FIOffset = MFI->getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea();
714 FIOffset = TFI->getFrameIndexOffset(MF, FrameIndex);
716 if (MI.getOperand(i+3).isImm()) {
717 // Offset is a 32-bit integer.
718 int Offset = FIOffset + (int)(MI.getOperand(i + 3).getImm());
719 MI.getOperand(i + 3).ChangeToImmediate(Offset);
721 // Offset is symbolic. This is extremely rare.
722 uint64_t Offset = FIOffset + (uint64_t)MI.getOperand(i+3).getOffset();
723 MI.getOperand(i+3).setOffset(Offset);
727 unsigned X86RegisterInfo::getRARegister() const {
728 return Is64Bit ? X86::RIP // Should have dwarf #16.
729 : X86::EIP; // Should have dwarf #8.
732 unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
733 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
734 return TFI->hasFP(MF) ? FramePtr : StackPtr;
737 unsigned X86RegisterInfo::getEHExceptionRegister() const {
738 llvm_unreachable("What is the exception register");
742 unsigned X86RegisterInfo::getEHHandlerRegister() const {
743 llvm_unreachable("What is the exception handler register");
748 unsigned getX86SubSuperRegister(unsigned Reg, EVT VT, bool High) {
749 switch (VT.getSimpleVT().SimpleTy) {
755 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
757 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
759 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
761 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
767 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
769 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
771 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
773 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
775 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
777 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
779 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
781 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
783 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
785 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
787 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
789 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
791 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
793 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
795 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
797 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
804 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
806 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
808 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
810 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
812 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
814 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
816 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
818 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
820 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
822 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
824 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
826 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
828 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
830 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
832 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
834 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
840 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
842 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
844 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
846 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
848 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
850 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
852 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
854 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
856 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
858 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
860 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
862 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
864 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
866 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
868 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
870 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
876 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
878 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
880 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
882 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
884 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
886 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
888 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
890 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
892 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
894 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
896 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
898 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
900 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
902 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
904 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
906 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
916 struct MSAH : public MachineFunctionPass {
918 MSAH() : MachineFunctionPass(ID) {}
920 virtual bool runOnMachineFunction(MachineFunction &MF) {
921 const X86TargetMachine *TM =
922 static_cast<const X86TargetMachine *>(&MF.getTarget());
923 const TargetFrameLowering *TFI = TM->getFrameLowering();
924 MachineRegisterInfo &RI = MF.getRegInfo();
925 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
926 unsigned StackAlignment = TFI->getStackAlignment();
928 // Be over-conservative: scan over all vreg defs and find whether vector
929 // registers are used. If yes, there is a possibility that vector register
930 // will be spilled and thus require dynamic stack realignment.
931 for (unsigned i = 0, e = RI.getNumVirtRegs(); i != e; ++i) {
932 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
933 if (RI.getRegClass(Reg)->getAlignment() > StackAlignment) {
934 FuncInfo->setReserveFP(true);
942 virtual const char *getPassName() const {
943 return "X86 Maximal Stack Alignment Check";
946 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
947 AU.setPreservesCFG();
948 MachineFunctionPass::getAnalysisUsage(AU);
956 llvm::createX86MaxStackAlignmentHeuristicPass() { return new MSAH(); }