1 //===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
16 #include "X86RegisterInfo.h"
17 #include "X86FrameLowering.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineFunctionPass.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineModuleInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/MachineValueType.h"
31 #include "llvm/IR/Constants.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/Type.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Target/TargetFrameLowering.h"
38 #include "llvm/Target/TargetInstrInfo.h"
39 #include "llvm/Target/TargetMachine.h"
40 #include "llvm/Target/TargetOptions.h"
44 #define GET_REGINFO_TARGET_DESC
45 #include "X86GenRegisterInfo.inc"
48 EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
49 cl::desc("Enable use of a base pointer for complex stack frames"));
51 X86RegisterInfo::X86RegisterInfo(const Triple &TT)
52 : X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP),
53 X86_MC::getDwarfRegFlavour(TT, false),
54 X86_MC::getDwarfRegFlavour(TT, true),
55 (TT.isArch64Bit() ? X86::RIP : X86::EIP)) {
56 X86_MC::InitLLVM2SEHRegisterMapping(this);
58 // Cache some information.
59 Is64Bit = TT.isArch64Bit();
60 IsWin64 = Is64Bit && TT.isOSWindows();
62 // Use a callee-saved register as the base pointer. These registers must
63 // not conflict with any ABI requirements. For example, in 32-bit mode PIC
64 // requires GOT in the EBX register before function calls via PLT GOT pointer.
67 // This matches the simplified 32-bit pointer code in the data layout
69 // FIXME: Should use the data layout?
70 bool Use64BitReg = TT.getEnvironment() != Triple::GNUX32;
71 StackPtr = Use64BitReg ? X86::RSP : X86::ESP;
72 FramePtr = Use64BitReg ? X86::RBP : X86::EBP;
73 BasePtr = Use64BitReg ? X86::RBX : X86::EBX;
83 X86RegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
84 // ExeDepsFixer and PostRAScheduler require liveness.
89 X86RegisterInfo::getSEHRegNum(unsigned i) const {
90 return getEncodingValue(i);
93 const TargetRegisterClass *
94 X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC,
96 // The sub_8bit sub-register index is more constrained in 32-bit mode.
97 // It behaves just like the sub_8bit_hi index.
98 if (!Is64Bit && Idx == X86::sub_8bit)
99 Idx = X86::sub_8bit_hi;
101 // Forward to TableGen's default version.
102 return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
105 const TargetRegisterClass *
106 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
107 const TargetRegisterClass *B,
108 unsigned SubIdx) const {
109 // The sub_8bit sub-register index is more constrained in 32-bit mode.
110 if (!Is64Bit && SubIdx == X86::sub_8bit) {
111 A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi);
115 return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx);
118 const TargetRegisterClass *
119 X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
120 const MachineFunction &MF) const {
121 // Don't allow super-classes of GR8_NOREX. This class is only used after
122 // extracting sub_8bit_hi sub-registers. The H sub-registers cannot be copied
123 // to the full GR8 register class in 64-bit mode, so we cannot allow the
124 // reigster class inflation.
126 // The GR8_NOREX class is always used in a way that won't be constrained to a
127 // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the
129 if (RC == &X86::GR8_NOREXRegClass)
132 const TargetRegisterClass *Super = RC;
133 TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
135 switch (Super->getID()) {
136 case X86::GR8RegClassID:
137 case X86::GR16RegClassID:
138 case X86::GR32RegClassID:
139 case X86::GR64RegClassID:
140 case X86::FR32RegClassID:
141 case X86::FR64RegClassID:
142 case X86::RFP32RegClassID:
143 case X86::RFP64RegClassID:
144 case X86::RFP80RegClassID:
145 case X86::VR128RegClassID:
146 case X86::VR256RegClassID:
147 // Don't return a super-class that would shrink the spill size.
148 // That can happen with the vector and float classes.
149 if (Super->getSize() == RC->getSize())
157 const TargetRegisterClass *
158 X86RegisterInfo::getPointerRegClass(const MachineFunction &MF,
159 unsigned Kind) const {
160 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
162 default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
163 case 0: // Normal GPRs.
164 if (Subtarget.isTarget64BitLP64())
165 return &X86::GR64RegClass;
166 return &X86::GR32RegClass;
167 case 1: // Normal GPRs except the stack pointer (for encoding reasons).
168 if (Subtarget.isTarget64BitLP64())
169 return &X86::GR64_NOSPRegClass;
170 return &X86::GR32_NOSPRegClass;
171 case 2: // NOREX GPRs.
172 if (Subtarget.isTarget64BitLP64())
173 return &X86::GR64_NOREXRegClass;
174 return &X86::GR32_NOREXRegClass;
175 case 3: // NOREX GPRs except the stack pointer (for encoding reasons).
176 if (Subtarget.isTarget64BitLP64())
177 return &X86::GR64_NOREX_NOSPRegClass;
178 return &X86::GR32_NOREX_NOSPRegClass;
179 case 4: // Available for tailcall (not callee-saved GPRs).
180 const Function *F = MF.getFunction();
181 if (IsWin64 || (F && F->getCallingConv() == CallingConv::X86_64_Win64))
182 return &X86::GR64_TCW64RegClass;
184 return &X86::GR64_TCRegClass;
186 bool hasHipeCC = (F ? F->getCallingConv() == CallingConv::HiPE : false);
188 return &X86::GR32RegClass;
189 return &X86::GR32_TCRegClass;
193 const TargetRegisterClass *
194 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
195 if (RC == &X86::CCRRegClass) {
197 return &X86::GR64RegClass;
199 return &X86::GR32RegClass;
205 X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
206 MachineFunction &MF) const {
207 const X86FrameLowering *TFI = getFrameLowering(MF);
209 unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
210 switch (RC->getID()) {
213 case X86::GR32RegClassID:
215 case X86::GR64RegClassID:
217 case X86::VR128RegClassID:
218 return Is64Bit ? 10 : 4;
219 case X86::VR64RegClassID:
225 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
226 const X86Subtarget &Subtarget = MF->getSubtarget<X86Subtarget>();
227 bool HasAVX = Subtarget.hasAVX();
228 bool HasAVX512 = Subtarget.hasAVX512();
229 bool CallsEHReturn = MF->getMMI().callsEHReturn();
231 assert(MF && "MachineFunction required");
232 switch (MF->getFunction()->getCallingConv()) {
233 case CallingConv::GHC:
234 case CallingConv::HiPE:
235 return CSR_NoRegs_SaveList;
236 case CallingConv::AnyReg:
238 return CSR_64_AllRegs_AVX_SaveList;
239 return CSR_64_AllRegs_SaveList;
240 case CallingConv::PreserveMost:
241 return CSR_64_RT_MostRegs_SaveList;
242 case CallingConv::PreserveAll:
244 return CSR_64_RT_AllRegs_AVX_SaveList;
245 return CSR_64_RT_AllRegs_SaveList;
246 case CallingConv::Intel_OCL_BI: {
247 if (HasAVX512 && IsWin64)
248 return CSR_Win64_Intel_OCL_BI_AVX512_SaveList;
249 if (HasAVX512 && Is64Bit)
250 return CSR_64_Intel_OCL_BI_AVX512_SaveList;
251 if (HasAVX && IsWin64)
252 return CSR_Win64_Intel_OCL_BI_AVX_SaveList;
253 if (HasAVX && Is64Bit)
254 return CSR_64_Intel_OCL_BI_AVX_SaveList;
255 if (!HasAVX && !IsWin64 && Is64Bit)
256 return CSR_64_Intel_OCL_BI_SaveList;
259 case CallingConv::HHVM:
260 return CSR_64_HHVM_SaveList;
261 case CallingConv::Cold:
263 return CSR_64_MostRegs_SaveList;
265 case CallingConv::X86_64_Win64:
266 return CSR_Win64_SaveList;
267 case CallingConv::X86_64_SysV:
269 return CSR_64EHRet_SaveList;
270 return CSR_64_SaveList;
277 return CSR_Win64_SaveList;
279 return CSR_64EHRet_SaveList;
280 return CSR_64_SaveList;
283 return CSR_32EHRet_SaveList;
284 return CSR_32_SaveList;
288 X86RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
289 CallingConv::ID CC) const {
290 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
291 bool HasAVX = Subtarget.hasAVX();
292 bool HasAVX512 = Subtarget.hasAVX512();
295 case CallingConv::GHC:
296 case CallingConv::HiPE:
297 return CSR_NoRegs_RegMask;
298 case CallingConv::AnyReg:
300 return CSR_64_AllRegs_AVX_RegMask;
301 return CSR_64_AllRegs_RegMask;
302 case CallingConv::PreserveMost:
303 return CSR_64_RT_MostRegs_RegMask;
304 case CallingConv::PreserveAll:
306 return CSR_64_RT_AllRegs_AVX_RegMask;
307 return CSR_64_RT_AllRegs_RegMask;
308 case CallingConv::Intel_OCL_BI: {
309 if (HasAVX512 && IsWin64)
310 return CSR_Win64_Intel_OCL_BI_AVX512_RegMask;
311 if (HasAVX512 && Is64Bit)
312 return CSR_64_Intel_OCL_BI_AVX512_RegMask;
313 if (HasAVX && IsWin64)
314 return CSR_Win64_Intel_OCL_BI_AVX_RegMask;
315 if (HasAVX && Is64Bit)
316 return CSR_64_Intel_OCL_BI_AVX_RegMask;
317 if (!HasAVX && !IsWin64 && Is64Bit)
318 return CSR_64_Intel_OCL_BI_RegMask;
321 case CallingConv::HHVM:
322 return CSR_64_HHVM_RegMask;
323 case CallingConv::Cold:
325 return CSR_64_MostRegs_RegMask;
329 case CallingConv::X86_64_Win64:
330 return CSR_Win64_RegMask;
331 case CallingConv::X86_64_SysV:
332 return CSR_64_RegMask;
335 // Unlike getCalleeSavedRegs(), we don't have MMI so we can't check
339 return CSR_Win64_RegMask;
340 return CSR_64_RegMask;
342 return CSR_32_RegMask;
346 X86RegisterInfo::getNoPreservedMask() const {
347 return CSR_NoRegs_RegMask;
350 const uint32_t *X86RegisterInfo::getDarwinTLSCallPreservedMask() const {
351 return CSR_64_TLS_Darwin_RegMask;
354 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
355 BitVector Reserved(getNumRegs());
356 const X86FrameLowering *TFI = getFrameLowering(MF);
358 // Set the stack-pointer register and its aliases as reserved.
359 for (MCSubRegIterator I(X86::RSP, this, /*IncludeSelf=*/true); I.isValid();
363 // Set the instruction pointer register and its aliases as reserved.
364 for (MCSubRegIterator I(X86::RIP, this, /*IncludeSelf=*/true); I.isValid();
368 // Set the frame-pointer register and its aliases as reserved if needed.
369 if (TFI->hasFP(MF)) {
370 for (MCSubRegIterator I(X86::RBP, this, /*IncludeSelf=*/true); I.isValid();
375 // Set the base-pointer register and its aliases as reserved if needed.
376 if (hasBasePointer(MF)) {
377 CallingConv::ID CC = MF.getFunction()->getCallingConv();
378 const uint32_t *RegMask = getCallPreservedMask(MF, CC);
379 if (MachineOperand::clobbersPhysReg(RegMask, getBaseRegister()))
381 "Stack realignment in presence of dynamic allocas is not supported with"
382 "this calling convention.");
384 unsigned BasePtr = getX86SubSuperRegister(getBaseRegister(), MVT::i64,
386 for (MCSubRegIterator I(BasePtr, this, /*IncludeSelf=*/true);
391 // Mark the segment registers as reserved.
392 Reserved.set(X86::CS);
393 Reserved.set(X86::SS);
394 Reserved.set(X86::DS);
395 Reserved.set(X86::ES);
396 Reserved.set(X86::FS);
397 Reserved.set(X86::GS);
399 // Mark the floating point stack registers as reserved.
400 for (unsigned n = 0; n != 8; ++n)
401 Reserved.set(X86::ST0 + n);
403 // Reserve the registers that only exist in 64-bit mode.
405 // These 8-bit registers are part of the x86-64 extension even though their
406 // super-registers are old 32-bits.
407 Reserved.set(X86::SIL);
408 Reserved.set(X86::DIL);
409 Reserved.set(X86::BPL);
410 Reserved.set(X86::SPL);
412 for (unsigned n = 0; n != 8; ++n) {
414 for (MCRegAliasIterator AI(X86::R8 + n, this, true); AI.isValid(); ++AI)
418 for (MCRegAliasIterator AI(X86::XMM8 + n, this, true); AI.isValid(); ++AI)
422 if (!Is64Bit || !MF.getSubtarget<X86Subtarget>().hasAVX512()) {
423 for (unsigned n = 16; n != 32; ++n) {
424 for (MCRegAliasIterator AI(X86::XMM0 + n, this, true); AI.isValid(); ++AI)
432 void X86RegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask) const {
433 // Check if the EFLAGS register is marked as live-out. This shouldn't happen,
434 // because the calling convention defines the EFLAGS register as NOT
437 // Unfortunatelly the EFLAGS show up as live-out after branch folding. Adding
438 // an assert to track this and clear the register afterwards to avoid
439 // unnecessary crashes during release builds.
440 assert(!(Mask[X86::EFLAGS / 32] & (1U << (X86::EFLAGS % 32))) &&
441 "EFLAGS are not live-out from a patchpoint.");
443 // Also clean other registers that don't need preserving (IP).
444 for (auto Reg : {X86::EFLAGS, X86::RIP, X86::EIP, X86::IP})
445 Mask[Reg / 32] &= ~(1U << (Reg % 32));
448 //===----------------------------------------------------------------------===//
449 // Stack Frame Processing methods
450 //===----------------------------------------------------------------------===//
452 static bool CantUseSP(const MachineFrameInfo *MFI) {
453 return MFI->hasVarSizedObjects() || MFI->hasOpaqueSPAdjustment();
456 bool X86RegisterInfo::hasBasePointer(const MachineFunction &MF) const {
457 const MachineFrameInfo *MFI = MF.getFrameInfo();
459 if (!EnableBasePointer)
462 // When we need stack realignment, we can't address the stack from the frame
463 // pointer. When we have dynamic allocas or stack-adjusting inline asm, we
464 // can't address variables from the stack pointer. MS inline asm can
465 // reference locals while also adjusting the stack pointer. When we can't
466 // use both the SP and the FP, we need a separate base pointer register.
467 bool CantUseFP = needsStackRealignment(MF);
468 return CantUseFP && CantUseSP(MFI);
471 bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
472 if (!TargetRegisterInfo::canRealignStack(MF))
475 const MachineFrameInfo *MFI = MF.getFrameInfo();
476 const MachineRegisterInfo *MRI = &MF.getRegInfo();
478 // Stack realignment requires a frame pointer. If we already started
479 // register allocation with frame pointer elimination, it is too late now.
480 if (!MRI->canReserveReg(FramePtr))
483 // If a base pointer is necessary. Check that it isn't too late to reserve
486 return MRI->canReserveReg(BasePtr);
490 bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
491 unsigned Reg, int &FrameIdx) const {
492 // Since X86 defines assignCalleeSavedSpillSlots which always return true
493 // this function neither used nor tested.
494 llvm_unreachable("Unused function on X86. Otherwise need a test case.");
498 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
499 int SPAdj, unsigned FIOperandNum,
500 RegScavenger *RS) const {
501 MachineInstr &MI = *II;
502 MachineFunction &MF = *MI.getParent()->getParent();
503 const X86FrameLowering *TFI = getFrameLowering(MF);
504 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
507 unsigned Opc = MI.getOpcode();
508 bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm ||
509 Opc == X86::TCRETURNmi || Opc == X86::TCRETURNmi64;
511 if (hasBasePointer(MF))
512 BasePtr = (FrameIndex < 0 ? FramePtr : getBaseRegister());
513 else if (needsStackRealignment(MF))
514 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
518 BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr);
520 // LOCAL_ESCAPE uses a single offset, with no register. It only works in the
521 // simple FP case, and doesn't work with stack realignment. On 32-bit, the
522 // offset is from the traditional base pointer location. On 64-bit, the
523 // offset is from the SP at the end of the prologue, not the FP location. This
524 // matches the behavior of llvm.frameaddress.
525 unsigned IgnoredFrameReg;
526 if (Opc == TargetOpcode::LOCAL_ESCAPE) {
527 MachineOperand &FI = MI.getOperand(FIOperandNum);
529 Offset = TFI->getFrameIndexReference(MF, FrameIndex, IgnoredFrameReg);
530 FI.ChangeToImmediate(Offset);
534 // For LEA64_32r when BasePtr is 32-bits (X32) we can use full-size 64-bit
535 // register as source operand, semantic is the same and destination is
536 // 32-bits. It saves one byte per lea in code since 0x67 prefix is avoided.
537 if (Opc == X86::LEA64_32r && X86::GR32RegClass.contains(BasePtr))
538 BasePtr = getX86SubSuperRegister(BasePtr, MVT::i64, false);
540 // This must be part of a four operand memory reference. Replace the
541 // FrameIndex with base register with EBP. Add an offset to the offset.
542 MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
544 // Now add the frame object offset to the offset from EBP.
547 // Tail call jmp happens after FP is popped.
548 const MachineFrameInfo *MFI = MF.getFrameInfo();
549 FIOffset = MFI->getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea();
551 FIOffset = TFI->getFrameIndexReference(MF, FrameIndex, IgnoredFrameReg);
553 if (BasePtr == StackPtr)
556 // The frame index format for stackmaps and patchpoints is different from the
557 // X86 format. It only has a FI and an offset.
558 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
559 assert(BasePtr == FramePtr && "Expected the FP as base register");
560 int64_t Offset = MI.getOperand(FIOperandNum + 1).getImm() + FIOffset;
561 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
565 if (MI.getOperand(FIOperandNum+3).isImm()) {
566 // Offset is a 32-bit integer.
567 int Imm = (int)(MI.getOperand(FIOperandNum + 3).getImm());
568 int Offset = FIOffset + Imm;
569 assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
570 "Requesting 64-bit offset in 32-bit immediate!");
571 MI.getOperand(FIOperandNum + 3).ChangeToImmediate(Offset);
573 // Offset is symbolic. This is extremely rare.
574 uint64_t Offset = FIOffset +
575 (uint64_t)MI.getOperand(FIOperandNum+3).getOffset();
576 MI.getOperand(FIOperandNum + 3).setOffset(Offset);
580 unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
581 const X86FrameLowering *TFI = getFrameLowering(MF);
582 return TFI->hasFP(MF) ? FramePtr : StackPtr;
586 X86RegisterInfo::getPtrSizedFrameRegister(const MachineFunction &MF) const {
587 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
588 unsigned FrameReg = getFrameRegister(MF);
589 if (Subtarget.isTarget64BitILP32())
590 FrameReg = getX86SubSuperRegister(FrameReg, MVT::i32, false);
595 unsigned getX86SubSuperRegisterOrZero(unsigned Reg, MVT::SimpleValueType VT,
602 default: return getX86SubSuperRegister(Reg, MVT::i64);
603 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
605 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
607 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
609 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
611 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
613 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
615 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
617 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
623 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
625 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
627 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
629 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
631 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
633 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
635 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
637 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
639 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
641 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
643 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
645 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
647 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
649 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
651 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
653 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
660 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
662 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
664 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
666 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
668 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
670 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
672 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
674 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
676 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
678 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
680 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
682 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
684 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
686 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
688 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
690 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
696 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
698 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
700 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
702 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
704 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
706 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
708 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
710 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
712 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
714 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
716 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
718 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
720 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
722 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
724 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
726 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
732 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
734 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
736 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
738 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
740 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
742 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
744 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
746 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
748 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
750 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
752 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
754 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
756 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
758 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
760 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
762 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
768 unsigned getX86SubSuperRegister(unsigned Reg, MVT::SimpleValueType VT,
770 unsigned Res = getX86SubSuperRegisterOrZero(Reg, VT, High);
772 llvm_unreachable("Unexpected register or VT");
776 unsigned get512BitSuperRegister(unsigned Reg) {
777 if (Reg >= X86::XMM0 && Reg <= X86::XMM31)
778 return X86::ZMM0 + (Reg - X86::XMM0);
779 if (Reg >= X86::YMM0 && Reg <= X86::YMM31)
780 return X86::ZMM0 + (Reg - X86::YMM0);
781 if (Reg >= X86::ZMM0 && Reg <= X86::ZMM31)
783 llvm_unreachable("Unexpected SIMD register");