1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineLocation.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/Target/TargetFrameInfo.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/STLExtras.h"
40 #include "llvm/Support/CommandLine.h"
41 #include "llvm/Support/ErrorHandling.h"
44 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
45 const TargetInstrInfo &tii)
46 : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() ?
47 X86::ADJCALLSTACKDOWN64 :
48 X86::ADJCALLSTACKDOWN32,
49 tm.getSubtarget<X86Subtarget>().is64Bit() ?
50 X86::ADJCALLSTACKUP64 :
51 X86::ADJCALLSTACKUP32),
53 // Cache some information.
54 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
55 Is64Bit = Subtarget->is64Bit();
56 IsWin64 = Subtarget->isTargetWin64();
57 StackAlign = TM.getFrameInfo()->getStackAlignment();
70 /// getDwarfRegNum - This function maps LLVM register identifiers to the DWARF
71 /// specific numbering, used in debug info and exception tables.
72 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
73 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
74 unsigned Flavour = DWARFFlavour::X86_64;
76 if (!Subtarget->is64Bit()) {
77 if (Subtarget->isTargetDarwin()) {
79 Flavour = DWARFFlavour::X86_32_DarwinEH;
81 Flavour = DWARFFlavour::X86_32_Generic;
82 } else if (Subtarget->isTargetCygMing()) {
83 // Unsupported by now, just quick fallback
84 Flavour = DWARFFlavour::X86_32_Generic;
86 Flavour = DWARFFlavour::X86_32_Generic;
90 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
93 /// getX86RegNum - This function maps LLVM register identifiers to their X86
94 /// specific numbering, which is used in various places encoding instructions.
95 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
97 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
98 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
99 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
100 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
101 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
103 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
105 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
107 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
110 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
112 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
114 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
116 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
118 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
120 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
122 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
124 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
127 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
128 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
129 return RegNo-X86::ST0;
131 case X86::XMM0: case X86::XMM8: case X86::MM0:
133 case X86::XMM1: case X86::XMM9: case X86::MM1:
135 case X86::XMM2: case X86::XMM10: case X86::MM2:
137 case X86::XMM3: case X86::XMM11: case X86::MM3:
139 case X86::XMM4: case X86::XMM12: case X86::MM4:
141 case X86::XMM5: case X86::XMM13: case X86::MM5:
143 case X86::XMM6: case X86::XMM14: case X86::MM6:
145 case X86::XMM7: case X86::XMM15: case X86::MM7:
149 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
150 llvm_unreachable("Register allocator hasn't allocated reg correctly yet!");
155 const TargetRegisterClass *
156 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
157 const TargetRegisterClass *B,
158 unsigned SubIdx) const {
163 if (B == &X86::GR8RegClass) {
164 if (A->getSize() == 2 || A->getSize() == 4 || A->getSize() == 8)
166 } else if (B == &X86::GR8_ABCD_LRegClass || B == &X86::GR8_ABCD_HRegClass) {
167 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
168 A == &X86::GR64_NOREXRegClass ||
169 A == &X86::GR64_NOSPRegClass ||
170 A == &X86::GR64_NOREX_NOSPRegClass)
171 return &X86::GR64_ABCDRegClass;
172 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
173 A == &X86::GR32_NOREXRegClass ||
174 A == &X86::GR32_NOSPRegClass)
175 return &X86::GR32_ABCDRegClass;
176 else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
177 A == &X86::GR16_NOREXRegClass)
178 return &X86::GR16_ABCDRegClass;
179 } else if (B == &X86::GR8_NOREXRegClass) {
180 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
181 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
182 return &X86::GR64_NOREXRegClass;
183 else if (A == &X86::GR64_ABCDRegClass)
184 return &X86::GR64_ABCDRegClass;
185 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
186 A == &X86::GR32_NOSPRegClass)
187 return &X86::GR32_NOREXRegClass;
188 else if (A == &X86::GR32_ABCDRegClass)
189 return &X86::GR32_ABCDRegClass;
190 else if (A == &X86::GR16RegClass || A == &X86::GR16_NOREXRegClass)
191 return &X86::GR16_NOREXRegClass;
192 else if (A == &X86::GR16_ABCDRegClass)
193 return &X86::GR16_ABCDRegClass;
198 if (B == &X86::GR8_ABCD_HRegClass) {
199 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
200 A == &X86::GR64_NOREXRegClass ||
201 A == &X86::GR64_NOSPRegClass ||
202 A == &X86::GR64_NOREX_NOSPRegClass)
203 return &X86::GR64_ABCDRegClass;
204 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
205 A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
206 return &X86::GR32_ABCDRegClass;
207 else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
208 A == &X86::GR16_NOREXRegClass)
209 return &X86::GR16_ABCDRegClass;
214 if (B == &X86::GR16RegClass) {
215 if (A->getSize() == 4 || A->getSize() == 8)
217 } else if (B == &X86::GR16_ABCDRegClass) {
218 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
219 A == &X86::GR64_NOREXRegClass ||
220 A == &X86::GR64_NOSPRegClass ||
221 A == &X86::GR64_NOREX_NOSPRegClass)
222 return &X86::GR64_ABCDRegClass;
223 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
224 A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
225 return &X86::GR32_ABCDRegClass;
226 } else if (B == &X86::GR16_NOREXRegClass) {
227 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
228 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
229 return &X86::GR64_NOREXRegClass;
230 else if (A == &X86::GR64_ABCDRegClass)
231 return &X86::GR64_ABCDRegClass;
232 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
233 A == &X86::GR32_NOSPRegClass)
234 return &X86::GR32_NOREXRegClass;
235 else if (A == &X86::GR32_ABCDRegClass)
236 return &X86::GR64_ABCDRegClass;
241 if (B == &X86::GR32RegClass || B == &X86::GR32_NOSPRegClass) {
242 if (A->getSize() == 8)
244 } else if (B == &X86::GR32_ABCDRegClass) {
245 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
246 A == &X86::GR64_NOREXRegClass ||
247 A == &X86::GR64_NOSPRegClass ||
248 A == &X86::GR64_NOREX_NOSPRegClass)
249 return &X86::GR64_ABCDRegClass;
250 } else if (B == &X86::GR32_NOREXRegClass) {
251 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
252 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
253 return &X86::GR64_NOREXRegClass;
254 else if (A == &X86::GR64_ABCDRegClass)
255 return &X86::GR64_ABCDRegClass;
262 const TargetRegisterClass *
263 X86RegisterInfo::getPointerRegClass(unsigned Kind) const {
265 default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
266 case 0: // Normal GPRs.
267 if (TM.getSubtarget<X86Subtarget>().is64Bit())
268 return &X86::GR64RegClass;
269 return &X86::GR32RegClass;
270 case 1: // Normal GRPs except the stack pointer (for encoding reasons).
271 if (TM.getSubtarget<X86Subtarget>().is64Bit())
272 return &X86::GR64_NOSPRegClass;
273 return &X86::GR32_NOSPRegClass;
277 const TargetRegisterClass *
278 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
279 if (RC == &X86::CCRRegClass) {
281 return &X86::GR64RegClass;
283 return &X86::GR32RegClass;
289 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
290 bool callsEHReturn = false;
293 const MachineFrameInfo *MFI = MF->getFrameInfo();
294 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
295 callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
298 static const unsigned CalleeSavedRegs32Bit[] = {
299 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
302 static const unsigned CalleeSavedRegs32EHRet[] = {
303 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
306 static const unsigned CalleeSavedRegs64Bit[] = {
307 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
310 static const unsigned CalleeSavedRegs64EHRet[] = {
311 X86::RAX, X86::RDX, X86::RBX, X86::R12,
312 X86::R13, X86::R14, X86::R15, X86::RBP, 0
315 static const unsigned CalleeSavedRegsWin64[] = {
316 X86::RBX, X86::RBP, X86::RDI, X86::RSI,
317 X86::R12, X86::R13, X86::R14, X86::R15,
318 X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9,
319 X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13,
320 X86::XMM14, X86::XMM15, 0
325 return CalleeSavedRegsWin64;
327 return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit);
329 return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit);
333 const TargetRegisterClass* const*
334 X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
335 bool callsEHReturn = false;
338 const MachineFrameInfo *MFI = MF->getFrameInfo();
339 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
340 callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
343 static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
344 &X86::GR32RegClass, &X86::GR32RegClass,
345 &X86::GR32RegClass, &X86::GR32RegClass, 0
347 static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
348 &X86::GR32RegClass, &X86::GR32RegClass,
349 &X86::GR32RegClass, &X86::GR32RegClass,
350 &X86::GR32RegClass, &X86::GR32RegClass, 0
352 static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
353 &X86::GR64RegClass, &X86::GR64RegClass,
354 &X86::GR64RegClass, &X86::GR64RegClass,
355 &X86::GR64RegClass, &X86::GR64RegClass, 0
357 static const TargetRegisterClass * const CalleeSavedRegClasses64EHRet[] = {
358 &X86::GR64RegClass, &X86::GR64RegClass,
359 &X86::GR64RegClass, &X86::GR64RegClass,
360 &X86::GR64RegClass, &X86::GR64RegClass,
361 &X86::GR64RegClass, &X86::GR64RegClass, 0
363 static const TargetRegisterClass * const CalleeSavedRegClassesWin64[] = {
364 &X86::GR64RegClass, &X86::GR64RegClass,
365 &X86::GR64RegClass, &X86::GR64RegClass,
366 &X86::GR64RegClass, &X86::GR64RegClass,
367 &X86::GR64RegClass, &X86::GR64RegClass,
368 &X86::VR128RegClass, &X86::VR128RegClass,
369 &X86::VR128RegClass, &X86::VR128RegClass,
370 &X86::VR128RegClass, &X86::VR128RegClass,
371 &X86::VR128RegClass, &X86::VR128RegClass,
372 &X86::VR128RegClass, &X86::VR128RegClass, 0
377 return CalleeSavedRegClassesWin64;
379 return (callsEHReturn ?
380 CalleeSavedRegClasses64EHRet : CalleeSavedRegClasses64Bit);
382 return (callsEHReturn ?
383 CalleeSavedRegClasses32EHRet : CalleeSavedRegClasses32Bit);
387 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
388 BitVector Reserved(getNumRegs());
389 // Set the stack-pointer register and its aliases as reserved.
390 Reserved.set(X86::RSP);
391 Reserved.set(X86::ESP);
392 Reserved.set(X86::SP);
393 Reserved.set(X86::SPL);
395 // Set the frame-pointer register and its aliases as reserved if needed.
397 Reserved.set(X86::RBP);
398 Reserved.set(X86::EBP);
399 Reserved.set(X86::BP);
400 Reserved.set(X86::BPL);
403 // Mark the x87 stack registers as reserved, since they don't behave normally
404 // with respect to liveness. We don't fully model the effects of x87 stack
405 // pushes and pops after stackification.
406 Reserved.set(X86::ST0);
407 Reserved.set(X86::ST1);
408 Reserved.set(X86::ST2);
409 Reserved.set(X86::ST3);
410 Reserved.set(X86::ST4);
411 Reserved.set(X86::ST5);
412 Reserved.set(X86::ST6);
413 Reserved.set(X86::ST7);
417 //===----------------------------------------------------------------------===//
418 // Stack Frame Processing methods
419 //===----------------------------------------------------------------------===//
421 static unsigned calculateMaxStackAlignment(const MachineFrameInfo *FFI) {
422 unsigned MaxAlign = 0;
424 for (int i = FFI->getObjectIndexBegin(),
425 e = FFI->getObjectIndexEnd(); i != e; ++i) {
426 if (FFI->isDeadObjectIndex(i))
429 unsigned Align = FFI->getObjectAlignment(i);
430 MaxAlign = std::max(MaxAlign, Align);
436 /// hasFP - Return true if the specified function should have a dedicated frame
437 /// pointer register. This is true if the function has variable sized allocas
438 /// or if frame pointer elimination is disabled.
439 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
440 const MachineFrameInfo *MFI = MF.getFrameInfo();
441 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
443 return (NoFramePointerElim ||
444 needsStackRealignment(MF) ||
445 MFI->hasVarSizedObjects() ||
446 MFI->isFrameAddressTaken() ||
447 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
448 (MMI && MMI->callsUnwindInit()));
451 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
452 const MachineFrameInfo *MFI = MF.getFrameInfo();
453 bool requiresRealignment =
454 RealignStack && (MFI->getMaxAlignment() > StackAlign);
456 // FIXME: Currently we don't support stack realignment for functions with
457 // variable-sized allocas
458 if (requiresRealignment && MFI->hasVarSizedObjects())
460 "Stack realignment in presense of dynamic allocas is not supported");
462 return requiresRealignment;
465 bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
466 return !MF.getFrameInfo()->hasVarSizedObjects();
469 bool X86RegisterInfo::hasReservedSpillSlot(MachineFunction &MF, unsigned Reg,
470 int &FrameIdx) const {
471 if (Reg == FramePtr && hasFP(MF)) {
472 FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
479 X86RegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
480 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
481 MachineFrameInfo *MFI = MF.getFrameInfo();
482 int Offset = MFI->getObjectOffset(FI) - TFI.getOffsetOfLocalArea();
483 uint64_t StackSize = MFI->getStackSize();
485 if (needsStackRealignment(MF)) {
487 // Skip the saved EBP.
490 unsigned Align = MFI->getObjectAlignment(FI);
491 assert( (-(Offset + StackSize)) % Align == 0);
493 return Offset + StackSize;
495 // FIXME: Support tail calls
498 return Offset + StackSize;
500 // Skip the saved EBP.
503 // Skip the RETADDR move area
504 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
505 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
506 if (TailCallReturnAddrDelta < 0)
507 Offset -= TailCallReturnAddrDelta;
513 void X86RegisterInfo::
514 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
515 MachineBasicBlock::iterator I) const {
516 if (!hasReservedCallFrame(MF)) {
517 // If the stack pointer can be changed after prologue, turn the
518 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
519 // adjcallstackdown instruction into 'add ESP, <amt>'
520 // TODO: consider using push / pop instead of sub + store / add
521 MachineInstr *Old = I;
522 uint64_t Amount = Old->getOperand(0).getImm();
524 // We need to keep the stack aligned properly. To do this, we round the
525 // amount of space needed for the outgoing arguments up to the next
526 // alignment boundary.
527 Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
529 MachineInstr *New = 0;
530 if (Old->getOpcode() == getCallFrameSetupOpcode()) {
531 New = BuildMI(MF, Old->getDebugLoc(),
532 TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri),
537 assert(Old->getOpcode() == getCallFrameDestroyOpcode());
539 // Factor out the amount the callee already popped.
540 uint64_t CalleeAmt = Old->getOperand(1).getImm();
544 unsigned Opc = (Amount < 128) ?
545 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
546 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
547 New = BuildMI(MF, Old->getDebugLoc(), TII.get(Opc), StackPtr)
554 // The EFLAGS implicit def is dead.
555 New->getOperand(3).setIsDead();
557 // Replace the pseudo instruction with a new instruction.
561 } else if (I->getOpcode() == getCallFrameDestroyOpcode()) {
562 // If we are performing frame pointer elimination and if the callee pops
563 // something off the stack pointer, add it back. We do this until we have
564 // more advanced stack pointer tracking ability.
565 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
566 unsigned Opc = (CalleeAmt < 128) ?
567 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
568 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
569 MachineInstr *Old = I;
571 BuildMI(MF, Old->getDebugLoc(), TII.get(Opc),
576 // The EFLAGS implicit def is dead.
577 New->getOperand(3).setIsDead();
586 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
587 int SPAdj, int *Value,
588 RegScavenger *RS) const{
589 assert(SPAdj == 0 && "Unexpected");
592 MachineInstr &MI = *II;
593 MachineFunction &MF = *MI.getParent()->getParent();
595 while (!MI.getOperand(i).isFI()) {
597 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
600 int FrameIndex = MI.getOperand(i).getIndex();
603 if (needsStackRealignment(MF))
604 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
606 BasePtr = (hasFP(MF) ? FramePtr : StackPtr);
608 // This must be part of a four operand memory reference. Replace the
609 // FrameIndex with base register with EBP. Add an offset to the offset.
610 MI.getOperand(i).ChangeToRegister(BasePtr, false);
612 // Now add the frame object offset to the offset from EBP.
613 if (MI.getOperand(i+3).isImm()) {
614 // Offset is a 32-bit integer.
615 int Offset = getFrameIndexOffset(MF, FrameIndex) +
616 (int)(MI.getOperand(i + 3).getImm());
618 MI.getOperand(i + 3).ChangeToImmediate(Offset);
620 // Offset is symbolic. This is extremely rare.
621 uint64_t Offset = getFrameIndexOffset(MF, FrameIndex) +
622 (uint64_t)MI.getOperand(i+3).getOffset();
623 MI.getOperand(i+3).setOffset(Offset);
629 X86RegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
630 RegScavenger *RS) const {
631 MachineFrameInfo *MFI = MF.getFrameInfo();
633 // Calculate and set max stack object alignment early, so we can decide
634 // whether we will need stack realignment (and thus FP).
635 unsigned MaxAlign = std::max(MFI->getMaxAlignment(),
636 calculateMaxStackAlignment(MFI));
638 MFI->setMaxAlignment(MaxAlign);
640 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
641 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
643 if (TailCallReturnAddrDelta < 0) {
644 // create RETURNADDR area
653 MFI->CreateFixedObject(-TailCallReturnAddrDelta,
654 (-1U*SlotSize)+TailCallReturnAddrDelta);
658 assert((TailCallReturnAddrDelta <= 0) &&
659 "The Delta should always be zero or negative");
660 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
662 // Create a frame entry for the EBP register that must be saved.
663 int FrameIdx = MFI->CreateFixedObject(SlotSize,
665 TFI.getOffsetOfLocalArea() +
666 TailCallReturnAddrDelta);
667 assert(FrameIdx == MFI->getObjectIndexBegin() &&
668 "Slot for EBP register must be last in order to be found!");
673 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
674 /// stack pointer by a constant value.
676 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
677 unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
678 const TargetInstrInfo &TII) {
679 bool isSub = NumBytes < 0;
680 uint64_t Offset = isSub ? -NumBytes : NumBytes;
683 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
684 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
686 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
687 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
688 uint64_t Chunk = (1LL << 31) - 1;
689 DebugLoc DL = (MBBI != MBB.end() ? MBBI->getDebugLoc() :
690 DebugLoc::getUnknownLoc());
693 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
695 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
698 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
703 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
705 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
706 unsigned StackPtr, uint64_t *NumBytes = NULL) {
707 if (MBBI == MBB.begin()) return;
709 MachineBasicBlock::iterator PI = prior(MBBI);
710 unsigned Opc = PI->getOpcode();
711 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
712 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
713 PI->getOperand(0).getReg() == StackPtr) {
715 *NumBytes += PI->getOperand(2).getImm();
717 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
718 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
719 PI->getOperand(0).getReg() == StackPtr) {
721 *NumBytes -= PI->getOperand(2).getImm();
726 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
728 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
729 MachineBasicBlock::iterator &MBBI,
730 unsigned StackPtr, uint64_t *NumBytes = NULL) {
731 // FIXME: THIS ISN'T RUN!!!
734 if (MBBI == MBB.end()) return;
736 MachineBasicBlock::iterator NI = next(MBBI);
737 if (NI == MBB.end()) return;
739 unsigned Opc = NI->getOpcode();
740 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
741 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
742 NI->getOperand(0).getReg() == StackPtr) {
744 *NumBytes -= NI->getOperand(2).getImm();
747 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
748 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
749 NI->getOperand(0).getReg() == StackPtr) {
751 *NumBytes += NI->getOperand(2).getImm();
757 /// mergeSPUpdates - Checks the instruction before/after the passed
758 /// instruction. If it is an ADD/SUB instruction it is deleted argument and the
759 /// stack adjustment is returned as a positive value for ADD and a negative for
761 static int mergeSPUpdates(MachineBasicBlock &MBB,
762 MachineBasicBlock::iterator &MBBI,
764 bool doMergeWithPrevious) {
765 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
766 (!doMergeWithPrevious && MBBI == MBB.end()))
769 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
770 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : next(MBBI);
771 unsigned Opc = PI->getOpcode();
774 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
775 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
776 PI->getOperand(0).getReg() == StackPtr){
777 Offset += PI->getOperand(2).getImm();
779 if (!doMergeWithPrevious) MBBI = NI;
780 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
781 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
782 PI->getOperand(0).getReg() == StackPtr) {
783 Offset -= PI->getOperand(2).getImm();
785 if (!doMergeWithPrevious) MBBI = NI;
791 void X86RegisterInfo::emitCalleeSavedFrameMoves(MachineFunction &MF,
793 unsigned FramePtr) const {
794 MachineFrameInfo *MFI = MF.getFrameInfo();
795 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
798 // Add callee saved registers to move list.
799 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
800 if (CSI.empty()) return;
802 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
803 const TargetData *TD = MF.getTarget().getTargetData();
804 bool HasFP = hasFP(MF);
806 // Calculate amount of bytes used for return address storing.
808 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
809 TargetFrameInfo::StackGrowsUp ?
810 TD->getPointerSize() : -TD->getPointerSize());
812 // FIXME: This is dirty hack. The code itself is pretty mess right now.
813 // It should be rewritten from scratch and generalized sometimes.
815 // Determine maximum offset (minumum due to stack growth).
816 int64_t MaxOffset = 0;
817 for (std::vector<CalleeSavedInfo>::const_iterator
818 I = CSI.begin(), E = CSI.end(); I != E; ++I)
819 MaxOffset = std::min(MaxOffset,
820 MFI->getObjectOffset(I->getFrameIdx()));
822 // Calculate offsets.
823 int64_t saveAreaOffset = (HasFP ? 3 : 2) * stackGrowth;
824 for (std::vector<CalleeSavedInfo>::const_iterator
825 I = CSI.begin(), E = CSI.end(); I != E; ++I) {
826 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
827 unsigned Reg = I->getReg();
828 Offset = MaxOffset - Offset + saveAreaOffset;
830 // Don't output a new machine move if we're re-saving the frame
831 // pointer. This happens when the PrologEpilogInserter has inserted an extra
832 // "PUSH" of the frame pointer -- the "emitPrologue" method automatically
833 // generates one when frame pointers are used. If we generate a "machine
834 // move" for this extra "PUSH", the linker will lose track of the fact that
835 // the frame pointer should have the value of the first "PUSH" when it's
838 // FIXME: This looks inelegant. It's possibly correct, but it's covering up
839 // another bug. I.e., one where we generate a prolog like this:
847 // The immediate re-push of EBP is unnecessary. At the least, it's an
848 // optimization bug. EBP can be used as a scratch register in certain
849 // cases, but probably not when we have a frame pointer.
850 if (HasFP && FramePtr == Reg)
853 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
854 MachineLocation CSSrc(Reg);
855 Moves.push_back(MachineMove(LabelId, CSDst, CSSrc));
859 /// emitPrologue - Push callee-saved registers onto the stack, which
860 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate
861 /// space for local variables. Also emit labels used by the exception handler to
862 /// generate the exception handling frames.
863 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
864 MachineBasicBlock &MBB = MF.front(); // Prologue goes in entry BB.
865 MachineBasicBlock::iterator MBBI = MBB.begin();
866 MachineFrameInfo *MFI = MF.getFrameInfo();
867 const Function *Fn = MF.getFunction();
868 const X86Subtarget *Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
869 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
870 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
871 bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
872 !Fn->doesNotThrow() || UnwindTablesMandatory;
873 uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment.
874 uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate.
875 bool HasFP = hasFP(MF);
878 // Add RETADDR move area to callee saved frame size.
879 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
880 if (TailCallReturnAddrDelta < 0)
881 X86FI->setCalleeSavedFrameSize(
882 X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
884 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
885 // function, and use up to 128 bytes of stack space, don't have a frame
886 // pointer, calls, or dynamic alloca then we do not need to adjust the
887 // stack pointer (we fit in the Red Zone).
888 if (Is64Bit && !Fn->hasFnAttr(Attribute::NoRedZone) &&
889 !needsStackRealignment(MF) &&
890 !MFI->hasVarSizedObjects() && // No dynamic alloca.
891 !MFI->hasCalls() && // No calls.
892 !Subtarget->isTargetWin64()) { // Win64 has no Red Zone
893 uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
894 if (HasFP) MinSize += SlotSize;
895 StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
896 MFI->setStackSize(StackSize);
897 } else if (Subtarget->isTargetWin64()) {
898 // We need to always allocate 32 bytes as register spill area.
899 // FIXME: We might reuse these 32 bytes for leaf functions.
901 MFI->setStackSize(StackSize);
904 // Insert stack pointer adjustment for later moving of return addr. Only
905 // applies to tail call optimized functions where the callee argument stack
906 // size is bigger than the callers.
907 if (TailCallReturnAddrDelta < 0) {
909 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri),
912 .addImm(-TailCallReturnAddrDelta);
913 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
916 // Mapping for machine moves:
918 // DST: VirtualFP AND
919 // SRC: VirtualFP => DW_CFA_def_cfa_offset
920 // ELSE => DW_CFA_def_cfa
922 // SRC: VirtualFP AND
923 // DST: Register => DW_CFA_def_cfa_register
926 // OFFSET < 0 => DW_CFA_offset_extended_sf
927 // REG < 64 => DW_CFA_offset + Reg
928 // ELSE => DW_CFA_offset_extended
930 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
931 const TargetData *TD = MF.getTarget().getTargetData();
932 uint64_t NumBytes = 0;
934 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
935 TargetFrameInfo::StackGrowsUp ?
936 TD->getPointerSize() : -TD->getPointerSize());
939 // Calculate required stack adjustment.
940 uint64_t FrameSize = StackSize - SlotSize;
941 if (needsStackRealignment(MF))
942 FrameSize = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
944 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
946 // Get the offset of the stack slot for the EBP register, which is
947 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
948 // Update the frame offset adjustment.
949 MFI->setOffsetAdjustment(-NumBytes);
951 // Save EBP/RBP into the appropriate stack slot.
952 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
953 .addReg(FramePtr, RegState::Kill);
955 if (needsFrameMoves) {
956 // Mark the place where EBP/RBP was saved.
957 unsigned FrameLabelId = MMI->NextLabelID();
958 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId);
960 // Define the current CFA rule to use the provided offset.
962 MachineLocation SPDst(MachineLocation::VirtualFP);
963 MachineLocation SPSrc(MachineLocation::VirtualFP, 2 * stackGrowth);
964 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
966 // FIXME: Verify & implement for FP
967 MachineLocation SPDst(StackPtr);
968 MachineLocation SPSrc(StackPtr, stackGrowth);
969 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
972 // Change the rule for the FramePtr to be an "offset" rule.
973 MachineLocation FPDst(MachineLocation::VirtualFP,
975 MachineLocation FPSrc(FramePtr);
976 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
979 // Update EBP with the new base value...
980 BuildMI(MBB, MBBI, DL,
981 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
984 if (needsFrameMoves) {
985 // Mark effective beginning of when frame pointer becomes valid.
986 unsigned FrameLabelId = MMI->NextLabelID();
987 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId);
989 // Define the current CFA to use the EBP/RBP register.
990 MachineLocation FPDst(FramePtr);
991 MachineLocation FPSrc(MachineLocation::VirtualFP);
992 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
995 // Mark the FramePtr as live-in in every block except the entry.
996 for (MachineFunction::iterator I = next(MF.begin()), E = MF.end();
998 I->addLiveIn(FramePtr);
1001 if (needsStackRealignment(MF)) {
1003 BuildMI(MBB, MBBI, DL,
1004 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri),
1005 StackPtr).addReg(StackPtr).addImm(-MaxAlign);
1007 // The EFLAGS implicit def is dead.
1008 MI->getOperand(3).setIsDead();
1011 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
1014 // Skip the callee-saved push instructions.
1015 bool PushedRegs = false;
1016 int StackOffset = 2 * stackGrowth;
1018 while (MBBI != MBB.end() &&
1019 (MBBI->getOpcode() == X86::PUSH32r ||
1020 MBBI->getOpcode() == X86::PUSH64r)) {
1024 if (!HasFP && needsFrameMoves) {
1025 // Mark callee-saved push instruction.
1026 unsigned LabelId = MMI->NextLabelID();
1027 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(LabelId);
1029 // Define the current CFA rule to use the provided offset.
1030 unsigned Ptr = StackSize ?
1031 MachineLocation::VirtualFP : StackPtr;
1032 MachineLocation SPDst(Ptr);
1033 MachineLocation SPSrc(Ptr, StackOffset);
1034 Moves.push_back(MachineMove(LabelId, SPDst, SPSrc));
1035 StackOffset += stackGrowth;
1039 if (MBBI != MBB.end())
1040 DL = MBBI->getDebugLoc();
1042 // Adjust stack pointer: ESP -= numbytes.
1043 if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
1044 // Check, whether EAX is livein for this function.
1045 bool isEAXAlive = false;
1046 for (MachineRegisterInfo::livein_iterator
1047 II = MF.getRegInfo().livein_begin(),
1048 EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
1049 unsigned Reg = II->first;
1050 isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
1051 Reg == X86::AH || Reg == X86::AL);
1054 // Function prologue calls _alloca to probe the stack when allocating more
1055 // than 4k bytes in one go. Touching the stack at 4K increments is necessary
1056 // to ensure that the guard pages used by the OS virtual memory manager are
1057 // allocated in correct sequence.
1059 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1061 BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
1062 .addExternalSymbol("_alloca");
1065 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
1066 .addReg(X86::EAX, RegState::Kill);
1068 // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
1069 // allocated bytes for EAX.
1070 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1071 .addImm(NumBytes - 4);
1072 BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
1073 .addExternalSymbol("_alloca");
1076 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
1078 StackPtr, false, NumBytes - 4);
1079 MBB.insert(MBBI, MI);
1081 } else if (NumBytes) {
1082 // If there is an SUB32ri of ESP immediately before this instruction, merge
1083 // the two. This can be the case when tail call elimination is enabled and
1084 // the callee has more arguments then the caller.
1085 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
1087 // If there is an ADD32ri or SUB32ri of ESP immediately after this
1088 // instruction, merge the two instructions.
1089 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
1092 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
1095 if ((NumBytes || PushedRegs) && needsFrameMoves) {
1096 // Mark end of stack pointer adjustment.
1097 unsigned LabelId = MMI->NextLabelID();
1098 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(LabelId);
1100 if (!HasFP && NumBytes) {
1101 // Define the current CFA rule to use the provided offset.
1103 MachineLocation SPDst(MachineLocation::VirtualFP);
1104 MachineLocation SPSrc(MachineLocation::VirtualFP,
1105 -StackSize + stackGrowth);
1106 Moves.push_back(MachineMove(LabelId, SPDst, SPSrc));
1108 // FIXME: Verify & implement for FP
1109 MachineLocation SPDst(StackPtr);
1110 MachineLocation SPSrc(StackPtr, stackGrowth);
1111 Moves.push_back(MachineMove(LabelId, SPDst, SPSrc));
1115 // Emit DWARF info specifying the offsets of the callee-saved registers.
1117 emitCalleeSavedFrameMoves(MF, LabelId, HasFP ? FramePtr : StackPtr);
1121 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
1122 MachineBasicBlock &MBB) const {
1123 const MachineFrameInfo *MFI = MF.getFrameInfo();
1124 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1125 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1126 unsigned RetOpcode = MBBI->getOpcode();
1127 DebugLoc DL = MBBI->getDebugLoc();
1129 switch (RetOpcode) {
1131 llvm_unreachable("Can only insert epilog into returning blocks");
1134 case X86::TCRETURNdi:
1135 case X86::TCRETURNri:
1136 case X86::TCRETURNri64:
1137 case X86::TCRETURNdi64:
1138 case X86::EH_RETURN:
1139 case X86::EH_RETURN64:
1143 break; // These are ok
1146 // Get the number of bytes to allocate from the FrameInfo.
1147 uint64_t StackSize = MFI->getStackSize();
1148 uint64_t MaxAlign = MFI->getMaxAlignment();
1149 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1150 uint64_t NumBytes = 0;
1153 // Calculate required stack adjustment.
1154 uint64_t FrameSize = StackSize - SlotSize;
1155 if (needsStackRealignment(MF))
1156 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
1158 NumBytes = FrameSize - CSSize;
1161 BuildMI(MBB, MBBI, DL,
1162 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
1164 NumBytes = StackSize - CSSize;
1167 // Skip the callee-saved pop instructions.
1168 MachineBasicBlock::iterator LastCSPop = MBBI;
1169 while (MBBI != MBB.begin()) {
1170 MachineBasicBlock::iterator PI = prior(MBBI);
1171 unsigned Opc = PI->getOpcode();
1173 if (Opc != X86::POP32r && Opc != X86::POP64r &&
1174 !PI->getDesc().isTerminator())
1180 DL = MBBI->getDebugLoc();
1182 // If there is an ADD32ri or SUB32ri of ESP immediately before this
1183 // instruction, merge the two instructions.
1184 if (NumBytes || MFI->hasVarSizedObjects())
1185 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
1187 // If dynamic alloca is used, then reset esp to point to the last callee-saved
1188 // slot before popping them off! Same applies for the case, when stack was
1190 if (needsStackRealignment(MF)) {
1191 // We cannot use LEA here, because stack pointer was realigned. We need to
1192 // deallocate local frame back.
1194 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1195 MBBI = prior(LastCSPop);
1198 BuildMI(MBB, MBBI, DL,
1199 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1200 StackPtr).addReg(FramePtr);
1201 } else if (MFI->hasVarSizedObjects()) {
1203 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
1205 addLeaRegOffset(BuildMI(MF, DL, TII.get(Opc), StackPtr),
1206 FramePtr, false, -CSSize);
1207 MBB.insert(MBBI, MI);
1209 BuildMI(MBB, MBBI, DL,
1210 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), StackPtr)
1213 } else if (NumBytes) {
1214 // Adjust stack pointer back: ESP += numbytes.
1215 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1218 // We're returning from function via eh_return.
1219 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
1220 MBBI = prior(MBB.end());
1221 MachineOperand &DestAddr = MBBI->getOperand(0);
1222 assert(DestAddr.isReg() && "Offset should be in register!");
1223 BuildMI(MBB, MBBI, DL,
1224 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1225 StackPtr).addReg(DestAddr.getReg());
1226 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
1227 RetOpcode== X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64) {
1228 // Tail call return: adjust the stack pointer and jump to callee.
1229 MBBI = prior(MBB.end());
1230 MachineOperand &JumpTarget = MBBI->getOperand(0);
1231 MachineOperand &StackAdjust = MBBI->getOperand(1);
1232 assert(StackAdjust.isImm() && "Expecting immediate value.");
1234 // Adjust stack pointer.
1235 int StackAdj = StackAdjust.getImm();
1236 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
1238 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
1240 // Incoporate the retaddr area.
1241 Offset = StackAdj-MaxTCDelta;
1242 assert(Offset >= 0 && "Offset should never be negative");
1245 // Check for possible merge with preceeding ADD instruction.
1246 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1247 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
1250 // Jump to label or value in register.
1251 if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64)
1252 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPd)).
1253 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1254 else if (RetOpcode== X86::TCRETURNri64)
1255 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
1257 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr), JumpTarget.getReg());
1259 // Delete the pseudo instruction TCRETURN.
1261 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
1262 (X86FI->getTCReturnAddrDelta() < 0)) {
1263 // Add the return addr area delta back since we are not tail calling.
1264 int delta = -1*X86FI->getTCReturnAddrDelta();
1265 MBBI = prior(MBB.end());
1267 // Check for possible merge with preceeding ADD instruction.
1268 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1269 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
1273 unsigned X86RegisterInfo::getRARegister() const {
1274 return Is64Bit ? X86::RIP // Should have dwarf #16.
1275 : X86::EIP; // Should have dwarf #8.
1278 unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
1279 return hasFP(MF) ? FramePtr : StackPtr;
1283 X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const {
1284 // Calculate amount of bytes used for return address storing
1285 int stackGrowth = (Is64Bit ? -8 : -4);
1287 // Initial state of the frame pointer is esp+4.
1288 MachineLocation Dst(MachineLocation::VirtualFP);
1289 MachineLocation Src(StackPtr, stackGrowth);
1290 Moves.push_back(MachineMove(0, Dst, Src));
1292 // Add return address to move list
1293 MachineLocation CSDst(StackPtr, stackGrowth);
1294 MachineLocation CSSrc(getRARegister());
1295 Moves.push_back(MachineMove(0, CSDst, CSSrc));
1298 unsigned X86RegisterInfo::getEHExceptionRegister() const {
1299 llvm_unreachable("What is the exception register");
1303 unsigned X86RegisterInfo::getEHHandlerRegister() const {
1304 llvm_unreachable("What is the exception handler register");
1309 unsigned getX86SubSuperRegister(unsigned Reg, EVT VT, bool High) {
1310 switch (VT.getSimpleVT().SimpleTy) {
1311 default: return Reg;
1316 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1318 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1320 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1322 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1328 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1330 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1332 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1334 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1336 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1338 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1340 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1342 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1344 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1346 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1348 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1350 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1352 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1354 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1356 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1358 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1364 default: return Reg;
1365 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1367 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1369 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1371 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1373 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1375 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1377 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1379 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1381 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1383 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1385 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1387 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1389 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1391 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1393 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1395 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1400 default: return Reg;
1401 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1403 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1405 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1407 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1409 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1411 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1413 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1415 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1417 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1419 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1421 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1423 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1425 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1427 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1429 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1431 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1436 default: return Reg;
1437 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1439 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1441 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1443 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1445 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1447 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1449 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1451 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1453 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1455 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1457 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1459 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1461 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1463 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1465 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1467 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1476 #include "X86GenRegisterInfo.inc"
1479 struct MSAC : public MachineFunctionPass {
1481 MSAC() : MachineFunctionPass(&ID) {}
1483 virtual bool runOnMachineFunction(MachineFunction &MF) {
1484 MachineFrameInfo *FFI = MF.getFrameInfo();
1485 MachineRegisterInfo &RI = MF.getRegInfo();
1487 // Calculate max stack alignment of all already allocated stack objects.
1488 unsigned MaxAlign = calculateMaxStackAlignment(FFI);
1490 // Be over-conservative: scan over all vreg defs and find, whether vector
1491 // registers are used. If yes - there is probability, that vector register
1492 // will be spilled and thus stack needs to be aligned properly.
1493 for (unsigned RegNum = TargetRegisterInfo::FirstVirtualRegister;
1494 RegNum < RI.getLastVirtReg(); ++RegNum)
1495 MaxAlign = std::max(MaxAlign, RI.getRegClass(RegNum)->getAlignment());
1497 if (FFI->getMaxAlignment() == MaxAlign)
1500 FFI->setMaxAlignment(MaxAlign);
1504 virtual const char *getPassName() const {
1505 return "X86 Maximal Stack Alignment Calculator";
1508 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
1509 AU.setPreservesCFG();
1510 MachineFunctionPass::getAnalysisUsage(AU);
1518 llvm::createX86MaxStackAlignmentCalculatorPass() { return new MSAC(); }