1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the MRegisterInfo class. This
11 // file is responsible for the frame pointer elimination optimization on X86.
13 //===----------------------------------------------------------------------===//
16 #include "X86RegisterInfo.h"
17 #include "X86InstrBuilder.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/Type.h"
24 #include "llvm/CodeGen/ValueTypes.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineLocation.h"
29 #include "llvm/CodeGen/MachineModuleInfo.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/Target/TargetAsmInfo.h"
32 #include "llvm/Target/TargetFrameInfo.h"
33 #include "llvm/Target/TargetInstrInfo.h"
34 #include "llvm/Target/TargetMachine.h"
35 #include "llvm/Target/TargetOptions.h"
36 #include "llvm/ADT/BitVector.h"
37 #include "llvm/ADT/STLExtras.h"
40 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
41 const TargetInstrInfo &tii)
42 : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP),
44 // Cache some information.
45 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
46 Is64Bit = Subtarget->is64Bit();
47 StackAlign = TM.getFrameInfo()->getStackAlignment();
59 // getDwarfRegNum - This function maps LLVM register identifiers to the
60 // Dwarf specific numbering, used in debug info and exception tables.
62 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
63 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
64 unsigned Flavour = DWARFFlavour::X86_64;
65 if (!Subtarget->is64Bit()) {
66 if (Subtarget->isTargetDarwin()) {
67 Flavour = DWARFFlavour::X86_32_Darwin;
68 } else if (Subtarget->isTargetCygMing()) {
69 // Unsupported by now, just quick fallback
70 Flavour = DWARFFlavour::X86_32_ELF;
72 Flavour = DWARFFlavour::X86_32_ELF;
76 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
79 // getX86RegNum - This function maps LLVM register identifiers to their X86
80 // specific numbering, which is used in various places encoding instructions.
82 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
84 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
85 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
86 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
87 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
88 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
90 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
92 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
94 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
97 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
99 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
101 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
103 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
105 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
107 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
109 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
111 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
114 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
115 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
116 return RegNo-X86::ST0;
118 case X86::XMM0: case X86::XMM8: case X86::MM0:
120 case X86::XMM1: case X86::XMM9: case X86::MM1:
122 case X86::XMM2: case X86::XMM10: case X86::MM2:
124 case X86::XMM3: case X86::XMM11: case X86::MM3:
126 case X86::XMM4: case X86::XMM12: case X86::MM4:
128 case X86::XMM5: case X86::XMM13: case X86::MM5:
130 case X86::XMM6: case X86::XMM14: case X86::MM6:
132 case X86::XMM7: case X86::XMM15: case X86::MM7:
136 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
137 assert(0 && "Register allocator hasn't allocated reg correctly yet!");
142 const TargetRegisterClass *
143 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
144 if (RC == &X86::CCRRegClass)
146 return &X86::GR64RegClass;
148 return &X86::GR32RegClass;
152 void X86RegisterInfo::reMaterialize(MachineBasicBlock &MBB,
153 MachineBasicBlock::iterator I,
155 const MachineInstr *Orig) const {
156 // MOV32r0 etc. are implemented with xor which clobbers condition code.
157 // Re-materialize them as movri instructions to avoid side effects.
158 switch (Orig->getOpcode()) {
160 BuildMI(MBB, I, TII.get(X86::MOV8ri), DestReg).addImm(0);
163 BuildMI(MBB, I, TII.get(X86::MOV16ri), DestReg).addImm(0);
166 BuildMI(MBB, I, TII.get(X86::MOV32ri), DestReg).addImm(0);
169 BuildMI(MBB, I, TII.get(X86::MOV64ri32), DestReg).addImm(0);
172 MachineInstr *MI = Orig->clone();
173 MI->getOperand(0).setReg(DestReg);
181 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
182 static const unsigned CalleeSavedRegs32Bit[] = {
183 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
186 static const unsigned CalleeSavedRegs32EHRet[] = {
187 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
190 static const unsigned CalleeSavedRegs64Bit[] = {
191 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
195 return CalleeSavedRegs64Bit;
198 MachineFrameInfo *MFI = MF->getFrameInfo();
199 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
200 if (MMI && MMI->callsEHReturn())
201 return CalleeSavedRegs32EHRet;
203 return CalleeSavedRegs32Bit;
207 const TargetRegisterClass* const*
208 X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
209 static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
210 &X86::GR32RegClass, &X86::GR32RegClass,
211 &X86::GR32RegClass, &X86::GR32RegClass, 0
213 static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
214 &X86::GR32RegClass, &X86::GR32RegClass,
215 &X86::GR32RegClass, &X86::GR32RegClass,
216 &X86::GR32RegClass, &X86::GR32RegClass, 0
218 static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
219 &X86::GR64RegClass, &X86::GR64RegClass,
220 &X86::GR64RegClass, &X86::GR64RegClass,
221 &X86::GR64RegClass, &X86::GR64RegClass, 0
225 return CalleeSavedRegClasses64Bit;
228 MachineFrameInfo *MFI = MF->getFrameInfo();
229 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
230 if (MMI && MMI->callsEHReturn())
231 return CalleeSavedRegClasses32EHRet;
233 return CalleeSavedRegClasses32Bit;
238 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
239 BitVector Reserved(getNumRegs());
240 Reserved.set(X86::RSP);
241 Reserved.set(X86::ESP);
242 Reserved.set(X86::SP);
243 Reserved.set(X86::SPL);
245 Reserved.set(X86::RBP);
246 Reserved.set(X86::EBP);
247 Reserved.set(X86::BP);
248 Reserved.set(X86::BPL);
253 //===----------------------------------------------------------------------===//
254 // Stack Frame Processing methods
255 //===----------------------------------------------------------------------===//
257 // hasFP - Return true if the specified function should have a dedicated frame
258 // pointer register. This is true if the function has variable sized allocas or
259 // if frame pointer elimination is disabled.
261 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
262 MachineFrameInfo *MFI = MF.getFrameInfo();
263 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
265 return (NoFramePointerElim ||
266 MFI->hasVarSizedObjects() ||
267 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
268 (MMI && MMI->callsUnwindInit()));
271 bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
272 return !MF.getFrameInfo()->hasVarSizedObjects();
275 void X86RegisterInfo::
276 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
277 MachineBasicBlock::iterator I) const {
278 if (!hasReservedCallFrame(MF)) {
279 // If the stack pointer can be changed after prologue, turn the
280 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
281 // adjcallstackdown instruction into 'add ESP, <amt>'
282 // TODO: consider using push / pop instead of sub + store / add
283 MachineInstr *Old = I;
284 uint64_t Amount = Old->getOperand(0).getImm();
286 // We need to keep the stack aligned properly. To do this, we round the
287 // amount of space needed for the outgoing arguments up to the next
288 // alignment boundary.
289 Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
291 MachineInstr *New = 0;
292 if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
293 New=BuildMI(TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri), StackPtr)
294 .addReg(StackPtr).addImm(Amount);
296 assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
297 // factor out the amount the callee already popped.
298 uint64_t CalleeAmt = Old->getOperand(1).getImm();
301 unsigned Opc = (Amount < 128) ?
302 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
303 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
304 New = BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(Amount);
308 // Replace the pseudo instruction with a new instruction...
309 if (New) MBB.insert(I, New);
311 } else if (I->getOpcode() == X86::ADJCALLSTACKUP) {
312 // If we are performing frame pointer elimination and if the callee pops
313 // something off the stack pointer, add it back. We do this until we have
314 // more advanced stack pointer tracking ability.
315 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
316 unsigned Opc = (CalleeAmt < 128) ?
317 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
318 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
320 BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(CalleeAmt);
328 void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
329 int SPAdj, RegScavenger *RS) const{
330 assert(SPAdj == 0 && "Unexpected");
333 MachineInstr &MI = *II;
334 MachineFunction &MF = *MI.getParent()->getParent();
335 while (!MI.getOperand(i).isFrameIndex()) {
337 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
340 int FrameIndex = MI.getOperand(i).getIndex();
341 // This must be part of a four operand memory reference. Replace the
342 // FrameIndex with base register with EBP. Add an offset to the offset.
343 MI.getOperand(i).ChangeToRegister(hasFP(MF) ? FramePtr : StackPtr, false);
345 // Now add the frame object offset to the offset from EBP.
346 int64_t Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
347 MI.getOperand(i+3).getImm()+SlotSize;
350 Offset += MF.getFrameInfo()->getStackSize();
352 Offset += SlotSize; // Skip the saved EBP
353 // Skip the RETADDR move area
354 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
355 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
356 if (TailCallReturnAddrDelta < 0) Offset -= TailCallReturnAddrDelta;
359 MI.getOperand(i+3).ChangeToImmediate(Offset);
363 X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
364 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
365 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
366 if (TailCallReturnAddrDelta < 0) {
367 // create RETURNADDR area
377 CreateFixedObject(-TailCallReturnAddrDelta,
378 (-1*SlotSize)+TailCallReturnAddrDelta);
381 assert((TailCallReturnAddrDelta <= 0) &&
382 "The Delta should always be zero or negative");
383 // Create a frame entry for the EBP register that must be saved.
384 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize,
386 TailCallReturnAddrDelta);
387 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
388 "Slot for EBP register must be last in order to be found!");
392 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
393 /// stack pointer by a constant value.
395 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
396 unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
397 const TargetInstrInfo &TII) {
398 bool isSub = NumBytes < 0;
399 uint64_t Offset = isSub ? -NumBytes : NumBytes;
402 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
403 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
405 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
406 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
407 uint64_t Chunk = (1LL << 31) - 1;
410 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
411 BuildMI(MBB, MBBI, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(ThisVal);
416 // mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
418 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
419 unsigned StackPtr, uint64_t *NumBytes = NULL) {
420 if (MBBI == MBB.begin()) return;
422 MachineBasicBlock::iterator PI = prior(MBBI);
423 unsigned Opc = PI->getOpcode();
424 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
425 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
426 PI->getOperand(0).getReg() == StackPtr) {
428 *NumBytes += PI->getOperand(2).getImm();
430 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
431 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
432 PI->getOperand(0).getReg() == StackPtr) {
434 *NumBytes -= PI->getOperand(2).getImm();
439 // mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
441 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
442 MachineBasicBlock::iterator &MBBI,
443 unsigned StackPtr, uint64_t *NumBytes = NULL) {
446 if (MBBI == MBB.end()) return;
448 MachineBasicBlock::iterator NI = next(MBBI);
449 if (NI == MBB.end()) return;
451 unsigned Opc = NI->getOpcode();
452 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
453 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
454 NI->getOperand(0).getReg() == StackPtr) {
456 *NumBytes -= NI->getOperand(2).getImm();
459 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
460 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
461 NI->getOperand(0).getReg() == StackPtr) {
463 *NumBytes += NI->getOperand(2).getImm();
469 /// mergeSPUpdates - Checks the instruction before/after the passed
470 /// instruction. If it is an ADD/SUB instruction it is deleted
471 /// argument and the stack adjustment is returned as a positive value for ADD
472 /// and a negative for SUB.
473 static int mergeSPUpdates(MachineBasicBlock &MBB,
474 MachineBasicBlock::iterator &MBBI,
476 bool doMergeWithPrevious) {
478 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
479 (!doMergeWithPrevious && MBBI == MBB.end()))
484 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
485 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : next(MBBI);
486 unsigned Opc = PI->getOpcode();
487 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
488 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
489 PI->getOperand(0).getReg() == StackPtr){
490 Offset += PI->getOperand(2).getImm();
492 if (!doMergeWithPrevious) MBBI = NI;
493 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
494 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
495 PI->getOperand(0).getReg() == StackPtr) {
496 Offset -= PI->getOperand(2).getImm();
498 if (!doMergeWithPrevious) MBBI = NI;
504 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
505 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
506 MachineFrameInfo *MFI = MF.getFrameInfo();
507 const Function* Fn = MF.getFunction();
508 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
509 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
510 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
511 MachineBasicBlock::iterator MBBI = MBB.begin();
513 // Prepare for frame info.
514 unsigned FrameLabelId = 0;
516 // Get the number of bytes to allocate from the FrameInfo.
517 uint64_t StackSize = MFI->getStackSize();
518 // Add RETADDR move area to callee saved frame size.
519 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
520 if (TailCallReturnAddrDelta < 0)
521 X86FI->setCalleeSavedFrameSize(
522 X86FI->getCalleeSavedFrameSize() +(-TailCallReturnAddrDelta));
523 uint64_t NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
525 // Insert stack pointer adjustment for later moving of return addr. Only
526 // applies to tail call optimized functions where the callee argument stack
527 // size is bigger than the callers.
528 if (TailCallReturnAddrDelta < 0) {
529 BuildMI(MBB, MBBI, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri),
530 StackPtr).addReg(StackPtr).addImm(-TailCallReturnAddrDelta);
534 // Get the offset of the stack slot for the EBP register... which is
535 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
536 // Update the frame offset adjustment.
537 MFI->setOffsetAdjustment(SlotSize-NumBytes);
539 // Save EBP into the appropriate stack slot...
540 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
542 NumBytes -= SlotSize;
544 if (MMI && MMI->needsFrameInfo()) {
545 // Mark effective beginning of when frame pointer becomes valid.
546 FrameLabelId = MMI->NextLabelID();
547 BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(FrameLabelId);
550 // Update EBP with the new base value...
551 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
555 unsigned ReadyLabelId = 0;
556 if (MMI && MMI->needsFrameInfo()) {
557 // Mark effective beginning of when frame pointer is ready.
558 ReadyLabelId = MMI->NextLabelID();
559 BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(ReadyLabelId);
562 // Skip the callee-saved push instructions.
563 while (MBBI != MBB.end() &&
564 (MBBI->getOpcode() == X86::PUSH32r ||
565 MBBI->getOpcode() == X86::PUSH64r))
568 if (NumBytes) { // adjust stack pointer: ESP -= numbytes
569 if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
570 // Check, whether EAX is livein for this function
571 bool isEAXAlive = false;
572 for (MachineRegisterInfo::livein_iterator
573 II = MF.getRegInfo().livein_begin(),
574 EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
575 unsigned Reg = II->first;
576 isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
577 Reg == X86::AH || Reg == X86::AL);
580 // Function prologue calls _alloca to probe the stack when allocating
581 // more than 4k bytes in one go. Touching the stack at 4K increments is
582 // necessary to ensure that the guard pages used by the OS virtual memory
583 // manager are allocated in correct sequence.
585 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes);
586 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
587 .addExternalSymbol("_alloca");
590 BuildMI(MBB, MBBI, TII.get(X86::PUSH32r), X86::EAX);
591 // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
592 // allocated bytes for EAX.
593 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes-4);
594 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
595 .addExternalSymbol("_alloca");
597 MachineInstr *MI = addRegOffset(BuildMI(TII.get(X86::MOV32rm),X86::EAX),
598 StackPtr, NumBytes-4);
599 MBB.insert(MBBI, MI);
602 // If there is an SUB32ri of ESP immediately before this instruction,
603 // merge the two. This can be the case when tail call elimination is
604 // enabled and the callee has more arguments then the caller.
605 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
606 // If there is an ADD32ri or SUB32ri of ESP immediately after this
607 // instruction, merge the two instructions.
608 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
611 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
615 if (MMI && MMI->needsFrameInfo()) {
616 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
617 const TargetData *TD = MF.getTarget().getTargetData();
619 // Calculate amount of bytes used for return address storing
621 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
622 TargetFrameInfo::StackGrowsUp ?
623 TD->getPointerSize() : -TD->getPointerSize());
626 // Show update of SP.
629 MachineLocation SPDst(MachineLocation::VirtualFP);
630 MachineLocation SPSrc(MachineLocation::VirtualFP, 2*stackGrowth);
631 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
633 MachineLocation SPDst(MachineLocation::VirtualFP);
634 MachineLocation SPSrc(MachineLocation::VirtualFP,
635 -StackSize+stackGrowth);
636 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
639 //FIXME: Verify & implement for FP
640 MachineLocation SPDst(StackPtr);
641 MachineLocation SPSrc(StackPtr, stackGrowth);
642 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
645 // Add callee saved registers to move list.
646 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
648 // FIXME: This is dirty hack. The code itself is pretty mess right now.
649 // It should be rewritten from scratch and generalized sometimes.
651 // Determine maximum offset (minumum due to stack growth)
652 int64_t MaxOffset = 0;
653 for (unsigned I = 0, E = CSI.size(); I!=E; ++I)
654 MaxOffset = std::min(MaxOffset,
655 MFI->getObjectOffset(CSI[I].getFrameIdx()));
658 int64_t saveAreaOffset = (hasFP(MF) ? 3 : 2)*stackGrowth;
659 for (unsigned I = 0, E = CSI.size(); I!=E; ++I) {
660 int64_t Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
661 unsigned Reg = CSI[I].getReg();
662 Offset = (MaxOffset-Offset+saveAreaOffset);
663 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
664 MachineLocation CSSrc(Reg);
665 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
670 MachineLocation FPDst(MachineLocation::VirtualFP, 2*stackGrowth);
671 MachineLocation FPSrc(FramePtr);
672 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
675 MachineLocation FPDst(hasFP(MF) ? FramePtr : StackPtr);
676 MachineLocation FPSrc(MachineLocation::VirtualFP);
677 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
680 // If it's main() on Cygwin\Mingw32 we should align stack as well
681 if (Fn->hasExternalLinkage() && Fn->getName() == "main" &&
682 Subtarget->isTargetCygMing()) {
683 BuildMI(MBB, MBBI, TII.get(X86::AND32ri), X86::ESP)
684 .addReg(X86::ESP).addImm(-StackAlign);
687 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(StackAlign);
688 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32)).addExternalSymbol("_alloca");
692 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
693 MachineBasicBlock &MBB) const {
694 const MachineFrameInfo *MFI = MF.getFrameInfo();
695 const Function* Fn = MF.getFunction();
696 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
697 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
698 MachineBasicBlock::iterator MBBI = prior(MBB.end());
699 unsigned RetOpcode = MBBI->getOpcode();
704 case X86::TCRETURNdi:
705 case X86::TCRETURNri:
706 case X86::TCRETURNri64:
707 case X86::TCRETURNdi64:
711 case X86::TAILJMPm: break; // These are ok
713 assert(0 && "Can only insert epilog into returning blocks");
716 // Get the number of bytes to allocate from the FrameInfo
717 uint64_t StackSize = MFI->getStackSize();
718 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
719 uint64_t NumBytes = StackSize - CSSize;
723 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
724 NumBytes -= SlotSize;
727 // Skip the callee-saved pop instructions.
728 while (MBBI != MBB.begin()) {
729 MachineBasicBlock::iterator PI = prior(MBBI);
730 unsigned Opc = PI->getOpcode();
731 if (Opc != X86::POP32r && Opc != X86::POP64r &&
732 !PI->getDesc().isTerminator())
737 // If there is an ADD32ri or SUB32ri of ESP immediately before this
738 // instruction, merge the two instructions.
739 if (NumBytes || MFI->hasVarSizedObjects())
740 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
742 // If dynamic alloca is used, then reset esp to point to the last callee-saved
743 // slot before popping them off! Also, if it's main() on Cygwin/Mingw32 we
744 // aligned stack in the prologue, - revert stack changes back. Note: we're
745 // assuming, that frame pointer was forced for main()
746 if (MFI->hasVarSizedObjects() ||
747 (Fn->hasExternalLinkage() && Fn->getName() == "main" &&
748 Subtarget->isTargetCygMing())) {
749 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
751 MachineInstr *MI = addRegOffset(BuildMI(TII.get(Opc), StackPtr),
753 MBB.insert(MBBI, MI);
755 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr).
761 // adjust stack pointer back: ESP += numbytes
763 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
765 // We're returning from function via eh_return.
766 if (RetOpcode == X86::EH_RETURN) {
767 MBBI = prior(MBB.end());
768 MachineOperand &DestAddr = MBBI->getOperand(0);
769 assert(DestAddr.isRegister() && "Offset should be in register!");
770 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr).
771 addReg(DestAddr.getReg());
772 // Tail call return: adjust the stack pointer and jump to callee
773 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
774 RetOpcode== X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64) {
775 MBBI = prior(MBB.end());
776 MachineOperand &JumpTarget = MBBI->getOperand(0);
777 MachineOperand &StackAdjust = MBBI->getOperand(1);
778 assert( StackAdjust.isImmediate() && "Expecting immediate value.");
780 // Adjust stack pointer.
781 int StackAdj = StackAdjust.getImm();
782 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
784 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
785 // Incoporate the retaddr area.
786 Offset = StackAdj-MaxTCDelta;
787 assert(Offset >= 0 && "Offset should never be negative");
789 // Check for possible merge with preceeding ADD instruction.
790 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
791 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
793 // Jump to label or value in register.
794 if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64)
795 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPd)).
796 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
797 else if (RetOpcode== X86::TCRETURNri64) {
798 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
800 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr), JumpTarget.getReg());
801 // Delete the pseudo instruction TCRETURN.
803 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
804 (X86FI->getTCReturnAddrDelta() < 0)) {
805 // Add the return addr area delta back since we are not tail calling.
806 int delta = -1*X86FI->getTCReturnAddrDelta();
807 MBBI = prior(MBB.end());
808 // Check for possible merge with preceeding ADD instruction.
809 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
810 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
814 unsigned X86RegisterInfo::getRARegister() const {
816 return X86::RIP; // Should have dwarf #16
818 return X86::EIP; // Should have dwarf #8
821 unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
822 return hasFP(MF) ? FramePtr : StackPtr;
825 void X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
827 // Calculate amount of bytes used for return address storing
828 int stackGrowth = (Is64Bit ? -8 : -4);
830 // Initial state of the frame pointer is esp+4.
831 MachineLocation Dst(MachineLocation::VirtualFP);
832 MachineLocation Src(StackPtr, stackGrowth);
833 Moves.push_back(MachineMove(0, Dst, Src));
835 // Add return address to move list
836 MachineLocation CSDst(StackPtr, stackGrowth);
837 MachineLocation CSSrc(getRARegister());
838 Moves.push_back(MachineMove(0, CSDst, CSSrc));
841 unsigned X86RegisterInfo::getEHExceptionRegister() const {
842 assert(0 && "What is the exception register");
846 unsigned X86RegisterInfo::getEHHandlerRegister() const {
847 assert(0 && "What is the exception handler register");
852 unsigned getX86SubSuperRegister(unsigned Reg, MVT::ValueType VT, bool High) {
859 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
861 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
863 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
865 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
871 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
873 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
875 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
877 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
879 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
881 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
883 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
885 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
887 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
889 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
891 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
893 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
895 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
897 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
899 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
901 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
908 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
910 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
912 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
914 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
916 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
918 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
920 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
922 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
924 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
926 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
928 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
930 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
932 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
934 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
936 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
938 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
944 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
946 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
948 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
950 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
952 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
954 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
956 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
958 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
960 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
962 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
964 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
966 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
968 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
970 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
972 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
974 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
980 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
982 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
984 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
986 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
988 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
990 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
992 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
994 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
996 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
998 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1000 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1002 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1004 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1006 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1008 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1010 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1019 #include "X86GenRegisterInfo.inc"