1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the MRegisterInfo class. This
11 // file is responsible for the frame pointer elimination optimization on X86.
13 //===----------------------------------------------------------------------===//
16 #include "X86RegisterInfo.h"
17 #include "X86InstrBuilder.h"
18 #include "llvm/Constants.h"
19 #include "llvm/Type.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineLocation.h"
25 #include "llvm/Target/TargetFrameInfo.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Target/TargetOptions.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/ADT/STLExtras.h"
36 NoFusing("disable-spill-fusing",
37 cl::desc("Disable fusing of spill code into instructions"));
39 PrintFailedFusing("print-failed-fuse-candidates",
40 cl::desc("Print instructions that the allocator wants to"
41 " fuse, but the X86 backend currently can't"),
45 X86RegisterInfo::X86RegisterInfo()
46 : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP) {}
48 void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
49 MachineBasicBlock::iterator MI,
50 unsigned SrcReg, int FrameIdx,
51 const TargetRegisterClass *RC) const {
53 if (RC == &X86::GR32RegClass) {
55 } else if (RC == &X86::GR16RegClass) {
57 } else if (RC == &X86::GR8RegClass) {
59 } else if (RC == &X86::GR32_RegClass) {
61 } else if (RC == &X86::GR16_RegClass) {
63 } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
65 } else if (RC == &X86::FR32RegClass) {
67 } else if (RC == &X86::FR64RegClass) {
69 } else if (RC == &X86::VR128RegClass) {
72 assert(0 && "Unknown regclass");
75 addFrameReference(BuildMI(MBB, MI, Opc, 5), FrameIdx).addReg(SrcReg);
78 void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
79 MachineBasicBlock::iterator MI,
80 unsigned DestReg, int FrameIdx,
81 const TargetRegisterClass *RC) const{
83 if (RC == &X86::GR32RegClass) {
85 } else if (RC == &X86::GR16RegClass) {
87 } else if (RC == &X86::GR8RegClass) {
89 } else if (RC == &X86::GR32_RegClass) {
91 } else if (RC == &X86::GR16_RegClass) {
93 } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
95 } else if (RC == &X86::FR32RegClass) {
97 } else if (RC == &X86::FR64RegClass) {
99 } else if (RC == &X86::VR128RegClass) {
102 assert(0 && "Unknown regclass");
105 addFrameReference(BuildMI(MBB, MI, Opc, 4, DestReg), FrameIdx);
108 void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
109 MachineBasicBlock::iterator MI,
110 unsigned DestReg, unsigned SrcReg,
111 const TargetRegisterClass *RC) const {
113 if (RC == &X86::GR32RegClass) {
115 } else if (RC == &X86::GR16RegClass) {
117 } else if (RC == &X86::GR8RegClass) {
119 } else if (RC == &X86::GR32_RegClass) {
121 } else if (RC == &X86::GR16_RegClass) {
123 } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
125 } else if (RC == &X86::FR32RegClass) {
126 Opc = X86::FsMOVAPSrr;
127 } else if (RC == &X86::FR64RegClass) {
128 Opc = X86::FsMOVAPDrr;
129 } else if (RC == &X86::VR128RegClass) {
132 assert(0 && "Unknown regclass");
135 BuildMI(MBB, MI, Opc, 1, DestReg).addReg(SrcReg);
139 static MachineInstr *MakeMInst(unsigned Opcode, unsigned FrameIndex,
141 return addFrameReference(BuildMI(Opcode, 4), FrameIndex);
144 static MachineInstr *MakeMRInst(unsigned Opcode, unsigned FrameIndex,
146 return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
147 .addReg(MI->getOperand(1).getReg());
150 static MachineInstr *MakeMRIInst(unsigned Opcode, unsigned FrameIndex,
152 return addFrameReference(BuildMI(Opcode, 6), FrameIndex)
153 .addReg(MI->getOperand(1).getReg())
154 .addImm(MI->getOperand(2).getImmedValue());
157 static MachineInstr *MakeMIInst(unsigned Opcode, unsigned FrameIndex,
159 if (MI->getOperand(1).isImmediate())
160 return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
161 .addImm(MI->getOperand(1).getImmedValue());
162 else if (MI->getOperand(1).isGlobalAddress())
163 return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
164 .addGlobalAddress(MI->getOperand(1).getGlobal(),
165 MI->getOperand(1).getOffset());
166 else if (MI->getOperand(1).isJumpTableIndex())
167 return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
168 .addJumpTableIndex(MI->getOperand(1).getJumpTableIndex());
169 assert(0 && "Unknown operand for MakeMI!");
173 static MachineInstr *MakeM0Inst(unsigned Opcode, unsigned FrameIndex,
175 return addFrameReference(BuildMI(Opcode, 5), FrameIndex).addImm(0);
178 static MachineInstr *MakeRMInst(unsigned Opcode, unsigned FrameIndex,
180 const MachineOperand& op = MI->getOperand(0);
181 return addFrameReference(BuildMI(Opcode, 5, op.getReg(), op.getUseType()),
185 static MachineInstr *MakeRMIInst(unsigned Opcode, unsigned FrameIndex,
187 const MachineOperand& op = MI->getOperand(0);
188 return addFrameReference(BuildMI(Opcode, 6, op.getReg(), op.getUseType()),
189 FrameIndex).addImm(MI->getOperand(2).getImmedValue());
193 MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr* MI,
195 int FrameIndex) const {
196 if (NoFusing) return NULL;
198 /// FIXME: This should obviously be autogenerated by tablegen when patterns
201 switch(MI->getOpcode()) {
202 case X86::XCHG8rr: return MakeMRInst(X86::XCHG8mr ,FrameIndex, MI);
203 case X86::XCHG16rr: return MakeMRInst(X86::XCHG16mr,FrameIndex, MI);
204 case X86::XCHG32rr: return MakeMRInst(X86::XCHG32mr,FrameIndex, MI);
205 case X86::MOV8rr: return MakeMRInst(X86::MOV8mr , FrameIndex, MI);
206 case X86::MOV16rr: return MakeMRInst(X86::MOV16mr, FrameIndex, MI);
207 case X86::MOV32rr: return MakeMRInst(X86::MOV32mr, FrameIndex, MI);
208 case X86::MOV8ri: return MakeMIInst(X86::MOV8mi , FrameIndex, MI);
209 case X86::MOV16ri: return MakeMIInst(X86::MOV16mi, FrameIndex, MI);
210 case X86::MOV32ri: return MakeMIInst(X86::MOV32mi, FrameIndex, MI);
211 case X86::MUL8r: return MakeMInst( X86::MUL8m , FrameIndex, MI);
212 case X86::MUL16r: return MakeMInst( X86::MUL16m, FrameIndex, MI);
213 case X86::MUL32r: return MakeMInst( X86::MUL32m, FrameIndex, MI);
214 case X86::IMUL8r: return MakeMInst( X86::IMUL8m , FrameIndex, MI);
215 case X86::IMUL16r: return MakeMInst( X86::IMUL16m, FrameIndex, MI);
216 case X86::IMUL32r: return MakeMInst( X86::IMUL32m, FrameIndex, MI);
217 case X86::DIV8r: return MakeMInst( X86::DIV8m , FrameIndex, MI);
218 case X86::DIV16r: return MakeMInst( X86::DIV16m, FrameIndex, MI);
219 case X86::DIV32r: return MakeMInst( X86::DIV32m, FrameIndex, MI);
220 case X86::IDIV8r: return MakeMInst( X86::IDIV8m , FrameIndex, MI);
221 case X86::IDIV16r: return MakeMInst( X86::IDIV16m, FrameIndex, MI);
222 case X86::IDIV32r: return MakeMInst( X86::IDIV32m, FrameIndex, MI);
223 case X86::NEG8r: return MakeMInst( X86::NEG8m , FrameIndex, MI);
224 case X86::NEG16r: return MakeMInst( X86::NEG16m, FrameIndex, MI);
225 case X86::NEG32r: return MakeMInst( X86::NEG32m, FrameIndex, MI);
226 case X86::NOT8r: return MakeMInst( X86::NOT8m , FrameIndex, MI);
227 case X86::NOT16r: return MakeMInst( X86::NOT16m, FrameIndex, MI);
228 case X86::NOT32r: return MakeMInst( X86::NOT32m, FrameIndex, MI);
229 case X86::INC8r: return MakeMInst( X86::INC8m , FrameIndex, MI);
230 case X86::INC16r: return MakeMInst( X86::INC16m, FrameIndex, MI);
231 case X86::INC32r: return MakeMInst( X86::INC32m, FrameIndex, MI);
232 case X86::DEC8r: return MakeMInst( X86::DEC8m , FrameIndex, MI);
233 case X86::DEC16r: return MakeMInst( X86::DEC16m, FrameIndex, MI);
234 case X86::DEC32r: return MakeMInst( X86::DEC32m, FrameIndex, MI);
235 case X86::ADD8rr: return MakeMRInst(X86::ADD8mr , FrameIndex, MI);
236 case X86::ADD16rr: return MakeMRInst(X86::ADD16mr, FrameIndex, MI);
237 case X86::ADD32rr: return MakeMRInst(X86::ADD32mr, FrameIndex, MI);
238 case X86::ADD8ri: return MakeMIInst(X86::ADD8mi , FrameIndex, MI);
239 case X86::ADD16ri: return MakeMIInst(X86::ADD16mi, FrameIndex, MI);
240 case X86::ADD32ri: return MakeMIInst(X86::ADD32mi, FrameIndex, MI);
241 case X86::ADD16ri8: return MakeMIInst(X86::ADD16mi8,FrameIndex, MI);
242 case X86::ADD32ri8: return MakeMIInst(X86::ADD32mi8,FrameIndex, MI);
243 case X86::ADC32rr: return MakeMRInst(X86::ADC32mr, FrameIndex, MI);
244 case X86::ADC32ri: return MakeMIInst(X86::ADC32mi, FrameIndex, MI);
245 case X86::ADC32ri8: return MakeMIInst(X86::ADC32mi8,FrameIndex, MI);
246 case X86::SUB8rr: return MakeMRInst(X86::SUB8mr , FrameIndex, MI);
247 case X86::SUB16rr: return MakeMRInst(X86::SUB16mr, FrameIndex, MI);
248 case X86::SUB32rr: return MakeMRInst(X86::SUB32mr, FrameIndex, MI);
249 case X86::SUB8ri: return MakeMIInst(X86::SUB8mi , FrameIndex, MI);
250 case X86::SUB16ri: return MakeMIInst(X86::SUB16mi, FrameIndex, MI);
251 case X86::SUB32ri: return MakeMIInst(X86::SUB32mi, FrameIndex, MI);
252 case X86::SUB16ri8: return MakeMIInst(X86::SUB16mi8,FrameIndex, MI);
253 case X86::SUB32ri8: return MakeMIInst(X86::SUB32mi8,FrameIndex, MI);
254 case X86::SBB32rr: return MakeMRInst(X86::SBB32mr, FrameIndex, MI);
255 case X86::SBB32ri: return MakeMIInst(X86::SBB32mi, FrameIndex, MI);
256 case X86::SBB32ri8: return MakeMIInst(X86::SBB32mi8,FrameIndex, MI);
257 case X86::AND8rr: return MakeMRInst(X86::AND8mr , FrameIndex, MI);
258 case X86::AND16rr: return MakeMRInst(X86::AND16mr, FrameIndex, MI);
259 case X86::AND32rr: return MakeMRInst(X86::AND32mr, FrameIndex, MI);
260 case X86::AND8ri: return MakeMIInst(X86::AND8mi , FrameIndex, MI);
261 case X86::AND16ri: return MakeMIInst(X86::AND16mi, FrameIndex, MI);
262 case X86::AND32ri: return MakeMIInst(X86::AND32mi, FrameIndex, MI);
263 case X86::AND16ri8: return MakeMIInst(X86::AND16mi8,FrameIndex, MI);
264 case X86::AND32ri8: return MakeMIInst(X86::AND32mi8,FrameIndex, MI);
265 case X86::OR8rr: return MakeMRInst(X86::OR8mr , FrameIndex, MI);
266 case X86::OR16rr: return MakeMRInst(X86::OR16mr, FrameIndex, MI);
267 case X86::OR32rr: return MakeMRInst(X86::OR32mr, FrameIndex, MI);
268 case X86::OR8ri: return MakeMIInst(X86::OR8mi , FrameIndex, MI);
269 case X86::OR16ri: return MakeMIInst(X86::OR16mi, FrameIndex, MI);
270 case X86::OR32ri: return MakeMIInst(X86::OR32mi, FrameIndex, MI);
271 case X86::OR16ri8: return MakeMIInst(X86::OR16mi8, FrameIndex, MI);
272 case X86::OR32ri8: return MakeMIInst(X86::OR32mi8, FrameIndex, MI);
273 case X86::XOR8rr: return MakeMRInst(X86::XOR8mr , FrameIndex, MI);
274 case X86::XOR16rr: return MakeMRInst(X86::XOR16mr, FrameIndex, MI);
275 case X86::XOR32rr: return MakeMRInst(X86::XOR32mr, FrameIndex, MI);
276 case X86::XOR8ri: return MakeMIInst(X86::XOR8mi , FrameIndex, MI);
277 case X86::XOR16ri: return MakeMIInst(X86::XOR16mi, FrameIndex, MI);
278 case X86::XOR32ri: return MakeMIInst(X86::XOR32mi, FrameIndex, MI);
279 case X86::XOR16ri8: return MakeMIInst(X86::XOR16mi8,FrameIndex, MI);
280 case X86::XOR32ri8: return MakeMIInst(X86::XOR32mi8,FrameIndex, MI);
281 case X86::SHL8rCL: return MakeMInst( X86::SHL8mCL ,FrameIndex, MI);
282 case X86::SHL16rCL: return MakeMInst( X86::SHL16mCL,FrameIndex, MI);
283 case X86::SHL32rCL: return MakeMInst( X86::SHL32mCL,FrameIndex, MI);
284 case X86::SHL8ri: return MakeMIInst(X86::SHL8mi , FrameIndex, MI);
285 case X86::SHL16ri: return MakeMIInst(X86::SHL16mi, FrameIndex, MI);
286 case X86::SHL32ri: return MakeMIInst(X86::SHL32mi, FrameIndex, MI);
287 case X86::SHR8rCL: return MakeMInst( X86::SHR8mCL ,FrameIndex, MI);
288 case X86::SHR16rCL: return MakeMInst( X86::SHR16mCL,FrameIndex, MI);
289 case X86::SHR32rCL: return MakeMInst( X86::SHR32mCL,FrameIndex, MI);
290 case X86::SHR8ri: return MakeMIInst(X86::SHR8mi , FrameIndex, MI);
291 case X86::SHR16ri: return MakeMIInst(X86::SHR16mi, FrameIndex, MI);
292 case X86::SHR32ri: return MakeMIInst(X86::SHR32mi, FrameIndex, MI);
293 case X86::SAR8rCL: return MakeMInst( X86::SAR8mCL ,FrameIndex, MI);
294 case X86::SAR16rCL: return MakeMInst( X86::SAR16mCL,FrameIndex, MI);
295 case X86::SAR32rCL: return MakeMInst( X86::SAR32mCL,FrameIndex, MI);
296 case X86::SAR8ri: return MakeMIInst(X86::SAR8mi , FrameIndex, MI);
297 case X86::SAR16ri: return MakeMIInst(X86::SAR16mi, FrameIndex, MI);
298 case X86::SAR32ri: return MakeMIInst(X86::SAR32mi, FrameIndex, MI);
299 case X86::ROL8rCL: return MakeMInst( X86::ROL8mCL ,FrameIndex, MI);
300 case X86::ROL16rCL: return MakeMInst( X86::ROL16mCL,FrameIndex, MI);
301 case X86::ROL32rCL: return MakeMInst( X86::ROL32mCL,FrameIndex, MI);
302 case X86::ROL8ri: return MakeMIInst(X86::ROL8mi , FrameIndex, MI);
303 case X86::ROL16ri: return MakeMIInst(X86::ROL16mi, FrameIndex, MI);
304 case X86::ROL32ri: return MakeMIInst(X86::ROL32mi, FrameIndex, MI);
305 case X86::ROR8rCL: return MakeMInst( X86::ROR8mCL ,FrameIndex, MI);
306 case X86::ROR16rCL: return MakeMInst( X86::ROR16mCL,FrameIndex, MI);
307 case X86::ROR32rCL: return MakeMInst( X86::ROR32mCL,FrameIndex, MI);
308 case X86::ROR8ri: return MakeMIInst(X86::ROR8mi , FrameIndex, MI);
309 case X86::ROR16ri: return MakeMIInst(X86::ROR16mi, FrameIndex, MI);
310 case X86::ROR32ri: return MakeMIInst(X86::ROR32mi, FrameIndex, MI);
311 case X86::SHLD32rrCL:return MakeMRInst( X86::SHLD32mrCL,FrameIndex, MI);
312 case X86::SHLD32rri8:return MakeMRIInst(X86::SHLD32mri8,FrameIndex, MI);
313 case X86::SHRD32rrCL:return MakeMRInst( X86::SHRD32mrCL,FrameIndex, MI);
314 case X86::SHRD32rri8:return MakeMRIInst(X86::SHRD32mri8,FrameIndex, MI);
315 case X86::SHLD16rrCL:return MakeMRInst( X86::SHLD16mrCL,FrameIndex, MI);
316 case X86::SHLD16rri8:return MakeMRIInst(X86::SHLD16mri8,FrameIndex, MI);
317 case X86::SHRD16rrCL:return MakeMRInst( X86::SHRD16mrCL,FrameIndex, MI);
318 case X86::SHRD16rri8:return MakeMRIInst(X86::SHRD16mri8,FrameIndex, MI);
319 case X86::SETBr: return MakeMInst( X86::SETBm, FrameIndex, MI);
320 case X86::SETAEr: return MakeMInst( X86::SETAEm, FrameIndex, MI);
321 case X86::SETEr: return MakeMInst( X86::SETEm, FrameIndex, MI);
322 case X86::SETNEr: return MakeMInst( X86::SETNEm, FrameIndex, MI);
323 case X86::SETBEr: return MakeMInst( X86::SETBEm, FrameIndex, MI);
324 case X86::SETAr: return MakeMInst( X86::SETAm, FrameIndex, MI);
325 case X86::SETSr: return MakeMInst( X86::SETSm, FrameIndex, MI);
326 case X86::SETNSr: return MakeMInst( X86::SETNSm, FrameIndex, MI);
327 case X86::SETPr: return MakeMInst( X86::SETPm, FrameIndex, MI);
328 case X86::SETNPr: return MakeMInst( X86::SETNPm, FrameIndex, MI);
329 case X86::SETLr: return MakeMInst( X86::SETLm, FrameIndex, MI);
330 case X86::SETGEr: return MakeMInst( X86::SETGEm, FrameIndex, MI);
331 case X86::SETLEr: return MakeMInst( X86::SETLEm, FrameIndex, MI);
332 case X86::SETGr: return MakeMInst( X86::SETGm, FrameIndex, MI);
333 // Alias instructions
334 case X86::MOV8r0: return MakeM0Inst(X86::MOV8mi, FrameIndex, MI);
335 case X86::MOV16r0: return MakeM0Inst(X86::MOV16mi, FrameIndex, MI);
336 case X86::MOV32r0: return MakeM0Inst(X86::MOV32mi, FrameIndex, MI);
337 // Alias scalar SSE instructions
338 case X86::FsMOVAPSrr: return MakeMRInst(X86::MOVSSmr, FrameIndex, MI);
339 case X86::FsMOVAPDrr: return MakeMRInst(X86::MOVSDmr, FrameIndex, MI);
340 // Scalar SSE instructions
341 case X86::MOVSSrr: return MakeMRInst(X86::MOVSSmr, FrameIndex, MI);
342 case X86::MOVSDrr: return MakeMRInst(X86::MOVSDmr, FrameIndex, MI);
343 // Packed SSE instructions
344 case X86::MOVAPSrr: return MakeMRInst(X86::MOVAPSmr, FrameIndex, MI);
345 case X86::MOVAPDrr: return MakeMRInst(X86::MOVAPDmr, FrameIndex, MI);
346 case X86::MOVUPSrr: return MakeMRInst(X86::MOVUPSmr, FrameIndex, MI);
347 case X86::MOVUPDrr: return MakeMRInst(X86::MOVUPDmr, FrameIndex, MI);
348 // Alias packed SSE instructions
349 case X86::MOVPS2SSrr:return MakeMRInst(X86::MOVPS2SSmr, FrameIndex, MI);
350 case X86::MOVPDI2DIrr:return MakeMRInst(X86::MOVPDI2DImr, FrameIndex, MI);
353 switch(MI->getOpcode()) {
354 case X86::XCHG8rr: return MakeRMInst(X86::XCHG8rm ,FrameIndex, MI);
355 case X86::XCHG16rr: return MakeRMInst(X86::XCHG16rm,FrameIndex, MI);
356 case X86::XCHG32rr: return MakeRMInst(X86::XCHG32rm,FrameIndex, MI);
357 case X86::MOV8rr: return MakeRMInst(X86::MOV8rm , FrameIndex, MI);
358 case X86::MOV16rr: return MakeRMInst(X86::MOV16rm, FrameIndex, MI);
359 case X86::MOV32rr: return MakeRMInst(X86::MOV32rm, FrameIndex, MI);
360 case X86::CMOVB16rr: return MakeRMInst(X86::CMOVB16rm , FrameIndex, MI);
361 case X86::CMOVB32rr: return MakeRMInst(X86::CMOVB32rm , FrameIndex, MI);
362 case X86::CMOVAE16rr: return MakeRMInst(X86::CMOVAE16rm , FrameIndex, MI);
363 case X86::CMOVAE32rr: return MakeRMInst(X86::CMOVAE32rm , FrameIndex, MI);
364 case X86::CMOVE16rr: return MakeRMInst(X86::CMOVE16rm , FrameIndex, MI);
365 case X86::CMOVE32rr: return MakeRMInst(X86::CMOVE32rm , FrameIndex, MI);
366 case X86::CMOVNE16rr:return MakeRMInst(X86::CMOVNE16rm, FrameIndex, MI);
367 case X86::CMOVNE32rr:return MakeRMInst(X86::CMOVNE32rm, FrameIndex, MI);
368 case X86::CMOVBE16rr:return MakeRMInst(X86::CMOVBE16rm, FrameIndex, MI);
369 case X86::CMOVBE32rr:return MakeRMInst(X86::CMOVBE32rm, FrameIndex, MI);
370 case X86::CMOVA16rr:return MakeRMInst(X86::CMOVA16rm, FrameIndex, MI);
371 case X86::CMOVA32rr:return MakeRMInst(X86::CMOVA32rm, FrameIndex, MI);
372 case X86::CMOVS16rr: return MakeRMInst(X86::CMOVS16rm , FrameIndex, MI);
373 case X86::CMOVS32rr: return MakeRMInst(X86::CMOVS32rm , FrameIndex, MI);
374 case X86::CMOVNS16rr: return MakeRMInst(X86::CMOVNS16rm , FrameIndex, MI);
375 case X86::CMOVNS32rr: return MakeRMInst(X86::CMOVNS32rm , FrameIndex, MI);
376 case X86::CMOVP16rr: return MakeRMInst(X86::CMOVP16rm , FrameIndex, MI);
377 case X86::CMOVP32rr: return MakeRMInst(X86::CMOVP32rm , FrameIndex, MI);
378 case X86::CMOVNP16rr: return MakeRMInst(X86::CMOVNP16rm , FrameIndex, MI);
379 case X86::CMOVNP32rr: return MakeRMInst(X86::CMOVNP32rm , FrameIndex, MI);
380 case X86::CMOVL16rr: return MakeRMInst(X86::CMOVL16rm , FrameIndex, MI);
381 case X86::CMOVL32rr: return MakeRMInst(X86::CMOVL32rm , FrameIndex, MI);
382 case X86::CMOVGE16rr: return MakeRMInst(X86::CMOVGE16rm , FrameIndex, MI);
383 case X86::CMOVGE32rr: return MakeRMInst(X86::CMOVGE32rm , FrameIndex, MI);
384 case X86::CMOVLE16rr: return MakeRMInst(X86::CMOVLE16rm , FrameIndex, MI);
385 case X86::CMOVLE32rr: return MakeRMInst(X86::CMOVLE32rm , FrameIndex, MI);
386 case X86::CMOVG16rr: return MakeRMInst(X86::CMOVG16rm , FrameIndex, MI);
387 case X86::CMOVG32rr: return MakeRMInst(X86::CMOVG32rm , FrameIndex, MI);
388 case X86::ADD8rr: return MakeRMInst(X86::ADD8rm , FrameIndex, MI);
389 case X86::ADD16rr: return MakeRMInst(X86::ADD16rm, FrameIndex, MI);
390 case X86::ADD32rr: return MakeRMInst(X86::ADD32rm, FrameIndex, MI);
391 case X86::ADC32rr: return MakeRMInst(X86::ADC32rm, FrameIndex, MI);
392 case X86::SUB8rr: return MakeRMInst(X86::SUB8rm , FrameIndex, MI);
393 case X86::SUB16rr: return MakeRMInst(X86::SUB16rm, FrameIndex, MI);
394 case X86::SUB32rr: return MakeRMInst(X86::SUB32rm, FrameIndex, MI);
395 case X86::SBB32rr: return MakeRMInst(X86::SBB32rm, FrameIndex, MI);
396 case X86::AND8rr: return MakeRMInst(X86::AND8rm , FrameIndex, MI);
397 case X86::AND16rr: return MakeRMInst(X86::AND16rm, FrameIndex, MI);
398 case X86::AND32rr: return MakeRMInst(X86::AND32rm, FrameIndex, MI);
399 case X86::OR8rr: return MakeRMInst(X86::OR8rm , FrameIndex, MI);
400 case X86::OR16rr: return MakeRMInst(X86::OR16rm, FrameIndex, MI);
401 case X86::OR32rr: return MakeRMInst(X86::OR32rm, FrameIndex, MI);
402 case X86::XOR8rr: return MakeRMInst(X86::XOR8rm , FrameIndex, MI);
403 case X86::XOR16rr: return MakeRMInst(X86::XOR16rm, FrameIndex, MI);
404 case X86::XOR32rr: return MakeRMInst(X86::XOR32rm, FrameIndex, MI);
405 case X86::IMUL16rr: return MakeRMInst(X86::IMUL16rm,FrameIndex, MI);
406 case X86::IMUL32rr: return MakeRMInst(X86::IMUL32rm,FrameIndex, MI);
407 case X86::IMUL16rri: return MakeRMIInst(X86::IMUL16rmi, FrameIndex, MI);
408 case X86::IMUL32rri: return MakeRMIInst(X86::IMUL32rmi, FrameIndex, MI);
409 case X86::IMUL16rri8:return MakeRMIInst(X86::IMUL16rmi8, FrameIndex, MI);
410 case X86::IMUL32rri8:return MakeRMIInst(X86::IMUL32rmi8, FrameIndex, MI);
411 case X86::TEST8rr: return MakeRMInst(X86::TEST8rm ,FrameIndex, MI);
412 case X86::TEST16rr: return MakeRMInst(X86::TEST16rm,FrameIndex, MI);
413 case X86::TEST32rr: return MakeRMInst(X86::TEST32rm,FrameIndex, MI);
414 case X86::TEST8ri: return MakeMIInst(X86::TEST8mi ,FrameIndex, MI);
415 case X86::TEST16ri: return MakeMIInst(X86::TEST16mi,FrameIndex, MI);
416 case X86::TEST32ri: return MakeMIInst(X86::TEST32mi,FrameIndex, MI);
417 case X86::CMP8rr: return MakeRMInst(X86::CMP8rm , FrameIndex, MI);
418 case X86::CMP16rr: return MakeRMInst(X86::CMP16rm, FrameIndex, MI);
419 case X86::CMP32rr: return MakeRMInst(X86::CMP32rm, FrameIndex, MI);
420 case X86::CMP8ri: return MakeRMInst(X86::CMP8mi , FrameIndex, MI);
421 case X86::CMP16ri: return MakeMIInst(X86::CMP16mi, FrameIndex, MI);
422 case X86::CMP32ri: return MakeMIInst(X86::CMP32mi, FrameIndex, MI);
423 case X86::CMP16ri8: return MakeMIInst(X86::CMP16mi8, FrameIndex, MI);
424 case X86::CMP32ri8: return MakeRMInst(X86::CMP32mi8, FrameIndex, MI);
425 case X86::MOVSX16rr8:return MakeRMInst(X86::MOVSX16rm8 , FrameIndex, MI);
426 case X86::MOVSX32rr8:return MakeRMInst(X86::MOVSX32rm8, FrameIndex, MI);
427 case X86::MOVSX32rr16:return MakeRMInst(X86::MOVSX32rm16, FrameIndex, MI);
428 case X86::MOVZX16rr8:return MakeRMInst(X86::MOVZX16rm8 , FrameIndex, MI);
429 case X86::MOVZX32rr8:return MakeRMInst(X86::MOVZX32rm8, FrameIndex, MI);
430 case X86::MOVZX32rr16:return MakeRMInst(X86::MOVZX32rm16, FrameIndex, MI);
431 // Alias scalar SSE instructions
432 case X86::FsMOVAPSrr:return MakeRMInst(X86::MOVSSrm, FrameIndex, MI);
433 case X86::FsMOVAPDrr:return MakeRMInst(X86::MOVSDrm, FrameIndex, MI);
434 // Scalar SSE instructions
435 case X86::MOVSSrr: return MakeRMInst(X86::MOVSSrm, FrameIndex, MI);
436 case X86::MOVSDrr: return MakeRMInst(X86::MOVSDrm, FrameIndex, MI);
437 case X86::CVTSS2SIrr:return MakeRMInst(X86::CVTSS2SIrm, FrameIndex, MI);
438 case X86::CVTTSS2SIrr:return MakeRMInst(X86::CVTTSS2SIrm, FrameIndex, MI);
439 case X86::CVTSD2SIrr:return MakeRMInst(X86::CVTSD2SIrm, FrameIndex, MI);
440 case X86::CVTTSD2SIrr:return MakeRMInst(X86::CVTTSD2SIrm, FrameIndex, MI);
441 case X86::CVTSS2SDrr:return MakeRMInst(X86::CVTSS2SDrm, FrameIndex, MI);
442 case X86::CVTSD2SSrr:return MakeRMInst(X86::CVTSD2SSrm, FrameIndex, MI);
443 case X86::CVTSI2SSrr:return MakeRMInst(X86::CVTSI2SSrm, FrameIndex, MI);
444 case X86::CVTSI2SDrr:return MakeRMInst(X86::CVTSI2SDrm, FrameIndex, MI);
445 case X86::Int_CVTTSS2SIrr:
446 return MakeRMInst(X86::Int_CVTTSS2SIrm, FrameIndex, MI);
447 case X86::Int_CVTTSD2SIrr:
448 return MakeRMInst(X86::Int_CVTTSD2SIrm, FrameIndex, MI);
449 case X86::Int_CVTSI2SSrr:
450 return MakeRMInst(X86::Int_CVTSI2SSrm, FrameIndex, MI);
451 case X86::SQRTSSr: return MakeRMInst(X86::SQRTSSm, FrameIndex, MI);
452 case X86::SQRTSDr: return MakeRMInst(X86::SQRTSDm, FrameIndex, MI);
453 case X86::ADDSSrr: return MakeRMInst(X86::ADDSSrm, FrameIndex, MI);
454 case X86::ADDSDrr: return MakeRMInst(X86::ADDSDrm, FrameIndex, MI);
455 case X86::MULSSrr: return MakeRMInst(X86::MULSSrm, FrameIndex, MI);
456 case X86::MULSDrr: return MakeRMInst(X86::MULSDrm, FrameIndex, MI);
457 case X86::DIVSSrr: return MakeRMInst(X86::DIVSSrm, FrameIndex, MI);
458 case X86::DIVSDrr: return MakeRMInst(X86::DIVSDrm, FrameIndex, MI);
459 case X86::SUBSSrr: return MakeRMInst(X86::SUBSSrm, FrameIndex, MI);
460 case X86::SUBSDrr: return MakeRMInst(X86::SUBSDrm, FrameIndex, MI);
461 case X86::CMPSSrr: return MakeRMInst(X86::CMPSSrm, FrameIndex, MI);
462 case X86::CMPSDrr: return MakeRMInst(X86::CMPSDrm, FrameIndex, MI);
463 case X86::Int_CMPSSrr: return MakeRMInst(X86::Int_CMPSSrm, FrameIndex, MI);
464 case X86::Int_CMPSDrr: return MakeRMInst(X86::Int_CMPSDrm, FrameIndex, MI);
465 case X86::UCOMISSrr: return MakeRMInst(X86::UCOMISSrm, FrameIndex, MI);
466 case X86::UCOMISDrr: return MakeRMInst(X86::UCOMISDrm, FrameIndex, MI);
467 case X86::Int_UCOMISSrr:
468 return MakeRMInst(X86::Int_UCOMISSrm, FrameIndex, MI);
469 case X86::Int_UCOMISDrr:
470 return MakeRMInst(X86::Int_UCOMISDrm, FrameIndex, MI);
471 case X86::Int_COMISSrr:
472 return MakeRMInst(X86::Int_COMISSrm, FrameIndex, MI);
473 case X86::Int_COMISDrr:
474 return MakeRMInst(X86::Int_COMISDrm, FrameIndex, MI);
475 // Packed SSE instructions
476 case X86::MOVAPSrr: return MakeRMInst(X86::MOVAPSrm, FrameIndex, MI);
477 case X86::MOVAPDrr: return MakeRMInst(X86::MOVAPDrm, FrameIndex, MI);
478 case X86::MOVUPSrr: return MakeRMInst(X86::MOVUPSrm, FrameIndex, MI);
479 case X86::MOVUPDrr: return MakeRMInst(X86::MOVUPDrm, FrameIndex, MI);
480 case X86::MOVSHDUPrr:return MakeRMInst(X86::MOVSHDUPrm, FrameIndex, MI);
481 case X86::MOVSLDUPrr:return MakeRMInst(X86::MOVSLDUPrm, FrameIndex, MI);
482 case X86::MOVDDUPrr: return MakeRMInst(X86::MOVDDUPrm, FrameIndex, MI);
483 case X86::CVTDQ2PSrr:return MakeRMInst(X86::CVTDQ2PSrm, FrameIndex, MI);
484 case X86::CVTDQ2PDrr:return MakeRMInst(X86::CVTDQ2PDrm, FrameIndex, MI);
485 case X86::CVTPS2DQrr:return MakeRMInst(X86::CVTPS2DQrm, FrameIndex, MI);
486 case X86::CVTTPS2DQrr:return MakeRMInst(X86::CVTTPS2DQrm, FrameIndex, MI);
487 case X86::CVTPD2DQrr:return MakeRMInst(X86::CVTPD2DQrm, FrameIndex, MI);
488 case X86::CVTTPD2DQrr:return MakeRMInst(X86::CVTTPD2DQrm, FrameIndex, MI);
489 case X86::CVTPS2PDrr:return MakeRMInst(X86::CVTPS2PDrm, FrameIndex, MI);
490 case X86::CVTPD2PSrr:return MakeRMInst(X86::CVTPD2PSrm, FrameIndex, MI);
491 case X86::Int_CVTSI2SDrr:
492 return MakeRMInst(X86::Int_CVTSI2SDrm, FrameIndex, MI);
493 case X86::Int_CVTSD2SSrr:
494 return MakeRMInst(X86::Int_CVTSD2SSrm, FrameIndex, MI);
495 case X86::Int_CVTSS2SDrr:
496 return MakeRMInst(X86::Int_CVTSS2SDrm, FrameIndex, MI);
497 case X86::ADDPSrr: return MakeRMInst(X86::ADDPSrm, FrameIndex, MI);
498 case X86::ADDPDrr: return MakeRMInst(X86::ADDPDrm, FrameIndex, MI);
499 case X86::SUBPSrr: return MakeRMInst(X86::SUBPSrm, FrameIndex, MI);
500 case X86::SUBPDrr: return MakeRMInst(X86::SUBPDrm, FrameIndex, MI);
501 case X86::MULPSrr: return MakeRMInst(X86::MULPSrm, FrameIndex, MI);
502 case X86::MULPDrr: return MakeRMInst(X86::MULPDrm, FrameIndex, MI);
503 case X86::DIVPSrr: return MakeRMInst(X86::DIVPSrm, FrameIndex, MI);
504 case X86::DIVPDrr: return MakeRMInst(X86::DIVPDrm, FrameIndex, MI);
505 case X86::ADDSUBPSrr:return MakeRMInst(X86::ADDSUBPSrm, FrameIndex, MI);
506 case X86::ADDSUBPDrr:return MakeRMInst(X86::ADDSUBPDrm, FrameIndex, MI);
507 case X86::HADDPSrr: return MakeRMInst(X86::HADDPSrm, FrameIndex, MI);
508 case X86::HADDPDrr: return MakeRMInst(X86::HADDPDrm, FrameIndex, MI);
509 case X86::HSUBPSrr: return MakeRMInst(X86::HSUBPSrm, FrameIndex, MI);
510 case X86::HSUBPDrr: return MakeRMInst(X86::HSUBPDrm, FrameIndex, MI);
511 case X86::SQRTPSr: return MakeRMInst(X86::SQRTPSm, FrameIndex, MI);
512 case X86::SQRTPDr: return MakeRMInst(X86::SQRTPDm, FrameIndex, MI);
513 case X86::RSQRTPSr: return MakeRMInst(X86::RSQRTPSm, FrameIndex, MI);
514 case X86::RCPPSr: return MakeRMInst(X86::RCPPSm, FrameIndex, MI);
515 case X86::MAXPSrr: return MakeRMInst(X86::MAXPSrm, FrameIndex, MI);
516 case X86::MAXPDrr: return MakeRMInst(X86::MAXPDrm, FrameIndex, MI);
517 case X86::MINPSrr: return MakeRMInst(X86::MINPSrm, FrameIndex, MI);
518 case X86::MINPDrr: return MakeRMInst(X86::MINPDrm, FrameIndex, MI);
519 case X86::ANDPSrr: return MakeRMInst(X86::ANDPSrm, FrameIndex, MI);
520 case X86::ANDPDrr: return MakeRMInst(X86::ANDPDrm, FrameIndex, MI);
521 case X86::ORPSrr: return MakeRMInst(X86::ORPSrm, FrameIndex, MI);
522 case X86::ORPDrr: return MakeRMInst(X86::ORPDrm, FrameIndex, MI);
523 case X86::XORPSrr: return MakeRMInst(X86::XORPSrm, FrameIndex, MI);
524 case X86::XORPDrr: return MakeRMInst(X86::XORPDrm, FrameIndex, MI);
525 case X86::ANDNPSrr: return MakeRMInst(X86::ANDNPSrm, FrameIndex, MI);
526 case X86::ANDNPDrr: return MakeRMInst(X86::ANDNPDrm, FrameIndex, MI);
527 case X86::CMPPSrri: return MakeRMIInst(X86::CMPPSrmi, FrameIndex, MI);
528 case X86::CMPPDrri: return MakeRMIInst(X86::CMPPDrmi, FrameIndex, MI);
529 case X86::SHUFPSrri: return MakeRMIInst(X86::SHUFPSrmi, FrameIndex, MI);
530 case X86::SHUFPDrri: return MakeRMIInst(X86::SHUFPDrmi, FrameIndex, MI);
531 case X86::UNPCKHPSrr:return MakeRMInst(X86::UNPCKHPSrm, FrameIndex, MI);
532 case X86::UNPCKHPDrr:return MakeRMInst(X86::UNPCKHPDrm, FrameIndex, MI);
533 case X86::UNPCKLPSrr:return MakeRMInst(X86::UNPCKLPSrm, FrameIndex, MI);
534 case X86::UNPCKLPDrr:return MakeRMInst(X86::UNPCKLPDrm, FrameIndex, MI);
535 case X86::PADDBrr: return MakeRMInst(X86::PADDBrm, FrameIndex, MI);
536 case X86::PADDWrr: return MakeRMInst(X86::PADDWrm, FrameIndex, MI);
537 case X86::PADDDrr: return MakeRMInst(X86::PADDDrm, FrameIndex, MI);
538 case X86::PADDSBrr: return MakeRMInst(X86::PADDSBrm, FrameIndex, MI);
539 case X86::PADDSWrr: return MakeRMInst(X86::PADDSWrm, FrameIndex, MI);
540 case X86::PSUBBrr: return MakeRMInst(X86::PSUBBrm, FrameIndex, MI);
541 case X86::PSUBWrr: return MakeRMInst(X86::PSUBWrm, FrameIndex, MI);
542 case X86::PSUBDrr: return MakeRMInst(X86::PSUBDrm, FrameIndex, MI);
543 case X86::PSUBSBrr: return MakeRMInst(X86::PSUBSBrm, FrameIndex, MI);
544 case X86::PSUBSWrr: return MakeRMInst(X86::PSUBSWrm, FrameIndex, MI);
545 case X86::PMULHUWrr: return MakeRMInst(X86::PMULHUWrm, FrameIndex, MI);
546 case X86::PMULHWrr: return MakeRMInst(X86::PMULHWrm, FrameIndex, MI);
547 case X86::PMULLWrr: return MakeRMInst(X86::PMULLWrm, FrameIndex, MI);
548 case X86::PMULUDQrr: return MakeRMInst(X86::PMULUDQrm, FrameIndex, MI);
549 case X86::PMADDWDrr: return MakeRMInst(X86::PMADDWDrm, FrameIndex, MI);
550 case X86::PAVGBrr: return MakeRMInst(X86::PAVGBrm, FrameIndex, MI);
551 case X86::PAVGWrr: return MakeRMInst(X86::PAVGWrm, FrameIndex, MI);
552 case X86::PMAXUBrr: return MakeRMInst(X86::PMAXUBrm, FrameIndex, MI);
553 case X86::PMAXSWrr: return MakeRMInst(X86::PMAXSWrm, FrameIndex, MI);
554 case X86::PMINUBrr: return MakeRMInst(X86::PMINUBrm, FrameIndex, MI);
555 case X86::PMINSWrr: return MakeRMInst(X86::PMINSWrm, FrameIndex, MI);
556 case X86::PSADBWrr: return MakeRMInst(X86::PSADBWrm, FrameIndex, MI);
557 case X86::PSLLWrr: return MakeRMInst(X86::PSLLWrm, FrameIndex, MI);
558 case X86::PSLLDrr: return MakeRMInst(X86::PSLLDrm, FrameIndex, MI);
559 case X86::PSLLQrr: return MakeRMInst(X86::PSLLQrm, FrameIndex, MI);
560 case X86::PSRLWrr: return MakeRMInst(X86::PSRLWrm, FrameIndex, MI);
561 case X86::PSRLDrr: return MakeRMInst(X86::PSRLDrm, FrameIndex, MI);
562 case X86::PSRLQrr: return MakeRMInst(X86::PSRLQrm, FrameIndex, MI);
563 case X86::PSRAWrr: return MakeRMInst(X86::PSRAWrm, FrameIndex, MI);
564 case X86::PSRADrr: return MakeRMInst(X86::PSRADrm, FrameIndex, MI);
565 case X86::PANDrr: return MakeRMInst(X86::PANDrm, FrameIndex, MI);
566 case X86::PORrr: return MakeRMInst(X86::PORrm, FrameIndex, MI);
567 case X86::PXORrr: return MakeRMInst(X86::PXORrm, FrameIndex, MI);
568 case X86::PANDNrr: return MakeRMInst(X86::PANDNrm, FrameIndex, MI);
569 case X86::PCMPEQBrr: return MakeRMInst(X86::PCMPEQBrm, FrameIndex, MI);
570 case X86::PCMPEQWrr: return MakeRMInst(X86::PCMPEQWrm, FrameIndex, MI);
571 case X86::PCMPEQDrr: return MakeRMInst(X86::PCMPEQDrm, FrameIndex, MI);
572 case X86::PCMPGTBrr: return MakeRMInst(X86::PCMPGTBrm, FrameIndex, MI);
573 case X86::PCMPGTWrr: return MakeRMInst(X86::PCMPGTWrm, FrameIndex, MI);
574 case X86::PCMPGTDrr: return MakeRMInst(X86::PCMPGTDrm, FrameIndex, MI);
575 case X86::PACKSSWBrr:return MakeRMInst(X86::PACKSSWBrm, FrameIndex, MI);
576 case X86::PACKSSDWrr:return MakeRMInst(X86::PACKSSDWrm, FrameIndex, MI);
577 case X86::PACKUSWBrr:return MakeRMInst(X86::PACKUSWBrm, FrameIndex, MI);
578 case X86::PSHUFDri: return MakeRMIInst(X86::PSHUFDmi, FrameIndex, MI);
579 case X86::PSHUFHWri: return MakeRMIInst(X86::PSHUFHWmi, FrameIndex, MI);
580 case X86::PSHUFLWri: return MakeRMIInst(X86::PSHUFLWmi, FrameIndex, MI);
581 case X86::PUNPCKLBWrr:return MakeRMInst(X86::PUNPCKLBWrm, FrameIndex, MI);
582 case X86::PUNPCKLWDrr:return MakeRMInst(X86::PUNPCKLWDrm, FrameIndex, MI);
583 case X86::PUNPCKLDQrr:return MakeRMInst(X86::PUNPCKLDQrm, FrameIndex, MI);
584 case X86::PUNPCKLQDQrr:return MakeRMInst(X86::PUNPCKLQDQrm, FrameIndex, MI);
585 case X86::PUNPCKHBWrr:return MakeRMInst(X86::PUNPCKHBWrm, FrameIndex, MI);
586 case X86::PUNPCKHWDrr:return MakeRMInst(X86::PUNPCKHWDrm, FrameIndex, MI);
587 case X86::PUNPCKHDQrr:return MakeRMInst(X86::PUNPCKHDQrm, FrameIndex, MI);
588 case X86::PUNPCKHQDQrr:return MakeRMInst(X86::PUNPCKHQDQrm, FrameIndex, MI);
589 case X86::PINSRWrri: return MakeRMIInst(X86::PINSRWrmi, FrameIndex, MI);
590 // Alias packed SSE instructions
591 case X86::MOVSS2PSrr:return MakeRMInst(X86::MOVSS2PSrm, FrameIndex, MI);
592 case X86::MOVSD2PDrr:return MakeRMInst(X86::MOVSD2PDrm, FrameIndex, MI);
593 case X86::MOVDI2PDIrr:return MakeRMInst(X86::MOVDI2PDIrm, FrameIndex, MI);
594 case X86::MOVQI2PQIrr:return MakeRMInst(X86::MOVQI2PQIrm, FrameIndex, MI);
597 if (PrintFailedFusing)
598 std::cerr << "We failed to fuse ("
599 << ((i == 1) ? "r" : "s") << "): " << *MI;
603 //===----------------------------------------------------------------------===//
604 // Stack Frame Processing methods
605 //===----------------------------------------------------------------------===//
607 // hasFP - Return true if the specified function should have a dedicated frame
608 // pointer register. This is true if the function has variable sized allocas or
609 // if frame pointer elimination is disabled.
611 static bool hasFP(MachineFunction &MF) {
612 return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
615 void X86RegisterInfo::
616 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
617 MachineBasicBlock::iterator I) const {
619 // If we have a frame pointer, turn the adjcallstackup instruction into a
620 // 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
622 MachineInstr *Old = I;
623 unsigned Amount = Old->getOperand(0).getImmedValue();
625 // We need to keep the stack aligned properly. To do this, we round the
626 // amount of space needed for the outgoing arguments up to the next
627 // alignment boundary.
628 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
629 Amount = (Amount+Align-1)/Align*Align;
631 MachineInstr *New = 0;
632 if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
633 New=BuildMI(X86::SUB32ri, 1, X86::ESP, MachineOperand::UseAndDef)
636 assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
637 // factor out the amount the callee already popped.
638 unsigned CalleeAmt = Old->getOperand(1).getImmedValue();
641 unsigned Opc = Amount < 128 ? X86::ADD32ri8 : X86::ADD32ri;
642 New = BuildMI(Opc, 1, X86::ESP,
643 MachineOperand::UseAndDef).addImm(Amount);
647 // Replace the pseudo instruction with a new instruction...
648 if (New) MBB.insert(I, New);
650 } else if (I->getOpcode() == X86::ADJCALLSTACKUP) {
651 // If we are performing frame pointer elimination and if the callee pops
652 // something off the stack pointer, add it back. We do this until we have
653 // more advanced stack pointer tracking ability.
654 if (unsigned CalleeAmt = I->getOperand(1).getImmedValue()) {
655 unsigned Opc = CalleeAmt < 128 ? X86::SUB32ri8 : X86::SUB32ri;
657 BuildMI(Opc, 1, X86::ESP,
658 MachineOperand::UseAndDef).addImm(CalleeAmt);
666 void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{
668 MachineInstr &MI = *II;
669 MachineFunction &MF = *MI.getParent()->getParent();
670 while (!MI.getOperand(i).isFrameIndex()) {
672 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
675 int FrameIndex = MI.getOperand(i).getFrameIndex();
677 // This must be part of a four operand memory reference. Replace the
678 // FrameIndex with base register with EBP. Add add an offset to the offset.
679 MI.getOperand(i).ChangeToRegister(hasFP(MF) ? X86::EBP : X86::ESP);
681 // Now add the frame object offset to the offset from EBP.
682 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
683 MI.getOperand(i+3).getImmedValue()+4;
686 Offset += MF.getFrameInfo()->getStackSize();
688 Offset += 4; // Skip the saved EBP
690 MI.getOperand(i+3).ChangeToImmediate(Offset);
694 X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
696 // Create a frame entry for the EBP register that must be saved.
697 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, -8);
698 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
699 "Slot for EBP register must be last in order to be found!");
703 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
704 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
705 MachineBasicBlock::iterator MBBI = MBB.begin();
706 MachineFrameInfo *MFI = MF.getFrameInfo();
709 // Get the number of bytes to allocate from the FrameInfo
710 unsigned NumBytes = MFI->getStackSize();
711 if (MFI->hasCalls() || MF.getFrameInfo()->hasVarSizedObjects()) {
712 // When we have no frame pointer, we reserve argument space for call sites
713 // in the function immediately on entry to the current function. This
714 // eliminates the need for add/sub ESP brackets around call sites.
717 NumBytes += MFI->getMaxCallFrameSize();
719 // Round the size to a multiple of the alignment (don't forget the 4 byte
721 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
722 NumBytes = ((NumBytes+4)+Align-1)/Align*Align - 4;
725 // Update frame info to pretend that this is part of the stack...
726 MFI->setStackSize(NumBytes);
728 if (NumBytes) { // adjust stack pointer: ESP -= numbytes
729 unsigned Opc = NumBytes < 128 ? X86::SUB32ri8 : X86::SUB32ri;
730 MI = BuildMI(Opc, 1, X86::ESP,MachineOperand::UseAndDef).addImm(NumBytes);
731 MBB.insert(MBBI, MI);
735 // Get the offset of the stack slot for the EBP register... which is
736 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
737 int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexBegin())+4;
739 // Save EBP into the appropriate stack slot...
740 MI = addRegOffset(BuildMI(X86::MOV32mr, 5), // mov [ESP-<offset>], EBP
741 X86::ESP, EBPOffset+NumBytes).addReg(X86::EBP);
742 MBB.insert(MBBI, MI);
744 // Update EBP with the new base value...
745 if (NumBytes == 4) // mov EBP, ESP
746 MI = BuildMI(X86::MOV32rr, 2, X86::EBP).addReg(X86::ESP);
747 else // lea EBP, [ESP+StackSize]
748 MI = addRegOffset(BuildMI(X86::LEA32r, 5, X86::EBP), X86::ESP,NumBytes-4);
750 MBB.insert(MBBI, MI);
754 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
755 MachineBasicBlock &MBB) const {
756 const MachineFrameInfo *MFI = MF.getFrameInfo();
757 MachineBasicBlock::iterator MBBI = prior(MBB.end());
759 switch (MBBI->getOpcode()) {
764 case X86::TAILJMPm: break; // These are ok
766 assert(0 && "Can only insert epilog into returning blocks");
770 // Get the offset of the stack slot for the EBP register... which is
771 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
772 int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexEnd()-1)+4;
775 BuildMI(MBB, MBBI, X86::MOV32rr, 1,X86::ESP).addReg(X86::EBP);
778 BuildMI(MBB, MBBI, X86::POP32r, 0, X86::EBP);
780 // Get the number of bytes allocated from the FrameInfo...
781 unsigned NumBytes = MFI->getStackSize();
783 if (NumBytes) { // adjust stack pointer back: ESP += numbytes
784 // If there is an ADD32ri or SUB32ri of ESP immediately before this
785 // instruction, merge the two instructions.
786 if (MBBI != MBB.begin()) {
787 MachineBasicBlock::iterator PI = prior(MBBI);
788 if ((PI->getOpcode() == X86::ADD32ri ||
789 PI->getOpcode() == X86::ADD32ri8) &&
790 PI->getOperand(0).getReg() == X86::ESP) {
791 NumBytes += PI->getOperand(1).getImmedValue();
793 } else if ((PI->getOpcode() == X86::SUB32ri ||
794 PI->getOpcode() == X86::SUB32ri8) &&
795 PI->getOperand(0).getReg() == X86::ESP) {
796 NumBytes -= PI->getOperand(1).getImmedValue();
798 } else if (PI->getOpcode() == X86::ADJSTACKPTRri) {
799 NumBytes += PI->getOperand(1).getImmedValue();
805 unsigned Opc = NumBytes < 128 ? X86::ADD32ri8 : X86::ADD32ri;
806 BuildMI(MBB, MBBI, Opc, 2)
807 .addReg(X86::ESP, MachineOperand::UseAndDef).addImm(NumBytes);
808 } else if ((int)NumBytes < 0) {
809 unsigned Opc = -NumBytes < 128 ? X86::SUB32ri8 : X86::SUB32ri;
810 BuildMI(MBB, MBBI, Opc, 2)
811 .addReg(X86::ESP, MachineOperand::UseAndDef).addImm(-NumBytes);
817 unsigned X86RegisterInfo::getRARegister() const {
818 return X86::ST0; // use a non-register register
821 unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
822 return hasFP(MF) ? X86::EBP : X86::ESP;
826 unsigned getX86SubSuperRegister(unsigned Reg, MVT::ValueType VT, bool High) {
833 case X86::AH: case X86::AL: case X86::AX: case X86::EAX:
835 case X86::DH: case X86::DL: case X86::DX: case X86::EDX:
837 case X86::CH: case X86::CL: case X86::CX: case X86::ECX:
839 case X86::BH: case X86::BL: case X86::BX: case X86::EBX:
845 case X86::AH: case X86::AL: case X86::AX: case X86::EAX:
847 case X86::DH: case X86::DL: case X86::DX: case X86::EDX:
849 case X86::CH: case X86::CL: case X86::CX: case X86::ECX:
851 case X86::BH: case X86::BL: case X86::BX: case X86::EBX:
858 case X86::AH: case X86::AL: case X86::AX: case X86::EAX:
860 case X86::DH: case X86::DL: case X86::DX: case X86::EDX:
862 case X86::CH: case X86::CL: case X86::CX: case X86::ECX:
864 case X86::BH: case X86::BL: case X86::BX: case X86::EBX:
877 default: return true;
878 case X86::AH: case X86::AL: case X86::AX: case X86::EAX:
880 case X86::DH: case X86::DL: case X86::DX: case X86::EDX:
882 case X86::CH: case X86::CL: case X86::CX: case X86::ECX:
884 case X86::BH: case X86::BL: case X86::BX: case X86::EBX:
901 #include "X86GenRegisterInfo.inc"