1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineLocation.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/Target/TargetAsmInfo.h"
34 #include "llvm/Target/TargetFrameInfo.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/STLExtras.h"
40 #include "llvm/Support/Compiler.h"
43 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
44 const TargetInstrInfo &tii)
45 : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP),
47 // Cache some information.
48 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
49 Is64Bit = Subtarget->is64Bit();
50 IsWin64 = Subtarget->isTargetWin64();
51 StackAlign = TM.getFrameInfo()->getStackAlignment();
63 // getDwarfRegNum - This function maps LLVM register identifiers to the
64 // Dwarf specific numbering, used in debug info and exception tables.
66 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
67 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
68 unsigned Flavour = DWARFFlavour::X86_64;
69 if (!Subtarget->is64Bit()) {
70 if (Subtarget->isTargetDarwin()) {
72 Flavour = DWARFFlavour::X86_32_DarwinEH;
74 Flavour = DWARFFlavour::X86_32_Generic;
75 } else if (Subtarget->isTargetCygMing()) {
76 // Unsupported by now, just quick fallback
77 Flavour = DWARFFlavour::X86_32_Generic;
79 Flavour = DWARFFlavour::X86_32_Generic;
83 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
86 // getX86RegNum - This function maps LLVM register identifiers to their X86
87 // specific numbering, which is used in various places encoding instructions.
89 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
91 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
92 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
93 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
94 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
95 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
97 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
99 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
101 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
104 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
106 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
108 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
110 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
112 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
114 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
116 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
118 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
121 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
122 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
123 return RegNo-X86::ST0;
125 case X86::XMM0: case X86::XMM8: case X86::MM0:
127 case X86::XMM1: case X86::XMM9: case X86::MM1:
129 case X86::XMM2: case X86::XMM10: case X86::MM2:
131 case X86::XMM3: case X86::XMM11: case X86::MM3:
133 case X86::XMM4: case X86::XMM12: case X86::MM4:
135 case X86::XMM5: case X86::XMM13: case X86::MM5:
137 case X86::XMM6: case X86::XMM14: case X86::MM6:
139 case X86::XMM7: case X86::XMM15: case X86::MM7:
143 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
144 assert(0 && "Register allocator hasn't allocated reg correctly yet!");
149 const TargetRegisterClass *
150 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
151 if (RC == &X86::CCRRegClass) {
153 return &X86::GR64RegClass;
155 return &X86::GR32RegClass;
161 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
162 bool callsEHReturn = false;
165 const MachineFrameInfo *MFI = MF->getFrameInfo();
166 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
167 callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
170 static const unsigned CalleeSavedRegs32Bit[] = {
171 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
174 static const unsigned CalleeSavedRegs32EHRet[] = {
175 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
178 static const unsigned CalleeSavedRegs64Bit[] = {
179 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
182 static const unsigned CalleeSavedRegs64EHRet[] = {
183 X86::RAX, X86::RDX, X86::RBX, X86::R12,
184 X86::R13, X86::R14, X86::R15, X86::RBP, 0
187 static const unsigned CalleeSavedRegsWin64[] = {
188 X86::RBX, X86::RBP, X86::RDI, X86::RSI,
189 X86::R12, X86::R13, X86::R14, X86::R15,
190 X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9,
191 X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13,
192 X86::XMM14, X86::XMM15, 0
197 return CalleeSavedRegsWin64;
199 return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit);
201 return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit);
205 const TargetRegisterClass* const*
206 X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
207 bool callsEHReturn = false;
210 const MachineFrameInfo *MFI = MF->getFrameInfo();
211 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
212 callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
215 static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
216 &X86::GR32RegClass, &X86::GR32RegClass,
217 &X86::GR32RegClass, &X86::GR32RegClass, 0
219 static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
220 &X86::GR32RegClass, &X86::GR32RegClass,
221 &X86::GR32RegClass, &X86::GR32RegClass,
222 &X86::GR32RegClass, &X86::GR32RegClass, 0
224 static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
225 &X86::GR64RegClass, &X86::GR64RegClass,
226 &X86::GR64RegClass, &X86::GR64RegClass,
227 &X86::GR64RegClass, &X86::GR64RegClass, 0
229 static const TargetRegisterClass * const CalleeSavedRegClasses64EHRet[] = {
230 &X86::GR64RegClass, &X86::GR64RegClass,
231 &X86::GR64RegClass, &X86::GR64RegClass,
232 &X86::GR64RegClass, &X86::GR64RegClass,
233 &X86::GR64RegClass, &X86::GR64RegClass, 0
235 static const TargetRegisterClass * const CalleeSavedRegClassesWin64[] = {
236 &X86::GR64RegClass, &X86::GR64RegClass,
237 &X86::GR64RegClass, &X86::GR64RegClass,
238 &X86::GR64RegClass, &X86::GR64RegClass,
239 &X86::GR64RegClass, &X86::GR64RegClass,
240 &X86::VR128RegClass, &X86::VR128RegClass,
241 &X86::VR128RegClass, &X86::VR128RegClass,
242 &X86::VR128RegClass, &X86::VR128RegClass,
243 &X86::VR128RegClass, &X86::VR128RegClass,
244 &X86::VR128RegClass, &X86::VR128RegClass, 0
249 return CalleeSavedRegClassesWin64;
251 return (callsEHReturn ?
252 CalleeSavedRegClasses64EHRet : CalleeSavedRegClasses64Bit);
254 return (callsEHReturn ?
255 CalleeSavedRegClasses32EHRet : CalleeSavedRegClasses32Bit);
259 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
260 BitVector Reserved(getNumRegs());
261 Reserved.set(X86::RSP);
262 Reserved.set(X86::ESP);
263 Reserved.set(X86::SP);
264 Reserved.set(X86::SPL);
266 Reserved.set(X86::RBP);
267 Reserved.set(X86::EBP);
268 Reserved.set(X86::BP);
269 Reserved.set(X86::BPL);
274 //===----------------------------------------------------------------------===//
275 // Stack Frame Processing methods
276 //===----------------------------------------------------------------------===//
278 static unsigned calculateMaxStackAlignment(const MachineFrameInfo *FFI) {
279 unsigned MaxAlign = 0;
280 for (int i = FFI->getObjectIndexBegin(),
281 e = FFI->getObjectIndexEnd(); i != e; ++i) {
282 if (FFI->isDeadObjectIndex(i))
284 unsigned Align = FFI->getObjectAlignment(i);
285 MaxAlign = std::max(MaxAlign, Align);
291 // hasFP - Return true if the specified function should have a dedicated frame
292 // pointer register. This is true if the function has variable sized allocas or
293 // if frame pointer elimination is disabled.
295 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
296 const MachineFrameInfo *MFI = MF.getFrameInfo();
297 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
299 return (NoFramePointerElim ||
300 needsStackRealignment(MF) ||
301 MFI->hasVarSizedObjects() ||
302 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
303 (MMI && MMI->callsUnwindInit()));
306 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
307 const MachineFrameInfo *MFI = MF.getFrameInfo();;
309 // FIXME: Currently we don't support stack realignment for functions with
310 // variable-sized allocas
311 return (RealignStack &&
312 (MFI->getMaxAlignment() > StackAlign &&
313 !MFI->hasVarSizedObjects()));
316 bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
317 return !MF.getFrameInfo()->hasVarSizedObjects();
321 X86RegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
322 int Offset = MF.getFrameInfo()->getObjectOffset(FI) + SlotSize;
323 uint64_t StackSize = MF.getFrameInfo()->getStackSize();
325 if (needsStackRealignment(MF)) {
327 // Skip the saved EBP
330 unsigned Align = MF.getFrameInfo()->getObjectAlignment(FI);
331 assert( (-(Offset + StackSize)) % Align == 0);
332 return Offset + StackSize;
335 // FIXME: Support tail calls
338 return Offset + StackSize;
340 // Skip the saved EBP
343 // Skip the RETADDR move area
344 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
345 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
346 if (TailCallReturnAddrDelta < 0) Offset -= TailCallReturnAddrDelta;
352 void X86RegisterInfo::
353 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
354 MachineBasicBlock::iterator I) const {
355 if (!hasReservedCallFrame(MF)) {
356 // If the stack pointer can be changed after prologue, turn the
357 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
358 // adjcallstackdown instruction into 'add ESP, <amt>'
359 // TODO: consider using push / pop instead of sub + store / add
360 MachineInstr *Old = I;
361 uint64_t Amount = Old->getOperand(0).getImm();
363 // We need to keep the stack aligned properly. To do this, we round the
364 // amount of space needed for the outgoing arguments up to the next
365 // alignment boundary.
366 Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
368 MachineInstr *New = 0;
369 if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
370 New = BuildMI(MF, TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri),
371 StackPtr).addReg(StackPtr).addImm(Amount);
373 assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
374 // factor out the amount the callee already popped.
375 uint64_t CalleeAmt = Old->getOperand(1).getImm();
378 unsigned Opc = (Amount < 128) ?
379 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
380 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
381 New = BuildMI(MF, TII.get(Opc), StackPtr)
382 .addReg(StackPtr).addImm(Amount);
386 // Replace the pseudo instruction with a new instruction...
387 if (New) MBB.insert(I, New);
389 } else if (I->getOpcode() == X86::ADJCALLSTACKUP) {
390 // If we are performing frame pointer elimination and if the callee pops
391 // something off the stack pointer, add it back. We do this until we have
392 // more advanced stack pointer tracking ability.
393 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
394 unsigned Opc = (CalleeAmt < 128) ?
395 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
396 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
398 BuildMI(MF, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(CalleeAmt);
406 void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
407 int SPAdj, RegScavenger *RS) const{
408 assert(SPAdj == 0 && "Unexpected");
411 MachineInstr &MI = *II;
412 MachineFunction &MF = *MI.getParent()->getParent();
413 while (!MI.getOperand(i).isFrameIndex()) {
415 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
418 int FrameIndex = MI.getOperand(i).getIndex();
421 if (needsStackRealignment(MF))
422 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
424 BasePtr = (hasFP(MF) ? FramePtr : StackPtr);
426 // This must be part of a four operand memory reference. Replace the
427 // FrameIndex with base register with EBP. Add an offset to the offset.
428 MI.getOperand(i).ChangeToRegister(BasePtr, false);
430 // Now add the frame object offset to the offset from EBP. Offset is a
432 int Offset = getFrameIndexOffset(MF, FrameIndex) +
433 (int)(MI.getOperand(i+3).getImm());
435 MI.getOperand(i+3).ChangeToImmediate(Offset);
439 X86RegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
440 RegScavenger *RS) const {
441 MachineFrameInfo *FFI = MF.getFrameInfo();
443 // Calculate and set max stack object alignment early, so we can decide
444 // whether we will need stack realignment (and thus FP).
445 unsigned MaxAlign = std::max(FFI->getMaxAlignment(),
446 calculateMaxStackAlignment(FFI));
448 FFI->setMaxAlignment(MaxAlign);
452 X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
453 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
454 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
455 if (TailCallReturnAddrDelta < 0) {
456 // create RETURNADDR area
466 CreateFixedObject(-TailCallReturnAddrDelta,
467 (-1*SlotSize)+TailCallReturnAddrDelta);
470 assert((TailCallReturnAddrDelta <= 0) &&
471 "The Delta should always be zero or negative");
472 // Create a frame entry for the EBP register that must be saved.
473 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize,
475 TailCallReturnAddrDelta);
476 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
477 "Slot for EBP register must be last in order to be found!");
481 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
482 /// stack pointer by a constant value.
484 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
485 unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
486 const TargetInstrInfo &TII) {
487 bool isSub = NumBytes < 0;
488 uint64_t Offset = isSub ? -NumBytes : NumBytes;
491 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
492 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
494 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
495 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
496 uint64_t Chunk = (1LL << 31) - 1;
499 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
500 BuildMI(MBB, MBBI, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(ThisVal);
505 // mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
507 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
508 unsigned StackPtr, uint64_t *NumBytes = NULL) {
509 if (MBBI == MBB.begin()) return;
511 MachineBasicBlock::iterator PI = prior(MBBI);
512 unsigned Opc = PI->getOpcode();
513 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
514 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
515 PI->getOperand(0).getReg() == StackPtr) {
517 *NumBytes += PI->getOperand(2).getImm();
519 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
520 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
521 PI->getOperand(0).getReg() == StackPtr) {
523 *NumBytes -= PI->getOperand(2).getImm();
528 // mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
530 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
531 MachineBasicBlock::iterator &MBBI,
532 unsigned StackPtr, uint64_t *NumBytes = NULL) {
535 if (MBBI == MBB.end()) return;
537 MachineBasicBlock::iterator NI = next(MBBI);
538 if (NI == MBB.end()) return;
540 unsigned Opc = NI->getOpcode();
541 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
542 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
543 NI->getOperand(0).getReg() == StackPtr) {
545 *NumBytes -= NI->getOperand(2).getImm();
548 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
549 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
550 NI->getOperand(0).getReg() == StackPtr) {
552 *NumBytes += NI->getOperand(2).getImm();
558 /// mergeSPUpdates - Checks the instruction before/after the passed
559 /// instruction. If it is an ADD/SUB instruction it is deleted
560 /// argument and the stack adjustment is returned as a positive value for ADD
561 /// and a negative for SUB.
562 static int mergeSPUpdates(MachineBasicBlock &MBB,
563 MachineBasicBlock::iterator &MBBI,
565 bool doMergeWithPrevious) {
567 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
568 (!doMergeWithPrevious && MBBI == MBB.end()))
573 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
574 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : next(MBBI);
575 unsigned Opc = PI->getOpcode();
576 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
577 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
578 PI->getOperand(0).getReg() == StackPtr){
579 Offset += PI->getOperand(2).getImm();
581 if (!doMergeWithPrevious) MBBI = NI;
582 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
583 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
584 PI->getOperand(0).getReg() == StackPtr) {
585 Offset -= PI->getOperand(2).getImm();
587 if (!doMergeWithPrevious) MBBI = NI;
593 void X86RegisterInfo::emitFrameMoves(MachineFunction &MF,
594 unsigned FrameLabelId,
595 unsigned ReadyLabelId) const {
596 MachineFrameInfo *MFI = MF.getFrameInfo();
597 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
601 uint64_t StackSize = MFI->getStackSize();
602 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
603 const TargetData *TD = MF.getTarget().getTargetData();
605 // Calculate amount of bytes used for return address storing
607 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
608 TargetFrameInfo::StackGrowsUp ?
609 TD->getPointerSize() : -TD->getPointerSize());
612 // Show update of SP.
615 MachineLocation SPDst(MachineLocation::VirtualFP);
616 MachineLocation SPSrc(MachineLocation::VirtualFP, 2*stackGrowth);
617 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
619 MachineLocation SPDst(MachineLocation::VirtualFP);
620 MachineLocation SPSrc(MachineLocation::VirtualFP,
621 -StackSize+stackGrowth);
622 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
625 //FIXME: Verify & implement for FP
626 MachineLocation SPDst(StackPtr);
627 MachineLocation SPSrc(StackPtr, stackGrowth);
628 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
631 // Add callee saved registers to move list.
632 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
634 // FIXME: This is dirty hack. The code itself is pretty mess right now.
635 // It should be rewritten from scratch and generalized sometimes.
637 // Determine maximum offset (minumum due to stack growth)
638 int64_t MaxOffset = 0;
639 for (unsigned I = 0, E = CSI.size(); I!=E; ++I)
640 MaxOffset = std::min(MaxOffset,
641 MFI->getObjectOffset(CSI[I].getFrameIdx()));
644 int64_t saveAreaOffset = (hasFP(MF) ? 3 : 2)*stackGrowth;
645 for (unsigned I = 0, E = CSI.size(); I!=E; ++I) {
646 int64_t Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
647 unsigned Reg = CSI[I].getReg();
648 Offset = (MaxOffset-Offset+saveAreaOffset);
649 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
650 MachineLocation CSSrc(Reg);
651 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
656 MachineLocation FPDst(MachineLocation::VirtualFP, 2*stackGrowth);
657 MachineLocation FPSrc(FramePtr);
658 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
661 MachineLocation FPDst(hasFP(MF) ? FramePtr : StackPtr);
662 MachineLocation FPSrc(MachineLocation::VirtualFP);
663 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
667 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
668 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
669 MachineFrameInfo *MFI = MF.getFrameInfo();
670 const Function* Fn = MF.getFunction();
671 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
672 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
673 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
674 MachineBasicBlock::iterator MBBI = MBB.begin();
675 bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
676 !Fn->doesNotThrow() ||
677 UnwindTablesMandatory;
678 // Prepare for frame info.
679 unsigned FrameLabelId = 0;
681 // Get the number of bytes to allocate from the FrameInfo.
682 uint64_t StackSize = MFI->getStackSize();
683 // Get desired stack alignment
684 uint64_t MaxAlign = MFI->getMaxAlignment();
686 // Add RETADDR move area to callee saved frame size.
687 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
688 if (TailCallReturnAddrDelta < 0)
689 X86FI->setCalleeSavedFrameSize(
690 X86FI->getCalleeSavedFrameSize() +(-TailCallReturnAddrDelta));
692 // Insert stack pointer adjustment for later moving of return addr. Only
693 // applies to tail call optimized functions where the callee argument stack
694 // size is bigger than the callers.
695 if (TailCallReturnAddrDelta < 0) {
696 BuildMI(MBB, MBBI, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri),
697 StackPtr).addReg(StackPtr).addImm(-TailCallReturnAddrDelta);
700 uint64_t NumBytes = 0;
702 // Calculate required stack adjustment
703 uint64_t FrameSize = StackSize - SlotSize;
704 if (needsStackRealignment(MF))
705 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
707 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
709 // Get the offset of the stack slot for the EBP register... which is
710 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
711 // Update the frame offset adjustment.
712 MFI->setOffsetAdjustment(-NumBytes);
714 // Save EBP into the appropriate stack slot...
715 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
718 if (needsFrameMoves) {
719 // Mark effective beginning of when frame pointer becomes valid.
720 FrameLabelId = MMI->NextLabelID();
721 BuildMI(MBB, MBBI, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId);
724 // Update EBP with the new base value...
725 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
729 if (needsStackRealignment(MF))
731 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri),
732 StackPtr).addReg(StackPtr).addImm(-MaxAlign);
734 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
736 unsigned ReadyLabelId = 0;
737 if (needsFrameMoves) {
738 // Mark effective beginning of when frame pointer is ready.
739 ReadyLabelId = MMI->NextLabelID();
740 BuildMI(MBB, MBBI, TII.get(X86::DBG_LABEL)).addImm(ReadyLabelId);
743 // Skip the callee-saved push instructions.
744 while (MBBI != MBB.end() &&
745 (MBBI->getOpcode() == X86::PUSH32r ||
746 MBBI->getOpcode() == X86::PUSH64r))
749 if (NumBytes) { // adjust stack pointer: ESP -= numbytes
750 if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
751 // Check, whether EAX is livein for this function
752 bool isEAXAlive = false;
753 for (MachineRegisterInfo::livein_iterator
754 II = MF.getRegInfo().livein_begin(),
755 EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
756 unsigned Reg = II->first;
757 isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
758 Reg == X86::AH || Reg == X86::AL);
761 // Function prologue calls _alloca to probe the stack when allocating
762 // more than 4k bytes in one go. Touching the stack at 4K increments is
763 // necessary to ensure that the guard pages used by the OS virtual memory
764 // manager are allocated in correct sequence.
766 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes);
767 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
768 .addExternalSymbol("_alloca");
771 BuildMI(MBB, MBBI, TII.get(X86::PUSH32r), X86::EAX);
772 // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
773 // allocated bytes for EAX.
774 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes-4);
775 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
776 .addExternalSymbol("_alloca");
778 MachineInstr *MI = addRegOffset(BuildMI(MF, TII.get(X86::MOV32rm),X86::EAX),
779 StackPtr, false, NumBytes-4);
780 MBB.insert(MBBI, MI);
783 // If there is an SUB32ri of ESP immediately before this instruction,
784 // merge the two. This can be the case when tail call elimination is
785 // enabled and the callee has more arguments then the caller.
786 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
787 // If there is an ADD32ri or SUB32ri of ESP immediately after this
788 // instruction, merge the two instructions.
789 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
792 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
797 emitFrameMoves(MF, FrameLabelId, ReadyLabelId);
800 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
801 MachineBasicBlock &MBB) const {
802 const MachineFrameInfo *MFI = MF.getFrameInfo();
803 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
804 MachineBasicBlock::iterator MBBI = prior(MBB.end());
805 unsigned RetOpcode = MBBI->getOpcode();
810 case X86::TCRETURNdi:
811 case X86::TCRETURNri:
812 case X86::TCRETURNri64:
813 case X86::TCRETURNdi64:
815 case X86::EH_RETURN64:
818 case X86::TAILJMPm: break; // These are ok
820 assert(0 && "Can only insert epilog into returning blocks");
823 // Get the number of bytes to allocate from the FrameInfo
824 uint64_t StackSize = MFI->getStackSize();
825 uint64_t MaxAlign = MFI->getMaxAlignment();
826 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
827 uint64_t NumBytes = 0;
830 // Calculate required stack adjustment
831 uint64_t FrameSize = StackSize - SlotSize;
832 if (needsStackRealignment(MF))
833 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
835 NumBytes = FrameSize - CSSize;
838 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
840 NumBytes = StackSize - CSSize;
842 // Skip the callee-saved pop instructions.
843 MachineBasicBlock::iterator LastCSPop = MBBI;
844 while (MBBI != MBB.begin()) {
845 MachineBasicBlock::iterator PI = prior(MBBI);
846 unsigned Opc = PI->getOpcode();
847 if (Opc != X86::POP32r && Opc != X86::POP64r &&
848 !PI->getDesc().isTerminator())
853 // If there is an ADD32ri or SUB32ri of ESP immediately before this
854 // instruction, merge the two instructions.
855 if (NumBytes || MFI->hasVarSizedObjects())
856 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
858 // If dynamic alloca is used, then reset esp to point to the last callee-saved
859 // slot before popping them off! Same applies for the case, when stack was
861 if (needsStackRealignment(MF)) {
862 // We cannot use LEA here, because stack pointer was realigned. We need to
863 // deallocate local frame back
865 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
866 MBBI = prior(LastCSPop);
870 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
871 StackPtr).addReg(FramePtr);
872 } else if (MFI->hasVarSizedObjects()) {
874 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
875 MachineInstr *MI = addRegOffset(BuildMI(MF, TII.get(Opc), StackPtr),
876 FramePtr, false, -CSSize);
877 MBB.insert(MBBI, MI);
879 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
880 StackPtr).addReg(FramePtr);
883 // adjust stack pointer back: ESP += numbytes
885 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
888 // We're returning from function via eh_return.
889 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
890 MBBI = prior(MBB.end());
891 MachineOperand &DestAddr = MBBI->getOperand(0);
892 assert(DestAddr.isRegister() && "Offset should be in register!");
894 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
895 StackPtr).addReg(DestAddr.getReg());
896 // Tail call return: adjust the stack pointer and jump to callee
897 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
898 RetOpcode== X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64) {
899 MBBI = prior(MBB.end());
900 MachineOperand &JumpTarget = MBBI->getOperand(0);
901 MachineOperand &StackAdjust = MBBI->getOperand(1);
902 assert( StackAdjust.isImmediate() && "Expecting immediate value.");
904 // Adjust stack pointer.
905 int StackAdj = StackAdjust.getImm();
906 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
908 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
909 // Incoporate the retaddr area.
910 Offset = StackAdj-MaxTCDelta;
911 assert(Offset >= 0 && "Offset should never be negative");
913 // Check for possible merge with preceeding ADD instruction.
914 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
915 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
917 // Jump to label or value in register.
918 if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64)
919 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPd)).
920 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
921 else if (RetOpcode== X86::TCRETURNri64) {
922 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
924 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr), JumpTarget.getReg());
925 // Delete the pseudo instruction TCRETURN.
927 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
928 (X86FI->getTCReturnAddrDelta() < 0)) {
929 // Add the return addr area delta back since we are not tail calling.
930 int delta = -1*X86FI->getTCReturnAddrDelta();
931 MBBI = prior(MBB.end());
932 // Check for possible merge with preceeding ADD instruction.
933 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
934 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
938 unsigned X86RegisterInfo::getRARegister() const {
940 return X86::RIP; // Should have dwarf #16
942 return X86::EIP; // Should have dwarf #8
945 unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
946 return hasFP(MF) ? FramePtr : StackPtr;
949 void X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
951 // Calculate amount of bytes used for return address storing
952 int stackGrowth = (Is64Bit ? -8 : -4);
954 // Initial state of the frame pointer is esp+4.
955 MachineLocation Dst(MachineLocation::VirtualFP);
956 MachineLocation Src(StackPtr, stackGrowth);
957 Moves.push_back(MachineMove(0, Dst, Src));
959 // Add return address to move list
960 MachineLocation CSDst(StackPtr, stackGrowth);
961 MachineLocation CSSrc(getRARegister());
962 Moves.push_back(MachineMove(0, CSDst, CSSrc));
965 unsigned X86RegisterInfo::getEHExceptionRegister() const {
966 assert(0 && "What is the exception register");
970 unsigned X86RegisterInfo::getEHHandlerRegister() const {
971 assert(0 && "What is the exception handler register");
976 unsigned getX86SubSuperRegister(unsigned Reg, MVT VT, bool High) {
977 switch (VT.getSimpleVT()) {
983 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
985 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
987 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
989 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
995 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
997 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
999 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1001 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1003 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1005 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1007 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1009 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1011 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1013 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1015 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1017 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1019 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1021 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1023 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1025 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1031 default: return Reg;
1032 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1034 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1036 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1038 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1040 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1042 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1044 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1046 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1048 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1050 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1052 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1054 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1056 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1058 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1060 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1062 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1067 default: return Reg;
1068 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1070 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1072 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1074 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1076 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1078 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1080 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1082 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1084 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1086 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1088 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1090 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1092 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1094 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1096 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1098 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1103 default: return Reg;
1104 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1106 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1108 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1110 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1112 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1114 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1116 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1118 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1120 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1122 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1124 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1126 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1128 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1130 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1132 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1134 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1143 #include "X86GenRegisterInfo.inc"
1146 struct VISIBILITY_HIDDEN MSAC : public MachineFunctionPass {
1148 MSAC() : MachineFunctionPass(&ID) {}
1150 virtual bool runOnMachineFunction(MachineFunction &MF) {
1151 MachineFrameInfo *FFI = MF.getFrameInfo();
1152 MachineRegisterInfo &RI = MF.getRegInfo();
1154 // Calculate max stack alignment of all already allocated stack objects.
1155 unsigned MaxAlign = calculateMaxStackAlignment(FFI);
1157 // Be over-conservative: scan over all vreg defs and find, whether vector
1158 // registers are used. If yes - there is probability, that vector register
1159 // will be spilled and thus stack needs to be aligned properly.
1160 for (unsigned RegNum = TargetRegisterInfo::FirstVirtualRegister;
1161 RegNum < RI.getLastVirtReg(); ++RegNum)
1162 MaxAlign = std::max(MaxAlign, RI.getRegClass(RegNum)->getAlignment());
1164 FFI->setMaxAlignment(MaxAlign);
1169 virtual const char *getPassName() const {
1170 return "X86 Maximal Stack Alignment Calculator";
1178 llvm::createX86MaxStackAlignmentCalculatorPass() { return new MSAC(); }