1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the MRegisterInfo class. This
11 // file is responsible for the frame pointer elimination optimization on X86.
13 //===----------------------------------------------------------------------===//
16 #include "X86RegisterInfo.h"
17 #include "X86InstrBuilder.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/Type.h"
24 #include "llvm/CodeGen/ValueTypes.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineLocation.h"
29 #include "llvm/Target/TargetFrameInfo.h"
30 #include "llvm/Target/TargetInstrInfo.h"
31 #include "llvm/Target/TargetMachine.h"
32 #include "llvm/Target/TargetOptions.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/ADT/STLExtras.h"
39 NoFusing("disable-spill-fusing",
40 cl::desc("Disable fusing of spill code into instructions"));
42 PrintFailedFusing("print-failed-fuse-candidates",
43 cl::desc("Print instructions that the allocator wants to"
44 " fuse, but the X86 backend currently can't"),
48 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
49 const TargetInstrInfo &tii)
50 : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP),
52 // Cache some information.
53 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
54 Is64Bit = Subtarget->is64Bit();
66 void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
67 MachineBasicBlock::iterator MI,
68 unsigned SrcReg, int FrameIdx,
69 const TargetRegisterClass *RC) const {
71 if (RC == &X86::GR64RegClass) {
73 } else if (RC == &X86::GR32RegClass) {
75 } else if (RC == &X86::GR16RegClass) {
77 } else if (RC == &X86::GR8RegClass) {
79 } else if (RC == &X86::GR32_RegClass) {
81 } else if (RC == &X86::GR16_RegClass) {
83 } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
85 } else if (RC == &X86::FR32RegClass) {
87 } else if (RC == &X86::FR64RegClass) {
89 } else if (RC == &X86::VR128RegClass) {
92 assert(0 && "Unknown regclass");
95 addFrameReference(BuildMI(MBB, MI, TII.get(Opc)), FrameIdx).addReg(SrcReg);
98 void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
99 MachineBasicBlock::iterator MI,
100 unsigned DestReg, int FrameIdx,
101 const TargetRegisterClass *RC) const{
103 if (RC == &X86::GR64RegClass) {
105 } else if (RC == &X86::GR32RegClass) {
107 } else if (RC == &X86::GR16RegClass) {
109 } else if (RC == &X86::GR8RegClass) {
111 } else if (RC == &X86::GR32_RegClass) {
113 } else if (RC == &X86::GR16_RegClass) {
115 } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
117 } else if (RC == &X86::FR32RegClass) {
119 } else if (RC == &X86::FR64RegClass) {
121 } else if (RC == &X86::VR128RegClass) {
124 assert(0 && "Unknown regclass");
127 addFrameReference(BuildMI(MBB, MI, TII.get(Opc), DestReg), FrameIdx);
130 void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
131 MachineBasicBlock::iterator MI,
132 unsigned DestReg, unsigned SrcReg,
133 const TargetRegisterClass *RC) const {
135 if (RC == &X86::GR64RegClass) {
137 } else if (RC == &X86::GR32RegClass) {
139 } else if (RC == &X86::GR16RegClass) {
141 } else if (RC == &X86::GR8RegClass) {
143 } else if (RC == &X86::GR32_RegClass) {
145 } else if (RC == &X86::GR16_RegClass) {
147 } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
149 } else if (RC == &X86::FR32RegClass) {
150 Opc = X86::FsMOVAPSrr;
151 } else if (RC == &X86::FR64RegClass) {
152 Opc = X86::FsMOVAPDrr;
153 } else if (RC == &X86::VR128RegClass) {
156 assert(0 && "Unknown regclass");
159 BuildMI(MBB, MI, TII.get(Opc), DestReg).addReg(SrcReg);
162 static MachineInstr *FuseTwoAddrInst(unsigned Opcode, unsigned FrameIndex,
164 const TargetInstrInfo &TII) {
165 unsigned NumOps = TII.getNumOperands(MI->getOpcode())-2;
166 // Create the base instruction with the memory operand as the first part.
167 MachineInstrBuilder MIB = addFrameReference(BuildMI(TII.get(Opcode)),
170 // Loop over the rest of the ri operands, converting them over.
171 for (unsigned i = 0; i != NumOps; ++i) {
172 MachineOperand &MO = MI->getOperand(i+2);
174 MIB = MIB.addReg(MO.getReg(), false, MO.isImplicit());
176 MIB = MIB.addImm(MO.getImm());
177 else if (MO.isGlobalAddress())
178 MIB = MIB.addGlobalAddress(MO.getGlobal(), MO.getOffset());
179 else if (MO.isJumpTableIndex())
180 MIB = MIB.addJumpTableIndex(MO.getJumpTableIndex());
182 assert(0 && "Unknown operand type!");
187 static MachineInstr *FuseInst(unsigned Opcode, unsigned OpNo,
188 unsigned FrameIndex, MachineInstr *MI,
189 const TargetInstrInfo &TII) {
190 MachineInstrBuilder MIB = BuildMI(TII.get(Opcode));
192 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
193 MachineOperand &MO = MI->getOperand(i);
195 assert(MO.isReg() && "Expected to fold into reg operand!");
196 MIB = addFrameReference(MIB, FrameIndex);
197 } else if (MO.isReg())
198 MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
200 MIB = MIB.addImm(MO.getImm());
201 else if (MO.isGlobalAddress())
202 MIB = MIB.addGlobalAddress(MO.getGlobal(), MO.getOffset());
203 else if (MO.isJumpTableIndex())
204 MIB = MIB.addJumpTableIndex(MO.getJumpTableIndex());
206 assert(0 && "Unknown operand for FuseInst!");
211 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII,
212 unsigned Opcode, unsigned FrameIndex,
214 return addFrameReference(BuildMI(TII.get(Opcode)), FrameIndex).addImm(0);
218 //===----------------------------------------------------------------------===//
219 // Efficient Lookup Table Support
220 //===----------------------------------------------------------------------===//
223 /// TableEntry - Maps the 'from' opcode to a fused form of the 'to' opcode.
226 unsigned from; // Original opcode.
227 unsigned to; // New opcode.
229 // less operators used by STL search.
230 bool operator<(const TableEntry &TE) const { return from < TE.from; }
231 friend bool operator<(const TableEntry &TE, unsigned V) {
234 friend bool operator<(unsigned V, const TableEntry &TE) {
240 /// TableIsSorted - Return true if the table is in 'from' opcode order.
242 static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) {
243 for (unsigned i = 1; i != NumEntries; ++i)
244 if (!(Table[i-1] < Table[i])) {
245 cerr << "Entries out of order " << Table[i-1].from
246 << " " << Table[i].from << "\n";
252 /// TableLookup - Return the table entry matching the specified opcode.
253 /// Otherwise return NULL.
254 static const TableEntry *TableLookup(const TableEntry *Table, unsigned N,
256 const TableEntry *I = std::lower_bound(Table, Table+N, Opcode);
257 if (I != Table+N && I->from == Opcode)
262 #define ARRAY_SIZE(TABLE) \
263 (sizeof(TABLE)/sizeof(TABLE[0]))
266 #define ASSERT_SORTED(TABLE)
268 #define ASSERT_SORTED(TABLE) \
269 { static bool TABLE##Checked = false; \
270 if (!TABLE##Checked) { \
271 assert(TableIsSorted(TABLE, ARRAY_SIZE(TABLE)) && \
272 "All lookup tables must be sorted for efficient access!"); \
273 TABLE##Checked = true; \
279 MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr *MI,
281 int FrameIndex) const {
283 if (NoFusing) return NULL;
285 // Table (and size) to search
286 const TableEntry *OpcodeTablePtr = NULL;
287 unsigned OpcodeTableSize = 0;
288 bool isTwoAddrFold = false;
289 unsigned NumOps = TII.getNumOperands(MI->getOpcode());
290 bool isTwoAddr = NumOps > 1 &&
291 MI->getInstrDescriptor()->getOperandConstraint(1, TOI::TIED_TO) != -1;
293 MachineInstr *NewMI = NULL;
294 // Folding a memory location into the two-address part of a two-address
295 // instruction is different than folding it other places. It requires
296 // replacing the *two* registers with the memory location.
297 if (isTwoAddr && NumOps >= 2 && i < 2 &&
298 MI->getOperand(0).isReg() &&
299 MI->getOperand(1).isReg() &&
300 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
301 static const TableEntry OpcodeTable[] = {
302 { X86::ADC32ri, X86::ADC32mi },
303 { X86::ADC32ri8, X86::ADC32mi8 },
304 { X86::ADC32rr, X86::ADC32mr },
305 { X86::ADC64ri32, X86::ADC64mi32 },
306 { X86::ADC64ri8, X86::ADC64mi8 },
307 { X86::ADC64rr, X86::ADC64mr },
308 { X86::ADD16ri, X86::ADD16mi },
309 { X86::ADD16ri8, X86::ADD16mi8 },
310 { X86::ADD16rr, X86::ADD16mr },
311 { X86::ADD32ri, X86::ADD32mi },
312 { X86::ADD32ri8, X86::ADD32mi8 },
313 { X86::ADD32rr, X86::ADD32mr },
314 { X86::ADD64ri32, X86::ADD64mi32 },
315 { X86::ADD64ri8, X86::ADD64mi8 },
316 { X86::ADD64rr, X86::ADD64mr },
317 { X86::ADD8ri, X86::ADD8mi },
318 { X86::ADD8rr, X86::ADD8mr },
319 { X86::AND16ri, X86::AND16mi },
320 { X86::AND16ri8, X86::AND16mi8 },
321 { X86::AND16rr, X86::AND16mr },
322 { X86::AND32ri, X86::AND32mi },
323 { X86::AND32ri8, X86::AND32mi8 },
324 { X86::AND32rr, X86::AND32mr },
325 { X86::AND64ri32, X86::AND64mi32 },
326 { X86::AND64ri8, X86::AND64mi8 },
327 { X86::AND64rr, X86::AND64mr },
328 { X86::AND8ri, X86::AND8mi },
329 { X86::AND8rr, X86::AND8mr },
330 { X86::DEC16r, X86::DEC16m },
331 { X86::DEC32r, X86::DEC32m },
332 { X86::DEC64_16r, X86::DEC16m },
333 { X86::DEC64_32r, X86::DEC32m },
334 { X86::DEC64r, X86::DEC64m },
335 { X86::DEC8r, X86::DEC8m },
336 { X86::INC16r, X86::INC16m },
337 { X86::INC32r, X86::INC32m },
338 { X86::INC64_16r, X86::INC16m },
339 { X86::INC64_32r, X86::INC32m },
340 { X86::INC64r, X86::INC64m },
341 { X86::INC8r, X86::INC8m },
342 { X86::NEG16r, X86::NEG16m },
343 { X86::NEG32r, X86::NEG32m },
344 { X86::NEG64r, X86::NEG64m },
345 { X86::NEG8r, X86::NEG8m },
346 { X86::NOT16r, X86::NOT16m },
347 { X86::NOT32r, X86::NOT32m },
348 { X86::NOT64r, X86::NOT64m },
349 { X86::NOT8r, X86::NOT8m },
350 { X86::OR16ri, X86::OR16mi },
351 { X86::OR16ri8, X86::OR16mi8 },
352 { X86::OR16rr, X86::OR16mr },
353 { X86::OR32ri, X86::OR32mi },
354 { X86::OR32ri8, X86::OR32mi8 },
355 { X86::OR32rr, X86::OR32mr },
356 { X86::OR64ri32, X86::OR64mi32 },
357 { X86::OR64ri8, X86::OR64mi8 },
358 { X86::OR64rr, X86::OR64mr },
359 { X86::OR8ri, X86::OR8mi },
360 { X86::OR8rr, X86::OR8mr },
361 { X86::ROL16r1, X86::ROL16m1 },
362 { X86::ROL16rCL, X86::ROL16mCL },
363 { X86::ROL16ri, X86::ROL16mi },
364 { X86::ROL32r1, X86::ROL32m1 },
365 { X86::ROL32rCL, X86::ROL32mCL },
366 { X86::ROL32ri, X86::ROL32mi },
367 { X86::ROL64r1, X86::ROL64m1 },
368 { X86::ROL64rCL, X86::ROL64mCL },
369 { X86::ROL64ri, X86::ROL64mi },
370 { X86::ROL8r1, X86::ROL8m1 },
371 { X86::ROL8rCL, X86::ROL8mCL },
372 { X86::ROL8ri, X86::ROL8mi },
373 { X86::ROR16r1, X86::ROR16m1 },
374 { X86::ROR16rCL, X86::ROR16mCL },
375 { X86::ROR16ri, X86::ROR16mi },
376 { X86::ROR32r1, X86::ROR32m1 },
377 { X86::ROR32rCL, X86::ROR32mCL },
378 { X86::ROR32ri, X86::ROR32mi },
379 { X86::ROR64r1, X86::ROR64m1 },
380 { X86::ROR64rCL, X86::ROR64mCL },
381 { X86::ROR64ri, X86::ROR64mi },
382 { X86::ROR8r1, X86::ROR8m1 },
383 { X86::ROR8rCL, X86::ROR8mCL },
384 { X86::ROR8ri, X86::ROR8mi },
385 { X86::SAR16r1, X86::SAR16m1 },
386 { X86::SAR16rCL, X86::SAR16mCL },
387 { X86::SAR16ri, X86::SAR16mi },
388 { X86::SAR32r1, X86::SAR32m1 },
389 { X86::SAR32rCL, X86::SAR32mCL },
390 { X86::SAR32ri, X86::SAR32mi },
391 { X86::SAR64r1, X86::SAR64m1 },
392 { X86::SAR64rCL, X86::SAR64mCL },
393 { X86::SAR64ri, X86::SAR64mi },
394 { X86::SAR8r1, X86::SAR8m1 },
395 { X86::SAR8rCL, X86::SAR8mCL },
396 { X86::SAR8ri, X86::SAR8mi },
397 { X86::SBB32ri, X86::SBB32mi },
398 { X86::SBB32ri8, X86::SBB32mi8 },
399 { X86::SBB32rr, X86::SBB32mr },
400 { X86::SBB64ri32, X86::SBB64mi32 },
401 { X86::SBB64ri8, X86::SBB64mi8 },
402 { X86::SBB64rr, X86::SBB64mr },
403 { X86::SHL16r1, X86::SHL16m1 },
404 { X86::SHL16rCL, X86::SHL16mCL },
405 { X86::SHL16ri, X86::SHL16mi },
406 { X86::SHL32r1, X86::SHL32m1 },
407 { X86::SHL32rCL, X86::SHL32mCL },
408 { X86::SHL32ri, X86::SHL32mi },
409 { X86::SHL64r1, X86::SHL64m1 },
410 { X86::SHL64rCL, X86::SHL64mCL },
411 { X86::SHL64ri, X86::SHL64mi },
412 { X86::SHL8r1, X86::SHL8m1 },
413 { X86::SHL8rCL, X86::SHL8mCL },
414 { X86::SHL8ri, X86::SHL8mi },
415 { X86::SHLD16rrCL, X86::SHLD16mrCL },
416 { X86::SHLD16rri8, X86::SHLD16mri8 },
417 { X86::SHLD32rrCL, X86::SHLD32mrCL },
418 { X86::SHLD32rri8, X86::SHLD32mri8 },
419 { X86::SHLD64rrCL, X86::SHLD64mrCL },
420 { X86::SHLD64rri8, X86::SHLD64mri8 },
421 { X86::SHR16r1, X86::SHR16m1 },
422 { X86::SHR16rCL, X86::SHR16mCL },
423 { X86::SHR16ri, X86::SHR16mi },
424 { X86::SHR32r1, X86::SHR32m1 },
425 { X86::SHR32rCL, X86::SHR32mCL },
426 { X86::SHR32ri, X86::SHR32mi },
427 { X86::SHR64r1, X86::SHR64m1 },
428 { X86::SHR64rCL, X86::SHR64mCL },
429 { X86::SHR64ri, X86::SHR64mi },
430 { X86::SHR8r1, X86::SHR8m1 },
431 { X86::SHR8rCL, X86::SHR8mCL },
432 { X86::SHR8ri, X86::SHR8mi },
433 { X86::SHRD16rrCL, X86::SHRD16mrCL },
434 { X86::SHRD16rri8, X86::SHRD16mri8 },
435 { X86::SHRD32rrCL, X86::SHRD32mrCL },
436 { X86::SHRD32rri8, X86::SHRD32mri8 },
437 { X86::SHRD64rrCL, X86::SHRD64mrCL },
438 { X86::SHRD64rri8, X86::SHRD64mri8 },
439 { X86::SUB16ri, X86::SUB16mi },
440 { X86::SUB16ri8, X86::SUB16mi8 },
441 { X86::SUB16rr, X86::SUB16mr },
442 { X86::SUB32ri, X86::SUB32mi },
443 { X86::SUB32ri8, X86::SUB32mi8 },
444 { X86::SUB32rr, X86::SUB32mr },
445 { X86::SUB64ri32, X86::SUB64mi32 },
446 { X86::SUB64ri8, X86::SUB64mi8 },
447 { X86::SUB64rr, X86::SUB64mr },
448 { X86::SUB8ri, X86::SUB8mi },
449 { X86::SUB8rr, X86::SUB8mr },
450 { X86::XOR16ri, X86::XOR16mi },
451 { X86::XOR16ri8, X86::XOR16mi8 },
452 { X86::XOR16rr, X86::XOR16mr },
453 { X86::XOR32ri, X86::XOR32mi },
454 { X86::XOR32ri8, X86::XOR32mi8 },
455 { X86::XOR32rr, X86::XOR32mr },
456 { X86::XOR64ri32, X86::XOR64mi32 },
457 { X86::XOR64ri8, X86::XOR64mi8 },
458 { X86::XOR64rr, X86::XOR64mr },
459 { X86::XOR8ri, X86::XOR8mi },
460 { X86::XOR8rr, X86::XOR8mr }
462 ASSERT_SORTED(OpcodeTable);
463 OpcodeTablePtr = OpcodeTable;
464 OpcodeTableSize = ARRAY_SIZE(OpcodeTable);
465 isTwoAddrFold = true;
466 } else if (i == 0) { // If operand 0
467 if (MI->getOpcode() == X86::MOV16r0)
468 NewMI = MakeM0Inst(TII, X86::MOV16mi, FrameIndex, MI);
469 else if (MI->getOpcode() == X86::MOV32r0)
470 NewMI = MakeM0Inst(TII, X86::MOV32mi, FrameIndex, MI);
471 else if (MI->getOpcode() == X86::MOV64r0)
472 NewMI = MakeM0Inst(TII, X86::MOV64mi32, FrameIndex, MI);
473 else if (MI->getOpcode() == X86::MOV8r0)
474 NewMI = MakeM0Inst(TII, X86::MOV8mi, FrameIndex, MI);
476 NewMI->copyKillDeadInfo(MI);
480 static const TableEntry OpcodeTable[] = {
481 { X86::CMP16ri, X86::CMP16mi },
482 { X86::CMP16ri8, X86::CMP16mi8 },
483 { X86::CMP32ri, X86::CMP32mi },
484 { X86::CMP32ri8, X86::CMP32mi8 },
485 { X86::CMP8ri, X86::CMP8mi },
486 { X86::DIV16r, X86::DIV16m },
487 { X86::DIV32r, X86::DIV32m },
488 { X86::DIV64r, X86::DIV64m },
489 { X86::DIV8r, X86::DIV8m },
490 { X86::FsMOVAPDrr, X86::MOVSDmr },
491 { X86::FsMOVAPSrr, X86::MOVSSmr },
492 { X86::IDIV16r, X86::IDIV16m },
493 { X86::IDIV32r, X86::IDIV32m },
494 { X86::IDIV64r, X86::IDIV64m },
495 { X86::IDIV8r, X86::IDIV8m },
496 { X86::IMUL16r, X86::IMUL16m },
497 { X86::IMUL32r, X86::IMUL32m },
498 { X86::IMUL64r, X86::IMUL64m },
499 { X86::IMUL8r, X86::IMUL8m },
500 { X86::MOV16ri, X86::MOV16mi },
501 { X86::MOV16rr, X86::MOV16mr },
502 { X86::MOV32ri, X86::MOV32mi },
503 { X86::MOV32rr, X86::MOV32mr },
504 { X86::MOV64ri32, X86::MOV64mi32 },
505 { X86::MOV64rr, X86::MOV64mr },
506 { X86::MOV8ri, X86::MOV8mi },
507 { X86::MOV8rr, X86::MOV8mr },
508 { X86::MOVAPDrr, X86::MOVAPDmr },
509 { X86::MOVAPSrr, X86::MOVAPSmr },
510 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr },
511 { X86::MOVPQIto64rr,X86::MOVPQIto64mr },
512 { X86::MOVPS2SSrr, X86::MOVPS2SSmr },
513 { X86::MOVSDrr, X86::MOVSDmr },
514 { X86::MOVSDto64rr, X86::MOVSDto64mr },
515 { X86::MOVSS2DIrr, X86::MOVSS2DImr },
516 { X86::MOVSSrr, X86::MOVSSmr },
517 { X86::MOVUPDrr, X86::MOVUPDmr },
518 { X86::MOVUPSrr, X86::MOVUPSmr },
519 { X86::MUL16r, X86::MUL16m },
520 { X86::MUL32r, X86::MUL32m },
521 { X86::MUL64r, X86::MUL64m },
522 { X86::MUL8r, X86::MUL8m },
523 { X86::SETAEr, X86::SETAEm },
524 { X86::SETAr, X86::SETAm },
525 { X86::SETBEr, X86::SETBEm },
526 { X86::SETBr, X86::SETBm },
527 { X86::SETEr, X86::SETEm },
528 { X86::SETGEr, X86::SETGEm },
529 { X86::SETGr, X86::SETGm },
530 { X86::SETLEr, X86::SETLEm },
531 { X86::SETLr, X86::SETLm },
532 { X86::SETNEr, X86::SETNEm },
533 { X86::SETNPr, X86::SETNPm },
534 { X86::SETNSr, X86::SETNSm },
535 { X86::SETPr, X86::SETPm },
536 { X86::SETSr, X86::SETSm },
537 { X86::TEST16ri, X86::TEST16mi },
538 { X86::TEST32ri, X86::TEST32mi },
539 { X86::TEST64ri32, X86::TEST64mi32 },
540 { X86::TEST8ri, X86::TEST8mi },
541 { X86::XCHG16rr, X86::XCHG16mr },
542 { X86::XCHG32rr, X86::XCHG32mr },
543 { X86::XCHG64rr, X86::XCHG64mr },
544 { X86::XCHG8rr, X86::XCHG8mr }
546 ASSERT_SORTED(OpcodeTable);
547 OpcodeTablePtr = OpcodeTable;
548 OpcodeTableSize = ARRAY_SIZE(OpcodeTable);
550 static const TableEntry OpcodeTable[] = {
551 { X86::CMP16rr, X86::CMP16rm },
552 { X86::CMP32rr, X86::CMP32rm },
553 { X86::CMP64ri32, X86::CMP64mi32 },
554 { X86::CMP64ri8, X86::CMP64mi8 },
555 { X86::CMP64rr, X86::CMP64rm },
556 { X86::CMP8rr, X86::CMP8rm },
557 { X86::CMPPDrri, X86::CMPPDrmi },
558 { X86::CMPPSrri, X86::CMPPSrmi },
559 { X86::CMPSDrr, X86::CMPSDrm },
560 { X86::CMPSSrr, X86::CMPSSrm },
561 { X86::CVTSD2SSrr, X86::CVTSD2SSrm },
562 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm },
563 { X86::CVTSI2SDrr, X86::CVTSI2SDrm },
564 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm },
565 { X86::CVTSI2SSrr, X86::CVTSI2SSrm },
566 { X86::CVTSS2SDrr, X86::CVTSS2SDrm },
567 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm },
568 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm },
569 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm },
570 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm },
571 { X86::FsMOVAPDrr, X86::MOVSDrm },
572 { X86::FsMOVAPSrr, X86::MOVSSrm },
573 { X86::IMUL16rri, X86::IMUL16rmi },
574 { X86::IMUL16rri8, X86::IMUL16rmi8 },
575 { X86::IMUL32rri, X86::IMUL32rmi },
576 { X86::IMUL32rri8, X86::IMUL32rmi8 },
577 { X86::IMUL64rr, X86::IMUL64rm },
578 { X86::IMUL64rri32, X86::IMUL64rmi32 },
579 { X86::IMUL64rri8, X86::IMUL64rmi8 },
580 { X86::Int_CMPSDrr, X86::Int_CMPSDrm },
581 { X86::Int_CMPSSrr, X86::Int_CMPSSrm },
582 { X86::Int_COMISDrr, X86::Int_COMISDrm },
583 { X86::Int_COMISSrr, X86::Int_COMISSrm },
584 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm },
585 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm },
586 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm },
587 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm },
588 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm },
589 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm },
590 { X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm },
591 { X86::Int_CVTSD2SIrr, X86::Int_CVTSD2SIrm },
592 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm },
593 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm },
594 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm },
595 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm },
596 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm },
597 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm },
598 { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm },
599 { X86::Int_CVTSS2SIrr, X86::Int_CVTSS2SIrm },
600 { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm },
601 { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm },
602 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm },
603 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm },
604 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm },
605 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm },
606 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm },
607 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm },
608 { X86::MOV16rr, X86::MOV16rm },
609 { X86::MOV32rr, X86::MOV32rm },
610 { X86::MOV64rr, X86::MOV64rm },
611 { X86::MOV64toPQIrr, X86::MOV64toPQIrm },
612 { X86::MOV64toSDrr, X86::MOV64toSDrm },
613 { X86::MOV8rr, X86::MOV8rm },
614 { X86::MOVAPDrr, X86::MOVAPDrm },
615 { X86::MOVAPSrr, X86::MOVAPSrm },
616 { X86::MOVDDUPrr, X86::MOVDDUPrm },
617 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm },
618 { X86::MOVDI2SSrr, X86::MOVDI2SSrm },
619 { X86::MOVSD2PDrr, X86::MOVSD2PDrm },
620 { X86::MOVSDrr, X86::MOVSDrm },
621 { X86::MOVSHDUPrr, X86::MOVSHDUPrm },
622 { X86::MOVSLDUPrr, X86::MOVSLDUPrm },
623 { X86::MOVSS2PSrr, X86::MOVSS2PSrm },
624 { X86::MOVSSrr, X86::MOVSSrm },
625 { X86::MOVSX16rr8, X86::MOVSX16rm8 },
626 { X86::MOVSX32rr16, X86::MOVSX32rm16 },
627 { X86::MOVSX32rr8, X86::MOVSX32rm8 },
628 { X86::MOVSX64rr16, X86::MOVSX64rm16 },
629 { X86::MOVSX64rr32, X86::MOVSX64rm32 },
630 { X86::MOVSX64rr8, X86::MOVSX64rm8 },
631 { X86::MOVUPDrr, X86::MOVUPDrm },
632 { X86::MOVUPSrr, X86::MOVUPSrm },
633 { X86::MOVZX16rr8, X86::MOVZX16rm8 },
634 { X86::MOVZX32rr16, X86::MOVZX32rm16 },
635 { X86::MOVZX32rr8, X86::MOVZX32rm8 },
636 { X86::MOVZX64rr16, X86::MOVZX64rm16 },
637 { X86::MOVZX64rr8, X86::MOVZX64rm8 },
638 { X86::PSHUFDri, X86::PSHUFDmi },
639 { X86::PSHUFHWri, X86::PSHUFHWmi },
640 { X86::PSHUFLWri, X86::PSHUFLWmi },
641 { X86::PsMOVZX64rr32, X86::PsMOVZX64rm32 },
642 { X86::TEST16rr, X86::TEST16rm },
643 { X86::TEST32rr, X86::TEST32rm },
644 { X86::TEST64rr, X86::TEST64rm },
645 { X86::TEST8rr, X86::TEST8rm },
646 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
647 { X86::UCOMISDrr, X86::UCOMISDrm },
648 { X86::UCOMISSrr, X86::UCOMISSrm },
649 { X86::XCHG16rr, X86::XCHG16rm },
650 { X86::XCHG32rr, X86::XCHG32rm },
651 { X86::XCHG64rr, X86::XCHG64rm },
652 { X86::XCHG8rr, X86::XCHG8rm }
654 ASSERT_SORTED(OpcodeTable);
655 OpcodeTablePtr = OpcodeTable;
656 OpcodeTableSize = ARRAY_SIZE(OpcodeTable);
658 static const TableEntry OpcodeTable[] = {
659 { X86::ADC32rr, X86::ADC32rm },
660 { X86::ADC64rr, X86::ADC64rm },
661 { X86::ADD16rr, X86::ADD16rm },
662 { X86::ADD32rr, X86::ADD32rm },
663 { X86::ADD64rr, X86::ADD64rm },
664 { X86::ADD8rr, X86::ADD8rm },
665 { X86::ADDPDrr, X86::ADDPDrm },
666 { X86::ADDPSrr, X86::ADDPSrm },
667 { X86::ADDSDrr, X86::ADDSDrm },
668 { X86::ADDSSrr, X86::ADDSSrm },
669 { X86::ADDSUBPDrr, X86::ADDSUBPDrm },
670 { X86::ADDSUBPSrr, X86::ADDSUBPSrm },
671 { X86::AND16rr, X86::AND16rm },
672 { X86::AND32rr, X86::AND32rm },
673 { X86::AND64rr, X86::AND64rm },
674 { X86::AND8rr, X86::AND8rm },
675 { X86::ANDNPDrr, X86::ANDNPDrm },
676 { X86::ANDNPSrr, X86::ANDNPSrm },
677 { X86::ANDPDrr, X86::ANDPDrm },
678 { X86::ANDPSrr, X86::ANDPSrm },
679 { X86::CMOVA16rr, X86::CMOVA16rm },
680 { X86::CMOVA32rr, X86::CMOVA32rm },
681 { X86::CMOVA64rr, X86::CMOVA64rm },
682 { X86::CMOVAE16rr, X86::CMOVAE16rm },
683 { X86::CMOVAE32rr, X86::CMOVAE32rm },
684 { X86::CMOVAE64rr, X86::CMOVAE64rm },
685 { X86::CMOVB16rr, X86::CMOVB16rm },
686 { X86::CMOVB32rr, X86::CMOVB32rm },
687 { X86::CMOVB64rr, X86::CMOVB64rm },
688 { X86::CMOVBE16rr, X86::CMOVBE16rm },
689 { X86::CMOVBE32rr, X86::CMOVBE32rm },
690 { X86::CMOVBE64rr, X86::CMOVBE64rm },
691 { X86::CMOVE16rr, X86::CMOVE16rm },
692 { X86::CMOVE32rr, X86::CMOVE32rm },
693 { X86::CMOVE64rr, X86::CMOVE64rm },
694 { X86::CMOVG16rr, X86::CMOVG16rm },
695 { X86::CMOVG32rr, X86::CMOVG32rm },
696 { X86::CMOVG64rr, X86::CMOVG64rm },
697 { X86::CMOVGE16rr, X86::CMOVGE16rm },
698 { X86::CMOVGE32rr, X86::CMOVGE32rm },
699 { X86::CMOVGE64rr, X86::CMOVGE64rm },
700 { X86::CMOVL16rr, X86::CMOVL16rm },
701 { X86::CMOVL32rr, X86::CMOVL32rm },
702 { X86::CMOVL64rr, X86::CMOVL64rm },
703 { X86::CMOVLE16rr, X86::CMOVLE16rm },
704 { X86::CMOVLE32rr, X86::CMOVLE32rm },
705 { X86::CMOVLE64rr, X86::CMOVLE64rm },
706 { X86::CMOVNE16rr, X86::CMOVNE16rm },
707 { X86::CMOVNE32rr, X86::CMOVNE32rm },
708 { X86::CMOVNE64rr, X86::CMOVNE64rm },
709 { X86::CMOVNP16rr, X86::CMOVNP16rm },
710 { X86::CMOVNP32rr, X86::CMOVNP32rm },
711 { X86::CMOVNP64rr, X86::CMOVNP64rm },
712 { X86::CMOVNS16rr, X86::CMOVNS16rm },
713 { X86::CMOVNS32rr, X86::CMOVNS32rm },
714 { X86::CMOVNS64rr, X86::CMOVNS64rm },
715 { X86::CMOVP16rr, X86::CMOVP16rm },
716 { X86::CMOVP32rr, X86::CMOVP32rm },
717 { X86::CMOVP64rr, X86::CMOVP64rm },
718 { X86::CMOVS16rr, X86::CMOVS16rm },
719 { X86::CMOVS32rr, X86::CMOVS32rm },
720 { X86::CMOVS64rr, X86::CMOVS64rm },
721 { X86::DIVPDrr, X86::DIVPDrm },
722 { X86::DIVPSrr, X86::DIVPSrm },
723 { X86::DIVSDrr, X86::DIVSDrm },
724 { X86::DIVSSrr, X86::DIVSSrm },
725 { X86::HADDPDrr, X86::HADDPDrm },
726 { X86::HADDPSrr, X86::HADDPSrm },
727 { X86::HSUBPDrr, X86::HSUBPDrm },
728 { X86::HSUBPSrr, X86::HSUBPSrm },
729 { X86::IMUL16rr, X86::IMUL16rm },
730 { X86::IMUL32rr, X86::IMUL32rm },
731 { X86::MAXPDrr, X86::MAXPDrm },
732 { X86::MAXPSrr, X86::MAXPSrm },
733 { X86::MINPDrr, X86::MINPDrm },
734 { X86::MINPSrr, X86::MINPSrm },
735 { X86::MULPDrr, X86::MULPDrm },
736 { X86::MULPSrr, X86::MULPSrm },
737 { X86::MULSDrr, X86::MULSDrm },
738 { X86::MULSSrr, X86::MULSSrm },
739 { X86::OR16rr, X86::OR16rm },
740 { X86::OR32rr, X86::OR32rm },
741 { X86::OR64rr, X86::OR64rm },
742 { X86::OR8rr, X86::OR8rm },
743 { X86::ORPDrr, X86::ORPDrm },
744 { X86::ORPSrr, X86::ORPSrm },
745 { X86::PACKSSDWrr, X86::PACKSSDWrm },
746 { X86::PACKSSWBrr, X86::PACKSSWBrm },
747 { X86::PACKUSWBrr, X86::PACKUSWBrm },
748 { X86::PADDBrr, X86::PADDBrm },
749 { X86::PADDDrr, X86::PADDDrm },
750 { X86::PADDSBrr, X86::PADDSBrm },
751 { X86::PADDSWrr, X86::PADDSWrm },
752 { X86::PADDWrr, X86::PADDWrm },
753 { X86::PANDNrr, X86::PANDNrm },
754 { X86::PANDrr, X86::PANDrm },
755 { X86::PAVGBrr, X86::PAVGBrm },
756 { X86::PAVGWrr, X86::PAVGWrm },
757 { X86::PCMPEQBrr, X86::PCMPEQBrm },
758 { X86::PCMPEQDrr, X86::PCMPEQDrm },
759 { X86::PCMPEQWrr, X86::PCMPEQWrm },
760 { X86::PCMPGTBrr, X86::PCMPGTBrm },
761 { X86::PCMPGTDrr, X86::PCMPGTDrm },
762 { X86::PCMPGTWrr, X86::PCMPGTWrm },
763 { X86::PINSRWrri, X86::PINSRWrmi },
764 { X86::PMADDWDrr, X86::PMADDWDrm },
765 { X86::PMAXSWrr, X86::PMAXSWrm },
766 { X86::PMAXUBrr, X86::PMAXUBrm },
767 { X86::PMINSWrr, X86::PMINSWrm },
768 { X86::PMINUBrr, X86::PMINUBrm },
769 { X86::PMULHUWrr, X86::PMULHUWrm },
770 { X86::PMULHWrr, X86::PMULHWrm },
771 { X86::PMULLWrr, X86::PMULLWrm },
772 { X86::PMULUDQrr, X86::PMULUDQrm },
773 { X86::PORrr, X86::PORrm },
774 { X86::PSADBWrr, X86::PSADBWrm },
775 { X86::PSLLDrr, X86::PSLLDrm },
776 { X86::PSLLQrr, X86::PSLLQrm },
777 { X86::PSLLWrr, X86::PSLLWrm },
778 { X86::PSRADrr, X86::PSRADrm },
779 { X86::PSRAWrr, X86::PSRAWrm },
780 { X86::PSRLDrr, X86::PSRLDrm },
781 { X86::PSRLQrr, X86::PSRLQrm },
782 { X86::PSRLWrr, X86::PSRLWrm },
783 { X86::PSUBBrr, X86::PSUBBrm },
784 { X86::PSUBDrr, X86::PSUBDrm },
785 { X86::PSUBSBrr, X86::PSUBSBrm },
786 { X86::PSUBSWrr, X86::PSUBSWrm },
787 { X86::PSUBWrr, X86::PSUBWrm },
788 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm },
789 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm },
790 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm },
791 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm },
792 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm },
793 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm },
794 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm },
795 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm },
796 { X86::PXORrr, X86::PXORrm },
797 { X86::RCPPSr, X86::RCPPSm },
798 { X86::RSQRTPSr, X86::RSQRTPSm },
799 { X86::SBB32rr, X86::SBB32rm },
800 { X86::SBB64rr, X86::SBB64rm },
801 { X86::SHUFPDrri, X86::SHUFPDrmi },
802 { X86::SHUFPSrri, X86::SHUFPSrmi },
803 { X86::SQRTPDr, X86::SQRTPDm },
804 { X86::SQRTPSr, X86::SQRTPSm },
805 { X86::SQRTSDr, X86::SQRTSDm },
806 { X86::SQRTSSr, X86::SQRTSSm },
807 { X86::SUB16rr, X86::SUB16rm },
808 { X86::SUB32rr, X86::SUB32rm },
809 { X86::SUB64rr, X86::SUB64rm },
810 { X86::SUB8rr, X86::SUB8rm },
811 { X86::SUBPDrr, X86::SUBPDrm },
812 { X86::SUBPSrr, X86::SUBPSrm },
813 { X86::SUBSDrr, X86::SUBSDrm },
814 { X86::SUBSSrr, X86::SUBSSrm },
815 // FIXME: TEST*rr -> swapped operand of TEST*mr.
816 { X86::UNPCKHPDrr, X86::UNPCKHPDrm },
817 { X86::UNPCKHPSrr, X86::UNPCKHPSrm },
818 { X86::UNPCKLPDrr, X86::UNPCKLPDrm },
819 { X86::UNPCKLPSrr, X86::UNPCKLPSrm },
820 { X86::XOR16rr, X86::XOR16rm },
821 { X86::XOR32rr, X86::XOR32rm },
822 { X86::XOR64rr, X86::XOR64rm },
823 { X86::XOR8rr, X86::XOR8rm },
824 { X86::XORPDrr, X86::XORPDrm },
825 { X86::XORPSrr, X86::XORPSrm }
827 ASSERT_SORTED(OpcodeTable);
828 OpcodeTablePtr = OpcodeTable;
829 OpcodeTableSize = ARRAY_SIZE(OpcodeTable);
832 // If table selected...
833 if (OpcodeTablePtr) {
834 // Find the Opcode to fuse
835 unsigned fromOpcode = MI->getOpcode();
836 // Lookup fromOpcode in table
837 if (const TableEntry *Entry = TableLookup(OpcodeTablePtr, OpcodeTableSize,
840 NewMI = FuseTwoAddrInst(Entry->to, FrameIndex, MI, TII);
842 NewMI = FuseInst(Entry->to, i, FrameIndex, MI, TII);
843 NewMI->copyKillDeadInfo(MI);
849 if (PrintFailedFusing)
850 cerr << "We failed to fuse ("
851 << ((i == 1) ? "r" : "s") << "): " << *MI;
856 const unsigned *X86RegisterInfo::getCalleeSaveRegs() const {
857 static const unsigned CalleeSaveRegs32Bit[] = {
858 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
860 static const unsigned CalleeSaveRegs64Bit[] = {
861 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
864 return Is64Bit ? CalleeSaveRegs64Bit : CalleeSaveRegs32Bit;
867 const TargetRegisterClass* const*
868 X86RegisterInfo::getCalleeSaveRegClasses() const {
869 static const TargetRegisterClass * const CalleeSaveRegClasses32Bit[] = {
870 &X86::GR32RegClass, &X86::GR32RegClass,
871 &X86::GR32RegClass, &X86::GR32RegClass, 0
873 static const TargetRegisterClass * const CalleeSaveRegClasses64Bit[] = {
874 &X86::GR64RegClass, &X86::GR64RegClass,
875 &X86::GR64RegClass, &X86::GR64RegClass,
876 &X86::GR64RegClass, &X86::GR64RegClass, 0
879 return Is64Bit ? CalleeSaveRegClasses64Bit : CalleeSaveRegClasses32Bit;
882 //===----------------------------------------------------------------------===//
883 // Stack Frame Processing methods
884 //===----------------------------------------------------------------------===//
886 // hasFP - Return true if the specified function should have a dedicated frame
887 // pointer register. This is true if the function has variable sized allocas or
888 // if frame pointer elimination is disabled.
890 static bool hasFP(const MachineFunction &MF) {
891 return (NoFramePointerElim ||
892 MF.getFrameInfo()->hasVarSizedObjects() ||
893 MF.getInfo<X86FunctionInfo>()->getForceFramePointer());
896 void X86RegisterInfo::
897 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
898 MachineBasicBlock::iterator I) const {
900 // If we have a frame pointer, turn the adjcallstackup instruction into a
901 // 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
903 MachineInstr *Old = I;
904 unsigned Amount = Old->getOperand(0).getImmedValue();
906 // We need to keep the stack aligned properly. To do this, we round the
907 // amount of space needed for the outgoing arguments up to the next
908 // alignment boundary.
909 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
910 Amount = (Amount+Align-1)/Align*Align;
912 MachineInstr *New = 0;
913 if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
914 New=BuildMI(TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri), StackPtr)
915 .addReg(StackPtr).addImm(Amount);
917 assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
918 // factor out the amount the callee already popped.
919 unsigned CalleeAmt = Old->getOperand(1).getImmedValue();
922 unsigned Opc = (Amount < 128) ?
923 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
924 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
925 New = BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(Amount);
929 // Replace the pseudo instruction with a new instruction...
930 if (New) MBB.insert(I, New);
932 } else if (I->getOpcode() == X86::ADJCALLSTACKUP) {
933 // If we are performing frame pointer elimination and if the callee pops
934 // something off the stack pointer, add it back. We do this until we have
935 // more advanced stack pointer tracking ability.
936 if (unsigned CalleeAmt = I->getOperand(1).getImmedValue()) {
937 unsigned Opc = (CalleeAmt < 128) ?
938 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
939 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
941 BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(CalleeAmt);
949 void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{
951 MachineInstr &MI = *II;
952 MachineFunction &MF = *MI.getParent()->getParent();
953 while (!MI.getOperand(i).isFrameIndex()) {
955 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
958 int FrameIndex = MI.getOperand(i).getFrameIndex();
959 // This must be part of a four operand memory reference. Replace the
960 // FrameIndex with base register with EBP. Add an offset to the offset.
961 MI.getOperand(i).ChangeToRegister(hasFP(MF) ? FramePtr : StackPtr, false);
963 // Now add the frame object offset to the offset from EBP.
964 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
965 MI.getOperand(i+3).getImmedValue()+SlotSize;
968 Offset += MF.getFrameInfo()->getStackSize();
970 Offset += SlotSize; // Skip the saved EBP
972 MI.getOperand(i+3).ChangeToImmediate(Offset);
976 X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
978 // Create a frame entry for the EBP register that must be saved.
979 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize,SlotSize * -2);
980 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
981 "Slot for EBP register must be last in order to be found!");
985 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
986 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
987 MachineBasicBlock::iterator MBBI = MBB.begin();
988 MachineFrameInfo *MFI = MF.getFrameInfo();
989 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
990 const Function* Fn = MF.getFunction();
991 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
994 // Get the number of bytes to allocate from the FrameInfo
995 unsigned NumBytes = MFI->getStackSize();
996 if (MFI->hasCalls() || MF.getFrameInfo()->hasVarSizedObjects()) {
997 // When we have no frame pointer, we reserve argument space for call sites
998 // in the function immediately on entry to the current function. This
999 // eliminates the need for add/sub ESP brackets around call sites.
1002 NumBytes += MFI->getMaxCallFrameSize();
1004 // Round the size to a multiple of the alignment (don't forget the 4/8 byte
1006 NumBytes = ((NumBytes+SlotSize)+Align-1)/Align*Align - SlotSize;
1009 // Update frame info to pretend that this is part of the stack...
1010 MFI->setStackSize(NumBytes);
1012 if (NumBytes) { // adjust stack pointer: ESP -= numbytes
1013 if (NumBytes >= 4096 && Subtarget->isTargetCygwin()) {
1014 // Function prologue calls _alloca to probe the stack when allocating
1015 // more than 4k bytes in one go. Touching the stack at 4K increments is
1016 // necessary to ensure that the guard pages used by the OS virtual memory
1017 // manager are allocated in correct sequence.
1018 MI = BuildMI(TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes);
1019 MBB.insert(MBBI, MI);
1020 MI = BuildMI(TII.get(X86::CALLpcrel32)).addExternalSymbol("_alloca");
1021 MBB.insert(MBBI, MI);
1023 unsigned Opc = (NumBytes < 128) ?
1024 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
1025 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
1026 MI= BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(NumBytes);
1027 MBB.insert(MBBI, MI);
1032 // Get the offset of the stack slot for the EBP register... which is
1033 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
1034 int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexBegin())+SlotSize;
1035 // Update the frame offset adjustment.
1036 MFI->setOffsetAdjustment(SlotSize-NumBytes);
1038 // Save EBP into the appropriate stack slot...
1039 // mov [ESP-<offset>], EBP
1040 MI = addRegOffset(BuildMI(TII.get(Is64Bit ? X86::MOV64mr : X86::MOV32mr)),
1041 StackPtr, EBPOffset+NumBytes).addReg(FramePtr);
1042 MBB.insert(MBBI, MI);
1044 // Update EBP with the new base value...
1045 if (NumBytes == SlotSize) // mov EBP, ESP
1046 MI = BuildMI(TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr).
1048 else // lea EBP, [ESP+StackSize]
1049 MI = addRegOffset(BuildMI(TII.get(Is64Bit ? X86::LEA64r : X86::LEA32r),
1050 FramePtr), StackPtr, NumBytes-SlotSize);
1052 MBB.insert(MBBI, MI);
1055 // If it's main() on Cygwin\Mingw32 we should align stack as well
1056 if (Fn->hasExternalLinkage() && Fn->getName() == "main" &&
1057 Subtarget->isTargetCygwin()) {
1058 MI= BuildMI(TII.get(X86::AND32ri), X86::ESP).addReg(X86::ESP).addImm(-Align);
1059 MBB.insert(MBBI, MI);
1062 MI = BuildMI(TII.get(X86::MOV32ri), X86::EAX).addImm(Align);
1063 MBB.insert(MBBI, MI);
1064 MI = BuildMI(TII.get(X86::CALLpcrel32)).addExternalSymbol("_alloca");
1065 MBB.insert(MBBI, MI);
1069 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
1070 MachineBasicBlock &MBB) const {
1071 const MachineFrameInfo *MFI = MF.getFrameInfo();
1072 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1074 switch (MBBI->getOpcode()) {
1079 case X86::TAILJMPm: break; // These are ok
1081 assert(0 && "Can only insert epilog into returning blocks");
1086 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr).
1090 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
1092 // Get the number of bytes allocated from the FrameInfo...
1093 unsigned NumBytes = MFI->getStackSize();
1095 if (NumBytes) { // adjust stack pointer back: ESP += numbytes
1096 // If there is an ADD32ri or SUB32ri of ESP immediately before this
1097 // instruction, merge the two instructions.
1098 if (MBBI != MBB.begin()) {
1099 MachineBasicBlock::iterator PI = prior(MBBI);
1100 unsigned Opc = PI->getOpcode();
1101 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
1102 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
1103 PI->getOperand(0).getReg() == StackPtr) {
1104 NumBytes += PI->getOperand(2).getImmedValue();
1106 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
1107 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
1108 PI->getOperand(0).getReg() == StackPtr) {
1109 NumBytes -= PI->getOperand(2).getImmedValue();
1115 unsigned Opc = (NumBytes < 128) ?
1116 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
1117 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
1118 BuildMI(MBB, MBBI, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(NumBytes);
1119 } else if ((int)NumBytes < 0) {
1120 unsigned Opc = (-NumBytes < 128) ?
1121 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
1122 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
1123 BuildMI(MBB, MBBI, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(-NumBytes);
1129 unsigned X86RegisterInfo::getRARegister() const {
1130 return X86::ST0; // use a non-register register
1133 unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
1134 return hasFP(MF) ? FramePtr : StackPtr;
1138 unsigned getX86SubSuperRegister(unsigned Reg, MVT::ValueType VT, bool High) {
1140 default: return Reg;
1145 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1147 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1149 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1151 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1157 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1159 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1161 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1163 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1165 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1167 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1169 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1171 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1173 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1175 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1177 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1179 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1181 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1183 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1185 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1187 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1193 default: return Reg;
1194 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1196 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1198 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1200 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1202 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1204 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1206 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1208 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1210 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1212 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1214 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1216 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1218 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1220 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1222 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1224 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1229 default: return Reg;
1230 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1232 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1234 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1236 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1238 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1240 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1242 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1244 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1246 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1248 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1250 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1252 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1254 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1256 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1258 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1260 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1265 default: return Reg;
1266 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1268 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1270 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1272 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1274 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1276 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1278 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1280 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1282 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1284 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1286 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1288 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1290 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1292 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1294 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1296 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1305 #include "X86GenRegisterInfo.inc"