1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineLocation.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/Target/TargetAsmInfo.h"
34 #include "llvm/Target/TargetFrameInfo.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/STLExtras.h"
40 #include "llvm/Support/Compiler.h"
43 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
44 const TargetInstrInfo &tii)
45 : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() ?
46 X86::ADJCALLSTACKDOWN64 :
47 X86::ADJCALLSTACKDOWN32,
48 tm.getSubtarget<X86Subtarget>().is64Bit() ?
49 X86::ADJCALLSTACKUP64 :
50 X86::ADJCALLSTACKUP32),
52 // Cache some information.
53 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
54 Is64Bit = Subtarget->is64Bit();
55 IsWin64 = Subtarget->isTargetWin64();
56 StackAlign = TM.getFrameInfo()->getStackAlignment();
68 // getDwarfRegNum - This function maps LLVM register identifiers to the
69 // Dwarf specific numbering, used in debug info and exception tables.
71 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
72 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
73 unsigned Flavour = DWARFFlavour::X86_64;
74 if (!Subtarget->is64Bit()) {
75 if (Subtarget->isTargetDarwin()) {
77 Flavour = DWARFFlavour::X86_32_DarwinEH;
79 Flavour = DWARFFlavour::X86_32_Generic;
80 } else if (Subtarget->isTargetCygMing()) {
81 // Unsupported by now, just quick fallback
82 Flavour = DWARFFlavour::X86_32_Generic;
84 Flavour = DWARFFlavour::X86_32_Generic;
88 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
91 // getX86RegNum - This function maps LLVM register identifiers to their X86
92 // specific numbering, which is used in various places encoding instructions.
94 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
96 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
97 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
98 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
99 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
100 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
102 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
104 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
106 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
109 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
111 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
113 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
115 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
117 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
119 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
121 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
123 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
126 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
127 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
128 return RegNo-X86::ST0;
130 case X86::XMM0: case X86::XMM8: case X86::MM0:
132 case X86::XMM1: case X86::XMM9: case X86::MM1:
134 case X86::XMM2: case X86::XMM10: case X86::MM2:
136 case X86::XMM3: case X86::XMM11: case X86::MM3:
138 case X86::XMM4: case X86::XMM12: case X86::MM4:
140 case X86::XMM5: case X86::XMM13: case X86::MM5:
142 case X86::XMM6: case X86::XMM14: case X86::MM6:
144 case X86::XMM7: case X86::XMM15: case X86::MM7:
148 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
149 assert(0 && "Register allocator hasn't allocated reg correctly yet!");
154 const TargetRegisterClass *X86RegisterInfo::getPointerRegClass() const {
155 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
156 if (Subtarget->is64Bit())
157 return &X86::GR64RegClass;
159 return &X86::GR32RegClass;
162 const TargetRegisterClass *
163 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
164 if (RC == &X86::CCRRegClass) {
166 return &X86::GR64RegClass;
168 return &X86::GR32RegClass;
174 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
175 bool callsEHReturn = false;
178 const MachineFrameInfo *MFI = MF->getFrameInfo();
179 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
180 callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
183 static const unsigned CalleeSavedRegs32Bit[] = {
184 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
187 static const unsigned CalleeSavedRegs32EHRet[] = {
188 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
191 static const unsigned CalleeSavedRegs64Bit[] = {
192 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
195 static const unsigned CalleeSavedRegs64EHRet[] = {
196 X86::RAX, X86::RDX, X86::RBX, X86::R12,
197 X86::R13, X86::R14, X86::R15, X86::RBP, 0
200 static const unsigned CalleeSavedRegsWin64[] = {
201 X86::RBX, X86::RBP, X86::RDI, X86::RSI,
202 X86::R12, X86::R13, X86::R14, X86::R15,
203 X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9,
204 X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13,
205 X86::XMM14, X86::XMM15, 0
210 return CalleeSavedRegsWin64;
212 return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit);
214 return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit);
218 const TargetRegisterClass* const*
219 X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
220 bool callsEHReturn = false;
223 const MachineFrameInfo *MFI = MF->getFrameInfo();
224 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
225 callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
228 static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
229 &X86::GR32RegClass, &X86::GR32RegClass,
230 &X86::GR32RegClass, &X86::GR32RegClass, 0
232 static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
233 &X86::GR32RegClass, &X86::GR32RegClass,
234 &X86::GR32RegClass, &X86::GR32RegClass,
235 &X86::GR32RegClass, &X86::GR32RegClass, 0
237 static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
238 &X86::GR64RegClass, &X86::GR64RegClass,
239 &X86::GR64RegClass, &X86::GR64RegClass,
240 &X86::GR64RegClass, &X86::GR64RegClass, 0
242 static const TargetRegisterClass * const CalleeSavedRegClasses64EHRet[] = {
243 &X86::GR64RegClass, &X86::GR64RegClass,
244 &X86::GR64RegClass, &X86::GR64RegClass,
245 &X86::GR64RegClass, &X86::GR64RegClass,
246 &X86::GR64RegClass, &X86::GR64RegClass, 0
248 static const TargetRegisterClass * const CalleeSavedRegClassesWin64[] = {
249 &X86::GR64RegClass, &X86::GR64RegClass,
250 &X86::GR64RegClass, &X86::GR64RegClass,
251 &X86::GR64RegClass, &X86::GR64RegClass,
252 &X86::GR64RegClass, &X86::GR64RegClass,
253 &X86::VR128RegClass, &X86::VR128RegClass,
254 &X86::VR128RegClass, &X86::VR128RegClass,
255 &X86::VR128RegClass, &X86::VR128RegClass,
256 &X86::VR128RegClass, &X86::VR128RegClass,
257 &X86::VR128RegClass, &X86::VR128RegClass, 0
262 return CalleeSavedRegClassesWin64;
264 return (callsEHReturn ?
265 CalleeSavedRegClasses64EHRet : CalleeSavedRegClasses64Bit);
267 return (callsEHReturn ?
268 CalleeSavedRegClasses32EHRet : CalleeSavedRegClasses32Bit);
272 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
273 BitVector Reserved(getNumRegs());
274 // Set the stack-pointer register and its aliases as reserved.
275 Reserved.set(X86::RSP);
276 Reserved.set(X86::ESP);
277 Reserved.set(X86::SP);
278 Reserved.set(X86::SPL);
279 // Set the frame-pointer register and its aliases as reserved if needed.
281 Reserved.set(X86::RBP);
282 Reserved.set(X86::EBP);
283 Reserved.set(X86::BP);
284 Reserved.set(X86::BPL);
286 // Mark the x87 stack registers as reserved, since they don't
287 // behave normally with respect to liveness. We don't fully
288 // model the effects of x87 stack pushes and pops after
290 Reserved.set(X86::ST0);
291 Reserved.set(X86::ST1);
292 Reserved.set(X86::ST2);
293 Reserved.set(X86::ST3);
294 Reserved.set(X86::ST4);
295 Reserved.set(X86::ST5);
296 Reserved.set(X86::ST6);
297 Reserved.set(X86::ST7);
301 //===----------------------------------------------------------------------===//
302 // Stack Frame Processing methods
303 //===----------------------------------------------------------------------===//
305 static unsigned calculateMaxStackAlignment(const MachineFrameInfo *FFI) {
306 unsigned MaxAlign = 0;
307 for (int i = FFI->getObjectIndexBegin(),
308 e = FFI->getObjectIndexEnd(); i != e; ++i) {
309 if (FFI->isDeadObjectIndex(i))
311 unsigned Align = FFI->getObjectAlignment(i);
312 MaxAlign = std::max(MaxAlign, Align);
318 // hasFP - Return true if the specified function should have a dedicated frame
319 // pointer register. This is true if the function has variable sized allocas or
320 // if frame pointer elimination is disabled.
322 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
323 const MachineFrameInfo *MFI = MF.getFrameInfo();
324 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
326 return (NoFramePointerElim ||
327 needsStackRealignment(MF) ||
328 MFI->hasVarSizedObjects() ||
329 MFI->isFrameAddressTaken() ||
330 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
331 (MMI && MMI->callsUnwindInit()));
334 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
335 const MachineFrameInfo *MFI = MF.getFrameInfo();;
337 // FIXME: Currently we don't support stack realignment for functions with
338 // variable-sized allocas
339 return (RealignStack &&
340 (MFI->getMaxAlignment() > StackAlign &&
341 !MFI->hasVarSizedObjects()));
344 bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
345 return !MF.getFrameInfo()->hasVarSizedObjects();
349 X86RegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
350 int Offset = MF.getFrameInfo()->getObjectOffset(FI) + SlotSize;
351 uint64_t StackSize = MF.getFrameInfo()->getStackSize();
353 if (needsStackRealignment(MF)) {
355 // Skip the saved EBP
358 unsigned Align = MF.getFrameInfo()->getObjectAlignment(FI);
359 assert( (-(Offset + StackSize)) % Align == 0);
361 return Offset + StackSize;
364 // FIXME: Support tail calls
367 return Offset + StackSize;
369 // Skip the saved EBP
372 // Skip the RETADDR move area
373 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
374 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
375 if (TailCallReturnAddrDelta < 0) Offset -= TailCallReturnAddrDelta;
381 void X86RegisterInfo::
382 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
383 MachineBasicBlock::iterator I) const {
384 if (!hasReservedCallFrame(MF)) {
385 // If the stack pointer can be changed after prologue, turn the
386 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
387 // adjcallstackdown instruction into 'add ESP, <amt>'
388 // TODO: consider using push / pop instead of sub + store / add
389 MachineInstr *Old = I;
390 uint64_t Amount = Old->getOperand(0).getImm();
392 // We need to keep the stack aligned properly. To do this, we round the
393 // amount of space needed for the outgoing arguments up to the next
394 // alignment boundary.
395 Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
397 MachineInstr *New = 0;
398 if (Old->getOpcode() == getCallFrameSetupOpcode()) {
399 New = BuildMI(MF, Old->getDebugLoc(),
400 TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri),
401 StackPtr).addReg(StackPtr).addImm(Amount);
403 assert(Old->getOpcode() == getCallFrameDestroyOpcode());
404 // factor out the amount the callee already popped.
405 uint64_t CalleeAmt = Old->getOperand(1).getImm();
408 unsigned Opc = (Amount < 128) ?
409 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
410 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
411 New = BuildMI(MF, Old->getDebugLoc(), TII.get(Opc), StackPtr)
412 .addReg(StackPtr).addImm(Amount);
417 // The EFLAGS implicit def is dead.
418 New->getOperand(3).setIsDead();
420 // Replace the pseudo instruction with a new instruction...
424 } else if (I->getOpcode() == getCallFrameDestroyOpcode()) {
425 // If we are performing frame pointer elimination and if the callee pops
426 // something off the stack pointer, add it back. We do this until we have
427 // more advanced stack pointer tracking ability.
428 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
429 unsigned Opc = (CalleeAmt < 128) ?
430 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
431 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
432 MachineInstr *Old = I;
434 BuildMI(MF, Old->getDebugLoc(), TII.get(Opc),
435 StackPtr).addReg(StackPtr).addImm(CalleeAmt);
436 // The EFLAGS implicit def is dead.
437 New->getOperand(3).setIsDead();
446 void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
447 int SPAdj, RegScavenger *RS) const{
448 assert(SPAdj == 0 && "Unexpected");
451 MachineInstr &MI = *II;
452 MachineFunction &MF = *MI.getParent()->getParent();
453 while (!MI.getOperand(i).isFI()) {
455 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
458 int FrameIndex = MI.getOperand(i).getIndex();
461 if (needsStackRealignment(MF))
462 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
464 BasePtr = (hasFP(MF) ? FramePtr : StackPtr);
466 // This must be part of a four operand memory reference. Replace the
467 // FrameIndex with base register with EBP. Add an offset to the offset.
468 MI.getOperand(i).ChangeToRegister(BasePtr, false);
470 // Now add the frame object offset to the offset from EBP.
471 if (MI.getOperand(i+3).isImm()) {
472 // Offset is a 32-bit integer.
473 int Offset = getFrameIndexOffset(MF, FrameIndex) +
474 (int)(MI.getOperand(i+3).getImm());
476 MI.getOperand(i+3).ChangeToImmediate(Offset);
478 // Offset is symbolic. This is extremely rare.
479 uint64_t Offset = getFrameIndexOffset(MF, FrameIndex) +
480 (uint64_t)MI.getOperand(i+3).getOffset();
481 MI.getOperand(i+3).setOffset(Offset);
486 X86RegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
487 RegScavenger *RS) const {
488 MachineFrameInfo *FFI = MF.getFrameInfo();
490 // Calculate and set max stack object alignment early, so we can decide
491 // whether we will need stack realignment (and thus FP).
492 unsigned MaxAlign = std::max(FFI->getMaxAlignment(),
493 calculateMaxStackAlignment(FFI));
495 FFI->setMaxAlignment(MaxAlign);
499 X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
500 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
501 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
502 if (TailCallReturnAddrDelta < 0) {
503 // create RETURNADDR area
513 CreateFixedObject(-TailCallReturnAddrDelta,
514 (-1*SlotSize)+TailCallReturnAddrDelta);
517 assert((TailCallReturnAddrDelta <= 0) &&
518 "The Delta should always be zero or negative");
519 // Create a frame entry for the EBP register that must be saved.
520 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize,
522 TailCallReturnAddrDelta);
523 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
524 "Slot for EBP register must be last in order to be found!");
529 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
530 /// stack pointer by a constant value.
532 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
533 unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
534 const TargetInstrInfo &TII) {
535 bool isSub = NumBytes < 0;
536 uint64_t Offset = isSub ? -NumBytes : NumBytes;
539 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
540 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
542 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
543 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
544 uint64_t Chunk = (1LL << 31) - 1;
547 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
549 BuildMI(MBB, MBBI, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(ThisVal);
550 // The EFLAGS implicit def is dead.
551 MI->getOperand(3).setIsDead();
556 // mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
558 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
559 unsigned StackPtr, uint64_t *NumBytes = NULL) {
560 if (MBBI == MBB.begin()) return;
562 MachineBasicBlock::iterator PI = prior(MBBI);
563 unsigned Opc = PI->getOpcode();
564 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
565 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
566 PI->getOperand(0).getReg() == StackPtr) {
568 *NumBytes += PI->getOperand(2).getImm();
570 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
571 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
572 PI->getOperand(0).getReg() == StackPtr) {
574 *NumBytes -= PI->getOperand(2).getImm();
579 // mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
581 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
582 MachineBasicBlock::iterator &MBBI,
583 unsigned StackPtr, uint64_t *NumBytes = NULL) {
586 if (MBBI == MBB.end()) return;
588 MachineBasicBlock::iterator NI = next(MBBI);
589 if (NI == MBB.end()) return;
591 unsigned Opc = NI->getOpcode();
592 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
593 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
594 NI->getOperand(0).getReg() == StackPtr) {
596 *NumBytes -= NI->getOperand(2).getImm();
599 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
600 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
601 NI->getOperand(0).getReg() == StackPtr) {
603 *NumBytes += NI->getOperand(2).getImm();
609 /// mergeSPUpdates - Checks the instruction before/after the passed
610 /// instruction. If it is an ADD/SUB instruction it is deleted
611 /// argument and the stack adjustment is returned as a positive value for ADD
612 /// and a negative for SUB.
613 static int mergeSPUpdates(MachineBasicBlock &MBB,
614 MachineBasicBlock::iterator &MBBI,
616 bool doMergeWithPrevious) {
618 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
619 (!doMergeWithPrevious && MBBI == MBB.end()))
624 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
625 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : next(MBBI);
626 unsigned Opc = PI->getOpcode();
627 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
628 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
629 PI->getOperand(0).getReg() == StackPtr){
630 Offset += PI->getOperand(2).getImm();
632 if (!doMergeWithPrevious) MBBI = NI;
633 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
634 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
635 PI->getOperand(0).getReg() == StackPtr) {
636 Offset -= PI->getOperand(2).getImm();
638 if (!doMergeWithPrevious) MBBI = NI;
644 void X86RegisterInfo::emitFrameMoves(MachineFunction &MF,
645 unsigned FrameLabelId,
646 unsigned ReadyLabelId) const {
647 MachineFrameInfo *MFI = MF.getFrameInfo();
648 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
652 uint64_t StackSize = MFI->getStackSize();
653 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
654 const TargetData *TD = MF.getTarget().getTargetData();
656 // Calculate amount of bytes used for return address storing
658 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
659 TargetFrameInfo::StackGrowsUp ?
660 TD->getPointerSize() : -TD->getPointerSize());
663 // Show update of SP.
666 MachineLocation SPDst(MachineLocation::VirtualFP);
667 MachineLocation SPSrc(MachineLocation::VirtualFP, 2*stackGrowth);
668 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
670 MachineLocation SPDst(MachineLocation::VirtualFP);
671 MachineLocation SPSrc(MachineLocation::VirtualFP,
672 -StackSize+stackGrowth);
673 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
676 //FIXME: Verify & implement for FP
677 MachineLocation SPDst(StackPtr);
678 MachineLocation SPSrc(StackPtr, stackGrowth);
679 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
682 // Add callee saved registers to move list.
683 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
685 // FIXME: This is dirty hack. The code itself is pretty mess right now.
686 // It should be rewritten from scratch and generalized sometimes.
688 // Determine maximum offset (minumum due to stack growth)
689 int64_t MaxOffset = 0;
690 for (unsigned I = 0, E = CSI.size(); I!=E; ++I)
691 MaxOffset = std::min(MaxOffset,
692 MFI->getObjectOffset(CSI[I].getFrameIdx()));
695 int64_t saveAreaOffset = (hasFP(MF) ? 3 : 2)*stackGrowth;
696 for (unsigned I = 0, E = CSI.size(); I!=E; ++I) {
697 int64_t Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
698 unsigned Reg = CSI[I].getReg();
699 Offset = (MaxOffset-Offset+saveAreaOffset);
700 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
701 MachineLocation CSSrc(Reg);
702 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
707 MachineLocation FPDst(MachineLocation::VirtualFP, 2*stackGrowth);
708 MachineLocation FPSrc(FramePtr);
709 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
712 MachineLocation FPDst(hasFP(MF) ? FramePtr : StackPtr);
713 MachineLocation FPSrc(MachineLocation::VirtualFP);
714 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
718 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
719 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
720 MachineFrameInfo *MFI = MF.getFrameInfo();
721 const Function* Fn = MF.getFunction();
722 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
723 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
724 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
725 MachineBasicBlock::iterator MBBI = MBB.begin();
726 bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
727 !Fn->doesNotThrow() ||
728 UnwindTablesMandatory;
729 DebugLoc DL = DebugLoc::getUnknownLoc();
730 // Prepare for frame info.
731 unsigned FrameLabelId = 0;
733 // Get the number of bytes to allocate from the FrameInfo.
734 uint64_t StackSize = MFI->getStackSize();
735 // Get desired stack alignment
736 uint64_t MaxAlign = MFI->getMaxAlignment();
738 // Add RETADDR move area to callee saved frame size.
739 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
740 if (TailCallReturnAddrDelta < 0)
741 X86FI->setCalleeSavedFrameSize(
742 X86FI->getCalleeSavedFrameSize() +(-TailCallReturnAddrDelta));
744 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
745 // function, and use up to 128 bytes of stack space, don't have a frame
746 // pointer, calls, or dynamic alloca then we do not need to adjust the
747 // stack pointer (we fit in the Red Zone).
748 if (Is64Bit && !DisableRedZone &&
749 !needsStackRealignment(MF) &&
750 !MFI->hasVarSizedObjects() && // No dynamic alloca.
751 !MFI->hasCalls()) { // No calls.
752 uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
753 if (hasFP(MF)) MinSize += SlotSize;
754 StackSize = std::max(MinSize,
755 StackSize > 128 ? StackSize - 128 : 0);
756 MFI->setStackSize(StackSize);
759 // Insert stack pointer adjustment for later moving of return addr. Only
760 // applies to tail call optimized functions where the callee argument stack
761 // size is bigger than the callers.
762 if (TailCallReturnAddrDelta < 0) {
764 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri),
765 StackPtr).addReg(StackPtr).addImm(-TailCallReturnAddrDelta);
766 // The EFLAGS implicit def is dead.
767 MI->getOperand(3).setIsDead();
770 uint64_t NumBytes = 0;
772 // Calculate required stack adjustment
773 uint64_t FrameSize = StackSize - SlotSize;
774 if (needsStackRealignment(MF))
775 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
777 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
779 // Get the offset of the stack slot for the EBP register... which is
780 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
781 // Update the frame offset adjustment.
782 MFI->setOffsetAdjustment(-NumBytes);
784 // Save EBP into the appropriate stack slot...
785 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
786 .addReg(FramePtr, /*isDef=*/false, /*isImp=*/false, /*isKill=*/true);
788 if (needsFrameMoves) {
789 // Mark effective beginning of when frame pointer becomes valid.
790 FrameLabelId = MMI->NextLabelID();
791 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId);
794 // Update EBP with the new base value...
795 BuildMI(MBB, MBBI, DL,
796 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
799 // Mark the FramePtr as live-in in every block except the entry.
800 for (MachineFunction::iterator I = next(MF.begin()), E = MF.end();
802 I->addLiveIn(FramePtr);
805 if (needsStackRealignment(MF)) {
807 BuildMI(MBB, MBBI, DL,
808 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri),
809 StackPtr).addReg(StackPtr).addImm(-MaxAlign);
810 // The EFLAGS implicit def is dead.
811 MI->getOperand(3).setIsDead();
814 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
816 unsigned ReadyLabelId = 0;
817 if (needsFrameMoves) {
818 // Mark effective beginning of when frame pointer is ready.
819 ReadyLabelId = MMI->NextLabelID();
820 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(ReadyLabelId);
823 // Skip the callee-saved push instructions.
824 while (MBBI != MBB.end() &&
825 (MBBI->getOpcode() == X86::PUSH32r ||
826 MBBI->getOpcode() == X86::PUSH64r))
829 if (NumBytes) { // adjust stack pointer: ESP -= numbytes
830 if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
831 // Check, whether EAX is livein for this function
832 bool isEAXAlive = false;
833 for (MachineRegisterInfo::livein_iterator
834 II = MF.getRegInfo().livein_begin(),
835 EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
836 unsigned Reg = II->first;
837 isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
838 Reg == X86::AH || Reg == X86::AL);
841 // Function prologue calls _alloca to probe the stack when allocating
842 // more than 4k bytes in one go. Touching the stack at 4K increments is
843 // necessary to ensure that the guard pages used by the OS virtual memory
844 // manager are allocated in correct sequence.
846 BuildMI(MBB, MBBI,DL, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes);
847 BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
848 .addExternalSymbol("_alloca");
851 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
852 .addReg(X86::EAX, /*isDef=*/false, /*isImp=*/false, /*isKill=*/true);
853 // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
854 // allocated bytes for EAX.
855 BuildMI(MBB, MBBI, DL,
856 TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes-4);
857 BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
858 .addExternalSymbol("_alloca");
860 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
862 StackPtr, false, NumBytes-4);
863 MBB.insert(MBBI, MI);
866 // If there is an SUB32ri of ESP immediately before this instruction,
867 // merge the two. This can be the case when tail call elimination is
868 // enabled and the callee has more arguments then the caller.
869 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
870 // If there is an ADD32ri or SUB32ri of ESP immediately after this
871 // instruction, merge the two instructions.
872 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
875 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
880 emitFrameMoves(MF, FrameLabelId, ReadyLabelId);
883 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
884 MachineBasicBlock &MBB) const {
885 const MachineFrameInfo *MFI = MF.getFrameInfo();
886 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
887 MachineBasicBlock::iterator MBBI = prior(MBB.end());
888 unsigned RetOpcode = MBBI->getOpcode();
889 DebugLoc DL = DebugLoc::getUnknownLoc();
894 case X86::TCRETURNdi:
895 case X86::TCRETURNri:
896 case X86::TCRETURNri64:
897 case X86::TCRETURNdi64:
899 case X86::EH_RETURN64:
902 case X86::TAILJMPm: break; // These are ok
904 assert(0 && "Can only insert epilog into returning blocks");
907 // Get the number of bytes to allocate from the FrameInfo
908 uint64_t StackSize = MFI->getStackSize();
909 uint64_t MaxAlign = MFI->getMaxAlignment();
910 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
911 uint64_t NumBytes = 0;
914 // Calculate required stack adjustment
915 uint64_t FrameSize = StackSize - SlotSize;
916 if (needsStackRealignment(MF))
917 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
919 NumBytes = FrameSize - CSSize;
922 BuildMI(MBB, MBBI, DL,
923 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
925 NumBytes = StackSize - CSSize;
927 // Skip the callee-saved pop instructions.
928 MachineBasicBlock::iterator LastCSPop = MBBI;
929 while (MBBI != MBB.begin()) {
930 MachineBasicBlock::iterator PI = prior(MBBI);
931 unsigned Opc = PI->getOpcode();
932 if (Opc != X86::POP32r && Opc != X86::POP64r &&
933 !PI->getDesc().isTerminator())
938 // If there is an ADD32ri or SUB32ri of ESP immediately before this
939 // instruction, merge the two instructions.
940 if (NumBytes || MFI->hasVarSizedObjects())
941 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
943 // If dynamic alloca is used, then reset esp to point to the last callee-saved
944 // slot before popping them off! Same applies for the case, when stack was
946 if (needsStackRealignment(MF)) {
947 // We cannot use LEA here, because stack pointer was realigned. We need to
948 // deallocate local frame back
950 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
951 MBBI = prior(LastCSPop);
954 BuildMI(MBB, MBBI, DL,
955 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
956 StackPtr).addReg(FramePtr);
957 } else if (MFI->hasVarSizedObjects()) {
959 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
960 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(Opc), StackPtr),
961 FramePtr, false, -CSSize);
962 MBB.insert(MBBI, MI);
964 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
965 StackPtr).addReg(FramePtr);
968 // adjust stack pointer back: ESP += numbytes
970 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
973 // We're returning from function via eh_return.
974 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
975 MBBI = prior(MBB.end());
976 MachineOperand &DestAddr = MBBI->getOperand(0);
977 assert(DestAddr.isReg() && "Offset should be in register!");
978 BuildMI(MBB, MBBI, DL,
979 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
980 StackPtr).addReg(DestAddr.getReg());
981 // Tail call return: adjust the stack pointer and jump to callee
982 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
983 RetOpcode== X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64) {
984 MBBI = prior(MBB.end());
985 MachineOperand &JumpTarget = MBBI->getOperand(0);
986 MachineOperand &StackAdjust = MBBI->getOperand(1);
987 assert(StackAdjust.isImm() && "Expecting immediate value.");
989 // Adjust stack pointer.
990 int StackAdj = StackAdjust.getImm();
991 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
993 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
994 // Incoporate the retaddr area.
995 Offset = StackAdj-MaxTCDelta;
996 assert(Offset >= 0 && "Offset should never be negative");
998 // Check for possible merge with preceeding ADD instruction.
999 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1000 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
1002 // Jump to label or value in register.
1003 if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64)
1004 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPd)).
1005 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1006 else if (RetOpcode== X86::TCRETURNri64) {
1007 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
1009 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr), JumpTarget.getReg());
1010 // Delete the pseudo instruction TCRETURN.
1012 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
1013 (X86FI->getTCReturnAddrDelta() < 0)) {
1014 // Add the return addr area delta back since we are not tail calling.
1015 int delta = -1*X86FI->getTCReturnAddrDelta();
1016 MBBI = prior(MBB.end());
1017 // Check for possible merge with preceeding ADD instruction.
1018 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1019 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
1023 unsigned X86RegisterInfo::getRARegister() const {
1025 return X86::RIP; // Should have dwarf #16
1027 return X86::EIP; // Should have dwarf #8
1030 unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
1031 return hasFP(MF) ? FramePtr : StackPtr;
1034 void X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
1036 // Calculate amount of bytes used for return address storing
1037 int stackGrowth = (Is64Bit ? -8 : -4);
1039 // Initial state of the frame pointer is esp+4.
1040 MachineLocation Dst(MachineLocation::VirtualFP);
1041 MachineLocation Src(StackPtr, stackGrowth);
1042 Moves.push_back(MachineMove(0, Dst, Src));
1044 // Add return address to move list
1045 MachineLocation CSDst(StackPtr, stackGrowth);
1046 MachineLocation CSSrc(getRARegister());
1047 Moves.push_back(MachineMove(0, CSDst, CSSrc));
1050 unsigned X86RegisterInfo::getEHExceptionRegister() const {
1051 assert(0 && "What is the exception register");
1055 unsigned X86RegisterInfo::getEHHandlerRegister() const {
1056 assert(0 && "What is the exception handler register");
1061 unsigned getX86SubSuperRegister(unsigned Reg, MVT VT, bool High) {
1062 switch (VT.getSimpleVT()) {
1063 default: return Reg;
1068 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1070 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1072 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1074 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1080 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1082 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1084 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1086 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1088 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1090 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1092 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1094 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1096 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1098 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1100 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1102 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1104 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1106 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1108 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1110 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1116 default: return Reg;
1117 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1119 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1121 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1123 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1125 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1127 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1129 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1131 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1133 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1135 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1137 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1139 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1141 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1143 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1145 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1147 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1152 default: return Reg;
1153 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1155 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1157 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1159 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1161 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1163 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1165 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1167 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1169 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1171 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1173 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1175 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1177 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1179 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1181 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1183 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1188 default: return Reg;
1189 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1191 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1193 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1195 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1197 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1199 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1201 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1203 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1205 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1207 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1209 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1211 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1213 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1215 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1217 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1219 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1228 #include "X86GenRegisterInfo.inc"
1231 struct VISIBILITY_HIDDEN MSAC : public MachineFunctionPass {
1233 MSAC() : MachineFunctionPass(&ID) {}
1235 virtual bool runOnMachineFunction(MachineFunction &MF) {
1236 MachineFrameInfo *FFI = MF.getFrameInfo();
1237 MachineRegisterInfo &RI = MF.getRegInfo();
1239 // Calculate max stack alignment of all already allocated stack objects.
1240 unsigned MaxAlign = calculateMaxStackAlignment(FFI);
1242 // Be over-conservative: scan over all vreg defs and find, whether vector
1243 // registers are used. If yes - there is probability, that vector register
1244 // will be spilled and thus stack needs to be aligned properly.
1245 for (unsigned RegNum = TargetRegisterInfo::FirstVirtualRegister;
1246 RegNum < RI.getLastVirtReg(); ++RegNum)
1247 MaxAlign = std::max(MaxAlign, RI.getRegClass(RegNum)->getAlignment());
1249 FFI->setMaxAlignment(MaxAlign);
1254 virtual const char *getPassName() const {
1255 return "X86 Maximal Stack Alignment Calculator";
1263 llvm::createX86MaxStackAlignmentCalculatorPass() { return new MSAC(); }