1 //===-- X86PeepholeOpt.cpp - X86 Peephole Optimizer -----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a peephole optimizer for the X86.
12 //===----------------------------------------------------------------------===//
15 #include "llvm/CodeGen/MachineFunctionPass.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "llvm/Target/MRegisterInfo.h"
18 #include "llvm/Target/TargetInstrInfo.h"
19 #include "llvm/Target/TargetMachine.h"
20 #include "llvm/ADT/Statistic.h"
21 #include "llvm/ADT/STLExtras.h"
26 Statistic<> NumPHOpts("x86-peephole",
27 "Number of peephole optimization performed");
28 Statistic<> NumPHMoves("x86-peephole", "Number of peephole moves folded");
29 struct PH : public MachineFunctionPass {
30 virtual bool runOnMachineFunction(MachineFunction &MF);
32 bool PeepholeOptimize(MachineBasicBlock &MBB,
33 MachineBasicBlock::iterator &I);
35 virtual const char *getPassName() const { return "X86 Peephole Optimizer"; }
39 FunctionPass *llvm::createX86PeepholeOptimizerPass() { return new PH(); }
41 bool PH::runOnMachineFunction(MachineFunction &MF) {
44 for (MachineFunction::iterator BI = MF.begin(), E = MF.end(); BI != E; ++BI)
45 for (MachineBasicBlock::iterator I = BI->begin(); I != BI->end(); )
46 if (PeepholeOptimize(*BI, I)) {
56 bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
57 MachineBasicBlock::iterator &I) {
58 assert(I != MBB.end());
59 MachineBasicBlock::iterator NextI = next(I);
62 MachineInstr *Next = (NextI != MBB.end()) ? &*NextI : (MachineInstr*)0;
64 switch (MI->getOpcode()) {
67 case X86::MOV32rr: // Destroy X = X copies...
68 if (MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
74 // A large number of X86 instructions have forms which take an 8-bit
75 // immediate despite the fact that the operands are 16 or 32 bits. Because
76 // this can save three bytes of code size (and icache space), we want to
77 // shrink them if possible.
78 case X86::IMUL16rri: case X86::IMUL32rri:
79 assert(MI->getNumOperands() == 3 && "These should all have 3 operands!");
80 if (MI->getOperand(2).isImmediate()) {
81 int Val = MI->getOperand(2).getImmedValue();
82 // If the value is the same when signed extended from 8 bits...
83 if (Val == (signed int)(signed char)Val) {
85 switch (MI->getOpcode()) {
86 default: assert(0 && "Unknown opcode value!");
87 case X86::IMUL16rri: Opcode = X86::IMUL16rri8; break;
88 case X86::IMUL32rri: Opcode = X86::IMUL32rri8; break;
90 unsigned R0 = MI->getOperand(0).getReg();
91 unsigned R1 = MI->getOperand(1).getReg();
92 I = MBB.insert(MBB.erase(I),
93 BuildMI(Opcode, 2, R0).addReg(R1).addZImm((char)Val));
100 case X86::IMUL16rmi: case X86::IMUL32rmi:
101 assert(MI->getNumOperands() == 6 && "These should all have 6 operands!");
102 if (MI->getOperand(5).isImmediate()) {
103 int Val = MI->getOperand(5).getImmedValue();
104 // If the value is the same when signed extended from 8 bits...
105 if (Val == (signed int)(signed char)Val) {
107 switch (MI->getOpcode()) {
108 default: assert(0 && "Unknown opcode value!");
109 case X86::IMUL16rmi: Opcode = X86::IMUL16rmi8; break;
110 case X86::IMUL32rmi: Opcode = X86::IMUL32rmi8; break;
112 unsigned R0 = MI->getOperand(0).getReg();
113 unsigned R1 = MI->getOperand(1).getReg();
114 unsigned Scale = MI->getOperand(2).getImmedValue();
115 unsigned R2 = MI->getOperand(3).getReg();
116 unsigned Offset = MI->getOperand(4).getImmedValue();
117 I = MBB.insert(MBB.erase(I),
118 BuildMI(Opcode, 5, R0).addReg(R1).addZImm(Scale).
119 addReg(R2).addSImm(Offset).addZImm((char)Val));
126 case X86::ADD16ri: case X86::ADD32ri: case X86::ADC32ri:
127 case X86::SUB16ri: case X86::SUB32ri:
128 case X86::SBB16ri: case X86::SBB32ri:
129 case X86::AND16ri: case X86::AND32ri:
130 case X86::OR16ri: case X86::OR32ri:
131 case X86::XOR16ri: case X86::XOR32ri:
132 assert(MI->getNumOperands() == 2 && "These should all have 2 operands!");
133 if (MI->getOperand(1).isImmediate()) {
134 int Val = MI->getOperand(1).getImmedValue();
135 // If the value is the same when signed extended from 8 bits...
136 if (Val == (signed int)(signed char)Val) {
138 switch (MI->getOpcode()) {
139 default: assert(0 && "Unknown opcode value!");
140 case X86::ADD16ri: Opcode = X86::ADD16ri8; break;
141 case X86::ADD32ri: Opcode = X86::ADD32ri8; break;
142 case X86::ADC32ri: Opcode = X86::ADC32ri8; break;
143 case X86::SUB16ri: Opcode = X86::SUB16ri8; break;
144 case X86::SUB32ri: Opcode = X86::SUB32ri8; break;
145 case X86::SBB16ri: Opcode = X86::SBB16ri8; break;
146 case X86::SBB32ri: Opcode = X86::SBB32ri8; break;
147 case X86::AND16ri: Opcode = X86::AND16ri8; break;
148 case X86::AND32ri: Opcode = X86::AND32ri8; break;
149 case X86::OR16ri: Opcode = X86::OR16ri8; break;
150 case X86::OR32ri: Opcode = X86::OR32ri8; break;
151 case X86::XOR16ri: Opcode = X86::XOR16ri8; break;
152 case X86::XOR32ri: Opcode = X86::XOR32ri8; break;
154 unsigned R0 = MI->getOperand(0).getReg();
155 I = MBB.insert(MBB.erase(I),
156 BuildMI(Opcode, 1, R0, MachineOperand::UseAndDef)
157 .addZImm((char)Val));
163 case X86::ADD16mi: case X86::ADD32mi: case X86::ADC32mi:
164 case X86::SUB16mi: case X86::SUB32mi:
165 case X86::SBB16mi: case X86::SBB32mi:
166 case X86::AND16mi: case X86::AND32mi:
167 case X86::OR16mi: case X86::OR32mi:
168 case X86::XOR16mi: case X86::XOR32mi:
169 assert(MI->getNumOperands() == 5 && "These should all have 5 operands!");
170 if (MI->getOperand(4).isImmediate()) {
171 int Val = MI->getOperand(4).getImmedValue();
172 // If the value is the same when signed extended from 8 bits...
173 if (Val == (signed int)(signed char)Val) {
175 switch (MI->getOpcode()) {
176 default: assert(0 && "Unknown opcode value!");
177 case X86::ADD16mi: Opcode = X86::ADD16mi8; break;
178 case X86::ADD32mi: Opcode = X86::ADD32mi8; break;
179 case X86::ADC32mi: Opcode = X86::ADC32mi8; break;
180 case X86::SUB16mi: Opcode = X86::SUB16mi8; break;
181 case X86::SUB32mi: Opcode = X86::SUB32mi8; break;
182 case X86::SBB16mi: Opcode = X86::SBB16mi8; break;
183 case X86::SBB32mi: Opcode = X86::SBB32mi8; break;
184 case X86::AND16mi: Opcode = X86::AND16mi8; break;
185 case X86::AND32mi: Opcode = X86::AND32mi8; break;
186 case X86::OR16mi: Opcode = X86::OR16mi8; break;
187 case X86::OR32mi: Opcode = X86::OR32mi8; break;
188 case X86::XOR16mi: Opcode = X86::XOR16mi8; break;
189 case X86::XOR32mi: Opcode = X86::XOR32mi8; break;
191 unsigned R0 = MI->getOperand(0).getReg();
192 unsigned Scale = MI->getOperand(1).getImmedValue();
193 unsigned R1 = MI->getOperand(2).getReg();
194 if (MI->getOperand(3).isImmediate()) {
195 unsigned Offset = MI->getOperand(3).getImmedValue();
196 I = MBB.insert(MBB.erase(I),
197 BuildMI(Opcode, 5).addReg(R0).addZImm(Scale).
198 addReg(R1).addSImm(Offset).addZImm((char)Val));
199 } else if (MI->getOperand(3).isGlobalAddress()) {
200 GlobalValue *GA = MI->getOperand(3).getGlobal();
201 int Offset = MI->getOperand(3).getOffset();
202 I = MBB.insert(MBB.erase(I),
203 BuildMI(Opcode, 5).addReg(R0).addZImm(Scale).
204 addReg(R1).addGlobalAddress(GA, false, Offset).
213 case X86::MOV32ri: Size++;
214 case X86::MOV16ri: Size++;
216 // FIXME: We can only do this transformation if we know that flags are not
217 // used here, because XOR clobbers the flags!
218 if (MI->getOperand(1).isImmediate()) { // avoid mov EAX, <value>
219 int Val = MI->getOperand(1).getImmedValue();
220 if (Val == 0) { // mov EAX, 0 -> xor EAX, EAX
221 static const unsigned Opcode[] ={X86::XOR8rr,X86::XOR16rr,X86::XOR32rr};
222 unsigned Reg = MI->getOperand(0).getReg();
223 I = MBB.insert(MBB.erase(I),
224 BuildMI(Opcode[Size], 2, Reg).addReg(Reg).addReg(Reg));
226 } else if (Val == -1) { // mov EAX, -1 -> or EAX, -1
227 // TODO: 'or Reg, -1' has a smaller encoding than 'mov Reg, -1'
232 case X86::BSWAP32r: // Change bswap EAX, bswap EAX into nothing
233 if (Next->getOpcode() == X86::BSWAP32r &&
234 MI->getOperand(0).getReg() == Next->getOperand(0).getReg()) {
235 I = MBB.erase(MBB.erase(I));
245 class UseDefChains : public MachineFunctionPass {
246 std::vector<MachineInstr*> DefiningInst;
248 // getDefinition - Return the machine instruction that defines the specified
249 // SSA virtual register.
250 MachineInstr *getDefinition(unsigned Reg) {
251 assert(MRegisterInfo::isVirtualRegister(Reg) &&
252 "use-def chains only exist for SSA registers!");
253 assert(Reg - MRegisterInfo::FirstVirtualRegister < DefiningInst.size() &&
254 "Unknown register number!");
255 assert(DefiningInst[Reg-MRegisterInfo::FirstVirtualRegister] &&
256 "Unknown register number!");
257 return DefiningInst[Reg-MRegisterInfo::FirstVirtualRegister];
260 // setDefinition - Update the use-def chains to indicate that MI defines
262 void setDefinition(unsigned Reg, MachineInstr *MI) {
263 if (Reg-MRegisterInfo::FirstVirtualRegister >= DefiningInst.size())
264 DefiningInst.resize(Reg-MRegisterInfo::FirstVirtualRegister+1);
265 DefiningInst[Reg-MRegisterInfo::FirstVirtualRegister] = MI;
268 // removeDefinition - Update the use-def chains to forget about Reg
270 void removeDefinition(unsigned Reg) {
271 assert(getDefinition(Reg)); // Check validity
272 DefiningInst[Reg-MRegisterInfo::FirstVirtualRegister] = 0;
275 virtual bool runOnMachineFunction(MachineFunction &MF) {
276 for (MachineFunction::iterator BI = MF.begin(), E = MF.end(); BI!=E; ++BI)
277 for (MachineBasicBlock::iterator I = BI->begin(); I != BI->end(); ++I) {
278 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
279 MachineOperand &MO = I->getOperand(i);
280 if (MO.isRegister() && MO.isDef() && !MO.isUse() &&
281 MRegisterInfo::isVirtualRegister(MO.getReg()))
282 setDefinition(MO.getReg(), I);
288 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
289 AU.setPreservesAll();
290 MachineFunctionPass::getAnalysisUsage(AU);
293 virtual void releaseMemory() {
294 std::vector<MachineInstr*>().swap(DefiningInst);
298 RegisterAnalysis<UseDefChains> X("use-def-chains",
299 "use-def chain construction for machine code");
304 Statistic<> NumSSAPHOpts("x86-ssa-peephole",
305 "Number of SSA peephole optimization performed");
307 /// SSAPH - This pass is an X86-specific, SSA-based, peephole optimizer. This
308 /// pass is really a bad idea: a better instruction selector should completely
309 /// supersume it. However, that will take some time to develop, and the
310 /// simple things this can do are important now.
311 class SSAPH : public MachineFunctionPass {
314 virtual bool runOnMachineFunction(MachineFunction &MF);
316 bool PeepholeOptimize(MachineBasicBlock &MBB,
317 MachineBasicBlock::iterator &I);
319 virtual const char *getPassName() const {
320 return "X86 SSA-based Peephole Optimizer";
323 /// Propagate - Set MI[DestOpNo] = Src[SrcOpNo], optionally change the
324 /// opcode of the instruction, then return true.
325 bool Propagate(MachineInstr *MI, unsigned DestOpNo,
326 MachineInstr *Src, unsigned SrcOpNo, unsigned NewOpcode = 0){
327 MI->getOperand(DestOpNo) = Src->getOperand(SrcOpNo);
328 if (NewOpcode) MI->setOpcode(NewOpcode);
332 /// OptimizeAddress - If we can fold the addressing arithmetic for this
333 /// memory instruction into the instruction itself, do so and return true.
334 bool OptimizeAddress(MachineInstr *MI, unsigned OpNo);
336 /// getDefininingInst - If the specified operand is a read of an SSA
337 /// register, return the machine instruction defining it, otherwise, return
339 MachineInstr *getDefiningInst(MachineOperand &MO) {
340 if (MO.isDef() || !MO.isRegister() ||
341 !MRegisterInfo::isVirtualRegister(MO.getReg())) return 0;
342 return UDC->getDefinition(MO.getReg());
345 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
346 AU.addRequired<UseDefChains>();
347 AU.addPreserved<UseDefChains>();
348 MachineFunctionPass::getAnalysisUsage(AU);
353 FunctionPass *llvm::createX86SSAPeepholeOptimizerPass() { return new SSAPH(); }
355 bool SSAPH::runOnMachineFunction(MachineFunction &MF) {
356 bool Changed = false;
359 UDC = &getAnalysis<UseDefChains>();
362 LocalChanged = false;
364 for (MachineFunction::iterator BI = MF.begin(), E = MF.end(); BI != E; ++BI)
365 for (MachineBasicBlock::iterator I = BI->begin(); I != BI->end(); )
366 if (PeepholeOptimize(*BI, I)) {
371 Changed |= LocalChanged;
372 } while (LocalChanged);
377 static bool isValidScaleAmount(unsigned Scale) {
378 return Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8;
381 /// OptimizeAddress - If we can fold the addressing arithmetic for this
382 /// memory instruction into the instruction itself, do so and return true.
383 bool SSAPH::OptimizeAddress(MachineInstr *MI, unsigned OpNo) {
384 MachineOperand &BaseRegOp = MI->getOperand(OpNo+0);
385 MachineOperand &ScaleOp = MI->getOperand(OpNo+1);
386 MachineOperand &IndexRegOp = MI->getOperand(OpNo+2);
387 MachineOperand &DisplacementOp = MI->getOperand(OpNo+3);
389 unsigned BaseReg = BaseRegOp.hasAllocatedReg() ? BaseRegOp.getReg() : 0;
390 unsigned Scale = ScaleOp.getImmedValue();
391 unsigned IndexReg = IndexRegOp.hasAllocatedReg() ? IndexRegOp.getReg() : 0;
393 bool Changed = false;
395 // If the base register is unset, and the index register is set with a scale
396 // of 1, move it to be the base register.
397 if (BaseRegOp.hasAllocatedReg() && BaseReg == 0 &&
398 Scale == 1 && IndexReg != 0) {
399 BaseRegOp.setReg(IndexReg);
400 IndexRegOp.setReg(0);
404 // Attempt to fold instructions used by the base register into the instruction
405 if (MachineInstr *DefInst = getDefiningInst(BaseRegOp)) {
406 switch (DefInst->getOpcode()) {
408 // If there is no displacement set for this instruction set one now.
409 // FIXME: If we can fold two immediates together, we should do so!
410 if (DisplacementOp.isImmediate() && !DisplacementOp.getImmedValue()) {
411 if (DefInst->getOperand(1).isImmediate()) {
413 return Propagate(MI, OpNo+3, DefInst, 1);
419 // If the source is a register-register add, and we do not yet have an
420 // index register, fold the add into the memory address.
422 BaseRegOp = DefInst->getOperand(1);
423 IndexRegOp = DefInst->getOperand(2);
424 ScaleOp.setImmedValue(1);
430 // If this shift could be folded into the index portion of the address if
431 // it were the index register, move it to the index register operand now,
432 // so it will be folded in below.
433 if ((Scale == 1 || (IndexReg == 0 && IndexRegOp.hasAllocatedReg())) &&
434 DefInst->getOperand(2).getImmedValue() < 4) {
435 std::swap(BaseRegOp, IndexRegOp);
436 ScaleOp.setImmedValue(1); Scale = 1;
437 std::swap(IndexReg, BaseReg);
444 // Attempt to fold instructions used by the index into the instruction
445 if (MachineInstr *DefInst = getDefiningInst(IndexRegOp)) {
446 switch (DefInst->getOpcode()) {
448 // Figure out what the resulting scale would be if we folded this shift.
449 unsigned ResScale = Scale * (1 << DefInst->getOperand(2).getImmedValue());
450 if (isValidScaleAmount(ResScale)) {
451 IndexRegOp = DefInst->getOperand(1);
452 ScaleOp.setImmedValue(ResScale);
463 bool SSAPH::PeepholeOptimize(MachineBasicBlock &MBB,
464 MachineBasicBlock::iterator &I) {
465 MachineBasicBlock::iterator NextI = next(I);
467 MachineInstr *MI = I;
468 MachineInstr *Next = (NextI != MBB.end()) ? &*NextI : (MachineInstr*)0;
470 bool Changed = false;
472 const TargetInstrInfo &TII = *MBB.getParent()->getTarget().getInstrInfo();
474 // Scan the operands of this instruction. If any operands are
475 // register-register copies, replace the operand with the source.
476 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
477 // Is this an SSA register use?
478 if (MachineInstr *DefInst = getDefiningInst(MI->getOperand(i))) {
479 // If the operand is a vreg-vreg copy, it is always safe to replace the
480 // source value with the input operand.
481 unsigned Source, Dest;
482 if (TII.isMoveInstr(*DefInst, Source, Dest)) {
483 // Don't propagate physical registers into any instructions.
484 if (DefInst->getOperand(1).isRegister() &&
485 MRegisterInfo::isVirtualRegister(Source)) {
486 MI->getOperand(i).setReg(Source);
494 // Perform instruction specific optimizations.
495 switch (MI->getOpcode()) {
497 // Register to memory stores. Format: <base,scale,indexreg,immdisp>, srcreg
498 case X86::MOV32mr: case X86::MOV16mr: case X86::MOV8mr:
499 case X86::MOV32mi: case X86::MOV16mi: case X86::MOV8mi:
500 // Check to see if we can fold the source instruction into this one...
501 if (MachineInstr *SrcInst = getDefiningInst(MI->getOperand(4))) {
502 switch (SrcInst->getOpcode()) {
503 // Fold the immediate value into the store, if possible.
504 case X86::MOV8ri: return Propagate(MI, 4, SrcInst, 1, X86::MOV8mi);
505 case X86::MOV16ri: return Propagate(MI, 4, SrcInst, 1, X86::MOV16mi);
506 case X86::MOV32ri: return Propagate(MI, 4, SrcInst, 1, X86::MOV32mi);
511 // If we can optimize the addressing expression, do so now.
512 if (OptimizeAddress(MI, 0))
519 // If we can optimize the addressing expression, do so now.
520 if (OptimizeAddress(MI, 1))