1 //===-- X86/X86MCCodeEmitter.cpp - Convert X86 code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the X86MCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "x86-emitter"
16 #include "X86InstrInfo.h"
17 #include "llvm/MC/MCCodeEmitter.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/Support/raw_ostream.h"
22 // FIXME: This should move to a header.
26 reloc_pcrel_word = FirstTargetFixupKind,
29 reloc_absolute_word_sext,
36 class X86MCCodeEmitter : public MCCodeEmitter {
37 X86MCCodeEmitter(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
38 void operator=(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
39 const TargetMachine &TM;
40 const TargetInstrInfo &TII;
43 X86MCCodeEmitter(TargetMachine &tm, bool is64Bit)
44 : TM(tm), TII(*TM.getInstrInfo()) {
45 Is64BitMode = is64Bit;
48 ~X86MCCodeEmitter() {}
50 unsigned getNumFixupKinds() const {
54 MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
55 static MCFixupKindInfo Infos[] = {
56 { "reloc_pcrel_word", 0, 4 * 8 },
57 { "reloc_picrel_word", 0, 4 * 8 },
58 { "reloc_absolute_word", 0, 4 * 8 },
59 { "reloc_absolute_word_sext", 0, 4 * 8 },
60 { "reloc_absolute_dword", 0, 8 * 8 }
63 assert(Kind >= FirstTargetFixupKind && Kind < MaxTargetFixupKind &&
65 return Infos[Kind - FirstTargetFixupKind];
68 static unsigned GetX86RegNum(const MCOperand &MO) {
69 return X86RegisterInfo::getX86RegNum(MO.getReg());
72 void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
77 void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
78 raw_ostream &OS) const {
79 // Output the constant in little endian byte order.
80 for (unsigned i = 0; i != Size; ++i) {
81 EmitByte(Val & 255, CurByte, OS);
86 void EmitDisplacementField(const MCOperand &Disp, unsigned &CurByte,
88 SmallVectorImpl<MCFixup> &Fixups) const;
90 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
92 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
93 return RM | (RegOpcode << 3) | (Mod << 6);
96 void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
97 unsigned &CurByte, raw_ostream &OS) const {
98 EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS);
101 void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base,
102 unsigned &CurByte, raw_ostream &OS) const {
103 // SIB byte is in the same format as the ModRMByte.
104 EmitByte(ModRMByte(SS, Index, Base), CurByte, OS);
108 void EmitMemModRMByte(const MCInst &MI, unsigned Op,
109 unsigned RegOpcodeField,
110 unsigned &CurByte, raw_ostream &OS,
111 SmallVectorImpl<MCFixup> &Fixups) const;
113 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
114 SmallVectorImpl<MCFixup> &Fixups) const;
118 } // end anonymous namespace
121 MCCodeEmitter *llvm::createX86_32MCCodeEmitter(const Target &,
123 return new X86MCCodeEmitter(TM, false);
126 MCCodeEmitter *llvm::createX86_64MCCodeEmitter(const Target &,
128 return new X86MCCodeEmitter(TM, true);
132 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
133 /// sign-extended field.
134 static bool isDisp8(int Value) {
135 return Value == (signed char)Value;
138 void X86MCCodeEmitter::
139 EmitDisplacementField(const MCOperand &DispOp,
140 unsigned &CurByte, raw_ostream &OS,
141 SmallVectorImpl<MCFixup> &Fixups) const {
142 // If this is a simple integer displacement that doesn't require a relocation,
144 if (DispOp.isImm()) {
145 EmitConstant(DispOp.getImm(), 4, CurByte, OS);
150 // Otherwise, this is something that requires a relocation. Emit it as such
152 unsigned RelocType = Is64BitMode ?
153 (IsPCRel ? X86::reloc_pcrel_word : X86::reloc_absolute_word_sext)
154 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
157 // Emit a symbolic constant as a fixup and 4 zeros.
158 Fixups.push_back(MCFixup::Create(CurByte, DispOp.getExpr(),
159 MCFixupKind(X86::reloc_absolute_word)));
160 EmitConstant(0, 4, CurByte, OS);
164 void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
165 unsigned RegOpcodeField,
168 SmallVectorImpl<MCFixup> &Fixups) const{
169 const MCOperand &Disp = MI.getOperand(Op+3);
170 const MCOperand &Base = MI.getOperand(Op);
171 const MCOperand &Scale = MI.getOperand(Op+1);
172 const MCOperand &IndexReg = MI.getOperand(Op+2);
173 unsigned BaseReg = Base.getReg();
175 // Determine whether a SIB byte is needed.
176 // If no BaseReg, issue a RIP relative instruction only if the MCE can
177 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
178 // 2-7) and absolute references.
179 if (// The SIB byte must be used if there is an index register.
180 IndexReg.getReg() == 0 &&
181 // The SIB byte must be used if the base is ESP/RSP.
182 BaseReg != X86::ESP && BaseReg != X86::RSP &&
183 // If there is no base register and we're in 64-bit mode, we need a SIB
184 // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
185 (!Is64BitMode || BaseReg != 0)) {
187 if (BaseReg == 0 || // [disp32] in X86-32 mode
188 BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
189 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
190 EmitDisplacementField(Disp, CurByte, OS, Fixups);
194 unsigned BaseRegNo = GetX86RegNum(Base);
196 // If the base is not EBP/ESP and there is no displacement, use simple
197 // indirect register encoding, this handles addresses like [EAX]. The
198 // encoding for [EBP] with no displacement means [disp32] so we handle it
199 // by emitting a displacement of 0 below.
200 if (Disp.isImm() && Disp.getImm() == 0 && BaseRegNo != N86::EBP) {
201 EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS);
205 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
206 if (Disp.isImm() && isDisp8(Disp.getImm())) {
207 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
208 EmitConstant(Disp.getImm(), 1, CurByte, OS);
212 // Otherwise, emit the most general non-SIB encoding: [REG+disp32]
213 EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS);
214 EmitDisplacementField(Disp, CurByte, OS, Fixups);
218 // We need a SIB byte, so start by outputting the ModR/M byte first
219 assert(IndexReg.getReg() != X86::ESP &&
220 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
222 bool ForceDisp32 = false;
223 bool ForceDisp8 = false;
225 // If there is no base register, we emit the special case SIB byte with
226 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
227 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
229 } else if (!Disp.isImm()) {
230 // Emit the normal disp32 encoding.
231 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
233 } else if (Disp.getImm() == 0 && BaseReg != X86::EBP) {
234 // Emit no displacement ModR/M byte
235 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
236 } else if (isDisp8(Disp.getImm())) {
237 // Emit the disp8 encoding.
238 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
239 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
241 // Emit the normal disp32 encoding.
242 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
245 // Calculate what the SS field value should be...
246 static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
247 unsigned SS = SSTable[Scale.getImm()];
250 // Handle the SIB byte for the case where there is no base, see Intel
251 // Manual 2A, table 2-7. The displacement has already been output.
253 if (IndexReg.getReg())
254 IndexRegNo = GetX86RegNum(IndexReg);
255 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
257 EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS);
260 if (IndexReg.getReg())
261 IndexRegNo = GetX86RegNum(IndexReg);
263 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
264 EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS);
267 // Do we need to output a displacement?
269 EmitConstant(Disp.getImm(), 1, CurByte, OS);
270 else if (ForceDisp32 || Disp.getImm() != 0)
271 EmitDisplacementField(Disp, CurByte, OS, Fixups);
274 /// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64
275 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
276 /// size, and 3) use of X86-64 extended registers.
277 static unsigned DetermineREXPrefix(const MCInst &MI, unsigned TSFlags,
278 const TargetInstrDesc &Desc) {
281 // Pseudo instructions do not need REX prefix byte.
282 if ((TSFlags & X86II::FormMask) == X86II::Pseudo)
284 if (TSFlags & X86II::REX_W)
287 if (MI.getNumOperands() == 0) return REX;
289 unsigned NumOps = MI.getNumOperands();
290 // FIXME: MCInst should explicitize the two-addrness.
291 bool isTwoAddr = NumOps > 1 &&
292 Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
294 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
295 unsigned i = isTwoAddr ? 1 : 0;
296 for (; i != NumOps; ++i) {
297 const MCOperand &MO = MI.getOperand(i);
298 if (!MO.isReg()) continue;
299 unsigned Reg = MO.getReg();
300 if (!X86InstrInfo::isX86_64NonExtLowByteReg(Reg)) continue;
301 // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything
302 // that returns non-zero.
307 switch (TSFlags & X86II::FormMask) {
308 case X86II::MRMInitReg: assert(0 && "FIXME: Remove this!");
309 case X86II::MRMSrcReg:
310 if (MI.getOperand(0).isReg() &&
311 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
313 i = isTwoAddr ? 2 : 1;
314 for (; i != NumOps; ++i) {
315 const MCOperand &MO = MI.getOperand(i);
316 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
320 case X86II::MRMSrcMem: {
321 if (MI.getOperand(0).isReg() &&
322 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
325 i = isTwoAddr ? 2 : 1;
326 for (; i != NumOps; ++i) {
327 const MCOperand &MO = MI.getOperand(i);
329 if (X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
336 case X86II::MRM0m: case X86II::MRM1m:
337 case X86II::MRM2m: case X86II::MRM3m:
338 case X86II::MRM4m: case X86II::MRM5m:
339 case X86II::MRM6m: case X86II::MRM7m:
340 case X86II::MRMDestMem: {
341 unsigned e = (isTwoAddr ? X86AddrNumOperands+1 : X86AddrNumOperands);
342 i = isTwoAddr ? 1 : 0;
343 if (NumOps > e && MI.getOperand(e).isReg() &&
344 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(e).getReg()))
347 for (; i != e; ++i) {
348 const MCOperand &MO = MI.getOperand(i);
350 if (X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
358 if (MI.getOperand(0).isReg() &&
359 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
361 i = isTwoAddr ? 2 : 1;
362 for (unsigned e = NumOps; i != e; ++i) {
363 const MCOperand &MO = MI.getOperand(i);
364 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
372 void X86MCCodeEmitter::
373 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
374 SmallVectorImpl<MCFixup> &Fixups) const {
375 unsigned Opcode = MI.getOpcode();
376 const TargetInstrDesc &Desc = TII.get(Opcode);
377 unsigned TSFlags = Desc.TSFlags;
379 // Keep track of the current byte being emitted.
380 unsigned CurByte = 0;
382 // FIXME: We should emit the prefixes in exactly the same order as GAS does,
383 // in order to provide diffability.
385 // Emit the lock opcode prefix as needed.
386 if (TSFlags & X86II::LOCK)
387 EmitByte(0xF0, CurByte, OS);
389 // Emit segment override opcode prefix as needed.
390 switch (TSFlags & X86II::SegOvrMask) {
391 default: assert(0 && "Invalid segment!");
392 case 0: break; // No segment override!
394 EmitByte(0x64, CurByte, OS);
397 EmitByte(0x65, CurByte, OS);
401 // Emit the repeat opcode prefix as needed.
402 if ((TSFlags & X86II::Op0Mask) == X86II::REP)
403 EmitByte(0xF3, CurByte, OS);
405 // Emit the operand size opcode prefix as needed.
406 if (TSFlags & X86II::OpSize)
407 EmitByte(0x66, CurByte, OS);
409 // Emit the address size opcode prefix as needed.
410 if (TSFlags & X86II::AdSize)
411 EmitByte(0x67, CurByte, OS);
413 bool Need0FPrefix = false;
414 switch (TSFlags & X86II::Op0Mask) {
415 default: assert(0 && "Invalid prefix!");
416 case 0: break; // No prefix!
417 case X86II::REP: break; // already handled.
418 case X86II::TB: // Two-byte opcode prefix
419 case X86II::T8: // 0F 38
420 case X86II::TA: // 0F 3A
423 case X86II::TF: // F2 0F 38
424 EmitByte(0xF2, CurByte, OS);
427 case X86II::XS: // F3 0F
428 EmitByte(0xF3, CurByte, OS);
431 case X86II::XD: // F2 0F
432 EmitByte(0xF2, CurByte, OS);
435 case X86II::D8: EmitByte(0xD8, CurByte, OS); break;
436 case X86II::D9: EmitByte(0xD9, CurByte, OS); break;
437 case X86II::DA: EmitByte(0xDA, CurByte, OS); break;
438 case X86II::DB: EmitByte(0xDB, CurByte, OS); break;
439 case X86II::DC: EmitByte(0xDC, CurByte, OS); break;
440 case X86II::DD: EmitByte(0xDD, CurByte, OS); break;
441 case X86II::DE: EmitByte(0xDE, CurByte, OS); break;
442 case X86II::DF: EmitByte(0xDF, CurByte, OS); break;
445 // Handle REX prefix.
446 // FIXME: Can this come before F2 etc to simplify emission?
448 if (unsigned REX = DetermineREXPrefix(MI, TSFlags, Desc))
449 EmitByte(0x40 | REX, CurByte, OS);
452 // 0x0F escape code must be emitted just before the opcode.
454 EmitByte(0x0F, CurByte, OS);
456 // FIXME: Pull this up into previous switch if REX can be moved earlier.
457 switch (TSFlags & X86II::Op0Mask) {
458 case X86II::TF: // F2 0F 38
459 case X86II::T8: // 0F 38
460 EmitByte(0x38, CurByte, OS);
462 case X86II::TA: // 0F 3A
463 EmitByte(0x3A, CurByte, OS);
467 // If this is a two-address instruction, skip one of the register operands.
468 unsigned NumOps = Desc.getNumOperands();
470 if (NumOps > 1 && Desc.getOperandConstraint(1, TOI::TIED_TO) != -1)
472 else if (NumOps > 2 && Desc.getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
473 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
476 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
477 switch (TSFlags & X86II::FormMask) {
478 case X86II::MRMInitReg:
479 assert(0 && "FIXME: Remove this form when the JIT moves to MCCodeEmitter!");
480 default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n";
481 assert(0 && "Unknown FormMask value in X86MCCodeEmitter!");
482 case X86II::RawFrm: {
483 EmitByte(BaseOpcode, CurByte, OS);
488 assert(0 && "Unimpl RawFrm expr");
492 case X86II::AddRegFrm: {
493 EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS);
497 const MCOperand &MO1 = MI.getOperand(CurOp++);
499 unsigned Size = X86II::getSizeOfImm(TSFlags);
500 EmitConstant(MO1.getImm(), Size, CurByte, OS);
504 assert(0 && "Unimpl AddRegFrm expr");
508 case X86II::MRMDestReg:
509 EmitByte(BaseOpcode, CurByte, OS);
510 EmitRegModRMByte(MI.getOperand(CurOp),
511 GetX86RegNum(MI.getOperand(CurOp+1)), CurByte, OS);
514 EmitConstant(MI.getOperand(CurOp++).getImm(),
515 X86II::getSizeOfImm(TSFlags), CurByte, OS);
518 case X86II::MRMDestMem:
519 EmitByte(BaseOpcode, CurByte, OS);
520 EmitMemModRMByte(MI, CurOp,
521 GetX86RegNum(MI.getOperand(CurOp + X86AddrNumOperands)),
522 CurByte, OS, Fixups);
523 CurOp += X86AddrNumOperands + 1;
525 EmitConstant(MI.getOperand(CurOp++).getImm(),
526 X86II::getSizeOfImm(TSFlags), CurByte, OS);
529 case X86II::MRMSrcReg:
530 EmitByte(BaseOpcode, CurByte, OS);
531 EmitRegModRMByte(MI.getOperand(CurOp+1), GetX86RegNum(MI.getOperand(CurOp)),
535 EmitConstant(MI.getOperand(CurOp++).getImm(),
536 X86II::getSizeOfImm(TSFlags), CurByte, OS);
539 case X86II::MRMSrcMem: {
540 EmitByte(BaseOpcode, CurByte, OS);
542 // FIXME: Maybe lea should have its own form? This is a horrible hack.
544 if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
545 Opcode == X86::LEA16r || Opcode == X86::LEA32r)
546 AddrOperands = X86AddrNumOperands - 1; // No segment register
548 AddrOperands = X86AddrNumOperands;
550 EmitMemModRMByte(MI, CurOp+1, GetX86RegNum(MI.getOperand(CurOp)),
551 CurByte, OS, Fixups);
552 CurOp += AddrOperands + 1;
554 EmitConstant(MI.getOperand(CurOp++).getImm(),
555 X86II::getSizeOfImm(TSFlags), CurByte, OS);
559 case X86II::MRM0r: case X86II::MRM1r:
560 case X86II::MRM2r: case X86II::MRM3r:
561 case X86II::MRM4r: case X86II::MRM5r:
562 case X86II::MRM6r: case X86II::MRM7r: {
563 EmitByte(BaseOpcode, CurByte, OS);
565 // Special handling of lfence, mfence, monitor, and mwait.
566 // FIXME: This is terrible, they should get proper encoding bits in TSFlags.
567 if (Opcode == X86::LFENCE || Opcode == X86::MFENCE ||
568 Opcode == X86::MONITOR || Opcode == X86::MWAIT) {
569 EmitByte(ModRMByte(3, (TSFlags & X86II::FormMask)-X86II::MRM0r, 0),
574 case X86::MONITOR: EmitByte(0xC8, CurByte, OS); break;
575 case X86::MWAIT: EmitByte(0xC9, CurByte, OS); break;
578 EmitRegModRMByte(MI.getOperand(CurOp++),
579 (TSFlags & X86II::FormMask)-X86II::MRM0r,
586 const MCOperand &MO1 = MI.getOperand(CurOp++);
588 EmitConstant(MO1.getImm(), X86II::getSizeOfImm(TSFlags), CurByte, OS);
592 assert(0 && "relo unimpl");
594 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
595 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
596 if (Opcode == X86::MOV64ri32)
597 rt = X86::reloc_absolute_word_sext; // FIXME: add X86II flag?
598 if (MO1.isGlobal()) {
599 bool Indirect = gvNeedsNonLazyPtr(MO1, TM);
600 emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
602 } else if (MO1.isSymbol())
603 emitExternalSymbolAddress(MO1.getSymbolName(), rt);
604 else if (MO1.isCPI())
605 emitConstPoolAddress(MO1.getIndex(), rt);
606 else if (MO1.isJTI())
607 emitJumpTableAddress(MO1.getIndex(), rt);
611 case X86II::MRM0m: case X86II::MRM1m:
612 case X86II::MRM2m: case X86II::MRM3m:
613 case X86II::MRM4m: case X86II::MRM5m:
614 case X86II::MRM6m: case X86II::MRM7m: {
615 EmitByte(BaseOpcode, CurByte, OS);
616 EmitMemModRMByte(MI, CurOp, (TSFlags & X86II::FormMask)-X86II::MRM0m,
617 CurByte, OS, Fixups);
618 CurOp += X86AddrNumOperands;
623 const MCOperand &MO = MI.getOperand(CurOp++);
625 EmitConstant(MO.getImm(), X86II::getSizeOfImm(TSFlags), CurByte, OS);
629 assert(0 && "relo not handled");
631 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
632 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
633 if (Opcode == X86::MOV64mi32)
634 rt = X86::reloc_absolute_word_sext; // FIXME: add X86II flag?
636 bool Indirect = gvNeedsNonLazyPtr(MO, TM);
637 emitGlobalAddress(MO.getGlobal(), rt, MO.getOffset(), 0,
639 } else if (MO.isSymbol())
640 emitExternalSymbolAddress(MO.getSymbolName(), rt);
642 emitConstPoolAddress(MO.getIndex(), rt);
644 emitJumpTableAddress(MO.getIndex(), rt);
652 if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) {
653 errs() << "Cannot encode all operands of: ";