1 //===-- X86/X86MCCodeEmitter.cpp - Convert X86 code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the X86MCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "x86-emitter"
16 #include "X86InstrInfo.h"
17 #include "llvm/MC/MCCodeEmitter.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/Support/raw_ostream.h"
22 // FIXME: This should move to a header.
26 reloc_pcrel_4byte = FirstTargetFixupKind, // 32-bit pcrel, e.g. a branch.
27 reloc_pcrel_1byte // 8-bit pcrel, e.g. branch_1
33 class X86MCCodeEmitter : public MCCodeEmitter {
34 X86MCCodeEmitter(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
35 void operator=(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
36 const TargetMachine &TM;
37 const TargetInstrInfo &TII;
40 X86MCCodeEmitter(TargetMachine &tm, bool is64Bit)
41 : TM(tm), TII(*TM.getInstrInfo()) {
42 Is64BitMode = is64Bit;
45 ~X86MCCodeEmitter() {}
47 unsigned getNumFixupKinds() const {
51 MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
52 static MCFixupKindInfo Infos[] = {
53 { "reloc_pcrel_4byte", 0, 4 * 8 },
54 { "reloc_pcrel_1byte", 0, 1 * 8 }
57 assert(Kind >= FirstTargetFixupKind && Kind < MaxTargetFixupKind &&
59 return Infos[Kind - FirstTargetFixupKind];
62 static unsigned GetX86RegNum(const MCOperand &MO) {
63 return X86RegisterInfo::getX86RegNum(MO.getReg());
66 void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
71 void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
72 raw_ostream &OS) const {
73 // Output the constant in little endian byte order.
74 for (unsigned i = 0; i != Size; ++i) {
75 EmitByte(Val & 255, CurByte, OS);
80 void EmitImmediate(const MCOperand &Disp, unsigned ImmSize,
81 unsigned &CurByte, raw_ostream &OS,
82 SmallVectorImpl<MCFixup> &Fixups) const;
84 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
86 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
87 return RM | (RegOpcode << 3) | (Mod << 6);
90 void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
91 unsigned &CurByte, raw_ostream &OS) const {
92 EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS);
95 void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base,
96 unsigned &CurByte, raw_ostream &OS) const {
97 // SIB byte is in the same format as the ModRMByte.
98 EmitByte(ModRMByte(SS, Index, Base), CurByte, OS);
102 void EmitMemModRMByte(const MCInst &MI, unsigned Op,
103 unsigned RegOpcodeField,
104 unsigned &CurByte, raw_ostream &OS,
105 SmallVectorImpl<MCFixup> &Fixups) const;
107 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
108 SmallVectorImpl<MCFixup> &Fixups) const;
112 } // end anonymous namespace
115 MCCodeEmitter *llvm::createX86_32MCCodeEmitter(const Target &,
117 return new X86MCCodeEmitter(TM, false);
120 MCCodeEmitter *llvm::createX86_64MCCodeEmitter(const Target &,
122 return new X86MCCodeEmitter(TM, true);
126 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
127 /// sign-extended field.
128 static bool isDisp8(int Value) {
129 return Value == (signed char)Value;
132 void X86MCCodeEmitter::
133 EmitImmediate(const MCOperand &DispOp, unsigned Size,
134 unsigned &CurByte, raw_ostream &OS,
135 SmallVectorImpl<MCFixup> &Fixups) const {
136 // If this is a simple integer displacement that doesn't require a relocation,
138 if (DispOp.isImm()) {
139 EmitConstant(DispOp.getImm(), Size, CurByte, OS);
143 // FIXME: Pass in the relocation type, this is just a hack..
146 FixupKind = FK_Data_1;
148 FixupKind = FK_Data_2;
150 FixupKind = FK_Data_4;
152 assert(Size == 8 && "Unknown immediate size");
153 FixupKind = FK_Data_8;
156 // Emit a symbolic constant as a fixup and 4 zeros.
157 Fixups.push_back(MCFixup::Create(CurByte, DispOp.getExpr(),
158 MCFixupKind(FixupKind)));
159 EmitConstant(0, Size, CurByte, OS);
163 void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
164 unsigned RegOpcodeField,
167 SmallVectorImpl<MCFixup> &Fixups) const{
168 const MCOperand &Disp = MI.getOperand(Op+3);
169 const MCOperand &Base = MI.getOperand(Op);
170 const MCOperand &Scale = MI.getOperand(Op+1);
171 const MCOperand &IndexReg = MI.getOperand(Op+2);
172 unsigned BaseReg = Base.getReg();
173 unsigned BaseRegNo = -1U;
174 if (BaseReg != 0 && BaseReg != X86::RIP)
175 BaseRegNo = GetX86RegNum(Base);
177 // Determine whether a SIB byte is needed.
178 // If no BaseReg, issue a RIP relative instruction only if the MCE can
179 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
180 // 2-7) and absolute references.
182 if (// The SIB byte must be used if there is an index register.
183 IndexReg.getReg() == 0 &&
184 // The SIB byte must be used if the base is ESP/RSP/R12, all of which
185 // encode to an R/M value of 4, which indicates that a SIB byte is
187 BaseRegNo != N86::ESP &&
188 // If there is no base register and we're in 64-bit mode, we need a SIB
189 // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
190 (!Is64BitMode || BaseReg != 0)) {
192 if (BaseReg == 0 || // [disp32] in X86-32 mode
193 BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
194 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
195 EmitImmediate(Disp, 4, CurByte, OS, Fixups);
199 // If the base is not EBP/ESP and there is no displacement, use simple
200 // indirect register encoding, this handles addresses like [EAX]. The
201 // encoding for [EBP] with no displacement means [disp32] so we handle it
202 // by emitting a displacement of 0 below.
203 if (Disp.isImm() && Disp.getImm() == 0 && BaseRegNo != N86::EBP) {
204 EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS);
208 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
209 if (Disp.isImm() && isDisp8(Disp.getImm())) {
210 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
211 EmitImmediate(Disp, 1, CurByte, OS, Fixups);
215 // Otherwise, emit the most general non-SIB encoding: [REG+disp32]
216 EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS);
217 EmitImmediate(Disp, 4, CurByte, OS, Fixups);
221 // We need a SIB byte, so start by outputting the ModR/M byte first
222 assert(IndexReg.getReg() != X86::ESP &&
223 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
225 bool ForceDisp32 = false;
226 bool ForceDisp8 = false;
228 // If there is no base register, we emit the special case SIB byte with
229 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
230 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
232 } else if (!Disp.isImm()) {
233 // Emit the normal disp32 encoding.
234 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
236 } else if (Disp.getImm() == 0 && BaseReg != X86::EBP) {
237 // Emit no displacement ModR/M byte
238 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
239 } else if (isDisp8(Disp.getImm())) {
240 // Emit the disp8 encoding.
241 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
242 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
244 // Emit the normal disp32 encoding.
245 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
248 // Calculate what the SS field value should be...
249 static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
250 unsigned SS = SSTable[Scale.getImm()];
253 // Handle the SIB byte for the case where there is no base, see Intel
254 // Manual 2A, table 2-7. The displacement has already been output.
256 if (IndexReg.getReg())
257 IndexRegNo = GetX86RegNum(IndexReg);
258 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
260 EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS);
263 if (IndexReg.getReg())
264 IndexRegNo = GetX86RegNum(IndexReg);
266 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
267 EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS);
270 // Do we need to output a displacement?
272 EmitImmediate(Disp, 1, CurByte, OS, Fixups);
273 else if (ForceDisp32 || Disp.getImm() != 0)
274 EmitImmediate(Disp, 4, CurByte, OS, Fixups);
277 /// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64
278 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
279 /// size, and 3) use of X86-64 extended registers.
280 static unsigned DetermineREXPrefix(const MCInst &MI, unsigned TSFlags,
281 const TargetInstrDesc &Desc) {
284 // Pseudo instructions do not need REX prefix byte.
285 if ((TSFlags & X86II::FormMask) == X86II::Pseudo)
287 if (TSFlags & X86II::REX_W)
290 if (MI.getNumOperands() == 0) return REX;
292 unsigned NumOps = MI.getNumOperands();
293 // FIXME: MCInst should explicitize the two-addrness.
294 bool isTwoAddr = NumOps > 1 &&
295 Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
297 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
298 unsigned i = isTwoAddr ? 1 : 0;
299 for (; i != NumOps; ++i) {
300 const MCOperand &MO = MI.getOperand(i);
301 if (!MO.isReg()) continue;
302 unsigned Reg = MO.getReg();
303 if (!X86InstrInfo::isX86_64NonExtLowByteReg(Reg)) continue;
304 // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything
305 // that returns non-zero.
310 switch (TSFlags & X86II::FormMask) {
311 case X86II::MRMInitReg: assert(0 && "FIXME: Remove this!");
312 case X86II::MRMSrcReg:
313 if (MI.getOperand(0).isReg() &&
314 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
316 i = isTwoAddr ? 2 : 1;
317 for (; i != NumOps; ++i) {
318 const MCOperand &MO = MI.getOperand(i);
319 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
323 case X86II::MRMSrcMem: {
324 if (MI.getOperand(0).isReg() &&
325 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
328 i = isTwoAddr ? 2 : 1;
329 for (; i != NumOps; ++i) {
330 const MCOperand &MO = MI.getOperand(i);
332 if (X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
339 case X86II::MRM0m: case X86II::MRM1m:
340 case X86II::MRM2m: case X86II::MRM3m:
341 case X86II::MRM4m: case X86II::MRM5m:
342 case X86II::MRM6m: case X86II::MRM7m:
343 case X86II::MRMDestMem: {
344 unsigned e = (isTwoAddr ? X86AddrNumOperands+1 : X86AddrNumOperands);
345 i = isTwoAddr ? 1 : 0;
346 if (NumOps > e && MI.getOperand(e).isReg() &&
347 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(e).getReg()))
350 for (; i != e; ++i) {
351 const MCOperand &MO = MI.getOperand(i);
353 if (X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
361 if (MI.getOperand(0).isReg() &&
362 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
364 i = isTwoAddr ? 2 : 1;
365 for (unsigned e = NumOps; i != e; ++i) {
366 const MCOperand &MO = MI.getOperand(i);
367 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
375 void X86MCCodeEmitter::
376 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
377 SmallVectorImpl<MCFixup> &Fixups) const {
378 unsigned Opcode = MI.getOpcode();
379 const TargetInstrDesc &Desc = TII.get(Opcode);
380 unsigned TSFlags = Desc.TSFlags;
382 // Keep track of the current byte being emitted.
383 unsigned CurByte = 0;
385 // FIXME: We should emit the prefixes in exactly the same order as GAS does,
386 // in order to provide diffability.
388 // Emit the lock opcode prefix as needed.
389 if (TSFlags & X86II::LOCK)
390 EmitByte(0xF0, CurByte, OS);
392 // Emit segment override opcode prefix as needed.
393 switch (TSFlags & X86II::SegOvrMask) {
394 default: assert(0 && "Invalid segment!");
395 case 0: break; // No segment override!
397 EmitByte(0x64, CurByte, OS);
400 EmitByte(0x65, CurByte, OS);
404 // Emit the repeat opcode prefix as needed.
405 if ((TSFlags & X86II::Op0Mask) == X86II::REP)
406 EmitByte(0xF3, CurByte, OS);
408 // Emit the operand size opcode prefix as needed.
409 if (TSFlags & X86II::OpSize)
410 EmitByte(0x66, CurByte, OS);
412 // Emit the address size opcode prefix as needed.
413 if (TSFlags & X86II::AdSize)
414 EmitByte(0x67, CurByte, OS);
416 bool Need0FPrefix = false;
417 switch (TSFlags & X86II::Op0Mask) {
418 default: assert(0 && "Invalid prefix!");
419 case 0: break; // No prefix!
420 case X86II::REP: break; // already handled.
421 case X86II::TB: // Two-byte opcode prefix
422 case X86II::T8: // 0F 38
423 case X86II::TA: // 0F 3A
426 case X86II::TF: // F2 0F 38
427 EmitByte(0xF2, CurByte, OS);
430 case X86II::XS: // F3 0F
431 EmitByte(0xF3, CurByte, OS);
434 case X86II::XD: // F2 0F
435 EmitByte(0xF2, CurByte, OS);
438 case X86II::D8: EmitByte(0xD8, CurByte, OS); break;
439 case X86II::D9: EmitByte(0xD9, CurByte, OS); break;
440 case X86II::DA: EmitByte(0xDA, CurByte, OS); break;
441 case X86II::DB: EmitByte(0xDB, CurByte, OS); break;
442 case X86II::DC: EmitByte(0xDC, CurByte, OS); break;
443 case X86II::DD: EmitByte(0xDD, CurByte, OS); break;
444 case X86II::DE: EmitByte(0xDE, CurByte, OS); break;
445 case X86II::DF: EmitByte(0xDF, CurByte, OS); break;
448 // Handle REX prefix.
449 // FIXME: Can this come before F2 etc to simplify emission?
451 if (unsigned REX = DetermineREXPrefix(MI, TSFlags, Desc))
452 EmitByte(0x40 | REX, CurByte, OS);
455 // 0x0F escape code must be emitted just before the opcode.
457 EmitByte(0x0F, CurByte, OS);
459 // FIXME: Pull this up into previous switch if REX can be moved earlier.
460 switch (TSFlags & X86II::Op0Mask) {
461 case X86II::TF: // F2 0F 38
462 case X86II::T8: // 0F 38
463 EmitByte(0x38, CurByte, OS);
465 case X86II::TA: // 0F 3A
466 EmitByte(0x3A, CurByte, OS);
470 // If this is a two-address instruction, skip one of the register operands.
471 unsigned NumOps = Desc.getNumOperands();
473 if (NumOps > 1 && Desc.getOperandConstraint(1, TOI::TIED_TO) != -1)
475 else if (NumOps > 2 && Desc.getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
476 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
479 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
480 switch (TSFlags & X86II::FormMask) {
481 case X86II::MRMInitReg:
482 assert(0 && "FIXME: Remove this form when the JIT moves to MCCodeEmitter!");
483 default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n";
484 assert(0 && "Unknown FormMask value in X86MCCodeEmitter!");
486 EmitByte(BaseOpcode, CurByte, OS);
489 case X86II::AddRegFrm:
490 EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS);
493 case X86II::MRMDestReg:
494 EmitByte(BaseOpcode, CurByte, OS);
495 EmitRegModRMByte(MI.getOperand(CurOp),
496 GetX86RegNum(MI.getOperand(CurOp+1)), CurByte, OS);
500 case X86II::MRMDestMem:
501 EmitByte(BaseOpcode, CurByte, OS);
502 EmitMemModRMByte(MI, CurOp,
503 GetX86RegNum(MI.getOperand(CurOp + X86AddrNumOperands)),
504 CurByte, OS, Fixups);
505 CurOp += X86AddrNumOperands + 1;
508 case X86II::MRMSrcReg:
509 EmitByte(BaseOpcode, CurByte, OS);
510 EmitRegModRMByte(MI.getOperand(CurOp+1), GetX86RegNum(MI.getOperand(CurOp)),
515 case X86II::MRMSrcMem: {
516 EmitByte(BaseOpcode, CurByte, OS);
518 // FIXME: Maybe lea should have its own form? This is a horrible hack.
520 if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
521 Opcode == X86::LEA16r || Opcode == X86::LEA32r)
522 AddrOperands = X86AddrNumOperands - 1; // No segment register
524 AddrOperands = X86AddrNumOperands;
526 EmitMemModRMByte(MI, CurOp+1, GetX86RegNum(MI.getOperand(CurOp)),
527 CurByte, OS, Fixups);
528 CurOp += AddrOperands + 1;
532 case X86II::MRM0r: case X86II::MRM1r:
533 case X86II::MRM2r: case X86II::MRM3r:
534 case X86II::MRM4r: case X86II::MRM5r:
535 case X86II::MRM6r: case X86II::MRM7r:
536 EmitByte(BaseOpcode, CurByte, OS);
538 // Special handling of lfence, mfence, monitor, and mwait.
539 // FIXME: This is terrible, they should get proper encoding bits in TSFlags.
540 if (Opcode == X86::LFENCE || Opcode == X86::MFENCE ||
541 Opcode == X86::MONITOR || Opcode == X86::MWAIT) {
542 EmitByte(ModRMByte(3, (TSFlags & X86II::FormMask)-X86II::MRM0r, 0),
547 case X86::MONITOR: EmitByte(0xC8, CurByte, OS); break;
548 case X86::MWAIT: EmitByte(0xC9, CurByte, OS); break;
551 EmitRegModRMByte(MI.getOperand(CurOp++),
552 (TSFlags & X86II::FormMask)-X86II::MRM0r,
556 case X86II::MRM0m: case X86II::MRM1m:
557 case X86II::MRM2m: case X86II::MRM3m:
558 case X86II::MRM4m: case X86II::MRM5m:
559 case X86II::MRM6m: case X86II::MRM7m:
560 EmitByte(BaseOpcode, CurByte, OS);
561 EmitMemModRMByte(MI, CurOp, (TSFlags & X86II::FormMask)-X86II::MRM0m,
562 CurByte, OS, Fixups);
563 CurOp += X86AddrNumOperands;
567 // If there is a remaining operand, it must be a trailing immediate. Emit it
568 // according to the right size for the instruction.
569 // FIXME: This should pass in whether the value is pc relative or not. This
570 // information should be aquired from TSFlags as well.
572 EmitImmediate(MI.getOperand(CurOp++), X86II::getSizeOfImm(TSFlags),
573 CurByte, OS, Fixups);
577 if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) {
578 errs() << "Cannot encode all operands of: ";