1 //====- X86InstrX86-64.td - Describe the X86 Instruction Set ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the Evan Cheng and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86-64 instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // Operand Definitions...
20 // 64-bits but only 32 bits are significant.
21 def i64i32imm : Operand<i64>;
22 // 64-bits but only 8 bits are significant.
23 def i64i8imm : Operand<i64>;
25 def lea64mem : Operand<i64> {
26 let PrintMethod = "printi64mem";
27 let MIOperandInfo = (ops GR64, i8imm, GR64, i32imm);
30 def lea64_32mem : Operand<i32> {
31 let PrintMethod = "printlea64_32mem";
32 let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
35 //===----------------------------------------------------------------------===//
36 // Complex Pattern Definitions...
38 def lea64addr : ComplexPattern<i64, 4, "SelectLEAAddr",
39 [add, mul, shl, or, frameindex, X86Wrapper],
42 //===----------------------------------------------------------------------===//
43 // Pattern fragments...
46 def i64immSExt32 : PatLeaf<(i64 imm), [{
47 // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
48 // sign extended field.
49 return (int64_t)N->getValue() == (int32_t)N->getValue();
52 def i64immZExt32 : PatLeaf<(i64 imm), [{
53 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
54 // unsignedsign extended field.
55 return (uint64_t)N->getValue() == (uint32_t)N->getValue();
58 def i64immSExt8 : PatLeaf<(i64 imm), [{
59 // i64immSExt8 predicate - True if the 64-bit immediate fits in a 8-bit
60 // sign extended field.
61 return (int64_t)N->getValue() == (int8_t)N->getValue();
64 def sextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (sextloadi1 node:$ptr))>;
65 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
66 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
67 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
69 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
70 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
71 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
72 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
74 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
75 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
76 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
77 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
79 //===----------------------------------------------------------------------===//
80 // Instruction list...
83 def IMPLICIT_DEF_GR64 : I<0, Pseudo, (outs GR64:$dst), (ins),
85 [(set GR64:$dst, (undef))]>;
87 //===----------------------------------------------------------------------===//
88 // Call Instructions...
91 // All calls clobber the non-callee saved registers...
92 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
93 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
94 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
95 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
96 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS] in {
97 def CALL64pcrel32 : I<0xE8, RawFrm, (outs), (ins i64imm:$dst, variable_ops),
98 "call\t${dst:call}", []>;
99 def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
100 "call\t{*}$dst", [(X86call GR64:$dst)]>;
101 def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops),
102 "call\t{*}$dst", []>;
106 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
107 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
108 [(brind GR64:$dst)]>;
109 def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
110 [(brind (loadi64 addr:$dst))]>;
113 //===----------------------------------------------------------------------===//
114 // Miscellaneous Instructions...
116 let Defs = [RBP,RSP], Uses = [RBP,RSP] in
117 def LEAVE64 : I<0xC9, RawFrm,
118 (outs), (ins), "leave", []>;
119 let Defs = [RSP], Uses = [RSP] in {
120 def POP64r : I<0x58, AddRegFrm,
121 (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
122 def PUSH64r : I<0x50, AddRegFrm,
123 (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
126 let Defs = [RSP, EFLAGS], Uses = [RSP] in
127 def POPFQ : I<0x9D, RawFrm, (outs), (ins), "popf", []>, REX_W;
128 let Defs = [RSP], Uses = [RSP, EFLAGS] in
129 def PUSHFQ : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
131 def LEA64_32r : I<0x8D, MRMSrcMem,
132 (outs GR32:$dst), (ins lea64_32mem:$src),
133 "lea{l}\t{$src|$dst}, {$dst|$src}",
134 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In64BitMode]>;
136 def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins lea64mem:$src),
137 "lea{q}\t{$src|$dst}, {$dst|$src}",
138 [(set GR64:$dst, lea64addr:$src)]>;
140 let isTwoAddress = 1 in
141 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
143 [(set GR64:$dst, (bswap GR64:$src))]>, TB;
145 def XCHG64rr : RI<0x87, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
146 "xchg{q}\t{$src2|$src1}, {$src1|$src2}", []>;
147 def XCHG64mr : RI<0x87, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
148 "xchg{q}\t{$src2|$src1}, {$src1|$src2}", []>;
149 def XCHG64rm : RI<0x87, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
150 "xchg{q}\t{$src2|$src1}, {$src1|$src2}", []>;
153 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI] in
154 def REP_MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
155 [(X86rep_movs i64)]>, REP;
156 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI] in
157 def REP_STOSQ : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
158 [(X86rep_stos i64)]>, REP;
160 //===----------------------------------------------------------------------===//
161 // Move Instructions...
164 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
165 "mov{q}\t{$src, $dst|$dst, $src}", []>;
167 let isReMaterializable = 1 in {
168 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
169 "movabs{q}\t{$src, $dst|$dst, $src}",
170 [(set GR64:$dst, imm:$src)]>;
171 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
172 "mov{q}\t{$src, $dst|$dst, $src}",
173 [(set GR64:$dst, i64immSExt32:$src)]>;
177 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
178 "mov{q}\t{$src, $dst|$dst, $src}",
179 [(set GR64:$dst, (load addr:$src))]>;
181 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
182 "mov{q}\t{$src, $dst|$dst, $src}",
183 [(store GR64:$src, addr:$dst)]>;
184 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
185 "mov{q}\t{$src, $dst|$dst, $src}",
186 [(store i64immSExt32:$src, addr:$dst)]>;
188 // Sign/Zero extenders
190 def MOVSX64rr8 : RI<0xBE, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
191 "movs{bq|x}\t{$src, $dst|$dst, $src}",
192 [(set GR64:$dst, (sext GR8:$src))]>, TB;
193 def MOVSX64rm8 : RI<0xBE, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
194 "movs{bq|x}\t{$src, $dst|$dst, $src}",
195 [(set GR64:$dst, (sextloadi64i8 addr:$src))]>, TB;
196 def MOVSX64rr16: RI<0xBF, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
197 "movs{wq|x}\t{$src, $dst|$dst, $src}",
198 [(set GR64:$dst, (sext GR16:$src))]>, TB;
199 def MOVSX64rm16: RI<0xBF, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
200 "movs{wq|x}\t{$src, $dst|$dst, $src}",
201 [(set GR64:$dst, (sextloadi64i16 addr:$src))]>, TB;
202 def MOVSX64rr32: RI<0x63, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
203 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
204 [(set GR64:$dst, (sext GR32:$src))]>;
205 def MOVSX64rm32: RI<0x63, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
206 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
207 [(set GR64:$dst, (sextloadi64i32 addr:$src))]>;
209 def MOVZX64rr8 : RI<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
210 "movz{bq|x}\t{$src, $dst|$dst, $src}",
211 [(set GR64:$dst, (zext GR8:$src))]>, TB;
212 def MOVZX64rm8 : RI<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
213 "movz{bq|x}\t{$src, $dst|$dst, $src}",
214 [(set GR64:$dst, (zextloadi64i8 addr:$src))]>, TB;
215 def MOVZX64rr16: RI<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
216 "movz{wq|x}\t{$src, $dst|$dst, $src}",
217 [(set GR64:$dst, (zext GR16:$src))]>, TB;
218 def MOVZX64rm16: RI<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
219 "movz{wq|x}\t{$src, $dst|$dst, $src}",
220 [(set GR64:$dst, (zextloadi64i16 addr:$src))]>, TB;
222 let Defs = [RAX], Uses = [EAX] in
223 def CDQE : RI<0x98, RawFrm, (outs), (ins),
224 "{cltq|cdqe}", []>; // RAX = signext(EAX)
226 let Defs = [RAX,RDX], Uses = [RAX] in
227 def CQO : RI<0x99, RawFrm, (outs), (ins),
228 "{cqto|cqo}", []>; // RDX:RAX = signext(RAX)
230 //===----------------------------------------------------------------------===//
231 // Arithmetic Instructions...
234 let Defs = [EFLAGS] in {
235 let isTwoAddress = 1 in {
236 let isConvertibleToThreeAddress = 1 in {
237 let isCommutable = 1 in
238 def ADD64rr : RI<0x01, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
239 "add{q}\t{$src2, $dst|$dst, $src2}",
240 [(set GR64:$dst, (add GR64:$src1, GR64:$src2))]>;
242 def ADD64ri32 : RIi32<0x81, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
243 "add{q}\t{$src2, $dst|$dst, $src2}",
244 [(set GR64:$dst, (add GR64:$src1, i64immSExt32:$src2))]>;
245 def ADD64ri8 : RIi8<0x83, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
246 "add{q}\t{$src2, $dst|$dst, $src2}",
247 [(set GR64:$dst, (add GR64:$src1, i64immSExt8:$src2))]>;
248 } // isConvertibleToThreeAddress
250 def ADD64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
251 "add{q}\t{$src2, $dst|$dst, $src2}",
252 [(set GR64:$dst, (add GR64:$src1, (load addr:$src2)))]>;
255 def ADD64mr : RI<0x01, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
256 "add{q}\t{$src2, $dst|$dst, $src2}",
257 [(store (add (load addr:$dst), GR64:$src2), addr:$dst)]>;
258 def ADD64mi32 : RIi32<0x81, MRM0m, (outs), (ins i64mem:$dst, i64i32imm :$src2),
259 "add{q}\t{$src2, $dst|$dst, $src2}",
260 [(store (add (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>;
261 def ADD64mi8 : RIi8<0x83, MRM0m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
262 "add{q}\t{$src2, $dst|$dst, $src2}",
263 [(store (add (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
265 let isTwoAddress = 1 in {
266 let isCommutable = 1 in
267 def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
268 "adc{q}\t{$src2, $dst|$dst, $src2}",
269 [(set GR64:$dst, (adde GR64:$src1, GR64:$src2))]>;
271 def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
272 "adc{q}\t{$src2, $dst|$dst, $src2}",
273 [(set GR64:$dst, (adde GR64:$src1, (load addr:$src2)))]>;
275 def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
276 "adc{q}\t{$src2, $dst|$dst, $src2}",
277 [(set GR64:$dst, (adde GR64:$src1, i64immSExt32:$src2))]>;
278 def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
279 "adc{q}\t{$src2, $dst|$dst, $src2}",
280 [(set GR64:$dst, (adde GR64:$src1, i64immSExt8:$src2))]>;
283 def ADC64mr : RI<0x11, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
284 "adc{q}\t{$src2, $dst|$dst, $src2}",
285 [(store (adde (load addr:$dst), GR64:$src2), addr:$dst)]>;
286 def ADC64mi32 : RIi32<0x81, MRM2m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
287 "adc{q}\t{$src2, $dst|$dst, $src2}",
288 [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
289 def ADC64mi8 : RIi8<0x83, MRM2m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
290 "adc{q}\t{$src2, $dst|$dst, $src2}",
291 [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
293 let isTwoAddress = 1 in {
294 def SUB64rr : RI<0x29, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
295 "sub{q}\t{$src2, $dst|$dst, $src2}",
296 [(set GR64:$dst, (sub GR64:$src1, GR64:$src2))]>;
298 def SUB64rm : RI<0x2B, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
299 "sub{q}\t{$src2, $dst|$dst, $src2}",
300 [(set GR64:$dst, (sub GR64:$src1, (load addr:$src2)))]>;
302 def SUB64ri32 : RIi32<0x81, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
303 "sub{q}\t{$src2, $dst|$dst, $src2}",
304 [(set GR64:$dst, (sub GR64:$src1, i64immSExt32:$src2))]>;
305 def SUB64ri8 : RIi8<0x83, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
306 "sub{q}\t{$src2, $dst|$dst, $src2}",
307 [(set GR64:$dst, (sub GR64:$src1, i64immSExt8:$src2))]>;
310 def SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
311 "sub{q}\t{$src2, $dst|$dst, $src2}",
312 [(store (sub (load addr:$dst), GR64:$src2), addr:$dst)]>;
313 def SUB64mi32 : RIi32<0x81, MRM5m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
314 "sub{q}\t{$src2, $dst|$dst, $src2}",
315 [(store (sub (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>;
316 def SUB64mi8 : RIi8<0x83, MRM5m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
317 "sub{q}\t{$src2, $dst|$dst, $src2}",
318 [(store (sub (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
320 let isTwoAddress = 1 in {
321 def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
322 "sbb{q}\t{$src2, $dst|$dst, $src2}",
323 [(set GR64:$dst, (sube GR64:$src1, GR64:$src2))]>;
325 def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
326 "sbb{q}\t{$src2, $dst|$dst, $src2}",
327 [(set GR64:$dst, (sube GR64:$src1, (load addr:$src2)))]>;
329 def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
330 "sbb{q}\t{$src2, $dst|$dst, $src2}",
331 [(set GR64:$dst, (sube GR64:$src1, i64immSExt32:$src2))]>;
332 def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
333 "sbb{q}\t{$src2, $dst|$dst, $src2}",
334 [(set GR64:$dst, (sube GR64:$src1, i64immSExt8:$src2))]>;
337 def SBB64mr : RI<0x19, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
338 "sbb{q}\t{$src2, $dst|$dst, $src2}",
339 [(store (sube (load addr:$dst), GR64:$src2), addr:$dst)]>;
340 def SBB64mi32 : RIi32<0x81, MRM3m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
341 "sbb{q}\t{$src2, $dst|$dst, $src2}",
342 [(store (sube (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>;
343 def SBB64mi8 : RIi8<0x83, MRM3m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
344 "sbb{q}\t{$src2, $dst|$dst, $src2}",
345 [(store (sube (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
348 // Unsigned multiplication
349 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in {
350 def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
351 "mul{q}\t$src", []>; // RAX,RDX = RAX*GR64
352 def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
353 "mul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
355 // Signed multiplication
356 def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src),
357 "imul{q}\t$src", []>; // RAX,RDX = RAX*GR64
358 def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src),
359 "imul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
362 let Defs = [EFLAGS] in {
363 let isTwoAddress = 1 in {
364 let isCommutable = 1 in
365 def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
366 "imul{q}\t{$src2, $dst|$dst, $src2}",
367 [(set GR64:$dst, (mul GR64:$src1, GR64:$src2))]>, TB;
369 def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
370 "imul{q}\t{$src2, $dst|$dst, $src2}",
371 [(set GR64:$dst, (mul GR64:$src1, (load addr:$src2)))]>, TB;
374 // Suprisingly enough, these are not two address instructions!
375 def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 = GR64*I32
376 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
377 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
378 [(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2))]>;
379 def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8
380 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
381 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
382 [(set GR64:$dst, (mul GR64:$src1, i64immSExt8:$src2))]>;
383 def IMUL64rmi32 : RIi32<0x69, MRMSrcMem, // GR64 = [mem64]*I32
384 (outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),
385 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
386 [(set GR64:$dst, (mul (load addr:$src1), i64immSExt32:$src2))]>;
387 def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8
388 (outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2),
389 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
390 [(set GR64:$dst, (mul (load addr:$src1), i64immSExt8:$src2))]>;
393 // Unsigned division / remainder
394 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in {
395 def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX
397 def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX
400 // Signed division / remainder
401 def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX
402 "idiv{q}\t$src", []>;
403 def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX
404 "idiv{q}\t$src", []>;
407 // Unary instructions
408 let Defs = [EFLAGS], CodeSize = 2 in {
409 let isTwoAddress = 1 in
410 def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src), "neg{q}\t$dst",
411 [(set GR64:$dst, (ineg GR64:$src))]>;
412 def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst",
413 [(store (ineg (loadi64 addr:$dst)), addr:$dst)]>;
415 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
416 def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src), "inc{q}\t$dst",
417 [(set GR64:$dst, (add GR64:$src, 1))]>;
418 def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",
419 [(store (add (loadi64 addr:$dst), 1), addr:$dst)]>;
421 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
422 def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src), "dec{q}\t$dst",
423 [(set GR64:$dst, (add GR64:$src, -1))]>;
424 def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
425 [(store (add (loadi64 addr:$dst), -1), addr:$dst)]>;
427 // In 64-bit mode, single byte INC and DEC cannot be encoded.
428 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in {
429 // Can transform into LEA.
430 def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
431 [(set GR16:$dst, (add GR16:$src, 1))]>,
432 OpSize, Requires<[In64BitMode]>;
433 def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
434 [(set GR32:$dst, (add GR32:$src, 1))]>,
435 Requires<[In64BitMode]>;
436 def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
437 [(set GR16:$dst, (add GR16:$src, -1))]>,
438 OpSize, Requires<[In64BitMode]>;
439 def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
440 [(set GR32:$dst, (add GR32:$src, -1))]>,
441 Requires<[In64BitMode]>;
442 } // isConvertibleToThreeAddress
443 } // Defs = [EFLAGS], CodeSize
446 let Defs = [EFLAGS] in {
447 // Shift instructions
448 let isTwoAddress = 1 in {
450 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src),
451 "shl{q}\t{%cl, $dst|$dst, %CL}",
452 [(set GR64:$dst, (shl GR64:$src, CL))]>;
453 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
454 "shl{q}\t{$src2, $dst|$dst, $src2}",
455 [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>;
456 def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
461 def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
462 "shl{q}\t{%cl, $dst|$dst, %CL}",
463 [(store (shl (loadi64 addr:$dst), CL), addr:$dst)]>;
464 def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, i8imm:$src),
465 "shl{q}\t{$src, $dst|$dst, $src}",
466 [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
467 def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),
469 [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
471 let isTwoAddress = 1 in {
473 def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src),
474 "shr{q}\t{%cl, $dst|$dst, %CL}",
475 [(set GR64:$dst, (srl GR64:$src, CL))]>;
476 def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
477 "shr{q}\t{$src2, $dst|$dst, $src2}",
478 [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))]>;
479 def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
481 [(set GR64:$dst, (srl GR64:$src1, (i8 1)))]>;
485 def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
486 "shr{q}\t{%cl, $dst|$dst, %CL}",
487 [(store (srl (loadi64 addr:$dst), CL), addr:$dst)]>;
488 def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, i8imm:$src),
489 "shr{q}\t{$src, $dst|$dst, $src}",
490 [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
491 def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),
493 [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
495 let isTwoAddress = 1 in {
497 def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src),
498 "sar{q}\t{%cl, $dst|$dst, %CL}",
499 [(set GR64:$dst, (sra GR64:$src, CL))]>;
500 def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
501 "sar{q}\t{$src2, $dst|$dst, $src2}",
502 [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))]>;
503 def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
505 [(set GR64:$dst, (sra GR64:$src1, (i8 1)))]>;
509 def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
510 "sar{q}\t{%cl, $dst|$dst, %CL}",
511 [(store (sra (loadi64 addr:$dst), CL), addr:$dst)]>;
512 def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, i8imm:$src),
513 "sar{q}\t{$src, $dst|$dst, $src}",
514 [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
515 def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
517 [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
519 // Rotate instructions
520 let isTwoAddress = 1 in {
522 def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src),
523 "rol{q}\t{%cl, $dst|$dst, %CL}",
524 [(set GR64:$dst, (rotl GR64:$src, CL))]>;
525 def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
526 "rol{q}\t{$src2, $dst|$dst, $src2}",
527 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))]>;
528 def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
530 [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))]>;
534 def ROL64mCL : I<0xD3, MRM0m, (outs), (ins i64mem:$dst),
535 "rol{q}\t{%cl, $dst|$dst, %CL}",
536 [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)]>;
537 def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, i8imm:$src),
538 "rol{q}\t{$src, $dst|$dst, $src}",
539 [(store (rotl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
540 def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),
542 [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
544 let isTwoAddress = 1 in {
546 def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src),
547 "ror{q}\t{%cl, $dst|$dst, %CL}",
548 [(set GR64:$dst, (rotr GR64:$src, CL))]>;
549 def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
550 "ror{q}\t{$src2, $dst|$dst, $src2}",
551 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))]>;
552 def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
554 [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))]>;
558 def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),
559 "ror{q}\t{%cl, $dst|$dst, %CL}",
560 [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)]>;
561 def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, i8imm:$src),
562 "ror{q}\t{$src, $dst|$dst, $src}",
563 [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
564 def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst),
566 [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
568 // Double shift instructions (generalizations of rotate)
569 let isTwoAddress = 1 in {
571 def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
572 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
573 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))]>, TB;
574 def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
575 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
576 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))]>, TB;
579 let isCommutable = 1 in { // FIXME: Update X86InstrInfo::commuteInstruction
580 def SHLD64rri8 : RIi8<0xA4, MRMDestReg,
581 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$src3),
582 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
583 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2,
586 def SHRD64rri8 : RIi8<0xAC, MRMDestReg,
587 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$src3),
588 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
589 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2,
596 def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
597 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
598 [(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL),
600 def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
601 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
602 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL),
605 def SHLD64mri8 : RIi8<0xA4, MRMDestMem,
606 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
607 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
608 [(store (X86shld (loadi64 addr:$dst), GR64:$src2,
609 (i8 imm:$src3)), addr:$dst)]>,
611 def SHRD64mri8 : RIi8<0xAC, MRMDestMem,
612 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
613 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
614 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2,
615 (i8 imm:$src3)), addr:$dst)]>,
619 //===----------------------------------------------------------------------===//
620 // Logical Instructions...
623 let isTwoAddress = 1 in
624 def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src), "not{q}\t$dst",
625 [(set GR64:$dst, (not GR64:$src))]>;
626 def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst",
627 [(store (not (loadi64 addr:$dst)), addr:$dst)]>;
629 let Defs = [EFLAGS] in {
630 let isTwoAddress = 1 in {
631 let isCommutable = 1 in
632 def AND64rr : RI<0x21, MRMDestReg,
633 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
634 "and{q}\t{$src2, $dst|$dst, $src2}",
635 [(set GR64:$dst, (and GR64:$src1, GR64:$src2))]>;
636 def AND64rm : RI<0x23, MRMSrcMem,
637 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
638 "and{q}\t{$src2, $dst|$dst, $src2}",
639 [(set GR64:$dst, (and GR64:$src1, (load addr:$src2)))]>;
640 def AND64ri32 : RIi32<0x81, MRM4r,
641 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
642 "and{q}\t{$src2, $dst|$dst, $src2}",
643 [(set GR64:$dst, (and GR64:$src1, i64immSExt32:$src2))]>;
644 def AND64ri8 : RIi8<0x83, MRM4r,
645 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
646 "and{q}\t{$src2, $dst|$dst, $src2}",
647 [(set GR64:$dst, (and GR64:$src1, i64immSExt8:$src2))]>;
650 def AND64mr : RI<0x21, MRMDestMem,
651 (outs), (ins i64mem:$dst, GR64:$src),
652 "and{q}\t{$src, $dst|$dst, $src}",
653 [(store (and (load addr:$dst), GR64:$src), addr:$dst)]>;
654 def AND64mi32 : RIi32<0x81, MRM4m,
655 (outs), (ins i64mem:$dst, i64i32imm:$src),
656 "and{q}\t{$src, $dst|$dst, $src}",
657 [(store (and (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst)]>;
658 def AND64mi8 : RIi8<0x83, MRM4m,
659 (outs), (ins i64mem:$dst, i64i8imm :$src),
660 "and{q}\t{$src, $dst|$dst, $src}",
661 [(store (and (load addr:$dst), i64immSExt8:$src), addr:$dst)]>;
663 let isTwoAddress = 1 in {
664 let isCommutable = 1 in
665 def OR64rr : RI<0x09, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
666 "or{q}\t{$src2, $dst|$dst, $src2}",
667 [(set GR64:$dst, (or GR64:$src1, GR64:$src2))]>;
668 def OR64rm : RI<0x0B, MRMSrcMem , (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
669 "or{q}\t{$src2, $dst|$dst, $src2}",
670 [(set GR64:$dst, (or GR64:$src1, (load addr:$src2)))]>;
671 def OR64ri32 : RIi32<0x81, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
672 "or{q}\t{$src2, $dst|$dst, $src2}",
673 [(set GR64:$dst, (or GR64:$src1, i64immSExt32:$src2))]>;
674 def OR64ri8 : RIi8<0x83, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
675 "or{q}\t{$src2, $dst|$dst, $src2}",
676 [(set GR64:$dst, (or GR64:$src1, i64immSExt8:$src2))]>;
679 def OR64mr : RI<0x09, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
680 "or{q}\t{$src, $dst|$dst, $src}",
681 [(store (or (load addr:$dst), GR64:$src), addr:$dst)]>;
682 def OR64mi32 : RIi32<0x81, MRM1m, (outs), (ins i64mem:$dst, i64i32imm:$src),
683 "or{q}\t{$src, $dst|$dst, $src}",
684 [(store (or (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst)]>;
685 def OR64mi8 : RIi8<0x83, MRM1m, (outs), (ins i64mem:$dst, i64i8imm:$src),
686 "or{q}\t{$src, $dst|$dst, $src}",
687 [(store (or (load addr:$dst), i64immSExt8:$src), addr:$dst)]>;
689 let isTwoAddress = 1 in {
690 let isCommutable = 1 in
691 def XOR64rr : RI<0x31, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
692 "xor{q}\t{$src2, $dst|$dst, $src2}",
693 [(set GR64:$dst, (xor GR64:$src1, GR64:$src2))]>;
694 def XOR64rm : RI<0x33, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
695 "xor{q}\t{$src2, $dst|$dst, $src2}",
696 [(set GR64:$dst, (xor GR64:$src1, (load addr:$src2)))]>;
697 def XOR64ri32 : RIi32<0x81, MRM6r,
698 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
699 "xor{q}\t{$src2, $dst|$dst, $src2}",
700 [(set GR64:$dst, (xor GR64:$src1, i64immSExt32:$src2))]>;
701 def XOR64ri8 : RIi8<0x83, MRM6r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
702 "xor{q}\t{$src2, $dst|$dst, $src2}",
703 [(set GR64:$dst, (xor GR64:$src1, i64immSExt8:$src2))]>;
706 def XOR64mr : RI<0x31, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
707 "xor{q}\t{$src, $dst|$dst, $src}",
708 [(store (xor (load addr:$dst), GR64:$src), addr:$dst)]>;
709 def XOR64mi32 : RIi32<0x81, MRM6m, (outs), (ins i64mem:$dst, i64i32imm:$src),
710 "xor{q}\t{$src, $dst|$dst, $src}",
711 [(store (xor (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst)]>;
712 def XOR64mi8 : RIi8<0x83, MRM6m, (outs), (ins i64mem:$dst, i64i8imm :$src),
713 "xor{q}\t{$src, $dst|$dst, $src}",
714 [(store (xor (load addr:$dst), i64immSExt8:$src), addr:$dst)]>;
717 //===----------------------------------------------------------------------===//
718 // Comparison Instructions...
721 // Integer comparison
722 let Defs = [EFLAGS] in {
723 let isCommutable = 1 in
724 def TEST64rr : RI<0x85, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
725 "test{q}\t{$src2, $src1|$src1, $src2}",
726 [(X86cmp (and GR64:$src1, GR64:$src2), 0)]>;
727 def TEST64rm : RI<0x85, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
728 "test{q}\t{$src2, $src1|$src1, $src2}",
729 [(X86cmp (and GR64:$src1, (loadi64 addr:$src2)), 0)]>;
730 def TEST64ri32 : RIi32<0xF7, MRM0r, (outs), (ins GR64:$src1, i64i32imm:$src2),
731 "test{q}\t{$src2, $src1|$src1, $src2}",
732 [(X86cmp (and GR64:$src1, i64immSExt32:$src2), 0)]>;
733 def TEST64mi32 : RIi32<0xF7, MRM0m, (outs), (ins i64mem:$src1, i64i32imm:$src2),
734 "test{q}\t{$src2, $src1|$src1, $src2}",
735 [(X86cmp (and (loadi64 addr:$src1), i64immSExt32:$src2), 0)]>;
737 def CMP64rr : RI<0x39, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
738 "cmp{q}\t{$src2, $src1|$src1, $src2}",
739 [(X86cmp GR64:$src1, GR64:$src2)]>;
740 def CMP64mr : RI<0x39, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
741 "cmp{q}\t{$src2, $src1|$src1, $src2}",
742 [(X86cmp (loadi64 addr:$src1), GR64:$src2)]>;
743 def CMP64rm : RI<0x3B, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
744 "cmp{q}\t{$src2, $src1|$src1, $src2}",
745 [(X86cmp GR64:$src1, (loadi64 addr:$src2))]>;
746 def CMP64ri32 : RIi32<0x81, MRM7r, (outs), (ins GR64:$src1, i64i32imm:$src2),
747 "cmp{q}\t{$src2, $src1|$src1, $src2}",
748 [(X86cmp GR64:$src1, i64immSExt32:$src2)]>;
749 def CMP64mi32 : RIi32<0x81, MRM7m, (outs), (ins i64mem:$src1, i64i32imm:$src2),
750 "cmp{q}\t{$src2, $src1|$src1, $src2}",
751 [(X86cmp (loadi64 addr:$src1), i64immSExt32:$src2)]>;
752 def CMP64mi8 : RIi8<0x83, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
753 "cmp{q}\t{$src2, $src1|$src1, $src2}",
754 [(X86cmp (loadi64 addr:$src1), i64immSExt8:$src2)]>;
755 def CMP64ri8 : RIi8<0x83, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
756 "cmp{q}\t{$src2, $src1|$src1, $src2}",
757 [(X86cmp GR64:$src1, i64immSExt8:$src2)]>;
760 let Defs = [EFLAGS] in {
761 let isCommutable = 1 in
762 def NEW_TEST64rr : RI<0x85, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
763 "test{q}\t{$src2, $src1|$src1, $src2}",
764 [(X86cmp_new (and GR64:$src1, GR64:$src2), 0),
766 def NEW_TEST64rm : RI<0x85, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
767 "test{q}\t{$src2, $src1|$src1, $src2}",
768 [(X86cmp_new (and GR64:$src1, (loadi64 addr:$src2)), 0),
770 def NEW_TEST64ri32 : RIi32<0xF7, MRM0r, (outs),
771 (ins GR64:$src1, i64i32imm:$src2),
772 "test{q}\t{$src2, $src1|$src1, $src2}",
773 [(X86cmp_new (and GR64:$src1, i64immSExt32:$src2), 0),
775 def NEW_TEST64mi32 : RIi32<0xF7, MRM0m, (outs),
776 (ins i64mem:$src1, i64i32imm:$src2),
777 "test{q}\t{$src2, $src1|$src1, $src2}",
778 [(X86cmp_new (and (loadi64 addr:$src1), i64immSExt32:$src2), 0),
781 def NEW_CMP64rr : RI<0x39, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
782 "cmp{q}\t{$src2, $src1|$src1, $src2}",
783 [(X86cmp_new GR64:$src1, GR64:$src2),
785 def NEW_CMP64mr : RI<0x39, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
786 "cmp{q}\t{$src2, $src1|$src1, $src2}",
787 [(X86cmp_new (loadi64 addr:$src1), GR64:$src2),
789 def NEW_CMP64rm : RI<0x3B, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
790 "cmp{q}\t{$src2, $src1|$src1, $src2}",
791 [(X86cmp_new GR64:$src1, (loadi64 addr:$src2)),
793 def NEW_CMP64ri32 : RIi32<0x81, MRM7r, (outs), (ins GR64:$src1, i64i32imm:$src2),
794 "cmp{q}\t{$src2, $src1|$src1, $src2}",
795 [(X86cmp_new GR64:$src1, i64immSExt32:$src2),
797 def NEW_CMP64mi32 : RIi32<0x81, MRM7m, (outs),
798 (ins i64mem:$src1, i64i32imm:$src2),
799 "cmp{q}\t{$src2, $src1|$src1, $src2}",
800 [(X86cmp_new (loadi64 addr:$src1), i64immSExt32:$src2),
802 def NEW_CMP64mi8 : RIi8<0x83, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
803 "cmp{q}\t{$src2, $src1|$src1, $src2}",
804 [(X86cmp_new (loadi64 addr:$src1), i64immSExt8:$src2),
806 def NEW_CMP64ri8 : RIi8<0x83, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
807 "cmp{q}\t{$src2, $src1|$src1, $src2}",
808 [(X86cmp_new GR64:$src1, i64immSExt8:$src2),
813 let Uses = [EFLAGS], isTwoAddress = 1 in {
814 def CMOVB64rr : RI<0x42, MRMSrcReg, // if <u, GR64 = GR64
815 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
816 "cmovb\t{$src2, $dst|$dst, $src2}",
817 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
819 def CMOVB64rm : RI<0x42, MRMSrcMem, // if <u, GR64 = [mem64]
820 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
821 "cmovb\t{$src2, $dst|$dst, $src2}",
822 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
824 def CMOVAE64rr: RI<0x43, MRMSrcReg, // if >=u, GR64 = GR64
825 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
826 "cmovae\t{$src2, $dst|$dst, $src2}",
827 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
829 def CMOVAE64rm: RI<0x43, MRMSrcMem, // if >=u, GR64 = [mem64]
830 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
831 "cmovae\t{$src2, $dst|$dst, $src2}",
832 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
834 def CMOVE64rr : RI<0x44, MRMSrcReg, // if ==, GR64 = GR64
835 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
836 "cmove\t{$src2, $dst|$dst, $src2}",
837 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
839 def CMOVE64rm : RI<0x44, MRMSrcMem, // if ==, GR64 = [mem64]
840 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
841 "cmove\t{$src2, $dst|$dst, $src2}",
842 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
844 def CMOVNE64rr: RI<0x45, MRMSrcReg, // if !=, GR64 = GR64
845 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
846 "cmovne\t{$src2, $dst|$dst, $src2}",
847 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
849 def CMOVNE64rm: RI<0x45, MRMSrcMem, // if !=, GR64 = [mem64]
850 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
851 "cmovne\t{$src2, $dst|$dst, $src2}",
852 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
854 def CMOVBE64rr: RI<0x46, MRMSrcReg, // if <=u, GR64 = GR64
855 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
856 "cmovbe\t{$src2, $dst|$dst, $src2}",
857 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
859 def CMOVBE64rm: RI<0x46, MRMSrcMem, // if <=u, GR64 = [mem64]
860 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
861 "cmovbe\t{$src2, $dst|$dst, $src2}",
862 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
864 def CMOVA64rr : RI<0x47, MRMSrcReg, // if >u, GR64 = GR64
865 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
866 "cmova\t{$src2, $dst|$dst, $src2}",
867 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
869 def CMOVA64rm : RI<0x47, MRMSrcMem, // if >u, GR64 = [mem64]
870 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
871 "cmova\t{$src2, $dst|$dst, $src2}",
872 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
874 def CMOVL64rr : RI<0x4C, MRMSrcReg, // if <s, GR64 = GR64
875 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
876 "cmovl\t{$src2, $dst|$dst, $src2}",
877 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
879 def CMOVL64rm : RI<0x4C, MRMSrcMem, // if <s, GR64 = [mem64]
880 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
881 "cmovl\t{$src2, $dst|$dst, $src2}",
882 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
884 def CMOVGE64rr: RI<0x4D, MRMSrcReg, // if >=s, GR64 = GR64
885 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
886 "cmovge\t{$src2, $dst|$dst, $src2}",
887 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
889 def CMOVGE64rm: RI<0x4D, MRMSrcMem, // if >=s, GR64 = [mem64]
890 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
891 "cmovge\t{$src2, $dst|$dst, $src2}",
892 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
894 def CMOVLE64rr: RI<0x4E, MRMSrcReg, // if <=s, GR64 = GR64
895 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
896 "cmovle\t{$src2, $dst|$dst, $src2}",
897 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
899 def CMOVLE64rm: RI<0x4E, MRMSrcMem, // if <=s, GR64 = [mem64]
900 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
901 "cmovle\t{$src2, $dst|$dst, $src2}",
902 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
904 def CMOVG64rr : RI<0x4F, MRMSrcReg, // if >s, GR64 = GR64
905 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
906 "cmovg\t{$src2, $dst|$dst, $src2}",
907 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
909 def CMOVG64rm : RI<0x4F, MRMSrcMem, // if >s, GR64 = [mem64]
910 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
911 "cmovg\t{$src2, $dst|$dst, $src2}",
912 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
914 def CMOVS64rr : RI<0x48, MRMSrcReg, // if signed, GR64 = GR64
915 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
916 "cmovs\t{$src2, $dst|$dst, $src2}",
917 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
919 def CMOVS64rm : RI<0x48, MRMSrcMem, // if signed, GR64 = [mem64]
920 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
921 "cmovs\t{$src2, $dst|$dst, $src2}",
922 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
924 def CMOVNS64rr: RI<0x49, MRMSrcReg, // if !signed, GR64 = GR64
925 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
926 "cmovns\t{$src2, $dst|$dst, $src2}",
927 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
929 def CMOVNS64rm: RI<0x49, MRMSrcMem, // if !signed, GR64 = [mem64]
930 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
931 "cmovns\t{$src2, $dst|$dst, $src2}",
932 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
934 def CMOVP64rr : RI<0x4A, MRMSrcReg, // if parity, GR64 = GR64
935 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
936 "cmovp\t{$src2, $dst|$dst, $src2}",
937 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
939 def CMOVP64rm : RI<0x4A, MRMSrcMem, // if parity, GR64 = [mem64]
940 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
941 "cmovp\t{$src2, $dst|$dst, $src2}",
942 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
944 def CMOVNP64rr : RI<0x4B, MRMSrcReg, // if !parity, GR64 = GR64
945 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
946 "cmovnp\t{$src2, $dst|$dst, $src2}",
947 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
949 def CMOVNP64rm : RI<0x4B, MRMSrcMem, // if !parity, GR64 = [mem64]
950 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
951 "cmovnp\t{$src2, $dst|$dst, $src2}",
952 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
955 def NEW_CMOVB64rr : RI<0x42, MRMSrcReg, // if <u, GR64 = GR64
956 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
957 "cmovb\t{$src2, $dst|$dst, $src2}",
958 [(set GR64:$dst, (X86cmov_new GR64:$src1, GR64:$src2,
959 X86_COND_B, EFLAGS))]>, TB;
960 def NEW_CMOVB64rm : RI<0x42, MRMSrcMem, // if <u, GR64 = [mem64]
961 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
962 "cmovb\t{$src2, $dst|$dst, $src2}",
963 [(set GR64:$dst, (X86cmov_new GR64:$src1, (loadi64 addr:$src2),
964 X86_COND_B, EFLAGS))]>, TB;
965 def NEW_CMOVAE64rr: RI<0x43, MRMSrcReg, // if >=u, GR64 = GR64
966 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
967 "cmovae\t{$src2, $dst|$dst, $src2}",
968 [(set GR64:$dst, (X86cmov_new GR64:$src1, GR64:$src2,
969 X86_COND_AE, EFLAGS))]>, TB;
970 def NEW_CMOVAE64rm: RI<0x43, MRMSrcMem, // if >=u, GR64 = [mem64]
971 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
972 "cmovae\t{$src2, $dst|$dst, $src2}",
973 [(set GR64:$dst, (X86cmov_new GR64:$src1, (loadi64 addr:$src2),
974 X86_COND_AE, EFLAGS))]>, TB;
975 def NEW_CMOVE64rr : RI<0x44, MRMSrcReg, // if ==, GR64 = GR64
976 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
977 "cmove\t{$src2, $dst|$dst, $src2}",
978 [(set GR64:$dst, (X86cmov_new GR64:$src1, GR64:$src2,
979 X86_COND_E, EFLAGS))]>, TB;
980 def NEW_CMOVE64rm : RI<0x44, MRMSrcMem, // if ==, GR64 = [mem64]
981 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
982 "cmove\t{$src2, $dst|$dst, $src2}",
983 [(set GR64:$dst, (X86cmov_new GR64:$src1, (loadi64 addr:$src2),
984 X86_COND_E, EFLAGS))]>, TB;
985 def NEW_CMOVNE64rr: RI<0x45, MRMSrcReg, // if !=, GR64 = GR64
986 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
987 "cmovne\t{$src2, $dst|$dst, $src2}",
988 [(set GR64:$dst, (X86cmov_new GR64:$src1, GR64:$src2,
989 X86_COND_NE, EFLAGS))]>, TB;
990 def NEW_CMOVNE64rm: RI<0x45, MRMSrcMem, // if !=, GR64 = [mem64]
991 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
992 "cmovne\t{$src2, $dst|$dst, $src2}",
993 [(set GR64:$dst, (X86cmov_new GR64:$src1, (loadi64 addr:$src2),
994 X86_COND_NE, EFLAGS))]>, TB;
995 def NEW_CMOVBE64rr: RI<0x46, MRMSrcReg, // if <=u, GR64 = GR64
996 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
997 "cmovbe\t{$src2, $dst|$dst, $src2}",
998 [(set GR64:$dst, (X86cmov_new GR64:$src1, GR64:$src2,
999 X86_COND_BE, EFLAGS))]>, TB;
1000 def NEW_CMOVBE64rm: RI<0x46, MRMSrcMem, // if <=u, GR64 = [mem64]
1001 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1002 "cmovbe\t{$src2, $dst|$dst, $src2}",
1003 [(set GR64:$dst, (X86cmov_new GR64:$src1, (loadi64 addr:$src2),
1004 X86_COND_BE, EFLAGS))]>, TB;
1005 def NEW_CMOVA64rr : RI<0x47, MRMSrcReg, // if >u, GR64 = GR64
1006 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1007 "cmova\t{$src2, $dst|$dst, $src2}",
1008 [(set GR64:$dst, (X86cmov_new GR64:$src1, GR64:$src2,
1009 X86_COND_A, EFLAGS))]>, TB;
1010 def NEW_CMOVA64rm : RI<0x47, MRMSrcMem, // if >u, GR64 = [mem64]
1011 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1012 "cmova\t{$src2, $dst|$dst, $src2}",
1013 [(set GR64:$dst, (X86cmov_new GR64:$src1, (loadi64 addr:$src2),
1014 X86_COND_A, EFLAGS))]>, TB;
1015 def NEW_CMOVL64rr : RI<0x4C, MRMSrcReg, // if <s, GR64 = GR64
1016 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1017 "cmovl\t{$src2, $dst|$dst, $src2}",
1018 [(set GR64:$dst, (X86cmov_new GR64:$src1, GR64:$src2,
1019 X86_COND_L, EFLAGS))]>, TB;
1020 def NEW_CMOVL64rm : RI<0x4C, MRMSrcMem, // if <s, GR64 = [mem64]
1021 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1022 "cmovl\t{$src2, $dst|$dst, $src2}",
1023 [(set GR64:$dst, (X86cmov_new GR64:$src1, (loadi64 addr:$src2),
1024 X86_COND_L, EFLAGS))]>, TB;
1025 def NEW_CMOVGE64rr: RI<0x4D, MRMSrcReg, // if >=s, GR64 = GR64
1026 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1027 "cmovge\t{$src2, $dst|$dst, $src2}",
1028 [(set GR64:$dst, (X86cmov_new GR64:$src1, GR64:$src2,
1029 X86_COND_GE, EFLAGS))]>, TB;
1030 def NEW_CMOVGE64rm: RI<0x4D, MRMSrcMem, // if >=s, GR64 = [mem64]
1031 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1032 "cmovge\t{$src2, $dst|$dst, $src2}",
1033 [(set GR64:$dst, (X86cmov_new GR64:$src1, (loadi64 addr:$src2),
1034 X86_COND_GE, EFLAGS))]>, TB;
1035 def NEW_CMOVLE64rr: RI<0x4E, MRMSrcReg, // if <=s, GR64 = GR64
1036 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1037 "cmovle\t{$src2, $dst|$dst, $src2}",
1038 [(set GR64:$dst, (X86cmov_new GR64:$src1, GR64:$src2,
1039 X86_COND_LE, EFLAGS))]>, TB;
1040 def NEW_CMOVLE64rm: RI<0x4E, MRMSrcMem, // if <=s, GR64 = [mem64]
1041 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1042 "cmovle\t{$src2, $dst|$dst, $src2}",
1043 [(set GR64:$dst, (X86cmov_new GR64:$src1, (loadi64 addr:$src2),
1044 X86_COND_LE, EFLAGS))]>, TB;
1045 def NEW_CMOVG64rr : RI<0x4F, MRMSrcReg, // if >s, GR64 = GR64
1046 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1047 "cmovg\t{$src2, $dst|$dst, $src2}",
1048 [(set GR64:$dst, (X86cmov_new GR64:$src1, GR64:$src2,
1049 X86_COND_G, EFLAGS))]>, TB;
1050 def NEW_CMOVG64rm : RI<0x4F, MRMSrcMem, // if >s, GR64 = [mem64]
1051 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1052 "cmovg\t{$src2, $dst|$dst, $src2}",
1053 [(set GR64:$dst, (X86cmov_new GR64:$src1, (loadi64 addr:$src2),
1054 X86_COND_G, EFLAGS))]>, TB;
1055 def NEW_CMOVS64rr : RI<0x48, MRMSrcReg, // if signed, GR64 = GR64
1056 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1057 "cmovs\t{$src2, $dst|$dst, $src2}",
1058 [(set GR64:$dst, (X86cmov_new GR64:$src1, GR64:$src2,
1059 X86_COND_S, EFLAGS))]>, TB;
1060 def NEW_CMOVS64rm : RI<0x48, MRMSrcMem, // if signed, GR64 = [mem64]
1061 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1062 "cmovs\t{$src2, $dst|$dst, $src2}",
1063 [(set GR64:$dst, (X86cmov_new GR64:$src1, (loadi64 addr:$src2),
1064 X86_COND_S, EFLAGS))]>, TB;
1065 def NEW_CMOVNS64rr: RI<0x49, MRMSrcReg, // if !signed, GR64 = GR64
1066 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1067 "cmovns\t{$src2, $dst|$dst, $src2}",
1068 [(set GR64:$dst, (X86cmov_new GR64:$src1, GR64:$src2,
1069 X86_COND_NS, EFLAGS))]>, TB;
1070 def NEW_CMOVNS64rm: RI<0x49, MRMSrcMem, // if !signed, GR64 = [mem64]
1071 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1072 "cmovns\t{$src2, $dst|$dst, $src2}",
1073 [(set GR64:$dst, (X86cmov_new GR64:$src1, (loadi64 addr:$src2),
1074 X86_COND_NS, EFLAGS))]>, TB;
1075 def NEW_CMOVP64rr : RI<0x4A, MRMSrcReg, // if parity, GR64 = GR64
1076 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1077 "cmovp\t{$src2, $dst|$dst, $src2}",
1078 [(set GR64:$dst, (X86cmov_new GR64:$src1, GR64:$src2,
1079 X86_COND_P, EFLAGS))]>, TB;
1080 def NEW_CMOVP64rm : RI<0x4A, MRMSrcMem, // if parity, GR64 = [mem64]
1081 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1082 "cmovp\t{$src2, $dst|$dst, $src2}",
1083 [(set GR64:$dst, (X86cmov_new GR64:$src1, (loadi64 addr:$src2),
1084 X86_COND_P, EFLAGS))]>, TB;
1085 def NEW_CMOVNP64rr : RI<0x4B, MRMSrcReg, // if !parity, GR64 = GR64
1086 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1087 "cmovnp\t{$src2, $dst|$dst, $src2}",
1088 [(set GR64:$dst, (X86cmov_new GR64:$src1, GR64:$src2,
1089 X86_COND_NP, EFLAGS))]>, TB;
1090 def NEW_CMOVNP64rm : RI<0x4B, MRMSrcMem, // if !parity, GR64 = [mem64]
1091 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1092 "cmovnp\t{$src2, $dst|$dst, $src2}",
1093 [(set GR64:$dst, (X86cmov_new GR64:$src1, (loadi64 addr:$src2),
1094 X86_COND_NP, EFLAGS))]>, TB;
1097 //===----------------------------------------------------------------------===//
1098 // Conversion Instructions...
1101 // f64 -> signed i64
1102 def Int_CVTSD2SI64rr: RSDI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1103 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1105 (int_x86_sse2_cvtsd2si64 VR128:$src))]>;
1106 def Int_CVTSD2SI64rm: RSDI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f128mem:$src),
1107 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1108 [(set GR64:$dst, (int_x86_sse2_cvtsd2si64
1109 (load addr:$src)))]>;
1110 def CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src),
1111 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1112 [(set GR64:$dst, (fp_to_sint FR64:$src))]>;
1113 def CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f64mem:$src),
1114 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1115 [(set GR64:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1116 def Int_CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1117 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1119 (int_x86_sse2_cvttsd2si64 VR128:$src))]>;
1120 def Int_CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f128mem:$src),
1121 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1123 (int_x86_sse2_cvttsd2si64
1124 (load addr:$src)))]>;
1126 // Signed i64 -> f64
1127 def CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1128 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1129 [(set FR64:$dst, (sint_to_fp GR64:$src))]>;
1130 def CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
1131 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1132 [(set FR64:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1133 let isTwoAddress = 1 in {
1134 def Int_CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg,
1135 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1136 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1138 (int_x86_sse2_cvtsi642sd VR128:$src1,
1140 def Int_CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem,
1141 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
1142 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1144 (int_x86_sse2_cvtsi642sd VR128:$src1,
1145 (loadi64 addr:$src2)))]>;
1148 // Signed i64 -> f32
1149 def CVTSI2SS64rr: RSSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR64:$src),
1150 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1151 [(set FR32:$dst, (sint_to_fp GR64:$src))]>;
1152 def CVTSI2SS64rm: RSSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i64mem:$src),
1153 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1154 [(set FR32:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1155 let isTwoAddress = 1 in {
1156 def Int_CVTSI2SS64rr: RSSI<0x2A, MRMSrcReg,
1157 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1158 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1159 []>; // TODO: add intrinsic
1160 def Int_CVTSI2SS64rm: RSSI<0x2A, MRMSrcMem,
1161 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
1162 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1163 []>; // TODO: add intrinsic
1166 // f32 -> signed i64
1167 def Int_CVTSS2SI64rr: RSSI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1168 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1170 (int_x86_sse_cvtss2si64 VR128:$src))]>;
1171 def Int_CVTSS2SI64rm: RSSI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1172 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1173 [(set GR64:$dst, (int_x86_sse_cvtss2si64
1174 (load addr:$src)))]>;
1175 def CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src),
1176 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1177 [(set GR64:$dst, (fp_to_sint FR32:$src))]>;
1178 def CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1179 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1180 [(set GR64:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
1181 def Int_CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1182 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1184 (int_x86_sse_cvttss2si64 VR128:$src))]>;
1185 def Int_CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1186 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1188 (int_x86_sse_cvttss2si64 (load addr:$src)))]>;
1190 let isTwoAddress = 1 in {
1191 def Int_CVTSI642SSrr : RSSI<0x2A, MRMSrcReg,
1192 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1193 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1195 (int_x86_sse_cvtsi642ss VR128:$src1,
1197 def Int_CVTSI642SSrm : RSSI<0x2A, MRMSrcMem,
1198 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
1199 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1201 (int_x86_sse_cvtsi642ss VR128:$src1,
1202 (loadi64 addr:$src2)))]>;
1205 //===----------------------------------------------------------------------===//
1206 // Alias Instructions
1207 //===----------------------------------------------------------------------===//
1210 // TODO: Remove this after proper i32 -> i64 zext support.
1211 def PsMOVZX64rr32: I<0x89, MRMDestReg, (outs GR64:$dst), (ins GR32:$src),
1212 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
1213 [(set GR64:$dst, (zext GR32:$src))]>;
1214 def PsMOVZX64rm32: I<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
1215 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
1216 [(set GR64:$dst, (zextloadi64i32 addr:$src))]>;
1219 // Alias instructions that map movr0 to xor. Use xorl instead of xorq; it's
1220 // equivalent due to implicit zero-extending, and it sometimes has a smaller
1222 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
1223 // FIXME: AddedComplexity gives MOV64r0 a higher priority than MOV64ri32. Remove
1224 // when we have a better way to specify isel priority.
1225 let Defs = [EFLAGS], AddedComplexity = 1, isReMaterializable = 1 in
1226 def MOV64r0 : RI<0x31, MRMInitReg, (outs GR64:$dst), (ins),
1227 "xor{l}\t${dst:subreg32}, ${dst:subreg32}",
1228 [(set GR64:$dst, 0)]>;
1230 // Materialize i64 constant where top 32-bits are zero.
1231 let AddedComplexity = 1, isReMaterializable = 1 in
1232 def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src),
1233 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
1234 [(set GR64:$dst, i64immZExt32:$src)]>;
1236 //===----------------------------------------------------------------------===//
1237 // Non-Instruction Patterns
1238 //===----------------------------------------------------------------------===//
1240 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
1241 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1242 (MOV64ri tconstpool :$dst)>, Requires<[NotSmallCode]>;
1243 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1244 (MOV64ri tjumptable :$dst)>, Requires<[NotSmallCode]>;
1245 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1246 (MOV64ri tglobaladdr :$dst)>, Requires<[NotSmallCode]>;
1247 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1248 (MOV64ri texternalsym:$dst)>, Requires<[NotSmallCode]>;
1250 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
1251 (MOV64mi32 addr:$dst, tconstpool:$src)>,
1252 Requires<[SmallCode, HasLow4G, IsStatic]>;
1253 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
1254 (MOV64mi32 addr:$dst, tjumptable:$src)>,
1255 Requires<[SmallCode, HasLow4G, IsStatic]>;
1256 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
1257 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
1258 Requires<[SmallCode, HasLow4G, IsStatic]>;
1259 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
1260 (MOV64mi32 addr:$dst, texternalsym:$src)>,
1261 Requires<[SmallCode, HasLow4G, IsStatic]>;
1264 // Direct PC relative function call for small code model. 32-bit displacement
1265 // sign extended to 64-bit.
1266 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1267 (CALL64pcrel32 tglobaladdr:$dst)>;
1268 def : Pat<(X86call (i64 texternalsym:$dst)),
1269 (CALL64pcrel32 texternalsym:$dst)>;
1271 def : Pat<(X86tailcall (i64 tglobaladdr:$dst)),
1272 (CALL64pcrel32 tglobaladdr:$dst)>;
1273 def : Pat<(X86tailcall (i64 texternalsym:$dst)),
1274 (CALL64pcrel32 texternalsym:$dst)>;
1276 def : Pat<(X86tailcall GR64:$dst),
1277 (CALL64r GR64:$dst)>;
1281 // TEST R,R is smaller than CMP R,0
1282 def : Pat<(X86cmp GR64:$src1, 0),
1283 (TEST64rr GR64:$src1, GR64:$src1)>;
1285 def : Pat<(parallel (X86cmp_new GR64:$src1, 0), (implicit EFLAGS)),
1286 (NEW_TEST64rr GR64:$src1, GR64:$src1)>;
1288 // {s|z}extload bool -> {s|z}extload byte
1289 def : Pat<(sextloadi64i1 addr:$src), (MOVSX64rm8 addr:$src)>;
1290 def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1293 def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1294 def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>;
1295 def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>;
1296 def : Pat<(extloadi64i32 addr:$src), (PsMOVZX64rm32 addr:$src)>;
1299 def : Pat<(i64 (anyext GR8 :$src)), (MOVZX64rr8 GR8 :$src)>;
1300 def : Pat<(i64 (anyext GR16:$src)), (MOVZX64rr16 GR16:$src)>;
1301 def : Pat<(i64 (anyext GR32:$src)), (PsMOVZX64rr32 GR32:$src)>;
1302 def : Pat<(i64 (anyext (loadi8 addr:$src))), (MOVZX64rm8 addr:$src)>;
1303 def : Pat<(i64 (anyext (loadi16 addr:$src))), (MOVZX64rm16 addr:$src)>;
1304 def : Pat<(i64 (anyext (loadi32 addr:$src))), (PsMOVZX64rm32 addr:$src)>;
1306 //===----------------------------------------------------------------------===//
1308 //===----------------------------------------------------------------------===//
1310 // (shl x, 1) ==> (add x, x)
1311 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
1313 // (or (x >> c) | (y << (64 - c))) ==> (shrd64 x, y, c)
1314 def : Pat<(or (srl GR64:$src1, CL:$amt),
1315 (shl GR64:$src2, (sub 64, CL:$amt))),
1316 (SHRD64rrCL GR64:$src1, GR64:$src2)>;
1318 def : Pat<(store (or (srl (loadi64 addr:$dst), CL:$amt),
1319 (shl GR64:$src2, (sub 64, CL:$amt))), addr:$dst),
1320 (SHRD64mrCL addr:$dst, GR64:$src2)>;
1322 // (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
1323 def : Pat<(or (shl GR64:$src1, CL:$amt),
1324 (srl GR64:$src2, (sub 64, CL:$amt))),
1325 (SHLD64rrCL GR64:$src1, GR64:$src2)>;
1327 def : Pat<(store (or (shl (loadi64 addr:$dst), CL:$amt),
1328 (srl GR64:$src2, (sub 64, CL:$amt))), addr:$dst),
1329 (SHLD64mrCL addr:$dst, GR64:$src2)>;
1331 // X86 specific add which produces a flag.
1332 def : Pat<(addc GR64:$src1, GR64:$src2),
1333 (ADD64rr GR64:$src1, GR64:$src2)>;
1334 def : Pat<(addc GR64:$src1, (load addr:$src2)),
1335 (ADD64rm GR64:$src1, addr:$src2)>;
1336 def : Pat<(addc GR64:$src1, i64immSExt32:$src2),
1337 (ADD64ri32 GR64:$src1, imm:$src2)>;
1338 def : Pat<(addc GR64:$src1, i64immSExt8:$src2),
1339 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1341 def : Pat<(subc GR64:$src1, GR64:$src2),
1342 (SUB64rr GR64:$src1, GR64:$src2)>;
1343 def : Pat<(subc GR64:$src1, (load addr:$src2)),
1344 (SUB64rm GR64:$src1, addr:$src2)>;
1345 def : Pat<(subc GR64:$src1, imm:$src2),
1346 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1347 def : Pat<(subc GR64:$src1, i64immSExt8:$src2),
1348 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1351 //===----------------------------------------------------------------------===//
1352 // X86-64 SSE Instructions
1353 //===----------------------------------------------------------------------===//
1355 // Move instructions...
1357 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
1358 "mov{d|q}\t{$src, $dst|$dst, $src}",
1360 (v2i64 (scalar_to_vector GR64:$src)))]>;
1361 def MOV64toPQIrm : RPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1362 "mov{d|q}\t{$src, $dst|$dst, $src}",
1364 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>;
1366 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
1367 "mov{d|q}\t{$src, $dst|$dst, $src}",
1368 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
1370 def MOVPQIto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
1371 "mov{d|q}\t{$src, $dst|$dst, $src}",
1372 [(store (i64 (vector_extract (v2i64 VR128:$src),
1373 (iPTR 0))), addr:$dst)]>;
1375 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1376 "mov{d|q}\t{$src, $dst|$dst, $src}",
1377 [(set FR64:$dst, (bitconvert GR64:$src))]>;
1378 def MOV64toSDrm : RPDI<0x6E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
1379 "mov{d|q}\t{$src, $dst|$dst, $src}",
1380 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
1382 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1383 "mov{d|q}\t{$src, $dst|$dst, $src}",
1384 [(set GR64:$dst, (bitconvert FR64:$src))]>;
1385 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1386 "mov{d|q}\t{$src, $dst|$dst, $src}",
1387 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;