1 //===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 class OpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm> {
17 InstrItinClass rr = arg_rr;
18 InstrItinClass rm = arg_rm;
19 // InstrSchedModel info.
20 X86FoldableSchedWrite Sched = WriteFAdd;
23 class SizeItins<OpndItins arg_s, OpndItins arg_d> {
29 class ShiftOpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm,
30 InstrItinClass arg_ri> {
31 InstrItinClass rr = arg_rr;
32 InstrItinClass rm = arg_rm;
33 InstrItinClass ri = arg_ri;
38 let Sched = WriteFAdd in {
39 def SSE_ALU_F32S : OpndItins<
40 IIC_SSE_ALU_F32S_RR, IIC_SSE_ALU_F32S_RM
43 def SSE_ALU_F64S : OpndItins<
44 IIC_SSE_ALU_F64S_RR, IIC_SSE_ALU_F64S_RM
48 def SSE_ALU_ITINS_S : SizeItins<
49 SSE_ALU_F32S, SSE_ALU_F64S
52 let Sched = WriteFMul in {
53 def SSE_MUL_F32S : OpndItins<
54 IIC_SSE_MUL_F32S_RR, IIC_SSE_MUL_F64S_RM
57 def SSE_MUL_F64S : OpndItins<
58 IIC_SSE_MUL_F64S_RR, IIC_SSE_MUL_F64S_RM
62 def SSE_MUL_ITINS_S : SizeItins<
63 SSE_MUL_F32S, SSE_MUL_F64S
66 let Sched = WriteFDiv in {
67 def SSE_DIV_F32S : OpndItins<
68 IIC_SSE_DIV_F32S_RR, IIC_SSE_DIV_F64S_RM
71 def SSE_DIV_F64S : OpndItins<
72 IIC_SSE_DIV_F64S_RR, IIC_SSE_DIV_F64S_RM
76 def SSE_DIV_ITINS_S : SizeItins<
77 SSE_DIV_F32S, SSE_DIV_F64S
81 let Sched = WriteFAdd in {
82 def SSE_ALU_F32P : OpndItins<
83 IIC_SSE_ALU_F32P_RR, IIC_SSE_ALU_F32P_RM
86 def SSE_ALU_F64P : OpndItins<
87 IIC_SSE_ALU_F64P_RR, IIC_SSE_ALU_F64P_RM
91 def SSE_ALU_ITINS_P : SizeItins<
92 SSE_ALU_F32P, SSE_ALU_F64P
95 let Sched = WriteFMul in {
96 def SSE_MUL_F32P : OpndItins<
97 IIC_SSE_MUL_F32P_RR, IIC_SSE_MUL_F64P_RM
100 def SSE_MUL_F64P : OpndItins<
101 IIC_SSE_MUL_F64P_RR, IIC_SSE_MUL_F64P_RM
105 def SSE_MUL_ITINS_P : SizeItins<
106 SSE_MUL_F32P, SSE_MUL_F64P
109 let Sched = WriteFDiv in {
110 def SSE_DIV_F32P : OpndItins<
111 IIC_SSE_DIV_F32P_RR, IIC_SSE_DIV_F64P_RM
114 def SSE_DIV_F64P : OpndItins<
115 IIC_SSE_DIV_F64P_RR, IIC_SSE_DIV_F64P_RM
119 def SSE_DIV_ITINS_P : SizeItins<
120 SSE_DIV_F32P, SSE_DIV_F64P
123 def SSE_BIT_ITINS_P : OpndItins<
124 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
127 let Sched = WriteVecALU in {
128 def SSE_INTALU_ITINS_P : OpndItins<
129 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
132 def SSE_INTALUQ_ITINS_P : OpndItins<
133 IIC_SSE_INTALUQ_P_RR, IIC_SSE_INTALUQ_P_RM
137 let Sched = WriteVecIMul in
138 def SSE_INTMUL_ITINS_P : OpndItins<
139 IIC_SSE_INTMUL_P_RR, IIC_SSE_INTMUL_P_RM
142 def SSE_INTSHIFT_ITINS_P : ShiftOpndItins<
143 IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM, IIC_SSE_INTSH_P_RI
146 def SSE_MOVA_ITINS : OpndItins<
147 IIC_SSE_MOVA_P_RR, IIC_SSE_MOVA_P_RM
150 def SSE_MOVU_ITINS : OpndItins<
151 IIC_SSE_MOVU_P_RR, IIC_SSE_MOVU_P_RM
154 //===----------------------------------------------------------------------===//
155 // SSE 1 & 2 Instructions Classes
156 //===----------------------------------------------------------------------===//
158 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
159 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
160 RegisterClass RC, X86MemOperand x86memop,
163 let isCommutable = 1 in {
164 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
166 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
167 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
168 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr>,
169 Sched<[itins.Sched]>;
171 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
173 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
174 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
175 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm>,
176 Sched<[itins.Sched.Folded, ReadAfterLd]>;
179 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
180 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
181 string asm, string SSEVer, string FPSizeStr,
182 Operand memopr, ComplexPattern mem_cpat,
185 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
187 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
188 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
189 [(set RC:$dst, (!cast<Intrinsic>(
190 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
191 RC:$src1, RC:$src2))], itins.rr>,
192 Sched<[itins.Sched]>;
193 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
195 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
196 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
197 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
198 SSEVer, "_", OpcodeStr, FPSizeStr))
199 RC:$src1, mem_cpat:$src2))], itins.rm>,
200 Sched<[itins.Sched.Folded, ReadAfterLd]>;
203 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
204 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
205 RegisterClass RC, ValueType vt,
206 X86MemOperand x86memop, PatFrag mem_frag,
207 Domain d, OpndItins itins, bit Is2Addr = 1> {
208 let isCommutable = 1 in
209 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
211 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
212 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
213 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
214 Sched<[itins.Sched]>;
216 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
218 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
219 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
220 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
222 Sched<[itins.Sched.Folded, ReadAfterLd]>;
225 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
226 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
227 string OpcodeStr, X86MemOperand x86memop,
228 list<dag> pat_rr, list<dag> pat_rm,
230 let isCommutable = 1, hasSideEffects = 0 in
231 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
233 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
234 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
235 pat_rr, NoItinerary, d>,
236 Sched<[WriteVecLogic]>;
237 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
239 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
240 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
241 pat_rm, NoItinerary, d>,
242 Sched<[WriteVecLogicLd, ReadAfterLd]>;
245 //===----------------------------------------------------------------------===//
246 // Non-instruction patterns
247 //===----------------------------------------------------------------------===//
249 // A vector extract of the first f32/f64 position is a subregister copy
250 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
251 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
252 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
253 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
255 // A 128-bit subvector extract from the first 256-bit vector position
256 // is a subregister copy that needs no instruction.
257 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (iPTR 0))),
258 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
259 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (iPTR 0))),
260 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
262 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (iPTR 0))),
263 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
264 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (iPTR 0))),
265 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
267 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (iPTR 0))),
268 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
269 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (iPTR 0))),
270 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
272 // A 128-bit subvector insert to the first 256-bit vector position
273 // is a subregister copy that needs no instruction.
274 let AddedComplexity = 25 in { // to give priority over vinsertf128rm
275 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)),
276 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
277 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)),
278 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
279 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)),
280 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
281 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)),
282 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
283 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (iPTR 0)),
284 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
285 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (iPTR 0)),
286 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
289 // Implicitly promote a 32-bit scalar to a vector.
290 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
291 (COPY_TO_REGCLASS FR32:$src, VR128)>;
292 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
293 (COPY_TO_REGCLASS FR32:$src, VR128)>;
294 // Implicitly promote a 64-bit scalar to a vector.
295 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
296 (COPY_TO_REGCLASS FR64:$src, VR128)>;
297 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
298 (COPY_TO_REGCLASS FR64:$src, VR128)>;
300 // Bitcasts between 128-bit vector types. Return the original type since
301 // no instruction is needed for the conversion
302 let Predicates = [HasSSE2] in {
303 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
304 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
305 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
306 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
307 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
308 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
309 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
310 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
311 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
312 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
313 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
314 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
315 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
316 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
317 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
318 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
319 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
320 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
321 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
322 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
323 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
324 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
325 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
326 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
327 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
328 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
329 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
330 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
331 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
332 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
335 // Bitcasts between 256-bit vector types. Return the original type since
336 // no instruction is needed for the conversion
337 let Predicates = [HasAVX] in {
338 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
339 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
340 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
341 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
342 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
343 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
344 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
345 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
346 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
347 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
348 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
349 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
350 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
351 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
352 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
353 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
354 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
355 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
356 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
357 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
358 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
359 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
360 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
361 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
362 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
363 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
364 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
365 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
366 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
367 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
370 // Alias instructions that map fld0 to xorps for sse or vxorps for avx.
371 // This is expanded by ExpandPostRAPseudos.
372 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
373 isPseudo = 1, SchedRW = [WriteZero] in {
374 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
375 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
376 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
377 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
380 //===----------------------------------------------------------------------===//
381 // AVX & SSE - Zero/One Vectors
382 //===----------------------------------------------------------------------===//
384 // Alias instruction that maps zero vector to pxor / xorp* for sse.
385 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
386 // swizzled by ExecutionDepsFix to pxor.
387 // We set canFoldAsLoad because this can be converted to a constant-pool
388 // load of an all-zeros value if folding it would be beneficial.
389 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
390 isPseudo = 1, SchedRW = [WriteZero] in {
391 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "",
392 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
395 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
396 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
397 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
398 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
399 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
402 // The same as done above but for AVX. The 256-bit AVX1 ISA doesn't support PI,
403 // and doesn't need it because on sandy bridge the register is set to zero
404 // at the rename stage without using any execution unit, so SET0PSY
405 // and SET0PDY can be used for vector int instructions without penalty
406 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
407 isPseudo = 1, Predicates = [HasAVX], SchedRW = [WriteZero] in {
408 def AVX_SET0 : I<0, Pseudo, (outs VR256:$dst), (ins), "",
409 [(set VR256:$dst, (v8f32 immAllZerosV))]>;
412 let Predicates = [HasAVX] in
413 def : Pat<(v4f64 immAllZerosV), (AVX_SET0)>;
415 let Predicates = [HasAVX2] in {
416 def : Pat<(v4i64 immAllZerosV), (AVX_SET0)>;
417 def : Pat<(v8i32 immAllZerosV), (AVX_SET0)>;
418 def : Pat<(v16i16 immAllZerosV), (AVX_SET0)>;
419 def : Pat<(v32i8 immAllZerosV), (AVX_SET0)>;
422 // AVX1 has no support for 256-bit integer instructions, but since the 128-bit
423 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
424 let Predicates = [HasAVX1Only] in {
425 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
426 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
427 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
429 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
430 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
431 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
433 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
434 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
435 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
437 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
438 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
439 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
442 // We set canFoldAsLoad because this can be converted to a constant-pool
443 // load of an all-ones value if folding it would be beneficial.
444 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
445 isPseudo = 1, SchedRW = [WriteZero] in {
446 def V_SETALLONES : I<0, Pseudo, (outs VR128:$dst), (ins), "",
447 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
448 let Predicates = [HasAVX2] in
449 def AVX2_SETALLONES : I<0, Pseudo, (outs VR256:$dst), (ins), "",
450 [(set VR256:$dst, (v8i32 immAllOnesV))]>;
454 //===----------------------------------------------------------------------===//
455 // SSE 1 & 2 - Move FP Scalar Instructions
457 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
458 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
459 // is used instead. Register-to-register movss/movsd is not modeled as an
460 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
461 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
462 //===----------------------------------------------------------------------===//
464 multiclass sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt,
465 X86MemOperand x86memop, string base_opc,
467 def rr : SI<0x10, MRMSrcReg, (outs VR128:$dst),
468 (ins VR128:$src1, RC:$src2),
469 !strconcat(base_opc, asm_opr),
470 [(set VR128:$dst, (vt (OpNode VR128:$src1,
471 (scalar_to_vector RC:$src2))))],
472 IIC_SSE_MOV_S_RR>, Sched<[WriteMove]>;
474 // For the disassembler
475 let isCodeGenOnly = 1, hasSideEffects = 0 in
476 def rr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
477 (ins VR128:$src1, RC:$src2),
478 !strconcat(base_opc, asm_opr),
479 [], IIC_SSE_MOV_S_RR>, Sched<[WriteMove]>;
482 multiclass sse12_move<RegisterClass RC, SDNode OpNode, ValueType vt,
483 X86MemOperand x86memop, string OpcodeStr> {
485 defm V#NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
486 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">,
489 def V#NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
490 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
491 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
492 VEX, VEX_LIG, Sched<[WriteStore]>;
494 let Constraints = "$src1 = $dst" in {
495 defm NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
496 "\t{$src2, $dst|$dst, $src2}">;
499 def NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
500 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
501 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
505 // Loading from memory automatically zeroing upper bits.
506 multiclass sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
507 PatFrag mem_pat, string OpcodeStr> {
508 def V#NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
509 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
510 [(set RC:$dst, (mem_pat addr:$src))],
511 IIC_SSE_MOV_S_RM>, VEX, VEX_LIG, Sched<[WriteLoad]>;
512 def NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
513 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
514 [(set RC:$dst, (mem_pat addr:$src))],
515 IIC_SSE_MOV_S_RM>, Sched<[WriteLoad]>;
518 defm MOVSS : sse12_move<FR32, X86Movss, v4f32, f32mem, "movss">, XS;
519 defm MOVSD : sse12_move<FR64, X86Movsd, v2f64, f64mem, "movsd">, XD;
521 let canFoldAsLoad = 1, isReMaterializable = 1 in {
522 defm MOVSS : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
524 let AddedComplexity = 20 in
525 defm MOVSD : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
529 let Predicates = [HasAVX] in {
530 let AddedComplexity = 15 in {
531 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
532 // MOVS{S,D} to the lower bits.
533 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
534 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
535 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
536 (VMOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
537 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
538 (VMOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
539 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
540 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
542 // Move low f32 and clear high bits.
543 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
544 (SUBREG_TO_REG (i32 0),
545 (VMOVSSrr (v4f32 (V_SET0)),
546 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm)), sub_xmm)>;
547 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
548 (SUBREG_TO_REG (i32 0),
549 (VMOVSSrr (v4i32 (V_SET0)),
550 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm)), sub_xmm)>;
553 let AddedComplexity = 20 in {
554 // MOVSSrm zeros the high parts of the register; represent this
555 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
556 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
557 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
558 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
559 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
560 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
561 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
563 // MOVSDrm zeros the high parts of the register; represent this
564 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
565 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
566 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
567 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
568 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
569 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
570 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
571 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
572 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
573 def : Pat<(v2f64 (X86vzload addr:$src)),
574 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
576 // Represent the same patterns above but in the form they appear for
578 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
579 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
580 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
581 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
582 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
583 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
584 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
585 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
586 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_xmm)>;
588 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
589 (v4f32 (scalar_to_vector FR32:$src)), (iPTR 0)))),
590 (SUBREG_TO_REG (i32 0),
591 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
593 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
594 (v2f64 (scalar_to_vector FR64:$src)), (iPTR 0)))),
595 (SUBREG_TO_REG (i64 0),
596 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
598 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
599 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
600 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_xmm)>;
602 // Move low f64 and clear high bits.
603 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
604 (SUBREG_TO_REG (i32 0),
605 (VMOVSDrr (v2f64 (V_SET0)),
606 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm)), sub_xmm)>;
608 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
609 (SUBREG_TO_REG (i32 0),
610 (VMOVSDrr (v2i64 (V_SET0)),
611 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm)), sub_xmm)>;
613 // Extract and store.
614 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
616 (VMOVSSmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32))>;
617 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
619 (VMOVSDmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64))>;
621 // Shuffle with VMOVSS
622 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
623 (VMOVSSrr (v4i32 VR128:$src1),
624 (COPY_TO_REGCLASS (v4i32 VR128:$src2), FR32))>;
625 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
626 (VMOVSSrr (v4f32 VR128:$src1),
627 (COPY_TO_REGCLASS (v4f32 VR128:$src2), FR32))>;
630 def : Pat<(v8i32 (X86Movss VR256:$src1, VR256:$src2)),
631 (SUBREG_TO_REG (i32 0),
632 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_xmm),
633 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_xmm)),
635 def : Pat<(v8f32 (X86Movss VR256:$src1, VR256:$src2)),
636 (SUBREG_TO_REG (i32 0),
637 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_xmm),
638 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_xmm)),
641 // Shuffle with VMOVSD
642 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
643 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
644 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
645 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
646 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
647 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
648 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
649 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
652 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
653 (SUBREG_TO_REG (i32 0),
654 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_xmm),
655 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_xmm)),
657 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
658 (SUBREG_TO_REG (i32 0),
659 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_xmm),
660 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_xmm)),
664 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
665 // is during lowering, where it's not possible to recognize the fold cause
666 // it has two uses through a bitcast. One use disappears at isel time and the
667 // fold opportunity reappears.
668 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
669 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
670 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
671 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
672 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
673 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
674 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
675 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
678 let Predicates = [UseSSE1] in {
679 let AddedComplexity = 15 in {
680 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
681 // MOVSS to the lower bits.
682 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
683 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
684 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
685 (MOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
686 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
687 (MOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
690 let AddedComplexity = 20 in {
691 // MOVSSrm already zeros the high parts of the register.
692 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
693 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
694 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
695 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
696 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
697 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
700 // Extract and store.
701 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
703 (MOVSSmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR32))>;
705 // Shuffle with MOVSS
706 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
707 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
708 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
709 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
712 let Predicates = [UseSSE2] in {
713 let AddedComplexity = 15 in {
714 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
715 // MOVSD to the lower bits.
716 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
717 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
720 let AddedComplexity = 20 in {
721 // MOVSDrm already zeros the high parts of the register.
722 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
723 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
724 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
725 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
726 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
727 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
728 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
729 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
730 def : Pat<(v2f64 (X86vzload addr:$src)),
731 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
734 // Extract and store.
735 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
737 (MOVSDmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR64))>;
739 // Shuffle with MOVSD
740 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
741 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
742 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
743 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
744 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
745 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
746 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
747 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
749 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
750 // is during lowering, where it's not possible to recognize the fold cause
751 // it has two uses through a bitcast. One use disappears at isel time and the
752 // fold opportunity reappears.
753 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
754 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
755 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
756 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
757 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
758 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
759 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
760 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
763 //===----------------------------------------------------------------------===//
764 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
765 //===----------------------------------------------------------------------===//
767 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
768 X86MemOperand x86memop, PatFrag ld_frag,
769 string asm, Domain d,
771 bit IsReMaterializable = 1> {
772 let neverHasSideEffects = 1 in
773 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
774 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], itins.rr, d>,
776 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
777 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
778 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
779 [(set RC:$dst, (ld_frag addr:$src))], itins.rm, d>,
783 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
784 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
786 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
787 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
789 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
790 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
792 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
793 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
796 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
797 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
799 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
800 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
801 TB, OpSize, VEX, VEX_L;
802 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
803 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
805 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
806 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
807 TB, OpSize, VEX, VEX_L;
808 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
809 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
811 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
812 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
814 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
815 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
817 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
818 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
821 let SchedRW = [WriteStore] in {
822 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
823 "movaps\t{$src, $dst|$dst, $src}",
824 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
825 IIC_SSE_MOVA_P_MR>, VEX;
826 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
827 "movapd\t{$src, $dst|$dst, $src}",
828 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
829 IIC_SSE_MOVA_P_MR>, VEX;
830 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
831 "movups\t{$src, $dst|$dst, $src}",
832 [(store (v4f32 VR128:$src), addr:$dst)],
833 IIC_SSE_MOVU_P_MR>, VEX;
834 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
835 "movupd\t{$src, $dst|$dst, $src}",
836 [(store (v2f64 VR128:$src), addr:$dst)],
837 IIC_SSE_MOVU_P_MR>, VEX;
838 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
839 "movaps\t{$src, $dst|$dst, $src}",
840 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)],
841 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
842 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
843 "movapd\t{$src, $dst|$dst, $src}",
844 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)],
845 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
846 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
847 "movups\t{$src, $dst|$dst, $src}",
848 [(store (v8f32 VR256:$src), addr:$dst)],
849 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
850 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
851 "movupd\t{$src, $dst|$dst, $src}",
852 [(store (v4f64 VR256:$src), addr:$dst)],
853 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
857 let isCodeGenOnly = 1, hasSideEffects = 0, SchedRW = [WriteMove] in {
858 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
860 "movaps\t{$src, $dst|$dst, $src}", [],
861 IIC_SSE_MOVA_P_RR>, VEX;
862 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
864 "movapd\t{$src, $dst|$dst, $src}", [],
865 IIC_SSE_MOVA_P_RR>, VEX;
866 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
868 "movups\t{$src, $dst|$dst, $src}", [],
869 IIC_SSE_MOVU_P_RR>, VEX;
870 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
872 "movupd\t{$src, $dst|$dst, $src}", [],
873 IIC_SSE_MOVU_P_RR>, VEX;
874 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
876 "movaps\t{$src, $dst|$dst, $src}", [],
877 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
878 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
880 "movapd\t{$src, $dst|$dst, $src}", [],
881 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
882 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
884 "movups\t{$src, $dst|$dst, $src}", [],
885 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
886 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
888 "movupd\t{$src, $dst|$dst, $src}", [],
889 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
892 let Predicates = [HasAVX] in {
893 def : Pat<(v8i32 (X86vzmovl
894 (insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)))),
895 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
896 def : Pat<(v4i64 (X86vzmovl
897 (insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)))),
898 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
899 def : Pat<(v8f32 (X86vzmovl
900 (insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)))),
901 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
902 def : Pat<(v4f64 (X86vzmovl
903 (insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)))),
904 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
908 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
909 (VMOVUPSYmr addr:$dst, VR256:$src)>;
910 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
911 (VMOVUPDYmr addr:$dst, VR256:$src)>;
913 let SchedRW = [WriteStore] in {
914 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
915 "movaps\t{$src, $dst|$dst, $src}",
916 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
918 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
919 "movapd\t{$src, $dst|$dst, $src}",
920 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
922 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
923 "movups\t{$src, $dst|$dst, $src}",
924 [(store (v4f32 VR128:$src), addr:$dst)],
926 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
927 "movupd\t{$src, $dst|$dst, $src}",
928 [(store (v2f64 VR128:$src), addr:$dst)],
933 let isCodeGenOnly = 1, hasSideEffects = 0, SchedRW = [WriteMove] in {
934 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
935 "movaps\t{$src, $dst|$dst, $src}", [],
937 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
938 "movapd\t{$src, $dst|$dst, $src}", [],
940 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
941 "movups\t{$src, $dst|$dst, $src}", [],
943 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
944 "movupd\t{$src, $dst|$dst, $src}", [],
948 let Predicates = [HasAVX] in {
949 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
950 (VMOVUPSmr addr:$dst, VR128:$src)>;
951 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
952 (VMOVUPDmr addr:$dst, VR128:$src)>;
955 let Predicates = [UseSSE1] in
956 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
957 (MOVUPSmr addr:$dst, VR128:$src)>;
958 let Predicates = [UseSSE2] in
959 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
960 (MOVUPDmr addr:$dst, VR128:$src)>;
962 // Use vmovaps/vmovups for AVX integer load/store.
963 let Predicates = [HasAVX] in {
964 // 128-bit load/store
965 def : Pat<(alignedloadv2i64 addr:$src),
966 (VMOVAPSrm addr:$src)>;
967 def : Pat<(loadv2i64 addr:$src),
968 (VMOVUPSrm addr:$src)>;
970 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
971 (VMOVAPSmr addr:$dst, VR128:$src)>;
972 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
973 (VMOVAPSmr addr:$dst, VR128:$src)>;
974 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
975 (VMOVAPSmr addr:$dst, VR128:$src)>;
976 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
977 (VMOVAPSmr addr:$dst, VR128:$src)>;
978 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
979 (VMOVUPSmr addr:$dst, VR128:$src)>;
980 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
981 (VMOVUPSmr addr:$dst, VR128:$src)>;
982 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
983 (VMOVUPSmr addr:$dst, VR128:$src)>;
984 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
985 (VMOVUPSmr addr:$dst, VR128:$src)>;
987 // 256-bit load/store
988 def : Pat<(alignedloadv4i64 addr:$src),
989 (VMOVAPSYrm addr:$src)>;
990 def : Pat<(loadv4i64 addr:$src),
991 (VMOVUPSYrm addr:$src)>;
992 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
993 (VMOVAPSYmr addr:$dst, VR256:$src)>;
994 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
995 (VMOVAPSYmr addr:$dst, VR256:$src)>;
996 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
997 (VMOVAPSYmr addr:$dst, VR256:$src)>;
998 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
999 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1000 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
1001 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1002 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
1003 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1004 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
1005 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1006 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
1007 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1009 // Special patterns for storing subvector extracts of lower 128-bits
1010 // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
1011 def : Pat<(alignedstore (v2f64 (extract_subvector
1012 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1013 (VMOVAPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1014 def : Pat<(alignedstore (v4f32 (extract_subvector
1015 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1016 (VMOVAPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1017 def : Pat<(alignedstore (v2i64 (extract_subvector
1018 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1019 (VMOVAPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1020 def : Pat<(alignedstore (v4i32 (extract_subvector
1021 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1022 (VMOVAPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1023 def : Pat<(alignedstore (v8i16 (extract_subvector
1024 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1025 (VMOVAPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1026 def : Pat<(alignedstore (v16i8 (extract_subvector
1027 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1028 (VMOVAPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1030 def : Pat<(store (v2f64 (extract_subvector
1031 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1032 (VMOVUPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1033 def : Pat<(store (v4f32 (extract_subvector
1034 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1035 (VMOVUPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1036 def : Pat<(store (v2i64 (extract_subvector
1037 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1038 (VMOVUPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1039 def : Pat<(store (v4i32 (extract_subvector
1040 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1041 (VMOVUPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1042 def : Pat<(store (v8i16 (extract_subvector
1043 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1044 (VMOVUPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1045 def : Pat<(store (v16i8 (extract_subvector
1046 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1047 (VMOVUPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1050 // Use movaps / movups for SSE integer load / store (one byte shorter).
1051 // The instructions selected below are then converted to MOVDQA/MOVDQU
1052 // during the SSE domain pass.
1053 let Predicates = [UseSSE1] in {
1054 def : Pat<(alignedloadv2i64 addr:$src),
1055 (MOVAPSrm addr:$src)>;
1056 def : Pat<(loadv2i64 addr:$src),
1057 (MOVUPSrm addr:$src)>;
1059 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1060 (MOVAPSmr addr:$dst, VR128:$src)>;
1061 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1062 (MOVAPSmr addr:$dst, VR128:$src)>;
1063 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1064 (MOVAPSmr addr:$dst, VR128:$src)>;
1065 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1066 (MOVAPSmr addr:$dst, VR128:$src)>;
1067 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1068 (MOVUPSmr addr:$dst, VR128:$src)>;
1069 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1070 (MOVUPSmr addr:$dst, VR128:$src)>;
1071 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1072 (MOVUPSmr addr:$dst, VR128:$src)>;
1073 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1074 (MOVUPSmr addr:$dst, VR128:$src)>;
1077 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
1078 // bits are disregarded. FIXME: Set encoding to pseudo!
1079 let neverHasSideEffects = 1, SchedRW = [WriteMove] in {
1080 def FsVMOVAPSrr : VPSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1081 "movaps\t{$src, $dst|$dst, $src}", [],
1082 IIC_SSE_MOVA_P_RR>, VEX;
1083 def FsVMOVAPDrr : VPDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1084 "movapd\t{$src, $dst|$dst, $src}", [],
1085 IIC_SSE_MOVA_P_RR>, VEX;
1086 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1087 "movaps\t{$src, $dst|$dst, $src}", [],
1089 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1090 "movapd\t{$src, $dst|$dst, $src}", [],
1094 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1095 // bits are disregarded. FIXME: Set encoding to pseudo!
1096 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1097 let isCodeGenOnly = 1 in {
1098 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1099 "movaps\t{$src, $dst|$dst, $src}",
1100 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1101 IIC_SSE_MOVA_P_RM>, VEX;
1102 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1103 "movapd\t{$src, $dst|$dst, $src}",
1104 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1105 IIC_SSE_MOVA_P_RM>, VEX;
1107 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1108 "movaps\t{$src, $dst|$dst, $src}",
1109 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1111 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1112 "movapd\t{$src, $dst|$dst, $src}",
1113 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1117 //===----------------------------------------------------------------------===//
1118 // SSE 1 & 2 - Move Low packed FP Instructions
1119 //===----------------------------------------------------------------------===//
1121 multiclass sse12_mov_hilo_packed_base<bits<8>opc, SDNode psnode, SDNode pdnode,
1122 string base_opc, string asm_opr,
1123 InstrItinClass itin> {
1124 def PSrm : PI<opc, MRMSrcMem,
1125 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1126 !strconcat(base_opc, "s", asm_opr),
1128 (psnode VR128:$src1,
1129 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1130 itin, SSEPackedSingle>, TB,
1131 Sched<[WriteShuffleLd, ReadAfterLd]>;
1133 def PDrm : PI<opc, MRMSrcMem,
1134 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1135 !strconcat(base_opc, "d", asm_opr),
1136 [(set VR128:$dst, (v2f64 (pdnode VR128:$src1,
1137 (scalar_to_vector (loadf64 addr:$src2)))))],
1138 itin, SSEPackedDouble>, TB, OpSize,
1139 Sched<[WriteShuffleLd, ReadAfterLd]>;
1143 multiclass sse12_mov_hilo_packed<bits<8>opc, SDNode psnode, SDNode pdnode,
1144 string base_opc, InstrItinClass itin> {
1145 defm V#NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1146 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1149 let Constraints = "$src1 = $dst" in
1150 defm NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1151 "\t{$src2, $dst|$dst, $src2}",
1155 let AddedComplexity = 20 in {
1156 defm MOVL : sse12_mov_hilo_packed<0x12, X86Movlps, X86Movlpd, "movlp",
1160 let SchedRW = [WriteStore] in {
1161 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1162 "movlps\t{$src, $dst|$dst, $src}",
1163 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1164 (iPTR 0))), addr:$dst)],
1165 IIC_SSE_MOV_LH>, VEX;
1166 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1167 "movlpd\t{$src, $dst|$dst, $src}",
1168 [(store (f64 (vector_extract (v2f64 VR128:$src),
1169 (iPTR 0))), addr:$dst)],
1170 IIC_SSE_MOV_LH>, VEX;
1171 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1172 "movlps\t{$src, $dst|$dst, $src}",
1173 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1174 (iPTR 0))), addr:$dst)],
1176 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1177 "movlpd\t{$src, $dst|$dst, $src}",
1178 [(store (f64 (vector_extract (v2f64 VR128:$src),
1179 (iPTR 0))), addr:$dst)],
1183 let Predicates = [HasAVX] in {
1184 // Shuffle with VMOVLPS
1185 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1186 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1187 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1188 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1190 // Shuffle with VMOVLPD
1191 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1192 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1193 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1194 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1197 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1199 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1200 def : Pat<(store (v4i32 (X86Movlps
1201 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1202 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1203 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1205 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1206 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1208 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1211 let Predicates = [UseSSE1] in {
1212 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1213 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1214 (iPTR 0))), addr:$src1),
1215 (MOVLPSmr addr:$src1, VR128:$src2)>;
1217 // Shuffle with MOVLPS
1218 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1219 (MOVLPSrm VR128:$src1, addr:$src2)>;
1220 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1221 (MOVLPSrm VR128:$src1, addr:$src2)>;
1222 def : Pat<(X86Movlps VR128:$src1,
1223 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1224 (MOVLPSrm VR128:$src1, addr:$src2)>;
1227 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1229 (MOVLPSmr addr:$src1, VR128:$src2)>;
1230 def : Pat<(store (v4i32 (X86Movlps
1231 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1233 (MOVLPSmr addr:$src1, VR128:$src2)>;
1236 let Predicates = [UseSSE2] in {
1237 // Shuffle with MOVLPD
1238 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1239 (MOVLPDrm VR128:$src1, addr:$src2)>;
1240 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1241 (MOVLPDrm VR128:$src1, addr:$src2)>;
1244 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1246 (MOVLPDmr addr:$src1, VR128:$src2)>;
1247 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1249 (MOVLPDmr addr:$src1, VR128:$src2)>;
1252 //===----------------------------------------------------------------------===//
1253 // SSE 1 & 2 - Move Hi packed FP Instructions
1254 //===----------------------------------------------------------------------===//
1256 let AddedComplexity = 20 in {
1257 defm MOVH : sse12_mov_hilo_packed<0x16, X86Movlhps, X86Movlhpd, "movhp",
1261 let SchedRW = [WriteStore] in {
1262 // v2f64 extract element 1 is always custom lowered to unpack high to low
1263 // and extract element 0 so the non-store version isn't too horrible.
1264 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1265 "movhps\t{$src, $dst|$dst, $src}",
1266 [(store (f64 (vector_extract
1267 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1268 (bc_v2f64 (v4f32 VR128:$src))),
1269 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1270 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1271 "movhpd\t{$src, $dst|$dst, $src}",
1272 [(store (f64 (vector_extract
1273 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1274 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1275 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1276 "movhps\t{$src, $dst|$dst, $src}",
1277 [(store (f64 (vector_extract
1278 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1279 (bc_v2f64 (v4f32 VR128:$src))),
1280 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1281 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1282 "movhpd\t{$src, $dst|$dst, $src}",
1283 [(store (f64 (vector_extract
1284 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1285 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1288 let Predicates = [HasAVX] in {
1290 def : Pat<(X86Movlhps VR128:$src1,
1291 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1292 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1293 def : Pat<(X86Movlhps VR128:$src1,
1294 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1295 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1297 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1298 // is during lowering, where it's not possible to recognize the load fold
1299 // cause it has two uses through a bitcast. One use disappears at isel time
1300 // and the fold opportunity reappears.
1301 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1302 (scalar_to_vector (loadf64 addr:$src2)))),
1303 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1306 let Predicates = [UseSSE1] in {
1308 def : Pat<(X86Movlhps VR128:$src1,
1309 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1310 (MOVHPSrm VR128:$src1, addr:$src2)>;
1311 def : Pat<(X86Movlhps VR128:$src1,
1312 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1313 (MOVHPSrm VR128:$src1, addr:$src2)>;
1316 let Predicates = [UseSSE2] in {
1317 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1318 // is during lowering, where it's not possible to recognize the load fold
1319 // cause it has two uses through a bitcast. One use disappears at isel time
1320 // and the fold opportunity reappears.
1321 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1322 (scalar_to_vector (loadf64 addr:$src2)))),
1323 (MOVHPDrm VR128:$src1, addr:$src2)>;
1326 //===----------------------------------------------------------------------===//
1327 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1328 //===----------------------------------------------------------------------===//
1330 let AddedComplexity = 20 in {
1331 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1332 (ins VR128:$src1, VR128:$src2),
1333 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1335 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1337 VEX_4V, Sched<[WriteShuffle]>;
1338 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1339 (ins VR128:$src1, VR128:$src2),
1340 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1342 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1344 VEX_4V, Sched<[WriteShuffle]>;
1346 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1347 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1348 (ins VR128:$src1, VR128:$src2),
1349 "movlhps\t{$src2, $dst|$dst, $src2}",
1351 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1352 IIC_SSE_MOV_LH>, Sched<[WriteShuffle]>;
1353 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1354 (ins VR128:$src1, VR128:$src2),
1355 "movhlps\t{$src2, $dst|$dst, $src2}",
1357 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1358 IIC_SSE_MOV_LH>, Sched<[WriteShuffle]>;
1361 let Predicates = [HasAVX] in {
1363 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1364 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1365 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1366 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1369 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1370 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1373 let Predicates = [UseSSE1] in {
1375 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1376 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1377 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1378 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1381 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1382 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1385 //===----------------------------------------------------------------------===//
1386 // SSE 1 & 2 - Conversion Instructions
1387 //===----------------------------------------------------------------------===//
1389 def SSE_CVT_PD : OpndItins<
1390 IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
1393 let Sched = WriteCvtI2F in
1394 def SSE_CVT_PS : OpndItins<
1395 IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
1398 let Sched = WriteCvtI2F in
1399 def SSE_CVT_Scalar : OpndItins<
1400 IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
1403 let Sched = WriteCvtF2I in
1404 def SSE_CVT_SS2SI_32 : OpndItins<
1405 IIC_SSE_CVT_SS2SI32_RR, IIC_SSE_CVT_SS2SI32_RM
1408 let Sched = WriteCvtF2I in
1409 def SSE_CVT_SS2SI_64 : OpndItins<
1410 IIC_SSE_CVT_SS2SI64_RR, IIC_SSE_CVT_SS2SI64_RM
1413 let Sched = WriteCvtF2I in
1414 def SSE_CVT_SD2SI : OpndItins<
1415 IIC_SSE_CVT_SD2SI_RR, IIC_SSE_CVT_SD2SI_RM
1418 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1419 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1420 string asm, OpndItins itins> {
1421 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1422 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1423 itins.rr>, Sched<[itins.Sched]>;
1424 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1425 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1426 itins.rm>, Sched<[itins.Sched.Folded]>;
1429 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1430 X86MemOperand x86memop, string asm, Domain d,
1432 let neverHasSideEffects = 1 in {
1433 def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1434 [], itins.rr, d>, Sched<[itins.Sched]>;
1436 def rm : I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1437 [], itins.rm, d>, Sched<[itins.Sched.Folded]>;
1441 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1442 X86MemOperand x86memop, string asm> {
1443 let neverHasSideEffects = 1 in {
1444 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1445 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1446 Sched<[WriteCvtI2F]>;
1448 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1449 (ins DstRC:$src1, x86memop:$src),
1450 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1451 Sched<[WriteCvtI2FLd, ReadAfterLd]>;
1452 } // neverHasSideEffects = 1
1455 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1456 "cvttss2si\t{$src, $dst|$dst, $src}",
1459 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1460 "cvttss2si\t{$src, $dst|$dst, $src}",
1462 XS, VEX, VEX_W, VEX_LIG;
1463 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1464 "cvttsd2si\t{$src, $dst|$dst, $src}",
1467 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1468 "cvttsd2si\t{$src, $dst|$dst, $src}",
1470 XD, VEX, VEX_W, VEX_LIG;
1472 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1473 (VCVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1474 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1475 (VCVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1476 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1477 (VCVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1478 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1479 (VCVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1480 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1481 (VCVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1482 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1483 (VCVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1484 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1485 (VCVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1486 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1487 (VCVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1489 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1490 // register, but the same isn't true when only using memory operands,
1491 // provide other assembly "l" and "q" forms to address this explicitly
1492 // where appropriate to do so.
1493 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss{l}">,
1494 XS, VEX_4V, VEX_LIG;
1495 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">,
1496 XS, VEX_4V, VEX_W, VEX_LIG;
1497 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">,
1498 XD, VEX_4V, VEX_LIG;
1499 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">,
1500 XD, VEX_4V, VEX_W, VEX_LIG;
1502 def : InstAlias<"vcvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1503 (VCVTSI2SSrm FR64:$dst, FR64:$src1, i32mem:$src)>;
1504 def : InstAlias<"vcvtsi2sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1505 (VCVTSI2SDrm FR64:$dst, FR64:$src1, i32mem:$src)>;
1507 let Predicates = [HasAVX] in {
1508 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1509 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1510 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1511 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1512 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1513 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1514 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1515 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1517 def : Pat<(f32 (sint_to_fp GR32:$src)),
1518 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1519 def : Pat<(f32 (sint_to_fp GR64:$src)),
1520 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1521 def : Pat<(f64 (sint_to_fp GR32:$src)),
1522 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1523 def : Pat<(f64 (sint_to_fp GR64:$src)),
1524 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1527 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1528 "cvttss2si\t{$src, $dst|$dst, $src}",
1529 SSE_CVT_SS2SI_32>, XS;
1530 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1531 "cvttss2si\t{$src, $dst|$dst, $src}",
1532 SSE_CVT_SS2SI_64>, XS, REX_W;
1533 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1534 "cvttsd2si\t{$src, $dst|$dst, $src}",
1536 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1537 "cvttsd2si\t{$src, $dst|$dst, $src}",
1538 SSE_CVT_SD2SI>, XD, REX_W;
1539 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1540 "cvtsi2ss{l}\t{$src, $dst|$dst, $src}",
1541 SSE_CVT_Scalar>, XS;
1542 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1543 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1544 SSE_CVT_Scalar>, XS, REX_W;
1545 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1546 "cvtsi2sd{l}\t{$src, $dst|$dst, $src}",
1547 SSE_CVT_Scalar>, XD;
1548 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1549 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1550 SSE_CVT_Scalar>, XD, REX_W;
1552 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1553 (CVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1554 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1555 (CVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1556 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1557 (CVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1558 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1559 (CVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1560 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1561 (CVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1562 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1563 (CVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1564 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1565 (CVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1566 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1567 (CVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1569 def : InstAlias<"cvtsi2ss\t{$src, $dst|$dst, $src}",
1570 (CVTSI2SSrm FR64:$dst, i32mem:$src)>;
1571 def : InstAlias<"cvtsi2sd\t{$src, $dst|$dst, $src}",
1572 (CVTSI2SDrm FR64:$dst, i32mem:$src)>;
1574 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1575 // and/or XMM operand(s).
1577 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1578 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
1579 string asm, OpndItins itins> {
1580 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1581 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1582 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr>,
1583 Sched<[itins.Sched]>;
1584 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
1585 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1586 [(set DstRC:$dst, (Int mem_cpat:$src))], itins.rm>,
1587 Sched<[itins.Sched.Folded]>;
1590 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1591 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1592 PatFrag ld_frag, string asm, OpndItins itins,
1594 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1596 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1597 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1598 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
1599 itins.rr>, Sched<[itins.Sched]>;
1600 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1601 (ins DstRC:$src1, x86memop:$src2),
1603 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1604 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1605 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
1606 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
1609 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32,
1610 int_x86_sse2_cvtsd2si, sdmem, sse_load_f64, "cvtsd2si",
1611 SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
1612 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1613 int_x86_sse2_cvtsd2si64, sdmem, sse_load_f64, "cvtsd2si",
1614 SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
1616 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1617 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD;
1618 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1619 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1622 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1623 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
1624 SSE_CVT_Scalar, 0>, XS, VEX_4V;
1625 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1626 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
1627 SSE_CVT_Scalar, 0>, XS, VEX_4V,
1629 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1630 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
1631 SSE_CVT_Scalar, 0>, XD, VEX_4V;
1632 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1633 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
1634 SSE_CVT_Scalar, 0>, XD,
1637 let Constraints = "$src1 = $dst" in {
1638 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1639 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1640 "cvtsi2ss{l}", SSE_CVT_Scalar>, XS;
1641 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1642 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1643 "cvtsi2ss{q}", SSE_CVT_Scalar>, XS, REX_W;
1644 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1645 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1646 "cvtsi2sd{l}", SSE_CVT_Scalar>, XD;
1647 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1648 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1649 "cvtsi2sd{q}", SSE_CVT_Scalar>, XD, REX_W;
1654 // Aliases for intrinsics
1655 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1656 ssmem, sse_load_f32, "cvttss2si",
1657 SSE_CVT_SS2SI_32>, XS, VEX;
1658 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1659 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1660 "cvttss2si", SSE_CVT_SS2SI_64>,
1662 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1663 sdmem, sse_load_f64, "cvttsd2si",
1664 SSE_CVT_SD2SI>, XD, VEX;
1665 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1666 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1667 "cvttsd2si", SSE_CVT_SD2SI>,
1669 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1670 ssmem, sse_load_f32, "cvttss2si",
1671 SSE_CVT_SS2SI_32>, XS;
1672 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1673 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1674 "cvttss2si", SSE_CVT_SS2SI_64>, XS, REX_W;
1675 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1676 sdmem, sse_load_f64, "cvttsd2si",
1678 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1679 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1680 "cvttsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1682 defm VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1683 ssmem, sse_load_f32, "cvtss2si",
1684 SSE_CVT_SS2SI_32>, XS, VEX, VEX_LIG;
1685 defm VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1686 ssmem, sse_load_f32, "cvtss2si",
1687 SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
1689 defm CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1690 ssmem, sse_load_f32, "cvtss2si",
1691 SSE_CVT_SS2SI_32>, XS;
1692 defm CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1693 ssmem, sse_load_f32, "cvtss2si",
1694 SSE_CVT_SS2SI_64>, XS, REX_W;
1696 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1697 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1698 SSEPackedSingle, SSE_CVT_PS>,
1699 TB, VEX, Requires<[HasAVX]>;
1700 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, i256mem,
1701 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1702 SSEPackedSingle, SSE_CVT_PS>,
1703 TB, VEX, VEX_L, Requires<[HasAVX]>;
1705 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1706 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1707 SSEPackedSingle, SSE_CVT_PS>,
1708 TB, Requires<[UseSSE2]>;
1710 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1711 (VCVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1712 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1713 (VCVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1714 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1715 (VCVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1716 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1717 (VCVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1718 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1719 (VCVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1720 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1721 (VCVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1722 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1723 (VCVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1724 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1725 (VCVTSD2SI64rm GR64:$dst, sdmem:$src), 0>;
1727 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1728 (CVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1729 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1730 (CVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1731 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1732 (CVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1733 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1734 (CVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1735 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1736 (CVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1737 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1738 (CVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1739 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1740 (CVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1741 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1742 (CVTSD2SI64rm GR64:$dst, sdmem:$src)>;
1746 // Convert scalar double to scalar single
1747 let neverHasSideEffects = 1 in {
1748 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1749 (ins FR64:$src1, FR64:$src2),
1750 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1751 IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG,
1752 Sched<[WriteCvtF2F]>;
1754 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1755 (ins FR64:$src1, f64mem:$src2),
1756 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1757 [], IIC_SSE_CVT_Scalar_RM>,
1758 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG,
1759 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1762 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1765 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1766 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1767 [(set FR32:$dst, (fround FR64:$src))],
1768 IIC_SSE_CVT_Scalar_RR>, Sched<[WriteCvtF2F]>;
1769 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1770 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1771 [(set FR32:$dst, (fround (loadf64 addr:$src)))],
1772 IIC_SSE_CVT_Scalar_RM>,
1774 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1776 def Int_VCVTSD2SSrr: I<0x5A, MRMSrcReg,
1777 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1778 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1780 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1781 IIC_SSE_CVT_Scalar_RR>, XD, VEX_4V, Requires<[HasAVX]>,
1782 Sched<[WriteCvtF2F]>;
1783 def Int_VCVTSD2SSrm: I<0x5A, MRMSrcReg,
1784 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1785 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1786 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1787 VR128:$src1, sse_load_f64:$src2))],
1788 IIC_SSE_CVT_Scalar_RM>, XD, VEX_4V, Requires<[HasAVX]>,
1789 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1791 let Constraints = "$src1 = $dst" in {
1792 def Int_CVTSD2SSrr: I<0x5A, MRMSrcReg,
1793 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1794 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1796 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1797 IIC_SSE_CVT_Scalar_RR>, XD, Requires<[UseSSE2]>,
1798 Sched<[WriteCvtF2F]>;
1799 def Int_CVTSD2SSrm: I<0x5A, MRMSrcReg,
1800 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1801 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1802 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1803 VR128:$src1, sse_load_f64:$src2))],
1804 IIC_SSE_CVT_Scalar_RM>, XD, Requires<[UseSSE2]>,
1805 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1808 // Convert scalar single to scalar double
1809 // SSE2 instructions with XS prefix
1810 let neverHasSideEffects = 1 in {
1811 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1812 (ins FR32:$src1, FR32:$src2),
1813 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1814 [], IIC_SSE_CVT_Scalar_RR>,
1815 XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG,
1816 Sched<[WriteCvtF2F]>;
1818 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1819 (ins FR32:$src1, f32mem:$src2),
1820 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1821 [], IIC_SSE_CVT_Scalar_RM>,
1822 XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>,
1823 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1826 def : Pat<(f64 (fextend FR32:$src)),
1827 (VCVTSS2SDrr FR32:$src, FR32:$src)>, Requires<[HasAVX]>;
1828 def : Pat<(fextend (loadf32 addr:$src)),
1829 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX]>;
1831 def : Pat<(extloadf32 addr:$src),
1832 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>,
1833 Requires<[HasAVX, OptForSize]>;
1834 def : Pat<(extloadf32 addr:$src),
1835 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (VMOVSSrm addr:$src))>,
1836 Requires<[HasAVX, OptForSpeed]>;
1838 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1839 "cvtss2sd\t{$src, $dst|$dst, $src}",
1840 [(set FR64:$dst, (fextend FR32:$src))],
1841 IIC_SSE_CVT_Scalar_RR>, XS,
1842 Requires<[UseSSE2]>, Sched<[WriteCvtF2F]>;
1843 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1844 "cvtss2sd\t{$src, $dst|$dst, $src}",
1845 [(set FR64:$dst, (extloadf32 addr:$src))],
1846 IIC_SSE_CVT_Scalar_RM>, XS,
1847 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1849 // extload f32 -> f64. This matches load+fextend because we have a hack in
1850 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1852 // Since these loads aren't folded into the fextend, we have to match it
1854 def : Pat<(fextend (loadf32 addr:$src)),
1855 (CVTSS2SDrm addr:$src)>, Requires<[UseSSE2]>;
1856 def : Pat<(extloadf32 addr:$src),
1857 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[UseSSE2, OptForSpeed]>;
1859 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1860 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1861 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1863 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1864 IIC_SSE_CVT_Scalar_RR>, XS, VEX_4V, Requires<[HasAVX]>,
1865 Sched<[WriteCvtF2F]>;
1866 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1867 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1868 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1870 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1871 IIC_SSE_CVT_Scalar_RM>, XS, VEX_4V, Requires<[HasAVX]>,
1872 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1873 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1874 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1875 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1876 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1878 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1879 IIC_SSE_CVT_Scalar_RR>, XS, Requires<[UseSSE2]>,
1880 Sched<[WriteCvtF2F]>;
1881 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1882 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1883 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1885 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1886 IIC_SSE_CVT_Scalar_RM>, XS, Requires<[UseSSE2]>,
1887 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1890 // Convert packed single/double fp to doubleword
1891 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1892 "cvtps2dq\t{$src, $dst|$dst, $src}",
1893 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1894 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
1895 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1896 "cvtps2dq\t{$src, $dst|$dst, $src}",
1898 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1899 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
1900 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1901 "cvtps2dq\t{$src, $dst|$dst, $src}",
1903 (int_x86_avx_cvt_ps2dq_256 VR256:$src))],
1904 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
1905 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1906 "cvtps2dq\t{$src, $dst|$dst, $src}",
1908 (int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)))],
1909 IIC_SSE_CVT_PS_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
1910 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1911 "cvtps2dq\t{$src, $dst|$dst, $src}",
1912 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1913 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
1914 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1915 "cvtps2dq\t{$src, $dst|$dst, $src}",
1917 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1918 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
1921 // Convert Packed Double FP to Packed DW Integers
1922 let Predicates = [HasAVX] in {
1923 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1924 // register, but the same isn't true when using memory operands instead.
1925 // Provide other assembly rr and rm forms to address this explicitly.
1926 def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1927 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1928 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1929 VEX, Sched<[WriteCvtF2I]>;
1932 def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}",
1933 (VCVTPD2DQrr VR128:$dst, VR128:$src)>;
1934 def VCVTPD2DQXrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1935 "vcvtpd2dqx\t{$src, $dst|$dst, $src}",
1937 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))]>, VEX,
1938 Sched<[WriteCvtF2ILd]>;
1941 def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1942 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
1944 (int_x86_avx_cvt_pd2dq_256 VR256:$src))]>, VEX, VEX_L,
1945 Sched<[WriteCvtF2I]>;
1946 def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1947 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
1949 (int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)))]>,
1950 VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
1951 def : InstAlias<"vcvtpd2dq\t{$src, $dst|$dst, $src}",
1952 (VCVTPD2DQYrr VR128:$dst, VR256:$src)>;
1955 def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1956 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1958 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))],
1959 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2ILd]>;
1960 def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1961 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1962 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
1963 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
1965 // Convert with truncation packed single/double fp to doubleword
1966 // SSE2 packed instructions with XS prefix
1967 def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1968 "cvttps2dq\t{$src, $dst|$dst, $src}",
1970 (int_x86_sse2_cvttps2dq VR128:$src))],
1971 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
1972 def VCVTTPS2DQrm : VS2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1973 "cvttps2dq\t{$src, $dst|$dst, $src}",
1974 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1975 (memopv4f32 addr:$src)))],
1976 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
1977 def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1978 "cvttps2dq\t{$src, $dst|$dst, $src}",
1980 (int_x86_avx_cvtt_ps2dq_256 VR256:$src))],
1981 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
1982 def VCVTTPS2DQYrm : VS2SI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1983 "cvttps2dq\t{$src, $dst|$dst, $src}",
1984 [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
1985 (memopv8f32 addr:$src)))],
1986 IIC_SSE_CVT_PS_RM>, VEX, VEX_L,
1987 Sched<[WriteCvtF2ILd]>;
1989 def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1990 "cvttps2dq\t{$src, $dst|$dst, $src}",
1991 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))],
1992 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
1993 def CVTTPS2DQrm : S2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1994 "cvttps2dq\t{$src, $dst|$dst, $src}",
1996 (int_x86_sse2_cvttps2dq (memopv4f32 addr:$src)))],
1997 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
1999 let Predicates = [HasAVX] in {
2000 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2001 (VCVTDQ2PSrr VR128:$src)>;
2002 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2003 (VCVTDQ2PSrm addr:$src)>;
2005 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2006 (VCVTDQ2PSrr VR128:$src)>;
2007 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
2008 (VCVTDQ2PSrm addr:$src)>;
2010 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2011 (VCVTTPS2DQrr VR128:$src)>;
2012 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
2013 (VCVTTPS2DQrm addr:$src)>;
2015 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
2016 (VCVTDQ2PSYrr VR256:$src)>;
2017 def : Pat<(v8f32 (sint_to_fp (bc_v8i32 (memopv4i64 addr:$src)))),
2018 (VCVTDQ2PSYrm addr:$src)>;
2020 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
2021 (VCVTTPS2DQYrr VR256:$src)>;
2022 def : Pat<(v8i32 (fp_to_sint (memopv8f32 addr:$src))),
2023 (VCVTTPS2DQYrm addr:$src)>;
2026 let Predicates = [UseSSE2] in {
2027 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2028 (CVTDQ2PSrr VR128:$src)>;
2029 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2030 (CVTDQ2PSrm addr:$src)>;
2032 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2033 (CVTDQ2PSrr VR128:$src)>;
2034 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
2035 (CVTDQ2PSrm addr:$src)>;
2037 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2038 (CVTTPS2DQrr VR128:$src)>;
2039 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
2040 (CVTTPS2DQrm addr:$src)>;
2043 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2044 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2046 (int_x86_sse2_cvttpd2dq VR128:$src))],
2047 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2I]>;
2049 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2050 // register, but the same isn't true when using memory operands instead.
2051 // Provide other assembly rr and rm forms to address this explicitly.
2054 def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}",
2055 (VCVTTPD2DQrr VR128:$dst, VR128:$src)>;
2056 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2057 "cvttpd2dqx\t{$src, $dst|$dst, $src}",
2058 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2059 (memopv2f64 addr:$src)))],
2060 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2063 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2064 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2066 (int_x86_avx_cvtt_pd2dq_256 VR256:$src))],
2067 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2068 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2069 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2071 (int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)))],
2072 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2073 def : InstAlias<"vcvttpd2dq\t{$src, $dst|$dst, $src}",
2074 (VCVTTPD2DQYrr VR128:$dst, VR256:$src)>;
2076 let Predicates = [HasAVX] in {
2077 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
2078 (VCVTTPD2DQYrr VR256:$src)>;
2079 def : Pat<(v4i32 (fp_to_sint (memopv4f64 addr:$src))),
2080 (VCVTTPD2DQYrm addr:$src)>;
2081 } // Predicates = [HasAVX]
2083 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2084 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2085 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))],
2086 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2087 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
2088 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2089 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2090 (memopv2f64 addr:$src)))],
2092 Sched<[WriteCvtF2ILd]>;
2094 // Convert packed single to packed double
2095 let Predicates = [HasAVX] in {
2096 // SSE2 instructions without OpSize prefix
2097 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2098 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2099 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2100 IIC_SSE_CVT_PD_RR>, TB, VEX, Sched<[WriteCvtF2F]>;
2101 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2102 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2103 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2104 IIC_SSE_CVT_PD_RM>, TB, VEX, Sched<[WriteCvtF2FLd]>;
2105 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2106 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2108 (int_x86_avx_cvt_ps2_pd_256 VR128:$src))],
2109 IIC_SSE_CVT_PD_RR>, TB, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2110 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
2111 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2113 (int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)))],
2114 IIC_SSE_CVT_PD_RM>, TB, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2117 let Predicates = [UseSSE2] in {
2118 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2119 "cvtps2pd\t{$src, $dst|$dst, $src}",
2120 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2121 IIC_SSE_CVT_PD_RR>, TB, Sched<[WriteCvtF2F]>;
2122 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2123 "cvtps2pd\t{$src, $dst|$dst, $src}",
2124 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2125 IIC_SSE_CVT_PD_RM>, TB, Sched<[WriteCvtF2FLd]>;
2128 // Convert Packed DW Integers to Packed Double FP
2129 let Predicates = [HasAVX] in {
2130 let neverHasSideEffects = 1, mayLoad = 1 in
2131 def VCVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2132 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2133 []>, VEX, Sched<[WriteCvtI2FLd]>;
2134 def VCVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2135 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2137 (int_x86_sse2_cvtdq2pd VR128:$src))]>, VEX,
2138 Sched<[WriteCvtI2F]>;
2139 def VCVTDQ2PDYrm : S2SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
2140 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2142 (int_x86_avx_cvtdq2_pd_256
2143 (bitconvert (memopv2i64 addr:$src))))]>, VEX, VEX_L,
2144 Sched<[WriteCvtI2FLd]>;
2145 def VCVTDQ2PDYrr : S2SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2146 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2148 (int_x86_avx_cvtdq2_pd_256 VR128:$src))]>, VEX, VEX_L,
2149 Sched<[WriteCvtI2F]>;
2152 let neverHasSideEffects = 1, mayLoad = 1 in
2153 def CVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2154 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
2155 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtI2FLd]>;
2156 def CVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2157 "cvtdq2pd\t{$src, $dst|$dst, $src}",
2158 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
2159 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtI2F]>;
2161 // AVX 256-bit register conversion intrinsics
2162 let Predicates = [HasAVX] in {
2163 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
2164 (VCVTDQ2PDYrr VR128:$src)>;
2165 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2166 (VCVTDQ2PDYrm addr:$src)>;
2167 } // Predicates = [HasAVX]
2169 // Convert packed double to packed single
2170 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2171 // register, but the same isn't true when using memory operands instead.
2172 // Provide other assembly rr and rm forms to address this explicitly.
2173 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2174 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2175 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2176 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2F]>;
2179 def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}",
2180 (VCVTPD2PSrr VR128:$dst, VR128:$src)>;
2181 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2182 "cvtpd2psx\t{$src, $dst|$dst, $src}",
2184 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2185 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2FLd]>;
2188 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2189 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2191 (int_x86_avx_cvt_pd2_ps_256 VR256:$src))],
2192 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2193 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2194 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2196 (int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)))],
2197 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2198 def : InstAlias<"vcvtpd2ps\t{$src, $dst|$dst, $src}",
2199 (VCVTPD2PSYrr VR128:$dst, VR256:$src)>;
2201 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2202 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2203 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2204 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2F]>;
2205 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2206 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2208 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2209 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2FLd]>;
2212 // AVX 256-bit register conversion intrinsics
2213 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
2214 // whenever possible to avoid declaring two versions of each one.
2215 let Predicates = [HasAVX] in {
2216 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
2217 (VCVTDQ2PSYrr VR256:$src)>;
2218 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (memopv4i64 addr:$src))),
2219 (VCVTDQ2PSYrm addr:$src)>;
2221 // Match fround and fextend for 128/256-bit conversions
2222 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2223 (VCVTPD2PSrr VR128:$src)>;
2224 def : Pat<(v4f32 (X86vfpround (memopv2f64 addr:$src))),
2225 (VCVTPD2PSXrm addr:$src)>;
2226 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
2227 (VCVTPD2PSYrr VR256:$src)>;
2228 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
2229 (VCVTPD2PSYrm addr:$src)>;
2231 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2232 (VCVTPS2PDrr VR128:$src)>;
2233 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
2234 (VCVTPS2PDYrr VR128:$src)>;
2235 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
2236 (VCVTPS2PDYrm addr:$src)>;
2239 let Predicates = [UseSSE2] in {
2240 // Match fround and fextend for 128 conversions
2241 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2242 (CVTPD2PSrr VR128:$src)>;
2243 def : Pat<(v4f32 (X86vfpround (memopv2f64 addr:$src))),
2244 (CVTPD2PSrm addr:$src)>;
2246 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2247 (CVTPS2PDrr VR128:$src)>;
2250 //===----------------------------------------------------------------------===//
2251 // SSE 1 & 2 - Compare Instructions
2252 //===----------------------------------------------------------------------===//
2254 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2255 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2256 Operand CC, SDNode OpNode, ValueType VT,
2257 PatFrag ld_frag, string asm, string asm_alt,
2259 def rr : SIi8<0xC2, MRMSrcReg,
2260 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2261 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
2262 itins.rr>, Sched<[itins.Sched]>;
2263 def rm : SIi8<0xC2, MRMSrcMem,
2264 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2265 [(set RC:$dst, (OpNode (VT RC:$src1),
2266 (ld_frag addr:$src2), imm:$cc))],
2268 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2270 // Accept explicit immediate argument form instead of comparison code.
2271 let neverHasSideEffects = 1 in {
2272 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2273 (ins RC:$src1, RC:$src2, i8imm:$cc), asm_alt, [],
2274 IIC_SSE_ALU_F32S_RR>, Sched<[itins.Sched]>;
2276 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2277 (ins RC:$src1, x86memop:$src2, i8imm:$cc), asm_alt, [],
2278 IIC_SSE_ALU_F32S_RM>,
2279 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2283 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, AVXCC, X86cmpss, f32, loadf32,
2284 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2285 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2287 XS, VEX_4V, VEX_LIG;
2288 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, AVXCC, X86cmpsd, f64, loadf64,
2289 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2290 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2291 SSE_ALU_F32S>, // same latency as 32 bit compare
2292 XD, VEX_4V, VEX_LIG;
2294 let Constraints = "$src1 = $dst" in {
2295 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC, X86cmpss, f32, loadf32,
2296 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2297 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}", SSE_ALU_F32S>,
2299 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC, X86cmpsd, f64, loadf64,
2300 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2301 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2302 SSE_ALU_F32S>, // same latency as 32 bit compare
2306 multiclass sse12_cmp_scalar_int<X86MemOperand x86memop, Operand CC,
2307 Intrinsic Int, string asm, OpndItins itins> {
2308 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2309 (ins VR128:$src1, VR128:$src, CC:$cc), asm,
2310 [(set VR128:$dst, (Int VR128:$src1,
2311 VR128:$src, imm:$cc))],
2313 Sched<[itins.Sched]>;
2314 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2315 (ins VR128:$src1, x86memop:$src, CC:$cc), asm,
2316 [(set VR128:$dst, (Int VR128:$src1,
2317 (load addr:$src), imm:$cc))],
2319 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2322 // Aliases to match intrinsics which expect XMM operand(s).
2323 defm Int_VCMPSS : sse12_cmp_scalar_int<f32mem, AVXCC, int_x86_sse_cmp_ss,
2324 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
2327 defm Int_VCMPSD : sse12_cmp_scalar_int<f64mem, AVXCC, int_x86_sse2_cmp_sd,
2328 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
2329 SSE_ALU_F32S>, // same latency as f32
2331 let Constraints = "$src1 = $dst" in {
2332 defm Int_CMPSS : sse12_cmp_scalar_int<f32mem, SSECC, int_x86_sse_cmp_ss,
2333 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
2335 defm Int_CMPSD : sse12_cmp_scalar_int<f64mem, SSECC, int_x86_sse2_cmp_sd,
2336 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
2337 SSE_ALU_F32S>, // same latency as f32
2342 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2343 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2344 ValueType vt, X86MemOperand x86memop,
2345 PatFrag ld_frag, string OpcodeStr, Domain d> {
2346 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2347 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2348 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2349 IIC_SSE_COMIS_RR, d>,
2351 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2352 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2353 [(set EFLAGS, (OpNode (vt RC:$src1),
2354 (ld_frag addr:$src2)))],
2355 IIC_SSE_COMIS_RM, d>,
2356 Sched<[WriteFAddLd, ReadAfterLd]>;
2359 let Defs = [EFLAGS] in {
2360 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2361 "ucomiss", SSEPackedSingle>, TB, VEX, VEX_LIG;
2362 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2363 "ucomisd", SSEPackedDouble>, TB, OpSize, VEX,
2365 let Pattern = []<dag> in {
2366 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2367 "comiss", SSEPackedSingle>, TB, VEX,
2369 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2370 "comisd", SSEPackedDouble>, TB, OpSize, VEX,
2374 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2375 load, "ucomiss", SSEPackedSingle>, TB, VEX;
2376 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2377 load, "ucomisd", SSEPackedDouble>, TB, OpSize, VEX;
2379 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2380 load, "comiss", SSEPackedSingle>, TB, VEX;
2381 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2382 load, "comisd", SSEPackedDouble>, TB, OpSize, VEX;
2383 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2384 "ucomiss", SSEPackedSingle>, TB;
2385 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2386 "ucomisd", SSEPackedDouble>, TB, OpSize;
2388 let Pattern = []<dag> in {
2389 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2390 "comiss", SSEPackedSingle>, TB;
2391 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2392 "comisd", SSEPackedDouble>, TB, OpSize;
2395 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2396 load, "ucomiss", SSEPackedSingle>, TB;
2397 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2398 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
2400 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2401 "comiss", SSEPackedSingle>, TB;
2402 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2403 "comisd", SSEPackedDouble>, TB, OpSize;
2404 } // Defs = [EFLAGS]
2406 // sse12_cmp_packed - sse 1 & 2 compare packed instructions
2407 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2408 Operand CC, Intrinsic Int, string asm,
2409 string asm_alt, Domain d> {
2410 def rri : PIi8<0xC2, MRMSrcReg,
2411 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2412 [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))],
2413 IIC_SSE_CMPP_RR, d>,
2415 def rmi : PIi8<0xC2, MRMSrcMem,
2416 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2417 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))],
2418 IIC_SSE_CMPP_RM, d>,
2419 Sched<[WriteFAddLd, ReadAfterLd]>;
2421 // Accept explicit immediate argument form instead of comparison code.
2422 let neverHasSideEffects = 1 in {
2423 def rri_alt : PIi8<0xC2, MRMSrcReg,
2424 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
2425 asm_alt, [], IIC_SSE_CMPP_RR, d>, Sched<[WriteFAdd]>;
2426 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2427 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
2428 asm_alt, [], IIC_SSE_CMPP_RM, d>,
2429 Sched<[WriteFAddLd, ReadAfterLd]>;
2433 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse_cmp_ps,
2434 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2435 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2436 SSEPackedSingle>, TB, VEX_4V;
2437 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse2_cmp_pd,
2438 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2439 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2440 SSEPackedDouble>, TB, OpSize, VEX_4V;
2441 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_ps_256,
2442 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2443 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2444 SSEPackedSingle>, TB, VEX_4V, VEX_L;
2445 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_pd_256,
2446 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2447 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2448 SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2449 let Constraints = "$src1 = $dst" in {
2450 defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse_cmp_ps,
2451 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2452 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2453 SSEPackedSingle>, TB;
2454 defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse2_cmp_pd,
2455 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2456 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2457 SSEPackedDouble>, TB, OpSize;
2460 let Predicates = [HasAVX] in {
2461 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2462 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2463 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2464 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2465 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2466 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2467 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2468 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2470 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2471 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2472 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
2473 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2474 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2475 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2476 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
2477 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2480 let Predicates = [UseSSE1] in {
2481 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2482 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2483 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2484 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2487 let Predicates = [UseSSE2] in {
2488 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2489 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2490 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2491 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2494 //===----------------------------------------------------------------------===//
2495 // SSE 1 & 2 - Shuffle Instructions
2496 //===----------------------------------------------------------------------===//
2498 /// sse12_shuffle - sse 1 & 2 shuffle instructions
2499 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2500 ValueType vt, string asm, PatFrag mem_frag,
2501 Domain d, bit IsConvertibleToThreeAddress = 0> {
2502 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2503 (ins RC:$src1, x86memop:$src2, i8imm:$src3), asm,
2504 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
2505 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2506 Sched<[WriteShuffleLd, ReadAfterLd]>;
2507 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
2508 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2509 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
2510 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
2511 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2512 Sched<[WriteShuffle]>;
2515 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2516 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2517 memopv4f32, SSEPackedSingle>, TB, VEX_4V;
2518 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2519 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2520 memopv8f32, SSEPackedSingle>, TB, VEX_4V, VEX_L;
2521 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2522 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2523 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2524 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2525 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2526 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2528 let Constraints = "$src1 = $dst" in {
2529 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2530 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2531 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
2533 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2534 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2535 memopv2f64, SSEPackedDouble, 1 /* cvt to pshufd */>,
2539 let Predicates = [HasAVX] in {
2540 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2541 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2542 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2543 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2544 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2546 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2547 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2548 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2549 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2550 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2553 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2554 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2555 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2556 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
2557 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2559 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2560 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2561 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2562 (memopv4i64 addr:$src2), (i8 imm:$imm))),
2563 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2566 let Predicates = [UseSSE1] in {
2567 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2568 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2569 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2570 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2571 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2574 let Predicates = [UseSSE2] in {
2575 // Generic SHUFPD patterns
2576 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2577 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2578 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2579 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2580 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2583 //===----------------------------------------------------------------------===//
2584 // SSE 1 & 2 - Unpack Instructions
2585 //===----------------------------------------------------------------------===//
2587 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
2588 multiclass sse12_unpack_interleave<bits<8> opc, SDNode OpNode, ValueType vt,
2589 PatFrag mem_frag, RegisterClass RC,
2590 X86MemOperand x86memop, string asm,
2592 def rr : PI<opc, MRMSrcReg,
2593 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2595 (vt (OpNode RC:$src1, RC:$src2)))],
2596 IIC_SSE_UNPCK, d>, Sched<[WriteShuffle]>;
2597 def rm : PI<opc, MRMSrcMem,
2598 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2600 (vt (OpNode RC:$src1,
2601 (mem_frag addr:$src2))))],
2603 Sched<[WriteShuffleLd, ReadAfterLd]>;
2606 defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2607 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2608 SSEPackedSingle>, TB, VEX_4V;
2609 defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2610 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2611 SSEPackedDouble>, TB, OpSize, VEX_4V;
2612 defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2613 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2614 SSEPackedSingle>, TB, VEX_4V;
2615 defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2616 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2617 SSEPackedDouble>, TB, OpSize, VEX_4V;
2619 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, memopv8f32,
2620 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2621 SSEPackedSingle>, TB, VEX_4V, VEX_L;
2622 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, memopv4f64,
2623 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2624 SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2625 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, memopv8f32,
2626 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2627 SSEPackedSingle>, TB, VEX_4V, VEX_L;
2628 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, memopv4f64,
2629 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2630 SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2632 let Constraints = "$src1 = $dst" in {
2633 defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2634 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2635 SSEPackedSingle>, TB;
2636 defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2637 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2638 SSEPackedDouble>, TB, OpSize;
2639 defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2640 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2641 SSEPackedSingle>, TB;
2642 defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2643 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2644 SSEPackedDouble>, TB, OpSize;
2645 } // Constraints = "$src1 = $dst"
2647 let Predicates = [HasAVX1Only] in {
2648 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
2649 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2650 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
2651 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2652 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
2653 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2654 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
2655 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2657 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (memopv4i64 addr:$src2))),
2658 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2659 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
2660 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2661 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (memopv4i64 addr:$src2))),
2662 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2663 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
2664 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2667 let Predicates = [HasAVX] in {
2668 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2669 // problem is during lowering, where it's not possible to recognize the load
2670 // fold cause it has two uses through a bitcast. One use disappears at isel
2671 // time and the fold opportunity reappears.
2672 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2673 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2676 let Predicates = [UseSSE2] in {
2677 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2678 // problem is during lowering, where it's not possible to recognize the load
2679 // fold cause it has two uses through a bitcast. One use disappears at isel
2680 // time and the fold opportunity reappears.
2681 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2682 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2685 //===----------------------------------------------------------------------===//
2686 // SSE 1 & 2 - Extract Floating-Point Sign mask
2687 //===----------------------------------------------------------------------===//
2689 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2690 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2692 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
2693 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2694 [(set GR32:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>,
2695 Sched<[WriteVecLogic]>;
2696 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
2697 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [],
2698 IIC_SSE_MOVMSK, d>, REX_W, Sched<[WriteVecLogic]>;
2701 let Predicates = [HasAVX] in {
2702 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2703 "movmskps", SSEPackedSingle>, TB, VEX;
2704 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2705 "movmskpd", SSEPackedDouble>, TB,
2707 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2708 "movmskps", SSEPackedSingle>, TB,
2710 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2711 "movmskpd", SSEPackedDouble>, TB,
2714 def : Pat<(i32 (X86fgetsign FR32:$src)),
2715 (VMOVMSKPSrr32 (COPY_TO_REGCLASS FR32:$src, VR128))>;
2716 def : Pat<(i64 (X86fgetsign FR32:$src)),
2717 (VMOVMSKPSrr64 (COPY_TO_REGCLASS FR32:$src, VR128))>;
2718 def : Pat<(i32 (X86fgetsign FR64:$src)),
2719 (VMOVMSKPDrr32 (COPY_TO_REGCLASS FR64:$src, VR128))>;
2720 def : Pat<(i64 (X86fgetsign FR64:$src)),
2721 (VMOVMSKPDrr64 (COPY_TO_REGCLASS FR64:$src, VR128))>;
2724 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2725 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2726 SSEPackedSingle>, TB, VEX, Sched<[WriteVecLogic]>;
2727 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2728 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2729 SSEPackedDouble>, TB,
2730 OpSize, VEX, Sched<[WriteVecLogic]>;
2731 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2732 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2733 SSEPackedSingle>, TB, VEX, VEX_L, Sched<[WriteVecLogic]>;
2734 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2735 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2736 SSEPackedDouble>, TB,
2737 OpSize, VEX, VEX_L, Sched<[WriteVecLogic]>;
2740 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2741 SSEPackedSingle>, TB;
2742 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2743 SSEPackedDouble>, TB, OpSize;
2745 def : Pat<(i32 (X86fgetsign FR32:$src)),
2746 (MOVMSKPSrr32 (COPY_TO_REGCLASS FR32:$src, VR128))>,
2747 Requires<[UseSSE1]>;
2748 def : Pat<(i64 (X86fgetsign FR32:$src)),
2749 (MOVMSKPSrr64 (COPY_TO_REGCLASS FR32:$src, VR128))>,
2750 Requires<[UseSSE1]>;
2751 def : Pat<(i32 (X86fgetsign FR64:$src)),
2752 (MOVMSKPDrr32 (COPY_TO_REGCLASS FR64:$src, VR128))>,
2753 Requires<[UseSSE2]>;
2754 def : Pat<(i64 (X86fgetsign FR64:$src)),
2755 (MOVMSKPDrr64 (COPY_TO_REGCLASS FR64:$src, VR128))>,
2756 Requires<[UseSSE2]>;
2758 //===---------------------------------------------------------------------===//
2759 // SSE2 - Packed Integer Logical Instructions
2760 //===---------------------------------------------------------------------===//
2762 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2764 /// PDI_binop_rm - Simple SSE2 binary operator.
2765 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2766 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2767 X86MemOperand x86memop, OpndItins itins,
2768 bit IsCommutable, bit Is2Addr> {
2769 let isCommutable = IsCommutable in
2770 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2771 (ins RC:$src1, RC:$src2),
2773 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2774 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2775 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
2776 Sched<[itins.Sched]>;
2777 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2778 (ins RC:$src1, x86memop:$src2),
2780 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2781 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2782 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2783 (bitconvert (memop_frag addr:$src2)))))],
2785 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2787 } // ExeDomain = SSEPackedInt
2789 multiclass PDI_binop_all<bits<8> opc, string OpcodeStr, SDNode Opcode,
2790 ValueType OpVT128, ValueType OpVT256,
2791 OpndItins itins, bit IsCommutable = 0> {
2792 let Predicates = [HasAVX] in
2793 defm V#NAME : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode, OpVT128,
2794 VR128, memopv2i64, i128mem, itins, IsCommutable, 0>, VEX_4V;
2796 let Constraints = "$src1 = $dst" in
2797 defm NAME : PDI_binop_rm<opc, OpcodeStr, Opcode, OpVT128, VR128,
2798 memopv2i64, i128mem, itins, IsCommutable, 1>;
2800 let Predicates = [HasAVX2] in
2801 defm V#NAME#Y : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode,
2802 OpVT256, VR256, memopv4i64, i256mem, itins,
2803 IsCommutable, 0>, VEX_4V, VEX_L;
2806 // These are ordered here for pattern ordering requirements with the fp versions
2808 defm PAND : PDI_binop_all<0xDB, "pand", and, v2i64, v4i64, SSE_BIT_ITINS_P, 1>;
2809 defm POR : PDI_binop_all<0xEB, "por", or, v2i64, v4i64, SSE_BIT_ITINS_P, 1>;
2810 defm PXOR : PDI_binop_all<0xEF, "pxor", xor, v2i64, v4i64, SSE_BIT_ITINS_P, 1>;
2811 defm PANDN : PDI_binop_all<0xDF, "pandn", X86andnp, v2i64, v4i64,
2812 SSE_BIT_ITINS_P, 0>;
2814 //===----------------------------------------------------------------------===//
2815 // SSE 1 & 2 - Logical Instructions
2816 //===----------------------------------------------------------------------===//
2818 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
2820 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
2821 SDNode OpNode, OpndItins itins> {
2822 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2823 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, itins, 0>,
2826 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2827 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, itins, 0>,
2830 let Constraints = "$src1 = $dst" in {
2831 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2832 f32, f128mem, memopfsf32, SSEPackedSingle, itins>,
2835 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2836 f64, f128mem, memopfsf64, SSEPackedDouble, itins>,
2841 // Alias bitwise logical operations using SSE logical ops on packed FP values.
2842 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand,
2844 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for,
2846 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor,
2849 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
2850 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef,
2853 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2855 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2857 defm V#NAME#PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2858 !strconcat(OpcodeStr, "ps"), f256mem,
2859 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2860 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2861 (memopv4i64 addr:$src2)))], 0>, TB, VEX_4V, VEX_L;
2863 defm V#NAME#PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2864 !strconcat(OpcodeStr, "pd"), f256mem,
2865 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2866 (bc_v4i64 (v4f64 VR256:$src2))))],
2867 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2868 (memopv4i64 addr:$src2)))], 0>,
2869 TB, OpSize, VEX_4V, VEX_L;
2871 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2872 // are all promoted to v2i64, and the patterns are covered by the int
2873 // version. This is needed in SSE only, because v2i64 isn't supported on
2874 // SSE1, but only on SSE2.
2875 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2876 !strconcat(OpcodeStr, "ps"), f128mem, [],
2877 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2878 (memopv2i64 addr:$src2)))], 0>, TB, VEX_4V;
2880 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2881 !strconcat(OpcodeStr, "pd"), f128mem,
2882 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2883 (bc_v2i64 (v2f64 VR128:$src2))))],
2884 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2885 (memopv2i64 addr:$src2)))], 0>,
2888 let Constraints = "$src1 = $dst" in {
2889 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2890 !strconcat(OpcodeStr, "ps"), f128mem,
2891 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2892 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2893 (memopv2i64 addr:$src2)))]>, TB;
2895 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2896 !strconcat(OpcodeStr, "pd"), f128mem,
2897 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2898 (bc_v2i64 (v2f64 VR128:$src2))))],
2899 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2900 (memopv2i64 addr:$src2)))]>, TB, OpSize;
2904 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2905 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2906 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2907 let isCommutable = 0 in
2908 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2910 //===----------------------------------------------------------------------===//
2911 // SSE 1 & 2 - Arithmetic Instructions
2912 //===----------------------------------------------------------------------===//
2914 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
2917 /// In addition, we also have a special variant of the scalar form here to
2918 /// represent the associated intrinsic operation. This form is unlike the
2919 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
2920 /// and leaves the top elements unmodified (therefore these cannot be commuted).
2922 /// These three forms can each be reg+reg or reg+mem.
2925 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
2927 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2930 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
2931 OpNode, FR32, f32mem,
2932 itins.s, Is2Addr>, XS;
2933 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
2934 OpNode, FR64, f64mem,
2935 itins.d, Is2Addr>, XD;
2938 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr,
2939 SDNode OpNode, SizeItins itins> {
2940 let Predicates = [HasAVX] in {
2941 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2942 VR128, v4f32, f128mem, memopv4f32,
2943 SSEPackedSingle, itins.s, 0>, TB, VEX_4V;
2944 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2945 VR128, v2f64, f128mem, memopv2f64,
2946 SSEPackedDouble, itins.d, 0>, TB, OpSize, VEX_4V;
2948 defm V#NAME#PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"),
2949 OpNode, VR256, v8f32, f256mem, memopv8f32,
2950 SSEPackedSingle, itins.s, 0>, TB, VEX_4V, VEX_L;
2951 defm V#NAME#PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"),
2952 OpNode, VR256, v4f64, f256mem, memopv4f64,
2953 SSEPackedDouble, itins.d, 0>, TB, OpSize, VEX_4V, VEX_L;
2956 let Constraints = "$src1 = $dst" in {
2957 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2958 v4f32, f128mem, memopv4f32, SSEPackedSingle,
2960 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2961 v2f64, f128mem, memopv2f64, SSEPackedDouble,
2962 itins.d, 1>, TB, OpSize;
2966 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
2969 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2970 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
2971 itins.s, Is2Addr>, XS;
2972 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2973 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
2974 itins.d, Is2Addr>, XD;
2977 // Binary Arithmetic instructions
2978 defm ADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P>;
2979 defm MUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P>;
2980 let isCommutable = 0 in {
2981 defm SUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P>;
2982 defm DIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_DIV_ITINS_P>;
2983 defm MAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>;
2984 defm MIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>;
2987 let isCodeGenOnly = 1 in {
2988 defm MAXC: basic_sse12_fp_binop_p<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P>;
2989 defm MINC: basic_sse12_fp_binop_p<0x5D, "min", X86fminc, SSE_ALU_ITINS_P>;
2992 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S, 0>,
2993 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S, 0>,
2995 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S, 0>,
2996 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S, 0>,
2999 let isCommutable = 0 in {
3000 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S, 0>,
3001 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S, 0>,
3003 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S, 0>,
3004 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S, 0>,
3006 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S, 0>,
3007 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S, 0>,
3009 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S, 0>,
3010 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S, 0>,
3014 let Constraints = "$src1 = $dst" in {
3015 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
3016 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S>;
3017 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S>,
3018 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S>;
3020 let isCommutable = 0 in {
3021 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>,
3022 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S>;
3023 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S>,
3024 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S>;
3025 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>,
3026 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S>;
3027 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>,
3028 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S>;
3032 let isCodeGenOnly = 1 in {
3033 defm VMAXC: basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S, 0>,
3035 defm VMINC: basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S, 0>,
3037 let Constraints = "$src1 = $dst" in {
3038 defm MAXC: basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S>;
3039 defm MINC: basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S>;
3044 /// In addition, we also have a special variant of the scalar form here to
3045 /// represent the associated intrinsic operation. This form is unlike the
3046 /// plain scalar form, in that it takes an entire vector (instead of a
3047 /// scalar) and leaves the top elements undefined.
3049 /// And, we have a special variant form for a full-vector intrinsic form.
3051 let Sched = WriteFSqrt in {
3052 def SSE_SQRTPS : OpndItins<
3053 IIC_SSE_SQRTPS_RR, IIC_SSE_SQRTPS_RM
3056 def SSE_SQRTSS : OpndItins<
3057 IIC_SSE_SQRTSS_RR, IIC_SSE_SQRTSS_RM
3060 def SSE_SQRTPD : OpndItins<
3061 IIC_SSE_SQRTPD_RR, IIC_SSE_SQRTPD_RM
3064 def SSE_SQRTSD : OpndItins<
3065 IIC_SSE_SQRTSD_RR, IIC_SSE_SQRTSD_RM
3069 let Sched = WriteFRcp in {
3070 def SSE_RCPP : OpndItins<
3071 IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM
3074 def SSE_RCPS : OpndItins<
3075 IIC_SSE_RCPS_RR, IIC_SSE_RCPS_RM
3079 /// sse1_fp_unop_s - SSE1 unops in scalar form.
3080 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
3081 SDNode OpNode, Intrinsic F32Int, OpndItins itins> {
3082 let Predicates = [HasAVX], hasSideEffects = 0 in {
3083 def V#NAME#SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst),
3084 (ins FR32:$src1, FR32:$src2),
3085 !strconcat("v", OpcodeStr,
3086 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3087 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3088 let mayLoad = 1 in {
3089 def V#NAME#SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
3090 (ins FR32:$src1,f32mem:$src2),
3091 !strconcat("v", OpcodeStr,
3092 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3093 []>, VEX_4V, VEX_LIG,
3094 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3095 def V#NAME#SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3096 (ins VR128:$src1, ssmem:$src2),
3097 !strconcat("v", OpcodeStr,
3098 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3099 []>, VEX_4V, VEX_LIG,
3100 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3104 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3105 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3106 [(set FR32:$dst, (OpNode FR32:$src))]>, Sched<[itins.Sched]>;
3107 // For scalar unary operations, fold a load into the operation
3108 // only in OptForSize mode. It eliminates an instruction, but it also
3109 // eliminates a whole-register clobber (the load), so it introduces a
3110 // partial register update condition.
3111 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3112 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3113 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3114 Requires<[UseSSE1, OptForSize]>, Sched<[itins.Sched.Folded]>;
3115 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3116 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3117 [(set VR128:$dst, (F32Int VR128:$src))], itins.rr>,
3118 Sched<[itins.Sched]>;
3119 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
3120 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3121 [(set VR128:$dst, (F32Int sse_load_f32:$src))], itins.rm>,
3122 Sched<[itins.Sched.Folded]>;
3125 /// sse1_fp_unop_s_rw - SSE1 unops where vector form has a read-write operand.
3126 multiclass sse1_fp_unop_rw<bits<8> opc, string OpcodeStr, SDNode OpNode,
3128 let Predicates = [HasAVX], hasSideEffects = 0 in {
3129 def V#NAME#SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst),
3130 (ins FR32:$src1, FR32:$src2),
3131 !strconcat("v", OpcodeStr,
3132 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3133 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3134 let mayLoad = 1 in {
3135 def V#NAME#SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
3136 (ins FR32:$src1,f32mem:$src2),
3137 !strconcat("v", OpcodeStr,
3138 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3139 []>, VEX_4V, VEX_LIG,
3140 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3141 def V#NAME#SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3142 (ins VR128:$src1, ssmem:$src2),
3143 !strconcat("v", OpcodeStr,
3144 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3145 []>, VEX_4V, VEX_LIG,
3146 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3150 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3151 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3152 [(set FR32:$dst, (OpNode FR32:$src))]>, Sched<[itins.Sched]>;
3153 // For scalar unary operations, fold a load into the operation
3154 // only in OptForSize mode. It eliminates an instruction, but it also
3155 // eliminates a whole-register clobber (the load), so it introduces a
3156 // partial register update condition.
3157 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3158 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3159 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3160 Requires<[UseSSE1, OptForSize]>, Sched<[itins.Sched.Folded]>;
3161 let Constraints = "$src1 = $dst" in {
3162 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
3163 (ins VR128:$src1, VR128:$src2),
3164 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
3165 [], itins.rr>, Sched<[itins.Sched]>;
3166 let mayLoad = 1, hasSideEffects = 0 in
3167 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3168 (ins VR128:$src1, ssmem:$src2),
3169 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
3170 [], itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3174 /// sse1_fp_unop_p - SSE1 unops in packed form.
3175 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3177 let Predicates = [HasAVX] in {
3178 def V#NAME#PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3179 !strconcat("v", OpcodeStr,
3180 "ps\t{$src, $dst|$dst, $src}"),
3181 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))],
3182 itins.rr>, VEX, Sched<[itins.Sched]>;
3183 def V#NAME#PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3184 !strconcat("v", OpcodeStr,
3185 "ps\t{$src, $dst|$dst, $src}"),
3186 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))],
3187 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3188 def V#NAME#PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3189 !strconcat("v", OpcodeStr,
3190 "ps\t{$src, $dst|$dst, $src}"),
3191 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))],
3192 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3193 def V#NAME#PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3194 !strconcat("v", OpcodeStr,
3195 "ps\t{$src, $dst|$dst, $src}"),
3196 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))],
3197 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3200 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3201 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3202 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))], itins.rr>,
3203 Sched<[itins.Sched]>;
3204 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3205 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3206 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))], itins.rm>,
3207 Sched<[itins.Sched.Folded]>;
3210 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
3211 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3212 Intrinsic V4F32Int, Intrinsic V8F32Int,
3214 let Predicates = [HasAVX] in {
3215 def V#NAME#PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3216 !strconcat("v", OpcodeStr,
3217 "ps\t{$src, $dst|$dst, $src}"),
3218 [(set VR128:$dst, (V4F32Int VR128:$src))],
3219 itins.rr>, VEX, Sched<[itins.Sched]>;
3220 def V#NAME#PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3221 !strconcat("v", OpcodeStr,
3222 "ps\t{$src, $dst|$dst, $src}"),
3223 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))],
3224 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3225 def V#NAME#PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3226 !strconcat("v", OpcodeStr,
3227 "ps\t{$src, $dst|$dst, $src}"),
3228 [(set VR256:$dst, (V8F32Int VR256:$src))],
3229 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3230 def V#NAME#PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst),
3232 !strconcat("v", OpcodeStr,
3233 "ps\t{$src, $dst|$dst, $src}"),
3234 [(set VR256:$dst, (V8F32Int (memopv8f32 addr:$src)))],
3235 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3238 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3239 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3240 [(set VR128:$dst, (V4F32Int VR128:$src))],
3241 itins.rr>, Sched<[itins.Sched]>;
3242 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3243 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3244 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))],
3245 itins.rm>, Sched<[itins.Sched.Folded]>;
3248 /// sse2_fp_unop_s - SSE2 unops in scalar form.
3249 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
3250 SDNode OpNode, Intrinsic F64Int, OpndItins itins> {
3251 let Predicates = [HasAVX], hasSideEffects = 0 in {
3252 def V#NAME#SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst),
3253 (ins FR64:$src1, FR64:$src2),
3254 !strconcat("v", OpcodeStr,
3255 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3256 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3257 let mayLoad = 1 in {
3258 def V#NAME#SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
3259 (ins FR64:$src1,f64mem:$src2),
3260 !strconcat("v", OpcodeStr,
3261 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3262 []>, VEX_4V, VEX_LIG,
3263 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3264 def V#NAME#SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
3265 (ins VR128:$src1, sdmem:$src2),
3266 !strconcat("v", OpcodeStr,
3267 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3268 []>, VEX_4V, VEX_LIG,
3269 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3273 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
3274 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3275 [(set FR64:$dst, (OpNode FR64:$src))], itins.rr>,
3276 Sched<[itins.Sched]>;
3277 // See the comments in sse1_fp_unop_s for why this is OptForSize.
3278 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
3279 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3280 [(set FR64:$dst, (OpNode (load addr:$src)))], itins.rm>, XD,
3281 Requires<[UseSSE2, OptForSize]>, Sched<[itins.Sched.Folded]>;
3282 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3283 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3284 [(set VR128:$dst, (F64Int VR128:$src))], itins.rr>,
3285 Sched<[itins.Sched]>;
3286 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
3287 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3288 [(set VR128:$dst, (F64Int sse_load_f64:$src))], itins.rm>,
3289 Sched<[itins.Sched.Folded]>;
3292 /// sse2_fp_unop_p - SSE2 unops in vector forms.
3293 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
3294 SDNode OpNode, OpndItins itins> {
3295 let Predicates = [HasAVX] in {
3296 def V#NAME#PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3297 !strconcat("v", OpcodeStr,
3298 "pd\t{$src, $dst|$dst, $src}"),
3299 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))],
3300 itins.rr>, VEX, Sched<[itins.Sched]>;
3301 def V#NAME#PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3302 !strconcat("v", OpcodeStr,
3303 "pd\t{$src, $dst|$dst, $src}"),
3304 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))],
3305 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3306 def V#NAME#PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3307 !strconcat("v", OpcodeStr,
3308 "pd\t{$src, $dst|$dst, $src}"),
3309 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))],
3310 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3311 def V#NAME#PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3312 !strconcat("v", OpcodeStr,
3313 "pd\t{$src, $dst|$dst, $src}"),
3314 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))],
3315 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3318 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3319 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3320 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))], itins.rr>,
3321 Sched<[itins.Sched]>;
3322 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3323 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3324 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))], itins.rm>,
3325 Sched<[itins.Sched.Folded]>;
3329 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss,
3331 sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPS>,
3332 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd,
3334 sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPD>;
3336 // Reciprocal approximations. Note that these typically require refinement
3337 // in order to obtain suitable precision.
3338 defm RSQRT : sse1_fp_unop_rw<0x52, "rsqrt", X86frsqrt, SSE_SQRTSS>,
3339 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_SQRTPS>,
3340 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps,
3341 int_x86_avx_rsqrt_ps_256, SSE_SQRTPS>;
3342 defm RCP : sse1_fp_unop_rw<0x53, "rcp", X86frcp, SSE_RCPS>,
3343 sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPP>,
3344 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps,
3345 int_x86_avx_rcp_ps_256, SSE_RCPP>;
3347 def : Pat<(f32 (fsqrt FR32:$src)),
3348 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3349 def : Pat<(f32 (fsqrt (load addr:$src))),
3350 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3351 Requires<[HasAVX, OptForSize]>;
3352 def : Pat<(f64 (fsqrt FR64:$src)),
3353 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
3354 def : Pat<(f64 (fsqrt (load addr:$src))),
3355 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
3356 Requires<[HasAVX, OptForSize]>;
3358 def : Pat<(f32 (X86frsqrt FR32:$src)),
3359 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3360 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3361 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3362 Requires<[HasAVX, OptForSize]>;
3364 def : Pat<(f32 (X86frcp FR32:$src)),
3365 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3366 def : Pat<(f32 (X86frcp (load addr:$src))),
3367 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3368 Requires<[HasAVX, OptForSize]>;
3370 let Predicates = [HasAVX] in {
3371 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3372 (COPY_TO_REGCLASS (VSQRTSSr (f32 (IMPLICIT_DEF)),
3373 (COPY_TO_REGCLASS VR128:$src, FR32)),
3375 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3376 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3378 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
3379 (COPY_TO_REGCLASS (VSQRTSDr (f64 (IMPLICIT_DEF)),
3380 (COPY_TO_REGCLASS VR128:$src, FR64)),
3382 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3383 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3385 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3386 (COPY_TO_REGCLASS (VRSQRTSSr (f32 (IMPLICIT_DEF)),
3387 (COPY_TO_REGCLASS VR128:$src, FR32)),
3389 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
3390 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3392 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3393 (COPY_TO_REGCLASS (VRCPSSr (f32 (IMPLICIT_DEF)),
3394 (COPY_TO_REGCLASS VR128:$src, FR32)),
3396 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
3397 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3400 // Reciprocal approximations. Note that these typically require refinement
3401 // in order to obtain suitable precision.
3402 let Predicates = [UseSSE1] in {
3403 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3404 (RSQRTSSr_Int VR128:$src, VR128:$src)>;
3405 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3406 (RCPSSr_Int VR128:$src, VR128:$src)>;
3409 // There is no f64 version of the reciprocal approximation instructions.
3411 //===----------------------------------------------------------------------===//
3412 // SSE 1 & 2 - Non-temporal stores
3413 //===----------------------------------------------------------------------===//
3415 let AddedComplexity = 400 in { // Prefer non-temporal versions
3416 let SchedRW = [WriteStore] in {
3417 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3418 (ins f128mem:$dst, VR128:$src),
3419 "movntps\t{$src, $dst|$dst, $src}",
3420 [(alignednontemporalstore (v4f32 VR128:$src),
3422 IIC_SSE_MOVNT>, VEX;
3423 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3424 (ins f128mem:$dst, VR128:$src),
3425 "movntpd\t{$src, $dst|$dst, $src}",
3426 [(alignednontemporalstore (v2f64 VR128:$src),
3428 IIC_SSE_MOVNT>, VEX;
3430 let ExeDomain = SSEPackedInt in
3431 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3432 (ins f128mem:$dst, VR128:$src),
3433 "movntdq\t{$src, $dst|$dst, $src}",
3434 [(alignednontemporalstore (v2i64 VR128:$src),
3436 IIC_SSE_MOVNT>, VEX;
3438 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3439 (ins f256mem:$dst, VR256:$src),
3440 "movntps\t{$src, $dst|$dst, $src}",
3441 [(alignednontemporalstore (v8f32 VR256:$src),
3443 IIC_SSE_MOVNT>, VEX, VEX_L;
3444 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3445 (ins f256mem:$dst, VR256:$src),
3446 "movntpd\t{$src, $dst|$dst, $src}",
3447 [(alignednontemporalstore (v4f64 VR256:$src),
3449 IIC_SSE_MOVNT>, VEX, VEX_L;
3450 let ExeDomain = SSEPackedInt in
3451 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3452 (ins f256mem:$dst, VR256:$src),
3453 "movntdq\t{$src, $dst|$dst, $src}",
3454 [(alignednontemporalstore (v4i64 VR256:$src),
3456 IIC_SSE_MOVNT>, VEX, VEX_L;
3458 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3459 "movntps\t{$src, $dst|$dst, $src}",
3460 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)],
3462 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3463 "movntpd\t{$src, $dst|$dst, $src}",
3464 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)],
3467 let ExeDomain = SSEPackedInt in
3468 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3469 "movntdq\t{$src, $dst|$dst, $src}",
3470 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)],
3473 // There is no AVX form for instructions below this point
3474 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3475 "movnti{l}\t{$src, $dst|$dst, $src}",
3476 [(nontemporalstore (i32 GR32:$src), addr:$dst)],
3478 TB, Requires<[HasSSE2]>;
3479 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3480 "movnti{q}\t{$src, $dst|$dst, $src}",
3481 [(nontemporalstore (i64 GR64:$src), addr:$dst)],
3483 TB, Requires<[HasSSE2]>;
3484 } // SchedRW = [WriteStore]
3486 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3487 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
3489 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3490 (MOVNTDQmr addr:$dst, VR128:$src)>, Requires<[UseSSE2]>;
3491 } // AddedComplexity
3493 //===----------------------------------------------------------------------===//
3494 // SSE 1 & 2 - Prefetch and memory fence
3495 //===----------------------------------------------------------------------===//
3497 // Prefetch intrinsic.
3498 let Predicates = [HasSSE1], SchedRW = [WriteLoad] in {
3499 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3500 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))],
3501 IIC_SSE_PREFETCH>, TB;
3502 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3503 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))],
3504 IIC_SSE_PREFETCH>, TB;
3505 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3506 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))],
3507 IIC_SSE_PREFETCH>, TB;
3508 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3509 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))],
3510 IIC_SSE_PREFETCH>, TB;
3513 // FIXME: How should these memory instructions be modeled?
3514 let SchedRW = [WriteLoad] in {
3516 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3517 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
3518 IIC_SSE_PREFETCH>, TB, Requires<[HasSSE2]>;
3520 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3521 // was introduced with SSE2, it's backward compatible.
3522 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", [], IIC_SSE_PAUSE>, REP;
3524 // Load, store, and memory fence
3525 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3526 "sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
3527 TB, Requires<[HasSSE1]>;
3528 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3529 "lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
3530 TB, Requires<[HasSSE2]>;
3531 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3532 "mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>,
3533 TB, Requires<[HasSSE2]>;
3536 def : Pat<(X86SFence), (SFENCE)>;
3537 def : Pat<(X86LFence), (LFENCE)>;
3538 def : Pat<(X86MFence), (MFENCE)>;
3540 //===----------------------------------------------------------------------===//
3541 // SSE 1 & 2 - Load/Store XCSR register
3542 //===----------------------------------------------------------------------===//
3544 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3545 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3546 IIC_SSE_LDMXCSR>, VEX, Sched<[WriteLoad]>;
3547 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3548 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3549 IIC_SSE_STMXCSR>, VEX, Sched<[WriteStore]>;
3551 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3552 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3553 IIC_SSE_LDMXCSR>, Sched<[WriteLoad]>;
3554 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3555 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3556 IIC_SSE_STMXCSR>, Sched<[WriteStore]>;
3558 //===---------------------------------------------------------------------===//
3559 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3560 //===---------------------------------------------------------------------===//
3562 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3564 let neverHasSideEffects = 1, SchedRW = [WriteMove] in {
3565 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3566 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3568 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3569 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3571 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3572 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3574 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3575 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3580 let isCodeGenOnly = 1, hasSideEffects = 0, SchedRW = [WriteMove] in {
3581 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3582 "movdqa\t{$src, $dst|$dst, $src}", [],
3585 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3586 "movdqa\t{$src, $dst|$dst, $src}", [],
3587 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
3588 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3589 "movdqu\t{$src, $dst|$dst, $src}", [],
3592 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3593 "movdqu\t{$src, $dst|$dst, $src}", [],
3594 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
3597 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3598 neverHasSideEffects = 1, SchedRW = [WriteLoad] in {
3599 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3600 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3602 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3603 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3605 let Predicates = [HasAVX] in {
3606 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3607 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3609 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3610 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3615 let mayStore = 1, neverHasSideEffects = 1, SchedRW = [WriteStore] in {
3616 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3617 (ins i128mem:$dst, VR128:$src),
3618 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3620 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3621 (ins i256mem:$dst, VR256:$src),
3622 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3624 let Predicates = [HasAVX] in {
3625 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3626 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3628 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3629 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3634 let SchedRW = [WriteMove] in {
3635 let neverHasSideEffects = 1 in
3636 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3637 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>;
3639 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3640 "movdqu\t{$src, $dst|$dst, $src}",
3641 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3644 let isCodeGenOnly = 1, hasSideEffects = 0 in {
3645 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3646 "movdqa\t{$src, $dst|$dst, $src}", [],
3649 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3650 "movdqu\t{$src, $dst|$dst, $src}",
3651 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3655 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3656 neverHasSideEffects = 1, SchedRW = [WriteLoad] in {
3657 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3658 "movdqa\t{$src, $dst|$dst, $src}",
3659 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/],
3661 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3662 "movdqu\t{$src, $dst|$dst, $src}",
3663 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/],
3665 XS, Requires<[UseSSE2]>;
3668 let mayStore = 1, SchedRW = [WriteStore] in {
3669 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3670 "movdqa\t{$src, $dst|$dst, $src}",
3671 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/],
3673 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3674 "movdqu\t{$src, $dst|$dst, $src}",
3675 [/*(store (v2i64 VR128:$src), addr:$dst)*/],
3677 XS, Requires<[UseSSE2]>;
3680 } // ExeDomain = SSEPackedInt
3682 let Predicates = [HasAVX] in {
3683 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3684 (VMOVDQUmr addr:$dst, VR128:$src)>;
3685 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3686 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3688 let Predicates = [UseSSE2] in
3689 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3690 (MOVDQUmr addr:$dst, VR128:$src)>;
3692 //===---------------------------------------------------------------------===//
3693 // SSE2 - Packed Integer Arithmetic Instructions
3694 //===---------------------------------------------------------------------===//
3696 let Sched = WriteVecIMul in
3697 def SSE_PMADD : OpndItins<
3698 IIC_SSE_PMADD, IIC_SSE_PMADD
3701 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3703 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3704 RegisterClass RC, PatFrag memop_frag,
3705 X86MemOperand x86memop,
3707 bit IsCommutable = 0,
3709 let isCommutable = IsCommutable in
3710 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3711 (ins RC:$src1, RC:$src2),
3713 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3714 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3715 [(set RC:$dst, (IntId RC:$src1, RC:$src2))], itins.rr>,
3716 Sched<[itins.Sched]>;
3717 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3718 (ins RC:$src1, x86memop:$src2),
3720 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3721 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3722 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))],
3723 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3726 multiclass PDI_binop_all_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
3727 Intrinsic IntId256, OpndItins itins,
3728 bit IsCommutable = 0> {
3729 let Predicates = [HasAVX] in
3730 defm V#NAME : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId128,
3731 VR128, memopv2i64, i128mem, itins,
3732 IsCommutable, 0>, VEX_4V;
3734 let Constraints = "$src1 = $dst" in
3735 defm NAME : PDI_binop_rm_int<opc, OpcodeStr, IntId128, VR128, memopv2i64,
3736 i128mem, itins, IsCommutable, 1>;
3738 let Predicates = [HasAVX2] in
3739 defm V#NAME#Y : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId256,
3740 VR256, memopv4i64, i256mem, itins,
3741 IsCommutable, 0>, VEX_4V, VEX_L;
3744 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
3745 string OpcodeStr, SDNode OpNode,
3746 SDNode OpNode2, RegisterClass RC,
3747 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
3748 ShiftOpndItins itins,
3750 // src2 is always 128-bit
3751 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3752 (ins RC:$src1, VR128:$src2),
3754 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3755 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3756 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
3757 itins.rr>, Sched<[WriteVecShift]>;
3758 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3759 (ins RC:$src1, i128mem:$src2),
3761 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3762 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3763 [(set RC:$dst, (DstVT (OpNode RC:$src1,
3764 (bc_frag (memopv2i64 addr:$src2)))))], itins.rm>,
3765 Sched<[WriteVecShiftLd, ReadAfterLd]>;
3766 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
3767 (ins RC:$src1, i32i8imm:$src2),
3769 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3770 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3771 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i32 imm:$src2))))], itins.ri>,
3772 Sched<[WriteVecShift]>;
3775 /// PDI_binop_rm2 - Simple SSE2 binary operator with different src and dst types
3776 multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
3777 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
3778 PatFrag memop_frag, X86MemOperand x86memop,
3780 bit IsCommutable = 0, bit Is2Addr = 1> {
3781 let isCommutable = IsCommutable in
3782 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3783 (ins RC:$src1, RC:$src2),
3785 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3786 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3787 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
3788 Sched<[itins.Sched]>;
3789 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3790 (ins RC:$src1, x86memop:$src2),
3792 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3793 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3794 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
3795 (bitconvert (memop_frag addr:$src2)))))]>,
3796 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3798 } // ExeDomain = SSEPackedInt
3800 defm PADDB : PDI_binop_all<0xFC, "paddb", add, v16i8, v32i8,
3801 SSE_INTALU_ITINS_P, 1>;
3802 defm PADDW : PDI_binop_all<0xFD, "paddw", add, v8i16, v16i16,
3803 SSE_INTALU_ITINS_P, 1>;
3804 defm PADDD : PDI_binop_all<0xFE, "paddd", add, v4i32, v8i32,
3805 SSE_INTALU_ITINS_P, 1>;
3806 defm PADDQ : PDI_binop_all<0xD4, "paddq", add, v2i64, v4i64,
3807 SSE_INTALUQ_ITINS_P, 1>;
3808 defm PMULLW : PDI_binop_all<0xD5, "pmullw", mul, v8i16, v16i16,
3809 SSE_INTMUL_ITINS_P, 1>;
3810 defm PSUBB : PDI_binop_all<0xF8, "psubb", sub, v16i8, v32i8,
3811 SSE_INTALU_ITINS_P, 0>;
3812 defm PSUBW : PDI_binop_all<0xF9, "psubw", sub, v8i16, v16i16,
3813 SSE_INTALU_ITINS_P, 0>;
3814 defm PSUBD : PDI_binop_all<0xFA, "psubd", sub, v4i32, v8i32,
3815 SSE_INTALU_ITINS_P, 0>;
3816 defm PSUBQ : PDI_binop_all<0xFB, "psubq", sub, v2i64, v4i64,
3817 SSE_INTALUQ_ITINS_P, 0>;
3818 defm PSUBUSB : PDI_binop_all<0xD8, "psubusb", X86subus, v16i8, v32i8,
3819 SSE_INTALU_ITINS_P, 0>;
3820 defm PSUBUSW : PDI_binop_all<0xD9, "psubusw", X86subus, v8i16, v16i16,
3821 SSE_INTALU_ITINS_P, 0>;
3822 defm PMINUB : PDI_binop_all<0xDA, "pminub", X86umin, v16i8, v32i8,
3823 SSE_INTALU_ITINS_P, 1>;
3824 defm PMINSW : PDI_binop_all<0xEA, "pminsw", X86smin, v8i16, v16i16,
3825 SSE_INTALU_ITINS_P, 1>;
3826 defm PMAXUB : PDI_binop_all<0xDE, "pmaxub", X86umax, v16i8, v32i8,
3827 SSE_INTALU_ITINS_P, 1>;
3828 defm PMAXSW : PDI_binop_all<0xEE, "pmaxsw", X86smax, v8i16, v16i16,
3829 SSE_INTALU_ITINS_P, 1>;
3832 defm PSUBSB : PDI_binop_all_int<0xE8, "psubsb", int_x86_sse2_psubs_b,
3833 int_x86_avx2_psubs_b, SSE_INTALU_ITINS_P, 0>;
3834 defm PSUBSW : PDI_binop_all_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
3835 int_x86_avx2_psubs_w, SSE_INTALU_ITINS_P, 0>;
3836 defm PADDSB : PDI_binop_all_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
3837 int_x86_avx2_padds_b, SSE_INTALU_ITINS_P, 1>;
3838 defm PADDSW : PDI_binop_all_int<0xED, "paddsw" , int_x86_sse2_padds_w,
3839 int_x86_avx2_padds_w, SSE_INTALU_ITINS_P, 1>;
3840 defm PADDUSB : PDI_binop_all_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
3841 int_x86_avx2_paddus_b, SSE_INTALU_ITINS_P, 1>;
3842 defm PADDUSW : PDI_binop_all_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
3843 int_x86_avx2_paddus_w, SSE_INTALU_ITINS_P, 1>;
3844 defm PMULHUW : PDI_binop_all_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w,
3845 int_x86_avx2_pmulhu_w, SSE_INTMUL_ITINS_P, 1>;
3846 defm PMULHW : PDI_binop_all_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w,
3847 int_x86_avx2_pmulh_w, SSE_INTMUL_ITINS_P, 1>;
3848 defm PMADDWD : PDI_binop_all_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
3849 int_x86_avx2_pmadd_wd, SSE_PMADD, 1>;
3850 defm PAVGB : PDI_binop_all_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
3851 int_x86_avx2_pavg_b, SSE_INTALU_ITINS_P, 1>;
3852 defm PAVGW : PDI_binop_all_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
3853 int_x86_avx2_pavg_w, SSE_INTALU_ITINS_P, 1>;
3854 defm PSADBW : PDI_binop_all_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
3855 int_x86_avx2_psad_bw, SSE_INTALU_ITINS_P, 1>;
3857 let Predicates = [HasAVX] in
3858 defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
3859 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
3861 let Predicates = [HasAVX2] in
3862 defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
3863 VR256, memopv4i64, i256mem,
3864 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3865 let Constraints = "$src1 = $dst" in
3866 defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
3867 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1>;
3869 //===---------------------------------------------------------------------===//
3870 // SSE2 - Packed Integer Logical Instructions
3871 //===---------------------------------------------------------------------===//
3873 let Predicates = [HasAVX] in {
3874 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3875 VR128, v8i16, v8i16, bc_v8i16,
3876 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3877 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3878 VR128, v4i32, v4i32, bc_v4i32,
3879 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3880 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3881 VR128, v2i64, v2i64, bc_v2i64,
3882 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3884 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3885 VR128, v8i16, v8i16, bc_v8i16,
3886 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3887 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3888 VR128, v4i32, v4i32, bc_v4i32,
3889 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3890 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3891 VR128, v2i64, v2i64, bc_v2i64,
3892 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3894 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
3895 VR128, v8i16, v8i16, bc_v8i16,
3896 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3897 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
3898 VR128, v4i32, v4i32, bc_v4i32,
3899 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3901 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
3902 // 128-bit logical shifts.
3903 def VPSLLDQri : PDIi8<0x73, MRM7r,
3904 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3905 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3907 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>,
3909 def VPSRLDQri : PDIi8<0x73, MRM3r,
3910 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3911 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3913 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>,
3915 // PSRADQri doesn't exist in SSE[1-3].
3917 } // Predicates = [HasAVX]
3919 let Predicates = [HasAVX2] in {
3920 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3921 VR256, v16i16, v8i16, bc_v8i16,
3922 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3923 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3924 VR256, v8i32, v4i32, bc_v4i32,
3925 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3926 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3927 VR256, v4i64, v2i64, bc_v2i64,
3928 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3930 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3931 VR256, v16i16, v8i16, bc_v8i16,
3932 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3933 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3934 VR256, v8i32, v4i32, bc_v4i32,
3935 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3936 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3937 VR256, v4i64, v2i64, bc_v2i64,
3938 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3940 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
3941 VR256, v16i16, v8i16, bc_v8i16,
3942 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3943 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
3944 VR256, v8i32, v4i32, bc_v4i32,
3945 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3947 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
3948 // 256-bit logical shifts.
3949 def VPSLLDQYri : PDIi8<0x73, MRM7r,
3950 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3951 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3953 (int_x86_avx2_psll_dq_bs VR256:$src1, imm:$src2))]>,
3955 def VPSRLDQYri : PDIi8<0x73, MRM3r,
3956 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3957 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3959 (int_x86_avx2_psrl_dq_bs VR256:$src1, imm:$src2))]>,
3961 // PSRADQYri doesn't exist in SSE[1-3].
3963 } // Predicates = [HasAVX2]
3965 let Constraints = "$src1 = $dst" in {
3966 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
3967 VR128, v8i16, v8i16, bc_v8i16,
3968 SSE_INTSHIFT_ITINS_P>;
3969 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
3970 VR128, v4i32, v4i32, bc_v4i32,
3971 SSE_INTSHIFT_ITINS_P>;
3972 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
3973 VR128, v2i64, v2i64, bc_v2i64,
3974 SSE_INTSHIFT_ITINS_P>;
3976 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
3977 VR128, v8i16, v8i16, bc_v8i16,
3978 SSE_INTSHIFT_ITINS_P>;
3979 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
3980 VR128, v4i32, v4i32, bc_v4i32,
3981 SSE_INTSHIFT_ITINS_P>;
3982 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
3983 VR128, v2i64, v2i64, bc_v2i64,
3984 SSE_INTSHIFT_ITINS_P>;
3986 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
3987 VR128, v8i16, v8i16, bc_v8i16,
3988 SSE_INTSHIFT_ITINS_P>;
3989 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
3990 VR128, v4i32, v4i32, bc_v4i32,
3991 SSE_INTSHIFT_ITINS_P>;
3993 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
3994 // 128-bit logical shifts.
3995 def PSLLDQri : PDIi8<0x73, MRM7r,
3996 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3997 "pslldq\t{$src2, $dst|$dst, $src2}",
3999 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>;
4000 def PSRLDQri : PDIi8<0x73, MRM3r,
4001 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4002 "psrldq\t{$src2, $dst|$dst, $src2}",
4004 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>;
4005 // PSRADQri doesn't exist in SSE[1-3].
4007 } // Constraints = "$src1 = $dst"
4009 let Predicates = [HasAVX] in {
4010 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4011 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4012 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4013 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4014 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4015 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4017 // Shift up / down and insert zero's.
4018 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4019 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4020 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4021 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4024 let Predicates = [HasAVX2] in {
4025 def : Pat<(int_x86_avx2_psll_dq VR256:$src1, imm:$src2),
4026 (VPSLLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4027 def : Pat<(int_x86_avx2_psrl_dq VR256:$src1, imm:$src2),
4028 (VPSRLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4031 let Predicates = [UseSSE2] in {
4032 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4033 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4034 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4035 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4036 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4037 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4039 // Shift up / down and insert zero's.
4040 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4041 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4042 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4043 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4046 //===---------------------------------------------------------------------===//
4047 // SSE2 - Packed Integer Comparison Instructions
4048 //===---------------------------------------------------------------------===//
4050 defm PCMPEQB : PDI_binop_all<0x74, "pcmpeqb", X86pcmpeq, v16i8, v32i8,
4051 SSE_INTALU_ITINS_P, 1>;
4052 defm PCMPEQW : PDI_binop_all<0x75, "pcmpeqw", X86pcmpeq, v8i16, v16i16,
4053 SSE_INTALU_ITINS_P, 1>;
4054 defm PCMPEQD : PDI_binop_all<0x76, "pcmpeqd", X86pcmpeq, v4i32, v8i32,
4055 SSE_INTALU_ITINS_P, 1>;
4056 defm PCMPGTB : PDI_binop_all<0x64, "pcmpgtb", X86pcmpgt, v16i8, v32i8,
4057 SSE_INTALU_ITINS_P, 0>;
4058 defm PCMPGTW : PDI_binop_all<0x65, "pcmpgtw", X86pcmpgt, v8i16, v16i16,
4059 SSE_INTALU_ITINS_P, 0>;
4060 defm PCMPGTD : PDI_binop_all<0x66, "pcmpgtd", X86pcmpgt, v4i32, v8i32,
4061 SSE_INTALU_ITINS_P, 0>;
4063 //===---------------------------------------------------------------------===//
4064 // SSE2 - Packed Integer Pack Instructions
4065 //===---------------------------------------------------------------------===//
4067 defm PACKSSWB : PDI_binop_all_int<0x63, "packsswb", int_x86_sse2_packsswb_128,
4068 int_x86_avx2_packsswb, SSE_INTALU_ITINS_P, 0>;
4069 defm PACKSSDW : PDI_binop_all_int<0x6B, "packssdw", int_x86_sse2_packssdw_128,
4070 int_x86_avx2_packssdw, SSE_INTALU_ITINS_P, 0>;
4071 defm PACKUSWB : PDI_binop_all_int<0x67, "packuswb", int_x86_sse2_packuswb_128,
4072 int_x86_avx2_packuswb, SSE_INTALU_ITINS_P, 0>;
4074 //===---------------------------------------------------------------------===//
4075 // SSE2 - Packed Integer Shuffle Instructions
4076 //===---------------------------------------------------------------------===//
4078 let ExeDomain = SSEPackedInt in {
4079 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt128, ValueType vt256,
4081 let Predicates = [HasAVX] in {
4082 def V#NAME#ri : Ii8<0x70, MRMSrcReg, (outs VR128:$dst),
4083 (ins VR128:$src1, i8imm:$src2),
4084 !strconcat("v", OpcodeStr,
4085 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4087 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4088 IIC_SSE_PSHUF>, VEX, Sched<[WriteShuffle]>;
4089 def V#NAME#mi : Ii8<0x70, MRMSrcMem, (outs VR128:$dst),
4090 (ins i128mem:$src1, i8imm:$src2),
4091 !strconcat("v", OpcodeStr,
4092 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4094 (vt128 (OpNode (bitconvert (memopv2i64 addr:$src1)),
4095 (i8 imm:$src2))))], IIC_SSE_PSHUF>, VEX,
4096 Sched<[WriteShuffleLd]>;
4099 let Predicates = [HasAVX2] in {
4100 def V#NAME#Yri : Ii8<0x70, MRMSrcReg, (outs VR256:$dst),
4101 (ins VR256:$src1, i8imm:$src2),
4102 !strconcat("v", OpcodeStr,
4103 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4105 (vt256 (OpNode VR256:$src1, (i8 imm:$src2))))],
4106 IIC_SSE_PSHUF>, VEX, VEX_L, Sched<[WriteShuffle]>;
4107 def V#NAME#Ymi : Ii8<0x70, MRMSrcMem, (outs VR256:$dst),
4108 (ins i256mem:$src1, i8imm:$src2),
4109 !strconcat("v", OpcodeStr,
4110 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4112 (vt256 (OpNode (bitconvert (memopv4i64 addr:$src1)),
4113 (i8 imm:$src2))))], IIC_SSE_PSHUF>, VEX, VEX_L,
4114 Sched<[WriteShuffleLd]>;
4117 let Predicates = [UseSSE2] in {
4118 def ri : Ii8<0x70, MRMSrcReg,
4119 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
4120 !strconcat(OpcodeStr,
4121 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4123 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4124 IIC_SSE_PSHUF>, Sched<[WriteShuffle]>;
4125 def mi : Ii8<0x70, MRMSrcMem,
4126 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
4127 !strconcat(OpcodeStr,
4128 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4130 (vt128 (OpNode (bitconvert (memopv2i64 addr:$src1)),
4131 (i8 imm:$src2))))], IIC_SSE_PSHUF>,
4132 Sched<[WriteShuffleLd]>;
4135 } // ExeDomain = SSEPackedInt
4137 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, v8i32, X86PShufd>, TB, OpSize;
4138 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, v16i16, X86PShufhw>, XS;
4139 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, v16i16, X86PShuflw>, XD;
4141 let Predicates = [HasAVX] in {
4142 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4143 (VPSHUFDmi addr:$src1, imm:$imm)>;
4144 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4145 (VPSHUFDri VR128:$src1, imm:$imm)>;
4148 let Predicates = [UseSSE2] in {
4149 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4150 (PSHUFDmi addr:$src1, imm:$imm)>;
4151 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4152 (PSHUFDri VR128:$src1, imm:$imm)>;
4155 //===---------------------------------------------------------------------===//
4156 // SSE2 - Packed Integer Unpack Instructions
4157 //===---------------------------------------------------------------------===//
4159 let ExeDomain = SSEPackedInt in {
4160 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
4161 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
4162 def rr : PDI<opc, MRMSrcReg,
4163 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4165 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4166 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4167 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))],
4168 IIC_SSE_UNPCK>, Sched<[WriteShuffle]>;
4169 def rm : PDI<opc, MRMSrcMem,
4170 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4172 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4173 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4174 [(set VR128:$dst, (OpNode VR128:$src1,
4175 (bc_frag (memopv2i64
4178 Sched<[WriteShuffleLd, ReadAfterLd]>;
4181 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
4182 SDNode OpNode, PatFrag bc_frag> {
4183 def Yrr : PDI<opc, MRMSrcReg,
4184 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4185 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4186 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>,
4187 Sched<[WriteShuffle]>;
4188 def Yrm : PDI<opc, MRMSrcMem,
4189 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4190 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4191 [(set VR256:$dst, (OpNode VR256:$src1,
4192 (bc_frag (memopv4i64 addr:$src2))))]>,
4193 Sched<[WriteShuffleLd, ReadAfterLd]>;
4196 let Predicates = [HasAVX] in {
4197 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
4198 bc_v16i8, 0>, VEX_4V;
4199 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
4200 bc_v8i16, 0>, VEX_4V;
4201 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
4202 bc_v4i32, 0>, VEX_4V;
4203 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
4204 bc_v2i64, 0>, VEX_4V;
4206 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
4207 bc_v16i8, 0>, VEX_4V;
4208 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
4209 bc_v8i16, 0>, VEX_4V;
4210 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
4211 bc_v4i32, 0>, VEX_4V;
4212 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
4213 bc_v2i64, 0>, VEX_4V;
4216 let Predicates = [HasAVX2] in {
4217 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
4218 bc_v32i8>, VEX_4V, VEX_L;
4219 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
4220 bc_v16i16>, VEX_4V, VEX_L;
4221 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
4222 bc_v8i32>, VEX_4V, VEX_L;
4223 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
4224 bc_v4i64>, VEX_4V, VEX_L;
4226 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
4227 bc_v32i8>, VEX_4V, VEX_L;
4228 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
4229 bc_v16i16>, VEX_4V, VEX_L;
4230 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
4231 bc_v8i32>, VEX_4V, VEX_L;
4232 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
4233 bc_v4i64>, VEX_4V, VEX_L;
4236 let Constraints = "$src1 = $dst" in {
4237 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
4239 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
4241 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
4243 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
4246 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
4248 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
4250 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4252 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4255 } // ExeDomain = SSEPackedInt
4257 //===---------------------------------------------------------------------===//
4258 // SSE2 - Packed Integer Extract and Insert
4259 //===---------------------------------------------------------------------===//
4261 let ExeDomain = SSEPackedInt in {
4262 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4263 def rri : Ii8<0xC4, MRMSrcReg,
4264 (outs VR128:$dst), (ins VR128:$src1,
4265 GR32:$src2, i32i8imm:$src3),
4267 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4268 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4270 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))], IIC_SSE_PINSRW>,
4271 Sched<[WriteShuffle]>;
4272 def rmi : Ii8<0xC4, MRMSrcMem,
4273 (outs VR128:$dst), (ins VR128:$src1,
4274 i16mem:$src2, i32i8imm:$src3),
4276 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4277 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4279 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4280 imm:$src3))], IIC_SSE_PINSRW>,
4281 Sched<[WriteShuffleLd, ReadAfterLd]>;
4285 let Predicates = [HasAVX] in
4286 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4287 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4288 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4289 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4290 imm:$src2))]>, TB, OpSize, VEX,
4291 Sched<[WriteShuffle]>;
4292 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4293 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4294 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4295 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4296 imm:$src2))], IIC_SSE_PEXTRW>,
4297 Sched<[WriteShuffleLd, ReadAfterLd]>;
4300 let Predicates = [HasAVX] in {
4301 defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V;
4302 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
4303 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4304 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
4305 []>, TB, OpSize, VEX_4V, Sched<[WriteShuffle]>;
4308 let Constraints = "$src1 = $dst" in
4309 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[UseSSE2]>;
4311 } // ExeDomain = SSEPackedInt
4313 //===---------------------------------------------------------------------===//
4314 // SSE2 - Packed Mask Creation
4315 //===---------------------------------------------------------------------===//
4317 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecLogic] in {
4319 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4320 "pmovmskb\t{$src, $dst|$dst, $src}",
4321 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4322 IIC_SSE_MOVMSK>, VEX;
4323 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
4324 "pmovmskb\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK>, VEX;
4326 let Predicates = [HasAVX2] in {
4327 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR256:$src),
4328 "pmovmskb\t{$src, $dst|$dst, $src}",
4329 [(set GR32:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>, VEX, VEX_L;
4330 def VPMOVMSKBYr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
4331 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
4334 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4335 "pmovmskb\t{$src, $dst|$dst, $src}",
4336 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4339 } // ExeDomain = SSEPackedInt
4341 //===---------------------------------------------------------------------===//
4342 // SSE2 - Conditional Store
4343 //===---------------------------------------------------------------------===//
4345 let ExeDomain = SSEPackedInt, SchedRW = [WriteStore] in {
4348 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4349 (ins VR128:$src, VR128:$mask),
4350 "maskmovdqu\t{$mask, $src|$src, $mask}",
4351 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4352 IIC_SSE_MASKMOV>, VEX;
4354 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4355 (ins VR128:$src, VR128:$mask),
4356 "maskmovdqu\t{$mask, $src|$src, $mask}",
4357 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4358 IIC_SSE_MASKMOV>, VEX;
4361 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4362 "maskmovdqu\t{$mask, $src|$src, $mask}",
4363 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4366 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4367 "maskmovdqu\t{$mask, $src|$src, $mask}",
4368 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4371 } // ExeDomain = SSEPackedInt
4373 //===---------------------------------------------------------------------===//
4374 // SSE2 - Move Doubleword
4375 //===---------------------------------------------------------------------===//
4377 //===---------------------------------------------------------------------===//
4378 // Move Int Doubleword to Packed Double Int
4380 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4381 "movd\t{$src, $dst|$dst, $src}",
4383 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4384 VEX, Sched<[WriteMove]>;
4385 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4386 "movd\t{$src, $dst|$dst, $src}",
4388 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4390 VEX, Sched<[WriteLoad]>;
4391 def VMOV64toPQIrr : VRPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4392 "mov{d|q}\t{$src, $dst|$dst, $src}",
4394 (v2i64 (scalar_to_vector GR64:$src)))],
4395 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4396 def VMOV64toSDrr : VRPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4397 "mov{d|q}\t{$src, $dst|$dst, $src}",
4398 [(set FR64:$dst, (bitconvert GR64:$src))],
4399 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4401 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4402 "movd\t{$src, $dst|$dst, $src}",
4404 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4406 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4407 "movd\t{$src, $dst|$dst, $src}",
4409 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4410 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4411 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4412 "mov{d|q}\t{$src, $dst|$dst, $src}",
4414 (v2i64 (scalar_to_vector GR64:$src)))],
4415 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4416 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4417 "mov{d|q}\t{$src, $dst|$dst, $src}",
4418 [(set FR64:$dst, (bitconvert GR64:$src))],
4419 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4421 //===---------------------------------------------------------------------===//
4422 // Move Int Doubleword to Single Scalar
4424 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4425 "movd\t{$src, $dst|$dst, $src}",
4426 [(set FR32:$dst, (bitconvert GR32:$src))],
4427 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4429 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4430 "movd\t{$src, $dst|$dst, $src}",
4431 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4433 VEX, Sched<[WriteLoad]>;
4434 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4435 "movd\t{$src, $dst|$dst, $src}",
4436 [(set FR32:$dst, (bitconvert GR32:$src))],
4437 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4439 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4440 "movd\t{$src, $dst|$dst, $src}",
4441 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4442 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4444 //===---------------------------------------------------------------------===//
4445 // Move Packed Doubleword Int to Packed Double Int
4447 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4448 "movd\t{$src, $dst|$dst, $src}",
4449 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4450 (iPTR 0)))], IIC_SSE_MOVD_ToGP>, VEX,
4452 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
4453 (ins i32mem:$dst, VR128:$src),
4454 "movd\t{$src, $dst|$dst, $src}",
4455 [(store (i32 (vector_extract (v4i32 VR128:$src),
4456 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
4457 VEX, Sched<[WriteLoad]>;
4458 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4459 "movd\t{$src, $dst|$dst, $src}",
4460 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4461 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
4463 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4464 "movd\t{$src, $dst|$dst, $src}",
4465 [(store (i32 (vector_extract (v4i32 VR128:$src),
4466 (iPTR 0))), addr:$dst)],
4467 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4469 //===---------------------------------------------------------------------===//
4470 // Move Packed Doubleword Int first element to Doubleword Int
4472 let SchedRW = [WriteMove] in {
4473 def VMOVPQIto64rr : VRPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4474 "mov{d|q}\t{$src, $dst|$dst, $src}",
4475 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4480 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4481 "mov{d|q}\t{$src, $dst|$dst, $src}",
4482 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4487 //===---------------------------------------------------------------------===//
4488 // Bitcast FR64 <-> GR64
4490 let Predicates = [HasAVX] in
4491 def VMOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4492 "vmovq\t{$src, $dst|$dst, $src}",
4493 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4494 VEX, Sched<[WriteLoad]>;
4495 def VMOVSDto64rr : VRPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4496 "mov{d|q}\t{$src, $dst|$dst, $src}",
4497 [(set GR64:$dst, (bitconvert FR64:$src))],
4498 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4499 def VMOVSDto64mr : VRPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4500 "movq\t{$src, $dst|$dst, $src}",
4501 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4502 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4504 def MOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4505 "movq\t{$src, $dst|$dst, $src}",
4506 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))],
4507 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4508 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4509 "mov{d|q}\t{$src, $dst|$dst, $src}",
4510 [(set GR64:$dst, (bitconvert FR64:$src))],
4511 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
4512 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4513 "movq\t{$src, $dst|$dst, $src}",
4514 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4515 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4517 //===---------------------------------------------------------------------===//
4518 // Move Scalar Single to Double Int
4520 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4521 "movd\t{$src, $dst|$dst, $src}",
4522 [(set GR32:$dst, (bitconvert FR32:$src))],
4523 IIC_SSE_MOVD_ToGP>, VEX, Sched<[WriteMove]>;
4524 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4525 "movd\t{$src, $dst|$dst, $src}",
4526 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4527 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4528 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4529 "movd\t{$src, $dst|$dst, $src}",
4530 [(set GR32:$dst, (bitconvert FR32:$src))],
4531 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
4532 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4533 "movd\t{$src, $dst|$dst, $src}",
4534 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4535 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4537 //===---------------------------------------------------------------------===//
4538 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4540 let SchedRW = [WriteMove] in {
4541 let AddedComplexity = 15 in {
4542 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4543 "movd\t{$src, $dst|$dst, $src}",
4544 [(set VR128:$dst, (v4i32 (X86vzmovl
4545 (v4i32 (scalar_to_vector GR32:$src)))))],
4546 IIC_SSE_MOVDQ>, VEX;
4547 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4548 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4549 [(set VR128:$dst, (v2i64 (X86vzmovl
4550 (v2i64 (scalar_to_vector GR64:$src)))))],
4554 let AddedComplexity = 15 in {
4555 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4556 "movd\t{$src, $dst|$dst, $src}",
4557 [(set VR128:$dst, (v4i32 (X86vzmovl
4558 (v4i32 (scalar_to_vector GR32:$src)))))],
4560 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4561 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4562 [(set VR128:$dst, (v2i64 (X86vzmovl
4563 (v2i64 (scalar_to_vector GR64:$src)))))],
4568 let AddedComplexity = 20, SchedRW = [WriteLoad] in {
4569 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4570 "movd\t{$src, $dst|$dst, $src}",
4572 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4573 (loadi32 addr:$src))))))],
4574 IIC_SSE_MOVDQ>, VEX;
4575 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4576 "movd\t{$src, $dst|$dst, $src}",
4578 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4579 (loadi32 addr:$src))))))],
4581 } // AddedComplexity, SchedRW
4583 let Predicates = [HasAVX] in {
4584 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
4585 let AddedComplexity = 20 in {
4586 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4587 (VMOVZDI2PDIrm addr:$src)>;
4588 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4589 (VMOVZDI2PDIrm addr:$src)>;
4591 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4592 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4593 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
4594 (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrr GR32:$src), sub_xmm)>;
4595 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4596 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
4597 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
4600 let Predicates = [UseSSE2], AddedComplexity = 20 in {
4601 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4602 (MOVZDI2PDIrm addr:$src)>;
4603 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4604 (MOVZDI2PDIrm addr:$src)>;
4607 // These are the correct encodings of the instructions so that we know how to
4608 // read correct assembly, even though we continue to emit the wrong ones for
4609 // compatibility with Darwin's buggy assembler.
4610 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4611 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4612 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4613 (MOV64toSDrr FR64:$dst, GR64:$src), 0>;
4614 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4615 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4616 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4617 (MOVSDto64rr GR64:$dst, FR64:$src), 0>;
4618 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4619 (VMOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4620 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4621 (MOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4623 //===---------------------------------------------------------------------===//
4624 // SSE2 - Move Quadword
4625 //===---------------------------------------------------------------------===//
4627 //===---------------------------------------------------------------------===//
4628 // Move Quadword Int to Packed Quadword Int
4631 let SchedRW = [WriteLoad] in {
4632 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4633 "vmovq\t{$src, $dst|$dst, $src}",
4635 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4636 VEX, Requires<[HasAVX]>;
4637 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4638 "movq\t{$src, $dst|$dst, $src}",
4640 (v2i64 (scalar_to_vector (loadi64 addr:$src))))],
4642 Requires<[UseSSE2]>; // SSE2 instruction with XS Prefix
4645 //===---------------------------------------------------------------------===//
4646 // Move Packed Quadword Int to Quadword Int
4648 let SchedRW = [WriteStore] in {
4649 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4650 "movq\t{$src, $dst|$dst, $src}",
4651 [(store (i64 (vector_extract (v2i64 VR128:$src),
4652 (iPTR 0))), addr:$dst)],
4653 IIC_SSE_MOVDQ>, VEX;
4654 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4655 "movq\t{$src, $dst|$dst, $src}",
4656 [(store (i64 (vector_extract (v2i64 VR128:$src),
4657 (iPTR 0))), addr:$dst)],
4661 //===---------------------------------------------------------------------===//
4662 // Store / copy lower 64-bits of a XMM register.
4664 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4665 "movq\t{$src, $dst|$dst, $src}",
4666 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX,
4667 Sched<[WriteStore]>;
4668 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4669 "movq\t{$src, $dst|$dst, $src}",
4670 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)],
4671 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4673 let AddedComplexity = 20 in
4674 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4675 "vmovq\t{$src, $dst|$dst, $src}",
4677 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4678 (loadi64 addr:$src))))))],
4680 XS, VEX, Requires<[HasAVX]>, Sched<[WriteLoad]>;
4682 let AddedComplexity = 20 in
4683 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4684 "movq\t{$src, $dst|$dst, $src}",
4686 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4687 (loadi64 addr:$src))))))],
4689 XS, Requires<[UseSSE2]>, Sched<[WriteLoad]>;
4691 let Predicates = [HasAVX], AddedComplexity = 20 in {
4692 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4693 (VMOVZQI2PQIrm addr:$src)>;
4694 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4695 (VMOVZQI2PQIrm addr:$src)>;
4696 def : Pat<(v2i64 (X86vzload addr:$src)),
4697 (VMOVZQI2PQIrm addr:$src)>;
4700 let Predicates = [UseSSE2], AddedComplexity = 20 in {
4701 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4702 (MOVZQI2PQIrm addr:$src)>;
4703 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4704 (MOVZQI2PQIrm addr:$src)>;
4705 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
4708 let Predicates = [HasAVX] in {
4709 def : Pat<(v4i64 (alignedX86vzload addr:$src)),
4710 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
4711 def : Pat<(v4i64 (X86vzload addr:$src)),
4712 (SUBREG_TO_REG (i32 0), (VMOVUPSrm addr:$src), sub_xmm)>;
4715 //===---------------------------------------------------------------------===//
4716 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
4717 // IA32 document. movq xmm1, xmm2 does clear the high bits.
4719 let SchedRW = [WriteVecLogic] in {
4720 let AddedComplexity = 15 in
4721 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4722 "vmovq\t{$src, $dst|$dst, $src}",
4723 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4725 XS, VEX, Requires<[HasAVX]>;
4726 let AddedComplexity = 15 in
4727 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4728 "movq\t{$src, $dst|$dst, $src}",
4729 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4731 XS, Requires<[UseSSE2]>;
4734 let SchedRW = [WriteVecLogicLd] in {
4735 let AddedComplexity = 20 in
4736 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4737 "vmovq\t{$src, $dst|$dst, $src}",
4738 [(set VR128:$dst, (v2i64 (X86vzmovl
4739 (loadv2i64 addr:$src))))],
4741 XS, VEX, Requires<[HasAVX]>;
4742 let AddedComplexity = 20 in {
4743 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4744 "movq\t{$src, $dst|$dst, $src}",
4745 [(set VR128:$dst, (v2i64 (X86vzmovl
4746 (loadv2i64 addr:$src))))],
4748 XS, Requires<[UseSSE2]>;
4752 let AddedComplexity = 20 in {
4753 let Predicates = [HasAVX] in {
4754 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4755 (VMOVZPQILo2PQIrm addr:$src)>;
4756 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4757 (VMOVZPQILo2PQIrr VR128:$src)>;
4759 let Predicates = [UseSSE2] in {
4760 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4761 (MOVZPQILo2PQIrm addr:$src)>;
4762 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4763 (MOVZPQILo2PQIrr VR128:$src)>;
4767 // Instructions to match in the assembler
4768 let SchedRW = [WriteMove] in {
4769 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4770 "movq\t{$src, $dst|$dst, $src}", [],
4771 IIC_SSE_MOVDQ>, VEX, VEX_W;
4772 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4773 "movq\t{$src, $dst|$dst, $src}", [],
4774 IIC_SSE_MOVDQ>, VEX, VEX_W;
4775 // Recognize "movd" with GR64 destination, but encode as a "movq"
4776 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4777 "movd\t{$src, $dst|$dst, $src}", [],
4778 IIC_SSE_MOVDQ>, VEX, VEX_W;
4781 // Instructions for the disassembler
4782 // xr = XMM register
4785 let SchedRW = [WriteMove] in {
4786 let Predicates = [HasAVX] in
4787 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4788 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
4789 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4790 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>, XS;
4793 //===---------------------------------------------------------------------===//
4794 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
4795 //===---------------------------------------------------------------------===//
4796 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
4797 ValueType vt, RegisterClass RC, PatFrag mem_frag,
4798 X86MemOperand x86memop> {
4799 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4800 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4801 [(set RC:$dst, (vt (OpNode RC:$src)))],
4802 IIC_SSE_MOV_LH>, Sched<[WriteShuffle]>;
4803 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4804 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4805 [(set RC:$dst, (OpNode (mem_frag addr:$src)))],
4806 IIC_SSE_MOV_LH>, Sched<[WriteShuffleLd]>;
4809 let Predicates = [HasAVX] in {
4810 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4811 v4f32, VR128, memopv4f32, f128mem>, VEX;
4812 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4813 v4f32, VR128, memopv4f32, f128mem>, VEX;
4814 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4815 v8f32, VR256, memopv8f32, f256mem>, VEX, VEX_L;
4816 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4817 v8f32, VR256, memopv8f32, f256mem>, VEX, VEX_L;
4819 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
4820 memopv4f32, f128mem>;
4821 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
4822 memopv4f32, f128mem>;
4824 let Predicates = [HasAVX] in {
4825 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4826 (VMOVSHDUPrr VR128:$src)>;
4827 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4828 (VMOVSHDUPrm addr:$src)>;
4829 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4830 (VMOVSLDUPrr VR128:$src)>;
4831 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4832 (VMOVSLDUPrm addr:$src)>;
4833 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
4834 (VMOVSHDUPYrr VR256:$src)>;
4835 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (memopv4i64 addr:$src)))),
4836 (VMOVSHDUPYrm addr:$src)>;
4837 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
4838 (VMOVSLDUPYrr VR256:$src)>;
4839 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (memopv4i64 addr:$src)))),
4840 (VMOVSLDUPYrm addr:$src)>;
4843 let Predicates = [UseSSE3] in {
4844 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4845 (MOVSHDUPrr VR128:$src)>;
4846 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4847 (MOVSHDUPrm addr:$src)>;
4848 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4849 (MOVSLDUPrr VR128:$src)>;
4850 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4851 (MOVSLDUPrm addr:$src)>;
4854 //===---------------------------------------------------------------------===//
4855 // SSE3 - Replicate Double FP - MOVDDUP
4856 //===---------------------------------------------------------------------===//
4858 multiclass sse3_replicate_dfp<string OpcodeStr> {
4859 let neverHasSideEffects = 1 in
4860 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4861 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4862 [], IIC_SSE_MOV_LH>, Sched<[WriteShuffle]>;
4863 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
4864 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4867 (scalar_to_vector (loadf64 addr:$src)))))],
4868 IIC_SSE_MOV_LH>, Sched<[WriteShuffleLd]>;
4871 // FIXME: Merge with above classe when there're patterns for the ymm version
4872 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
4873 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
4874 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4875 [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>,
4876 Sched<[WriteShuffle]>;
4877 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
4878 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4881 (scalar_to_vector (loadf64 addr:$src)))))]>,
4882 Sched<[WriteShuffleLd]>;
4885 let Predicates = [HasAVX] in {
4886 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
4887 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX, VEX_L;
4890 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
4892 let Predicates = [HasAVX] in {
4893 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4894 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4895 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4896 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4897 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4898 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4899 def : Pat<(X86Movddup (bc_v2f64
4900 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4901 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4904 def : Pat<(X86Movddup (memopv4f64 addr:$src)),
4905 (VMOVDDUPYrm addr:$src)>;
4906 def : Pat<(X86Movddup (memopv4i64 addr:$src)),
4907 (VMOVDDUPYrm addr:$src)>;
4908 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
4909 (VMOVDDUPYrm addr:$src)>;
4910 def : Pat<(X86Movddup (v4i64 VR256:$src)),
4911 (VMOVDDUPYrr VR256:$src)>;
4914 let Predicates = [UseSSE3] in {
4915 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4916 (MOVDDUPrm addr:$src)>;
4917 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4918 (MOVDDUPrm addr:$src)>;
4919 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4920 (MOVDDUPrm addr:$src)>;
4921 def : Pat<(X86Movddup (bc_v2f64
4922 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4923 (MOVDDUPrm addr:$src)>;
4926 //===---------------------------------------------------------------------===//
4927 // SSE3 - Move Unaligned Integer
4928 //===---------------------------------------------------------------------===//
4930 let SchedRW = [WriteLoad] in {
4931 let Predicates = [HasAVX] in {
4932 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4933 "vlddqu\t{$src, $dst|$dst, $src}",
4934 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
4935 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
4936 "vlddqu\t{$src, $dst|$dst, $src}",
4937 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>,
4940 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4941 "lddqu\t{$src, $dst|$dst, $src}",
4942 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))],
4946 //===---------------------------------------------------------------------===//
4947 // SSE3 - Arithmetic
4948 //===---------------------------------------------------------------------===//
4950 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
4951 X86MemOperand x86memop, OpndItins itins,
4953 def rr : I<0xD0, MRMSrcReg,
4954 (outs RC:$dst), (ins RC:$src1, RC:$src2),
4956 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4957 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4958 [(set RC:$dst, (Int RC:$src1, RC:$src2))], itins.rr>,
4959 Sched<[itins.Sched]>;
4960 def rm : I<0xD0, MRMSrcMem,
4961 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4963 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4964 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4965 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))], itins.rr>,
4966 Sched<[itins.Sched.Folded, ReadAfterLd]>;
4969 let Predicates = [HasAVX] in {
4970 let ExeDomain = SSEPackedSingle in {
4971 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
4972 f128mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V;
4973 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
4974 f256mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V, VEX_L;
4976 let ExeDomain = SSEPackedDouble in {
4977 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
4978 f128mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V;
4979 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
4980 f256mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V, VEX_L;
4983 let Constraints = "$src1 = $dst", Predicates = [UseSSE3] in {
4984 let ExeDomain = SSEPackedSingle in
4985 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
4986 f128mem, SSE_ALU_F32P>, TB, XD;
4987 let ExeDomain = SSEPackedDouble in
4988 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
4989 f128mem, SSE_ALU_F64P>, TB, OpSize;
4992 //===---------------------------------------------------------------------===//
4993 // SSE3 Instructions
4994 //===---------------------------------------------------------------------===//
4997 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
4998 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
4999 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5001 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5002 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5003 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5006 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5008 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5009 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5010 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5011 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5013 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5014 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5015 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5017 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5018 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5019 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5022 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5024 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5025 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5026 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5027 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5030 let Predicates = [HasAVX] in {
5031 let ExeDomain = SSEPackedSingle in {
5032 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
5033 X86fhadd, 0>, VEX_4V;
5034 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
5035 X86fhsub, 0>, VEX_4V;
5036 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
5037 X86fhadd, 0>, VEX_4V, VEX_L;
5038 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
5039 X86fhsub, 0>, VEX_4V, VEX_L;
5041 let ExeDomain = SSEPackedDouble in {
5042 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
5043 X86fhadd, 0>, VEX_4V;
5044 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
5045 X86fhsub, 0>, VEX_4V;
5046 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
5047 X86fhadd, 0>, VEX_4V, VEX_L;
5048 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
5049 X86fhsub, 0>, VEX_4V, VEX_L;
5053 let Constraints = "$src1 = $dst" in {
5054 let ExeDomain = SSEPackedSingle in {
5055 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd>;
5056 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub>;
5058 let ExeDomain = SSEPackedDouble in {
5059 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd>;
5060 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub>;
5064 //===---------------------------------------------------------------------===//
5065 // SSSE3 - Packed Absolute Instructions
5066 //===---------------------------------------------------------------------===//
5069 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5070 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
5071 Intrinsic IntId128> {
5072 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5074 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5075 [(set VR128:$dst, (IntId128 VR128:$src))], IIC_SSE_PABS_RR>,
5076 OpSize, Sched<[WriteVecALU]>;
5078 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5080 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5083 (bitconvert (memopv2i64 addr:$src))))], IIC_SSE_PABS_RM>,
5084 OpSize, Sched<[WriteVecALULd]>;
5087 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5088 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
5089 Intrinsic IntId256> {
5090 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5092 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5093 [(set VR256:$dst, (IntId256 VR256:$src))]>,
5094 OpSize, Sched<[WriteVecALU]>;
5096 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5098 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5101 (bitconvert (memopv4i64 addr:$src))))]>, OpSize,
5102 Sched<[WriteVecALULd]>;
5105 // Helper fragments to match sext vXi1 to vXiY.
5106 def v16i1sextv16i8 : PatLeaf<(v16i8 (X86pcmpgt (bc_v16i8 (v4i32 immAllZerosV)),
5108 def v8i1sextv8i16 : PatLeaf<(v8i16 (X86vsrai VR128:$src, (i32 15)))>;
5109 def v4i1sextv4i32 : PatLeaf<(v4i32 (X86vsrai VR128:$src, (i32 31)))>;
5110 def v32i1sextv32i8 : PatLeaf<(v32i8 (X86pcmpgt (bc_v32i8 (v8i32 immAllZerosV)),
5112 def v16i1sextv16i16: PatLeaf<(v16i16 (X86vsrai VR256:$src, (i32 15)))>;
5113 def v8i1sextv8i32 : PatLeaf<(v8i32 (X86vsrai VR256:$src, (i32 31)))>;
5115 let Predicates = [HasAVX] in {
5116 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb",
5117 int_x86_ssse3_pabs_b_128>, VEX;
5118 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw",
5119 int_x86_ssse3_pabs_w_128>, VEX;
5120 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd",
5121 int_x86_ssse3_pabs_d_128>, VEX;
5124 (bc_v2i64 (v16i1sextv16i8)),
5125 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5126 (VPABSBrr128 VR128:$src)>;
5128 (bc_v2i64 (v8i1sextv8i16)),
5129 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5130 (VPABSWrr128 VR128:$src)>;
5132 (bc_v2i64 (v4i1sextv4i32)),
5133 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5134 (VPABSDrr128 VR128:$src)>;
5137 let Predicates = [HasAVX2] in {
5138 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
5139 int_x86_avx2_pabs_b>, VEX, VEX_L;
5140 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
5141 int_x86_avx2_pabs_w>, VEX, VEX_L;
5142 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
5143 int_x86_avx2_pabs_d>, VEX, VEX_L;
5146 (bc_v4i64 (v32i1sextv32i8)),
5147 (bc_v4i64 (add (v32i8 VR256:$src), (v32i1sextv32i8)))),
5148 (VPABSBrr256 VR256:$src)>;
5150 (bc_v4i64 (v16i1sextv16i16)),
5151 (bc_v4i64 (add (v16i16 VR256:$src), (v16i1sextv16i16)))),
5152 (VPABSWrr256 VR256:$src)>;
5154 (bc_v4i64 (v8i1sextv8i32)),
5155 (bc_v4i64 (add (v8i32 VR256:$src), (v8i1sextv8i32)))),
5156 (VPABSDrr256 VR256:$src)>;
5159 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb",
5160 int_x86_ssse3_pabs_b_128>;
5161 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw",
5162 int_x86_ssse3_pabs_w_128>;
5163 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd",
5164 int_x86_ssse3_pabs_d_128>;
5166 let Predicates = [HasSSSE3] in {
5168 (bc_v2i64 (v16i1sextv16i8)),
5169 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5170 (PABSBrr128 VR128:$src)>;
5172 (bc_v2i64 (v8i1sextv8i16)),
5173 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5174 (PABSWrr128 VR128:$src)>;
5176 (bc_v2i64 (v4i1sextv4i32)),
5177 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5178 (PABSDrr128 VR128:$src)>;
5181 //===---------------------------------------------------------------------===//
5182 // SSSE3 - Packed Binary Operator Instructions
5183 //===---------------------------------------------------------------------===//
5185 let Sched = WriteVecALU in {
5186 def SSE_PHADDSUBD : OpndItins<
5187 IIC_SSE_PHADDSUBD_RR, IIC_SSE_PHADDSUBD_RM
5189 def SSE_PHADDSUBSW : OpndItins<
5190 IIC_SSE_PHADDSUBSW_RR, IIC_SSE_PHADDSUBSW_RM
5192 def SSE_PHADDSUBW : OpndItins<
5193 IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM
5196 let Sched = WriteShuffle in
5197 def SSE_PSHUFB : OpndItins<
5198 IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM
5200 let Sched = WriteVecALU in
5201 def SSE_PSIGN : OpndItins<
5202 IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM
5204 let Sched = WriteVecIMul in
5205 def SSE_PMULHRSW : OpndItins<
5206 IIC_SSE_PMULHRSW, IIC_SSE_PMULHRSW
5209 /// SS3I_binop_rm - Simple SSSE3 bin op
5210 multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5211 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
5212 X86MemOperand x86memop, OpndItins itins,
5214 let isCommutable = 1 in
5215 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
5216 (ins RC:$src1, RC:$src2),
5218 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5219 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5220 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
5221 OpSize, Sched<[itins.Sched]>;
5222 def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
5223 (ins RC:$src1, x86memop:$src2),
5225 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5226 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5228 (OpVT (OpNode RC:$src1,
5229 (bitconvert (memop_frag addr:$src2)))))], itins.rm>, OpSize,
5230 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5233 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
5234 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
5235 Intrinsic IntId128, OpndItins itins,
5237 let isCommutable = 1 in
5238 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5239 (ins VR128:$src1, VR128:$src2),
5241 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5242 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5243 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5244 OpSize, Sched<[itins.Sched]>;
5245 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5246 (ins VR128:$src1, i128mem:$src2),
5248 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5249 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5251 (IntId128 VR128:$src1,
5252 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize,
5253 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5256 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5257 Intrinsic IntId256> {
5258 let isCommutable = 1 in
5259 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5260 (ins VR256:$src1, VR256:$src2),
5261 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5262 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
5264 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5265 (ins VR256:$src1, i256mem:$src2),
5266 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5268 (IntId256 VR256:$src1,
5269 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
5272 let ImmT = NoImm, Predicates = [HasAVX] in {
5273 let isCommutable = 0 in {
5274 defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
5275 memopv2i64, i128mem,
5276 SSE_PHADDSUBW, 0>, VEX_4V;
5277 defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
5278 memopv2i64, i128mem,
5279 SSE_PHADDSUBD, 0>, VEX_4V;
5280 defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
5281 memopv2i64, i128mem,
5282 SSE_PHADDSUBW, 0>, VEX_4V;
5283 defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
5284 memopv2i64, i128mem,
5285 SSE_PHADDSUBD, 0>, VEX_4V;
5286 defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
5287 memopv2i64, i128mem,
5288 SSE_PSIGN, 0>, VEX_4V;
5289 defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
5290 memopv2i64, i128mem,
5291 SSE_PSIGN, 0>, VEX_4V;
5292 defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
5293 memopv2i64, i128mem,
5294 SSE_PSIGN, 0>, VEX_4V;
5295 defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
5296 memopv2i64, i128mem,
5297 SSE_PSHUFB, 0>, VEX_4V;
5298 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
5299 int_x86_ssse3_phadd_sw_128,
5300 SSE_PHADDSUBSW, 0>, VEX_4V;
5301 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
5302 int_x86_ssse3_phsub_sw_128,
5303 SSE_PHADDSUBSW, 0>, VEX_4V;
5304 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
5305 int_x86_ssse3_pmadd_ub_sw_128,
5306 SSE_PMADD, 0>, VEX_4V;
5308 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
5309 int_x86_ssse3_pmul_hr_sw_128,
5310 SSE_PMULHRSW, 0>, VEX_4V;
5313 let ImmT = NoImm, Predicates = [HasAVX2] in {
5314 let isCommutable = 0 in {
5315 defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
5316 memopv4i64, i256mem,
5317 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5318 defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
5319 memopv4i64, i256mem,
5320 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5321 defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
5322 memopv4i64, i256mem,
5323 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5324 defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
5325 memopv4i64, i256mem,
5326 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5327 defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
5328 memopv4i64, i256mem,
5329 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5330 defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
5331 memopv4i64, i256mem,
5332 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5333 defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
5334 memopv4i64, i256mem,
5335 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5336 defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
5337 memopv4i64, i256mem,
5338 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5339 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
5340 int_x86_avx2_phadd_sw>, VEX_4V, VEX_L;
5341 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
5342 int_x86_avx2_phsub_sw>, VEX_4V, VEX_L;
5343 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
5344 int_x86_avx2_pmadd_ub_sw>, VEX_4V, VEX_L;
5346 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
5347 int_x86_avx2_pmul_hr_sw>, VEX_4V, VEX_L;
5350 // None of these have i8 immediate fields.
5351 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5352 let isCommutable = 0 in {
5353 defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
5354 memopv2i64, i128mem, SSE_PHADDSUBW>;
5355 defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
5356 memopv2i64, i128mem, SSE_PHADDSUBD>;
5357 defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
5358 memopv2i64, i128mem, SSE_PHADDSUBW>;
5359 defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
5360 memopv2i64, i128mem, SSE_PHADDSUBD>;
5361 defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
5362 memopv2i64, i128mem, SSE_PSIGN>;
5363 defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
5364 memopv2i64, i128mem, SSE_PSIGN>;
5365 defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
5366 memopv2i64, i128mem, SSE_PSIGN>;
5367 defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
5368 memopv2i64, i128mem, SSE_PSHUFB>;
5369 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5370 int_x86_ssse3_phadd_sw_128,
5372 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5373 int_x86_ssse3_phsub_sw_128,
5375 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5376 int_x86_ssse3_pmadd_ub_sw_128, SSE_PMADD>;
5378 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5379 int_x86_ssse3_pmul_hr_sw_128,
5383 //===---------------------------------------------------------------------===//
5384 // SSSE3 - Packed Align Instruction Patterns
5385 //===---------------------------------------------------------------------===//
5387 multiclass ssse3_palignr<string asm, bit Is2Addr = 1> {
5388 let neverHasSideEffects = 1 in {
5389 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5390 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5392 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5394 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5395 [], IIC_SSE_PALIGNR>, OpSize, Sched<[WriteShuffle]>;
5397 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
5398 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5400 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5402 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5403 [], IIC_SSE_PALIGNR>, OpSize, Sched<[WriteShuffleLd, ReadAfterLd]>;
5407 multiclass ssse3_palignr_y<string asm, bit Is2Addr = 1> {
5408 let neverHasSideEffects = 1 in {
5409 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5410 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5412 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5413 []>, OpSize, Sched<[WriteShuffle]>;
5415 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
5416 (ins VR256:$src1, i256mem:$src2, i8imm:$src3),
5418 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5419 []>, OpSize, Sched<[WriteShuffleLd, ReadAfterLd]>;
5423 let Predicates = [HasAVX] in
5424 defm VPALIGN : ssse3_palignr<"vpalignr", 0>, VEX_4V;
5425 let Predicates = [HasAVX2] in
5426 defm VPALIGN : ssse3_palignr_y<"vpalignr", 0>, VEX_4V, VEX_L;
5427 let Constraints = "$src1 = $dst", Predicates = [UseSSSE3] in
5428 defm PALIGN : ssse3_palignr<"palignr">;
5430 let Predicates = [HasAVX2] in {
5431 def : Pat<(v8i32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5432 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5433 def : Pat<(v8f32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5434 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5435 def : Pat<(v16i16 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5436 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5437 def : Pat<(v32i8 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5438 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5441 let Predicates = [HasAVX] in {
5442 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5443 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5444 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5445 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5446 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5447 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5448 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5449 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5452 let Predicates = [UseSSSE3] in {
5453 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5454 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5455 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5456 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5457 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5458 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5459 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5460 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5463 //===---------------------------------------------------------------------===//
5464 // SSSE3 - Thread synchronization
5465 //===---------------------------------------------------------------------===//
5467 let SchedRW = [WriteSystem] in {
5468 let usesCustomInserter = 1 in {
5469 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
5470 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
5471 Requires<[HasSSE3]>;
5474 let Uses = [EAX, ECX, EDX] in
5475 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", [], IIC_SSE_MONITOR>,
5476 TB, Requires<[HasSSE3]>;
5477 let Uses = [ECX, EAX] in
5478 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait",
5479 [(int_x86_sse3_mwait ECX, EAX)], IIC_SSE_MWAIT>,
5480 TB, Requires<[HasSSE3]>;
5483 def : InstAlias<"mwait %eax, %ecx", (MWAITrr)>, Requires<[In32BitMode]>;
5484 def : InstAlias<"mwait %rax, %rcx", (MWAITrr)>, Requires<[In64BitMode]>;
5486 def : InstAlias<"monitor %eax, %ecx, %edx", (MONITORrrr)>,
5487 Requires<[In32BitMode]>;
5488 def : InstAlias<"monitor %rax, %rcx, %rdx", (MONITORrrr)>,
5489 Requires<[In64BitMode]>;
5491 //===----------------------------------------------------------------------===//
5492 // SSE4.1 - Packed Move with Sign/Zero Extend
5493 //===----------------------------------------------------------------------===//
5495 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5496 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5497 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5498 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5500 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5501 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5503 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5507 multiclass SS41I_binop_rm_int16_y<bits<8> opc, string OpcodeStr,
5509 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5510 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5511 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5513 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
5514 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5515 [(set VR256:$dst, (IntId (load addr:$src)))]>, OpSize;
5518 let Predicates = [HasAVX] in {
5519 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
5521 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
5523 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
5525 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
5527 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
5529 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
5533 let Predicates = [HasAVX2] in {
5534 defm VPMOVSXBW : SS41I_binop_rm_int16_y<0x20, "vpmovsxbw",
5535 int_x86_avx2_pmovsxbw>, VEX, VEX_L;
5536 defm VPMOVSXWD : SS41I_binop_rm_int16_y<0x23, "vpmovsxwd",
5537 int_x86_avx2_pmovsxwd>, VEX, VEX_L;
5538 defm VPMOVSXDQ : SS41I_binop_rm_int16_y<0x25, "vpmovsxdq",
5539 int_x86_avx2_pmovsxdq>, VEX, VEX_L;
5540 defm VPMOVZXBW : SS41I_binop_rm_int16_y<0x30, "vpmovzxbw",
5541 int_x86_avx2_pmovzxbw>, VEX, VEX_L;
5542 defm VPMOVZXWD : SS41I_binop_rm_int16_y<0x33, "vpmovzxwd",
5543 int_x86_avx2_pmovzxwd>, VEX, VEX_L;
5544 defm VPMOVZXDQ : SS41I_binop_rm_int16_y<0x35, "vpmovzxdq",
5545 int_x86_avx2_pmovzxdq>, VEX, VEX_L;
5548 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
5549 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
5550 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
5551 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
5552 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
5553 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
5555 let Predicates = [HasAVX] in {
5556 // Common patterns involving scalar load.
5557 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5558 (VPMOVSXBWrm addr:$src)>;
5559 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5560 (VPMOVSXBWrm addr:$src)>;
5561 def : Pat<(int_x86_sse41_pmovsxbw (bc_v16i8 (loadv2i64 addr:$src))),
5562 (VPMOVSXBWrm addr:$src)>;
5564 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5565 (VPMOVSXWDrm addr:$src)>;
5566 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5567 (VPMOVSXWDrm addr:$src)>;
5568 def : Pat<(int_x86_sse41_pmovsxwd (bc_v8i16 (loadv2i64 addr:$src))),
5569 (VPMOVSXWDrm addr:$src)>;
5571 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5572 (VPMOVSXDQrm addr:$src)>;
5573 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5574 (VPMOVSXDQrm addr:$src)>;
5575 def : Pat<(int_x86_sse41_pmovsxdq (bc_v4i32 (loadv2i64 addr:$src))),
5576 (VPMOVSXDQrm addr:$src)>;
5578 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5579 (VPMOVZXBWrm addr:$src)>;
5580 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5581 (VPMOVZXBWrm addr:$src)>;
5582 def : Pat<(int_x86_sse41_pmovzxbw (bc_v16i8 (loadv2i64 addr:$src))),
5583 (VPMOVZXBWrm addr:$src)>;
5585 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5586 (VPMOVZXWDrm addr:$src)>;
5587 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5588 (VPMOVZXWDrm addr:$src)>;
5589 def : Pat<(int_x86_sse41_pmovzxwd (bc_v8i16 (loadv2i64 addr:$src))),
5590 (VPMOVZXWDrm addr:$src)>;
5592 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5593 (VPMOVZXDQrm addr:$src)>;
5594 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5595 (VPMOVZXDQrm addr:$src)>;
5596 def : Pat<(int_x86_sse41_pmovzxdq (bc_v4i32 (loadv2i64 addr:$src))),
5597 (VPMOVZXDQrm addr:$src)>;
5600 let Predicates = [UseSSE41] in {
5601 // Common patterns involving scalar load.
5602 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5603 (PMOVSXBWrm addr:$src)>;
5604 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5605 (PMOVSXBWrm addr:$src)>;
5606 def : Pat<(int_x86_sse41_pmovsxbw (bc_v16i8 (loadv2i64 addr:$src))),
5607 (PMOVSXBWrm addr:$src)>;
5609 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5610 (PMOVSXWDrm addr:$src)>;
5611 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5612 (PMOVSXWDrm addr:$src)>;
5613 def : Pat<(int_x86_sse41_pmovsxwd (bc_v8i16 (loadv2i64 addr:$src))),
5614 (PMOVSXWDrm addr:$src)>;
5616 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5617 (PMOVSXDQrm addr:$src)>;
5618 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5619 (PMOVSXDQrm addr:$src)>;
5620 def : Pat<(int_x86_sse41_pmovsxdq (bc_v4i32 (loadv2i64 addr:$src))),
5621 (PMOVSXDQrm addr:$src)>;
5623 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5624 (PMOVZXBWrm addr:$src)>;
5625 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5626 (PMOVZXBWrm addr:$src)>;
5627 def : Pat<(int_x86_sse41_pmovzxbw (bc_v16i8 (loadv2i64 addr:$src))),
5628 (PMOVZXBWrm addr:$src)>;
5630 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5631 (PMOVZXWDrm addr:$src)>;
5632 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5633 (PMOVZXWDrm addr:$src)>;
5634 def : Pat<(int_x86_sse41_pmovzxwd (bc_v8i16 (loadv2i64 addr:$src))),
5635 (PMOVZXWDrm addr:$src)>;
5637 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5638 (PMOVZXDQrm addr:$src)>;
5639 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5640 (PMOVZXDQrm addr:$src)>;
5641 def : Pat<(int_x86_sse41_pmovzxdq (bc_v4i32 (loadv2i64 addr:$src))),
5642 (PMOVZXDQrm addr:$src)>;
5645 let Predicates = [HasAVX2] in {
5646 let AddedComplexity = 15 in {
5647 def : Pat<(v4i64 (X86vzmovly (v4i32 VR128:$src))),
5648 (VPMOVZXDQYrr VR128:$src)>;
5649 def : Pat<(v8i32 (X86vzmovly (v8i16 VR128:$src))),
5650 (VPMOVZXWDYrr VR128:$src)>;
5653 def : Pat<(v4i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQYrr VR128:$src)>;
5654 def : Pat<(v8i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDYrr VR128:$src)>;
5657 let Predicates = [HasAVX] in {
5658 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQrr VR128:$src)>;
5659 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDrr VR128:$src)>;
5662 let Predicates = [UseSSE41] in {
5663 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (PMOVSXDQrr VR128:$src)>;
5664 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (PMOVSXWDrr VR128:$src)>;
5668 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5669 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5670 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5671 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5673 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
5674 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5676 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5680 multiclass SS41I_binop_rm_int8_y<bits<8> opc, string OpcodeStr,
5682 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5683 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5684 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5686 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i32mem:$src),
5687 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5689 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5693 let Predicates = [HasAVX] in {
5694 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
5696 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
5698 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
5700 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
5704 let Predicates = [HasAVX2] in {
5705 defm VPMOVSXBD : SS41I_binop_rm_int8_y<0x21, "vpmovsxbd",
5706 int_x86_avx2_pmovsxbd>, VEX, VEX_L;
5707 defm VPMOVSXWQ : SS41I_binop_rm_int8_y<0x24, "vpmovsxwq",
5708 int_x86_avx2_pmovsxwq>, VEX, VEX_L;
5709 defm VPMOVZXBD : SS41I_binop_rm_int8_y<0x31, "vpmovzxbd",
5710 int_x86_avx2_pmovzxbd>, VEX, VEX_L;
5711 defm VPMOVZXWQ : SS41I_binop_rm_int8_y<0x34, "vpmovzxwq",
5712 int_x86_avx2_pmovzxwq>, VEX, VEX_L;
5715 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
5716 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
5717 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
5718 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
5720 let Predicates = [HasAVX] in {
5721 // Common patterns involving scalar load
5722 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5723 (VPMOVSXBDrm addr:$src)>;
5724 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5725 (VPMOVSXWQrm addr:$src)>;
5727 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5728 (VPMOVZXBDrm addr:$src)>;
5729 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5730 (VPMOVZXWQrm addr:$src)>;
5733 let Predicates = [UseSSE41] in {
5734 // Common patterns involving scalar load
5735 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5736 (PMOVSXBDrm addr:$src)>;
5737 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5738 (PMOVSXWQrm addr:$src)>;
5740 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5741 (PMOVZXBDrm addr:$src)>;
5742 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5743 (PMOVZXWQrm addr:$src)>;
5746 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5747 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5748 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5749 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5751 // Expecting a i16 load any extended to i32 value.
5752 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
5753 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5754 [(set VR128:$dst, (IntId (bitconvert
5755 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
5759 multiclass SS41I_binop_rm_int4_y<bits<8> opc, string OpcodeStr,
5761 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5762 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5763 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5765 // Expecting a i16 load any extended to i32 value.
5766 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i16mem:$src),
5767 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5768 [(set VR256:$dst, (IntId (bitconvert
5769 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5773 let Predicates = [HasAVX] in {
5774 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
5776 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
5779 let Predicates = [HasAVX2] in {
5780 defm VPMOVSXBQ : SS41I_binop_rm_int4_y<0x22, "vpmovsxbq",
5781 int_x86_avx2_pmovsxbq>, VEX, VEX_L;
5782 defm VPMOVZXBQ : SS41I_binop_rm_int4_y<0x32, "vpmovzxbq",
5783 int_x86_avx2_pmovzxbq>, VEX, VEX_L;
5785 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
5786 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
5788 let Predicates = [HasAVX2] in {
5789 def : Pat<(v16i16 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBWYrr VR128:$src)>;
5790 def : Pat<(v8i32 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBDYrr VR128:$src)>;
5791 def : Pat<(v4i64 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBQYrr VR128:$src)>;
5793 def : Pat<(v8i32 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWDYrr VR128:$src)>;
5794 def : Pat<(v4i64 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWQYrr VR128:$src)>;
5796 def : Pat<(v4i64 (X86vsext (v4i32 VR128:$src))), (VPMOVSXDQYrr VR128:$src)>;
5798 def : Pat<(v16i16 (X86vsext (v32i8 VR256:$src))),
5799 (VPMOVSXBWYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5800 def : Pat<(v8i32 (X86vsext (v32i8 VR256:$src))),
5801 (VPMOVSXBDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5802 def : Pat<(v4i64 (X86vsext (v32i8 VR256:$src))),
5803 (VPMOVSXBQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5805 def : Pat<(v8i32 (X86vsext (v16i16 VR256:$src))),
5806 (VPMOVSXWDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5807 def : Pat<(v4i64 (X86vsext (v16i16 VR256:$src))),
5808 (VPMOVSXWQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5810 def : Pat<(v4i64 (X86vsext (v8i32 VR256:$src))),
5811 (VPMOVSXDQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5813 def : Pat<(v8i32 (X86vsmovl (v8i16 (bitconvert (v2i64 (load addr:$src)))))),
5814 (VPMOVSXWDYrm addr:$src)>;
5815 def : Pat<(v4i64 (X86vsmovl (v4i32 (bitconvert (v2i64 (load addr:$src)))))),
5816 (VPMOVSXDQYrm addr:$src)>;
5818 def : Pat<(v8i32 (X86vsext (v16i8 (bitconvert (v2i64
5819 (scalar_to_vector (loadi64 addr:$src))))))),
5820 (VPMOVSXBDYrm addr:$src)>;
5821 def : Pat<(v8i32 (X86vsext (v16i8 (bitconvert (v2f64
5822 (scalar_to_vector (loadf64 addr:$src))))))),
5823 (VPMOVSXBDYrm addr:$src)>;
5825 def : Pat<(v4i64 (X86vsext (v8i16 (bitconvert (v2i64
5826 (scalar_to_vector (loadi64 addr:$src))))))),
5827 (VPMOVSXWQYrm addr:$src)>;
5828 def : Pat<(v4i64 (X86vsext (v8i16 (bitconvert (v2f64
5829 (scalar_to_vector (loadf64 addr:$src))))))),
5830 (VPMOVSXWQYrm addr:$src)>;
5832 def : Pat<(v4i64 (X86vsext (v16i8 (bitconvert (v4i32
5833 (scalar_to_vector (loadi32 addr:$src))))))),
5834 (VPMOVSXBQYrm addr:$src)>;
5837 let Predicates = [HasAVX] in {
5838 // Common patterns involving scalar load
5839 def : Pat<(int_x86_sse41_pmovsxbq
5840 (bitconvert (v4i32 (X86vzmovl
5841 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5842 (VPMOVSXBQrm addr:$src)>;
5844 def : Pat<(int_x86_sse41_pmovzxbq
5845 (bitconvert (v4i32 (X86vzmovl
5846 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5847 (VPMOVZXBQrm addr:$src)>;
5850 let Predicates = [UseSSE41] in {
5851 def : Pat<(v8i16 (X86vsext (v16i8 VR128:$src))), (PMOVSXBWrr VR128:$src)>;
5852 def : Pat<(v4i32 (X86vsext (v16i8 VR128:$src))), (PMOVSXBDrr VR128:$src)>;
5853 def : Pat<(v2i64 (X86vsext (v16i8 VR128:$src))), (PMOVSXBQrr VR128:$src)>;
5855 def : Pat<(v4i32 (X86vsext (v8i16 VR128:$src))), (PMOVSXWDrr VR128:$src)>;
5856 def : Pat<(v2i64 (X86vsext (v8i16 VR128:$src))), (PMOVSXWQrr VR128:$src)>;
5858 def : Pat<(v2i64 (X86vsext (v4i32 VR128:$src))), (PMOVSXDQrr VR128:$src)>;
5860 // Common patterns involving scalar load
5861 def : Pat<(int_x86_sse41_pmovsxbq
5862 (bitconvert (v4i32 (X86vzmovl
5863 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5864 (PMOVSXBQrm addr:$src)>;
5866 def : Pat<(int_x86_sse41_pmovzxbq
5867 (bitconvert (v4i32 (X86vzmovl
5868 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5869 (PMOVZXBQrm addr:$src)>;
5871 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2i64
5872 (scalar_to_vector (loadi64 addr:$src))))))),
5873 (PMOVSXWDrm addr:$src)>;
5874 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2f64
5875 (scalar_to_vector (loadf64 addr:$src))))))),
5876 (PMOVSXWDrm addr:$src)>;
5877 def : Pat<(v4i32 (X86vsext (v16i8 (bitconvert (v4i32
5878 (scalar_to_vector (loadi32 addr:$src))))))),
5879 (PMOVSXBDrm addr:$src)>;
5880 def : Pat<(v2i64 (X86vsext (v8i16 (bitconvert (v4i32
5881 (scalar_to_vector (loadi32 addr:$src))))))),
5882 (PMOVSXWQrm addr:$src)>;
5883 def : Pat<(v2i64 (X86vsext (v16i8 (bitconvert (v4i32
5884 (scalar_to_vector (extloadi32i16 addr:$src))))))),
5885 (PMOVSXBQrm addr:$src)>;
5886 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2i64
5887 (scalar_to_vector (loadi64 addr:$src))))))),
5888 (PMOVSXDQrm addr:$src)>;
5889 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2f64
5890 (scalar_to_vector (loadf64 addr:$src))))))),
5891 (PMOVSXDQrm addr:$src)>;
5892 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2i64
5893 (scalar_to_vector (loadi64 addr:$src))))))),
5894 (PMOVSXBWrm addr:$src)>;
5895 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2f64
5896 (scalar_to_vector (loadf64 addr:$src))))))),
5897 (PMOVSXBWrm addr:$src)>;
5900 let Predicates = [HasAVX2] in {
5901 def : Pat<(v16i16 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBWYrr VR128:$src)>;
5902 def : Pat<(v8i32 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBDYrr VR128:$src)>;
5903 def : Pat<(v4i64 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBQYrr VR128:$src)>;
5905 def : Pat<(v8i32 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWDYrr VR128:$src)>;
5906 def : Pat<(v4i64 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWQYrr VR128:$src)>;
5908 def : Pat<(v4i64 (X86vzext (v4i32 VR128:$src))), (VPMOVZXDQYrr VR128:$src)>;
5910 def : Pat<(v16i16 (X86vzext (v32i8 VR256:$src))),
5911 (VPMOVZXBWYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5912 def : Pat<(v8i32 (X86vzext (v32i8 VR256:$src))),
5913 (VPMOVZXBDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5914 def : Pat<(v4i64 (X86vzext (v32i8 VR256:$src))),
5915 (VPMOVZXBQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5917 def : Pat<(v8i32 (X86vzext (v16i16 VR256:$src))),
5918 (VPMOVZXWDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5919 def : Pat<(v4i64 (X86vzext (v16i16 VR256:$src))),
5920 (VPMOVZXWQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5922 def : Pat<(v4i64 (X86vzext (v8i32 VR256:$src))),
5923 (VPMOVZXDQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5926 let Predicates = [HasAVX] in {
5927 def : Pat<(v8i16 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBWrr VR128:$src)>;
5928 def : Pat<(v4i32 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBDrr VR128:$src)>;
5929 def : Pat<(v2i64 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBQrr VR128:$src)>;
5931 def : Pat<(v4i32 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWDrr VR128:$src)>;
5932 def : Pat<(v2i64 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWQrr VR128:$src)>;
5934 def : Pat<(v2i64 (X86vzext (v4i32 VR128:$src))), (VPMOVZXDQrr VR128:$src)>;
5936 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5937 (VPMOVZXBWrm addr:$src)>;
5938 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5939 (VPMOVZXBWrm addr:$src)>;
5940 def : Pat<(v4i32 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5941 (VPMOVZXBDrm addr:$src)>;
5942 def : Pat<(v2i64 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))),
5943 (VPMOVZXBQrm addr:$src)>;
5945 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5946 (VPMOVZXWDrm addr:$src)>;
5947 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5948 (VPMOVZXWDrm addr:$src)>;
5949 def : Pat<(v2i64 (X86vzext (v8i16 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5950 (VPMOVZXWQrm addr:$src)>;
5952 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5953 (VPMOVZXDQrm addr:$src)>;
5954 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5955 (VPMOVZXDQrm addr:$src)>;
5956 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (X86vzload addr:$src)))))),
5957 (VPMOVZXDQrm addr:$src)>;
5959 def : Pat<(v8i16 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBWrr VR128:$src)>;
5960 def : Pat<(v4i32 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBDrr VR128:$src)>;
5961 def : Pat<(v2i64 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBQrr VR128:$src)>;
5963 def : Pat<(v4i32 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWDrr VR128:$src)>;
5964 def : Pat<(v2i64 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWQrr VR128:$src)>;
5966 def : Pat<(v2i64 (X86vsext (v4i32 VR128:$src))), (VPMOVSXDQrr VR128:$src)>;
5968 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2i64
5969 (scalar_to_vector (loadi64 addr:$src))))))),
5970 (VPMOVSXWDrm addr:$src)>;
5971 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2i64
5972 (scalar_to_vector (loadi64 addr:$src))))))),
5973 (VPMOVSXDQrm addr:$src)>;
5974 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2f64
5975 (scalar_to_vector (loadf64 addr:$src))))))),
5976 (VPMOVSXWDrm addr:$src)>;
5977 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2f64
5978 (scalar_to_vector (loadf64 addr:$src))))))),
5979 (VPMOVSXDQrm addr:$src)>;
5980 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2i64
5981 (scalar_to_vector (loadi64 addr:$src))))))),
5982 (VPMOVSXBWrm addr:$src)>;
5983 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2f64
5984 (scalar_to_vector (loadf64 addr:$src))))))),
5985 (VPMOVSXBWrm addr:$src)>;
5987 def : Pat<(v4i32 (X86vsext (v16i8 (bitconvert (v4i32
5988 (scalar_to_vector (loadi32 addr:$src))))))),
5989 (VPMOVSXBDrm addr:$src)>;
5990 def : Pat<(v2i64 (X86vsext (v8i16 (bitconvert (v4i32
5991 (scalar_to_vector (loadi32 addr:$src))))))),
5992 (VPMOVSXWQrm addr:$src)>;
5993 def : Pat<(v2i64 (X86vsext (v16i8 (bitconvert (v4i32
5994 (scalar_to_vector (extloadi32i16 addr:$src))))))),
5995 (VPMOVSXBQrm addr:$src)>;
5998 let Predicates = [UseSSE41] in {
5999 def : Pat<(v8i16 (X86vzext (v16i8 VR128:$src))), (PMOVZXBWrr VR128:$src)>;
6000 def : Pat<(v4i32 (X86vzext (v16i8 VR128:$src))), (PMOVZXBDrr VR128:$src)>;
6001 def : Pat<(v2i64 (X86vzext (v16i8 VR128:$src))), (PMOVZXBQrr VR128:$src)>;
6003 def : Pat<(v4i32 (X86vzext (v8i16 VR128:$src))), (PMOVZXWDrr VR128:$src)>;
6004 def : Pat<(v2i64 (X86vzext (v8i16 VR128:$src))), (PMOVZXWQrr VR128:$src)>;
6006 def : Pat<(v2i64 (X86vzext (v4i32 VR128:$src))), (PMOVZXDQrr VR128:$src)>;
6008 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6009 (PMOVZXBWrm addr:$src)>;
6010 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6011 (PMOVZXBWrm addr:$src)>;
6012 def : Pat<(v4i32 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6013 (PMOVZXBDrm addr:$src)>;
6014 def : Pat<(v2i64 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))),
6015 (PMOVZXBQrm addr:$src)>;
6017 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6018 (PMOVZXWDrm addr:$src)>;
6019 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6020 (PMOVZXWDrm addr:$src)>;
6021 def : Pat<(v2i64 (X86vzext (v8i16 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6022 (PMOVZXWQrm addr:$src)>;
6024 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6025 (PMOVZXDQrm addr:$src)>;
6026 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6027 (PMOVZXDQrm addr:$src)>;
6028 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (X86vzload addr:$src)))))),
6029 (PMOVZXDQrm addr:$src)>;
6032 //===----------------------------------------------------------------------===//
6033 // SSE4.1 - Extract Instructions
6034 //===----------------------------------------------------------------------===//
6036 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
6037 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
6038 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
6039 (ins VR128:$src1, i32i8imm:$src2),
6040 !strconcat(OpcodeStr,
6041 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6042 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
6044 let neverHasSideEffects = 1, mayStore = 1 in
6045 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6046 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
6047 !strconcat(OpcodeStr,
6048 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6051 // There's an AssertZext in the way of writing the store pattern
6052 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
6055 let Predicates = [HasAVX] in {
6056 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
6057 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
6058 (ins VR128:$src1, i32i8imm:$src2),
6059 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
6062 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
6065 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
6066 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
6067 let neverHasSideEffects = 1, mayStore = 1 in
6068 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6069 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
6070 !strconcat(OpcodeStr,
6071 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6074 // There's an AssertZext in the way of writing the store pattern
6075 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
6078 let Predicates = [HasAVX] in
6079 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
6081 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
6084 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6085 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
6086 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
6087 (ins VR128:$src1, i32i8imm:$src2),
6088 !strconcat(OpcodeStr,
6089 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6091 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
6092 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6093 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
6094 !strconcat(OpcodeStr,
6095 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6096 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
6097 addr:$dst)]>, OpSize;
6100 let Predicates = [HasAVX] in
6101 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
6103 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
6105 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6106 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
6107 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
6108 (ins VR128:$src1, i32i8imm:$src2),
6109 !strconcat(OpcodeStr,
6110 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6112 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
6113 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6114 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
6115 !strconcat(OpcodeStr,
6116 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6117 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
6118 addr:$dst)]>, OpSize, REX_W;
6121 let Predicates = [HasAVX] in
6122 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
6124 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
6126 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
6128 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
6129 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
6130 (ins VR128:$src1, i32i8imm:$src2),
6131 !strconcat(OpcodeStr,
6132 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6134 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
6136 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6137 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
6138 !strconcat(OpcodeStr,
6139 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6140 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
6141 addr:$dst)]>, OpSize;
6144 let ExeDomain = SSEPackedSingle in {
6145 let Predicates = [HasAVX] in {
6146 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
6147 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
6148 (ins VR128:$src1, i32i8imm:$src2),
6149 "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
6152 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
6155 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
6156 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6159 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6161 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6164 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6165 Requires<[UseSSE41]>;
6167 //===----------------------------------------------------------------------===//
6168 // SSE4.1 - Insert Instructions
6169 //===----------------------------------------------------------------------===//
6171 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
6172 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6173 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
6175 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6177 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6179 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
6180 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6181 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
6183 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6185 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6187 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
6188 imm:$src3))]>, OpSize;
6191 let Predicates = [HasAVX] in
6192 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
6193 let Constraints = "$src1 = $dst" in
6194 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
6196 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
6197 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6198 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
6200 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6202 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6204 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
6206 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6207 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
6209 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6211 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6213 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
6214 imm:$src3)))]>, OpSize;
6217 let Predicates = [HasAVX] in
6218 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
6219 let Constraints = "$src1 = $dst" in
6220 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
6222 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
6223 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6224 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
6226 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6228 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6230 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
6232 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6233 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
6235 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6237 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6239 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
6240 imm:$src3)))]>, OpSize;
6243 let Predicates = [HasAVX] in
6244 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
6245 let Constraints = "$src1 = $dst" in
6246 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
6248 // insertps has a few different modes, there's the first two here below which
6249 // are optimized inserts that won't zero arbitrary elements in the destination
6250 // vector. The next one matches the intrinsic and could zero arbitrary elements
6251 // in the target vector.
6252 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
6253 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6254 (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),
6256 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6258 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6260 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
6262 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6263 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
6265 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6267 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6269 (X86insrtps VR128:$src1,
6270 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
6271 imm:$src3))]>, OpSize;
6274 let ExeDomain = SSEPackedSingle in {
6275 let Predicates = [HasAVX] in
6276 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
6277 let Constraints = "$src1 = $dst" in
6278 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
6281 //===----------------------------------------------------------------------===//
6282 // SSE4.1 - Round Instructions
6283 //===----------------------------------------------------------------------===//
6285 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
6286 X86MemOperand x86memop, RegisterClass RC,
6287 PatFrag mem_frag32, PatFrag mem_frag64,
6288 Intrinsic V4F32Int, Intrinsic V2F64Int> {
6289 let ExeDomain = SSEPackedSingle in {
6290 // Intrinsic operation, reg.
6291 // Vector intrinsic operation, reg
6292 def PSr : SS4AIi8<opcps, MRMSrcReg,
6293 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6294 !strconcat(OpcodeStr,
6295 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6296 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
6299 // Vector intrinsic operation, mem
6300 def PSm : SS4AIi8<opcps, MRMSrcMem,
6301 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6302 !strconcat(OpcodeStr,
6303 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6305 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
6307 } // ExeDomain = SSEPackedSingle
6309 let ExeDomain = SSEPackedDouble in {
6310 // Vector intrinsic operation, reg
6311 def PDr : SS4AIi8<opcpd, MRMSrcReg,
6312 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6313 !strconcat(OpcodeStr,
6314 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6315 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
6318 // Vector intrinsic operation, mem
6319 def PDm : SS4AIi8<opcpd, MRMSrcMem,
6320 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6321 !strconcat(OpcodeStr,
6322 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6324 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
6326 } // ExeDomain = SSEPackedDouble
6329 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6332 Intrinsic F64Int, bit Is2Addr = 1> {
6333 let ExeDomain = GenericDomain in {
6335 let hasSideEffects = 0 in
6336 def SSr : SS4AIi8<opcss, MRMSrcReg,
6337 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32i8imm:$src3),
6339 !strconcat(OpcodeStr,
6340 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6341 !strconcat(OpcodeStr,
6342 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6345 // Intrinsic operation, reg.
6346 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
6347 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6349 !strconcat(OpcodeStr,
6350 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6351 !strconcat(OpcodeStr,
6352 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6353 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6356 // Intrinsic operation, mem.
6357 def SSm : SS4AIi8<opcss, MRMSrcMem,
6358 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
6360 !strconcat(OpcodeStr,
6361 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6362 !strconcat(OpcodeStr,
6363 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6365 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
6369 let hasSideEffects = 0 in
6370 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6371 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32i8imm:$src3),
6373 !strconcat(OpcodeStr,
6374 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6375 !strconcat(OpcodeStr,
6376 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6379 // Intrinsic operation, reg.
6380 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
6381 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6383 !strconcat(OpcodeStr,
6384 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6385 !strconcat(OpcodeStr,
6386 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6387 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6390 // Intrinsic operation, mem.
6391 def SDm : SS4AIi8<opcsd, MRMSrcMem,
6392 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
6394 !strconcat(OpcodeStr,
6395 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6396 !strconcat(OpcodeStr,
6397 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6399 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
6401 } // ExeDomain = GenericDomain
6404 // FP round - roundss, roundps, roundsd, roundpd
6405 let Predicates = [HasAVX] in {
6407 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
6408 memopv4f32, memopv2f64,
6409 int_x86_sse41_round_ps,
6410 int_x86_sse41_round_pd>, VEX;
6411 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
6412 memopv8f32, memopv4f64,
6413 int_x86_avx_round_ps_256,
6414 int_x86_avx_round_pd_256>, VEX, VEX_L;
6415 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
6416 int_x86_sse41_round_ss,
6417 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
6419 def : Pat<(ffloor FR32:$src),
6420 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6421 def : Pat<(f64 (ffloor FR64:$src)),
6422 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6423 def : Pat<(f32 (fnearbyint FR32:$src)),
6424 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6425 def : Pat<(f64 (fnearbyint FR64:$src)),
6426 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6427 def : Pat<(f32 (fceil FR32:$src)),
6428 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6429 def : Pat<(f64 (fceil FR64:$src)),
6430 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6431 def : Pat<(f32 (frint FR32:$src)),
6432 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6433 def : Pat<(f64 (frint FR64:$src)),
6434 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6435 def : Pat<(f32 (ftrunc FR32:$src)),
6436 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6437 def : Pat<(f64 (ftrunc FR64:$src)),
6438 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6440 def : Pat<(v4f32 (ffloor VR128:$src)),
6441 (VROUNDPSr VR128:$src, (i32 0x1))>;
6442 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6443 (VROUNDPSr VR128:$src, (i32 0xC))>;
6444 def : Pat<(v4f32 (fceil VR128:$src)),
6445 (VROUNDPSr VR128:$src, (i32 0x2))>;
6446 def : Pat<(v4f32 (frint VR128:$src)),
6447 (VROUNDPSr VR128:$src, (i32 0x4))>;
6448 def : Pat<(v4f32 (ftrunc VR128:$src)),
6449 (VROUNDPSr VR128:$src, (i32 0x3))>;
6451 def : Pat<(v2f64 (ffloor VR128:$src)),
6452 (VROUNDPDr VR128:$src, (i32 0x1))>;
6453 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6454 (VROUNDPDr VR128:$src, (i32 0xC))>;
6455 def : Pat<(v2f64 (fceil VR128:$src)),
6456 (VROUNDPDr VR128:$src, (i32 0x2))>;
6457 def : Pat<(v2f64 (frint VR128:$src)),
6458 (VROUNDPDr VR128:$src, (i32 0x4))>;
6459 def : Pat<(v2f64 (ftrunc VR128:$src)),
6460 (VROUNDPDr VR128:$src, (i32 0x3))>;
6462 def : Pat<(v8f32 (ffloor VR256:$src)),
6463 (VROUNDYPSr VR256:$src, (i32 0x1))>;
6464 def : Pat<(v8f32 (fnearbyint VR256:$src)),
6465 (VROUNDYPSr VR256:$src, (i32 0xC))>;
6466 def : Pat<(v8f32 (fceil VR256:$src)),
6467 (VROUNDYPSr VR256:$src, (i32 0x2))>;
6468 def : Pat<(v8f32 (frint VR256:$src)),
6469 (VROUNDYPSr VR256:$src, (i32 0x4))>;
6470 def : Pat<(v8f32 (ftrunc VR256:$src)),
6471 (VROUNDYPSr VR256:$src, (i32 0x3))>;
6473 def : Pat<(v4f64 (ffloor VR256:$src)),
6474 (VROUNDYPDr VR256:$src, (i32 0x1))>;
6475 def : Pat<(v4f64 (fnearbyint VR256:$src)),
6476 (VROUNDYPDr VR256:$src, (i32 0xC))>;
6477 def : Pat<(v4f64 (fceil VR256:$src)),
6478 (VROUNDYPDr VR256:$src, (i32 0x2))>;
6479 def : Pat<(v4f64 (frint VR256:$src)),
6480 (VROUNDYPDr VR256:$src, (i32 0x4))>;
6481 def : Pat<(v4f64 (ftrunc VR256:$src)),
6482 (VROUNDYPDr VR256:$src, (i32 0x3))>;
6485 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
6486 memopv4f32, memopv2f64,
6487 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
6488 let Constraints = "$src1 = $dst" in
6489 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
6490 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
6492 let Predicates = [UseSSE41] in {
6493 def : Pat<(ffloor FR32:$src),
6494 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6495 def : Pat<(f64 (ffloor FR64:$src)),
6496 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6497 def : Pat<(f32 (fnearbyint FR32:$src)),
6498 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6499 def : Pat<(f64 (fnearbyint FR64:$src)),
6500 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6501 def : Pat<(f32 (fceil FR32:$src)),
6502 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6503 def : Pat<(f64 (fceil FR64:$src)),
6504 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6505 def : Pat<(f32 (frint FR32:$src)),
6506 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6507 def : Pat<(f64 (frint FR64:$src)),
6508 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6509 def : Pat<(f32 (ftrunc FR32:$src)),
6510 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6511 def : Pat<(f64 (ftrunc FR64:$src)),
6512 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6514 def : Pat<(v4f32 (ffloor VR128:$src)),
6515 (ROUNDPSr VR128:$src, (i32 0x1))>;
6516 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6517 (ROUNDPSr VR128:$src, (i32 0xC))>;
6518 def : Pat<(v4f32 (fceil VR128:$src)),
6519 (ROUNDPSr VR128:$src, (i32 0x2))>;
6520 def : Pat<(v4f32 (frint VR128:$src)),
6521 (ROUNDPSr VR128:$src, (i32 0x4))>;
6522 def : Pat<(v4f32 (ftrunc VR128:$src)),
6523 (ROUNDPSr VR128:$src, (i32 0x3))>;
6525 def : Pat<(v2f64 (ffloor VR128:$src)),
6526 (ROUNDPDr VR128:$src, (i32 0x1))>;
6527 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6528 (ROUNDPDr VR128:$src, (i32 0xC))>;
6529 def : Pat<(v2f64 (fceil VR128:$src)),
6530 (ROUNDPDr VR128:$src, (i32 0x2))>;
6531 def : Pat<(v2f64 (frint VR128:$src)),
6532 (ROUNDPDr VR128:$src, (i32 0x4))>;
6533 def : Pat<(v2f64 (ftrunc VR128:$src)),
6534 (ROUNDPDr VR128:$src, (i32 0x3))>;
6537 //===----------------------------------------------------------------------===//
6538 // SSE4.1 - Packed Bit Test
6539 //===----------------------------------------------------------------------===//
6541 // ptest instruction we'll lower to this in X86ISelLowering primarily from
6542 // the intel intrinsic that corresponds to this.
6543 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6544 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6545 "vptest\t{$src2, $src1|$src1, $src2}",
6546 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6548 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6549 "vptest\t{$src2, $src1|$src1, $src2}",
6550 [(set EFLAGS,(X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6553 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
6554 "vptest\t{$src2, $src1|$src1, $src2}",
6555 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
6557 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
6558 "vptest\t{$src2, $src1|$src1, $src2}",
6559 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
6563 let Defs = [EFLAGS] in {
6564 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6565 "ptest\t{$src2, $src1|$src1, $src2}",
6566 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6568 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6569 "ptest\t{$src2, $src1|$src1, $src2}",
6570 [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6574 // The bit test instructions below are AVX only
6575 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
6576 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
6577 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
6578 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6579 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
6580 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
6581 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6582 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
6586 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6587 let ExeDomain = SSEPackedSingle in {
6588 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
6589 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>,
6592 let ExeDomain = SSEPackedDouble in {
6593 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
6594 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>,
6599 //===----------------------------------------------------------------------===//
6600 // SSE4.1 - Misc Instructions
6601 //===----------------------------------------------------------------------===//
6603 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
6604 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
6605 "popcnt{w}\t{$src, $dst|$dst, $src}",
6606 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)]>,
6608 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
6609 "popcnt{w}\t{$src, $dst|$dst, $src}",
6610 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
6611 (implicit EFLAGS)]>, OpSize, XS;
6613 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
6614 "popcnt{l}\t{$src, $dst|$dst, $src}",
6615 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)]>,
6617 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
6618 "popcnt{l}\t{$src, $dst|$dst, $src}",
6619 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
6620 (implicit EFLAGS)]>, XS;
6622 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
6623 "popcnt{q}\t{$src, $dst|$dst, $src}",
6624 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)]>,
6626 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
6627 "popcnt{q}\t{$src, $dst|$dst, $src}",
6628 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
6629 (implicit EFLAGS)]>, XS;
6634 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
6635 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
6636 Intrinsic IntId128> {
6637 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6639 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6640 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
6641 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6643 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6646 (bitconvert (memopv2i64 addr:$src))))]>, OpSize;
6649 let Predicates = [HasAVX] in
6650 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
6651 int_x86_sse41_phminposuw>, VEX;
6652 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
6653 int_x86_sse41_phminposuw>;
6655 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
6656 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
6657 Intrinsic IntId128, bit Is2Addr = 1> {
6658 let isCommutable = 1 in
6659 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6660 (ins VR128:$src1, VR128:$src2),
6662 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6663 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6664 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
6665 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6666 (ins VR128:$src1, i128mem:$src2),
6668 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6669 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6671 (IntId128 VR128:$src1,
6672 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
6675 /// SS41I_binop_rm_int_y - Simple SSE 4.1 binary operator
6676 multiclass SS41I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
6677 Intrinsic IntId256> {
6678 let isCommutable = 1 in
6679 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst),
6680 (ins VR256:$src1, VR256:$src2),
6681 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6682 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>, OpSize;
6683 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst),
6684 (ins VR256:$src1, i256mem:$src2),
6685 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6687 (IntId256 VR256:$src1,
6688 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
6692 /// SS48I_binop_rm - Simple SSE41 binary operator.
6693 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6694 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6695 X86MemOperand x86memop, bit Is2Addr = 1> {
6696 let isCommutable = 1 in
6697 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6698 (ins RC:$src1, RC:$src2),
6700 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6701 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6702 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>, OpSize;
6703 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6704 (ins RC:$src1, x86memop:$src2),
6706 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6707 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6709 (OpVT (OpNode RC:$src1,
6710 (bitconvert (memop_frag addr:$src2)))))]>, OpSize;
6713 let Predicates = [HasAVX] in {
6714 let isCommutable = 0 in
6715 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
6717 defm VPMINSB : SS48I_binop_rm<0x38, "vpminsb", X86smin, v16i8, VR128,
6718 memopv2i64, i128mem, 0>, VEX_4V;
6719 defm VPMINSD : SS48I_binop_rm<0x39, "vpminsd", X86smin, v4i32, VR128,
6720 memopv2i64, i128mem, 0>, VEX_4V;
6721 defm VPMINUD : SS48I_binop_rm<0x3B, "vpminud", X86umin, v4i32, VR128,
6722 memopv2i64, i128mem, 0>, VEX_4V;
6723 defm VPMINUW : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v8i16, VR128,
6724 memopv2i64, i128mem, 0>, VEX_4V;
6725 defm VPMAXSB : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v16i8, VR128,
6726 memopv2i64, i128mem, 0>, VEX_4V;
6727 defm VPMAXSD : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v4i32, VR128,
6728 memopv2i64, i128mem, 0>, VEX_4V;
6729 defm VPMAXUD : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v4i32, VR128,
6730 memopv2i64, i128mem, 0>, VEX_4V;
6731 defm VPMAXUW : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v8i16, VR128,
6732 memopv2i64, i128mem, 0>, VEX_4V;
6733 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
6737 let Predicates = [HasAVX2] in {
6738 let isCommutable = 0 in
6739 defm VPACKUSDW : SS41I_binop_rm_int_y<0x2B, "vpackusdw",
6740 int_x86_avx2_packusdw>, VEX_4V, VEX_L;
6741 defm VPMINSBY : SS48I_binop_rm<0x38, "vpminsb", X86smin, v32i8, VR256,
6742 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6743 defm VPMINSDY : SS48I_binop_rm<0x39, "vpminsd", X86smin, v8i32, VR256,
6744 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6745 defm VPMINUDY : SS48I_binop_rm<0x3B, "vpminud", X86umin, v8i32, VR256,
6746 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6747 defm VPMINUWY : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v16i16, VR256,
6748 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6749 defm VPMAXSBY : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v32i8, VR256,
6750 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6751 defm VPMAXSDY : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v8i32, VR256,
6752 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6753 defm VPMAXUDY : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v8i32, VR256,
6754 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6755 defm VPMAXUWY : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v16i16, VR256,
6756 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6757 defm VPMULDQ : SS41I_binop_rm_int_y<0x28, "vpmuldq",
6758 int_x86_avx2_pmul_dq>, VEX_4V, VEX_L;
6761 let Constraints = "$src1 = $dst" in {
6762 let isCommutable = 0 in
6763 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
6764 defm PMINSB : SS48I_binop_rm<0x38, "pminsb", X86smin, v16i8, VR128,
6765 memopv2i64, i128mem>;
6766 defm PMINSD : SS48I_binop_rm<0x39, "pminsd", X86smin, v4i32, VR128,
6767 memopv2i64, i128mem>;
6768 defm PMINUD : SS48I_binop_rm<0x3B, "pminud", X86umin, v4i32, VR128,
6769 memopv2i64, i128mem>;
6770 defm PMINUW : SS48I_binop_rm<0x3A, "pminuw", X86umin, v8i16, VR128,
6771 memopv2i64, i128mem>;
6772 defm PMAXSB : SS48I_binop_rm<0x3C, "pmaxsb", X86smax, v16i8, VR128,
6773 memopv2i64, i128mem>;
6774 defm PMAXSD : SS48I_binop_rm<0x3D, "pmaxsd", X86smax, v4i32, VR128,
6775 memopv2i64, i128mem>;
6776 defm PMAXUD : SS48I_binop_rm<0x3F, "pmaxud", X86umax, v4i32, VR128,
6777 memopv2i64, i128mem>;
6778 defm PMAXUW : SS48I_binop_rm<0x3E, "pmaxuw", X86umax, v8i16, VR128,
6779 memopv2i64, i128mem>;
6780 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
6783 let Predicates = [HasAVX] in {
6784 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
6785 memopv2i64, i128mem, 0>, VEX_4V;
6786 defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
6787 memopv2i64, i128mem, 0>, VEX_4V;
6789 let Predicates = [HasAVX2] in {
6790 defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
6791 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6792 defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
6793 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6796 let Constraints = "$src1 = $dst" in {
6797 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
6798 memopv2i64, i128mem>;
6799 defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
6800 memopv2i64, i128mem>;
6803 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
6804 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
6805 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
6806 X86MemOperand x86memop, bit Is2Addr = 1> {
6807 let isCommutable = 1 in
6808 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6809 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
6811 !strconcat(OpcodeStr,
6812 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6813 !strconcat(OpcodeStr,
6814 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6815 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
6817 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6818 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
6820 !strconcat(OpcodeStr,
6821 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6822 !strconcat(OpcodeStr,
6823 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6826 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
6830 let Predicates = [HasAVX] in {
6831 let isCommutable = 0 in {
6832 let ExeDomain = SSEPackedSingle in {
6833 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
6834 VR128, memopv4f32, f128mem, 0>, VEX_4V;
6835 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
6836 int_x86_avx_blend_ps_256, VR256, memopv8f32,
6837 f256mem, 0>, VEX_4V, VEX_L;
6839 let ExeDomain = SSEPackedDouble in {
6840 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
6841 VR128, memopv2f64, f128mem, 0>, VEX_4V;
6842 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
6843 int_x86_avx_blend_pd_256,VR256, memopv4f64,
6844 f256mem, 0>, VEX_4V, VEX_L;
6846 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
6847 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6848 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
6849 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6851 let ExeDomain = SSEPackedSingle in
6852 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
6853 VR128, memopv4f32, f128mem, 0>, VEX_4V;
6854 let ExeDomain = SSEPackedDouble in
6855 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
6856 VR128, memopv2f64, f128mem, 0>, VEX_4V;
6857 let ExeDomain = SSEPackedSingle in
6858 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
6859 VR256, memopv8f32, i256mem, 0>, VEX_4V, VEX_L;
6862 let Predicates = [HasAVX2] in {
6863 let isCommutable = 0 in {
6864 defm VPBLENDWY : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_avx2_pblendw,
6865 VR256, memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6866 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
6867 VR256, memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6871 let Constraints = "$src1 = $dst" in {
6872 let isCommutable = 0 in {
6873 let ExeDomain = SSEPackedSingle in
6874 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
6875 VR128, memopv4f32, f128mem>;
6876 let ExeDomain = SSEPackedDouble in
6877 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
6878 VR128, memopv2f64, f128mem>;
6879 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
6880 VR128, memopv2i64, i128mem>;
6881 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
6882 VR128, memopv2i64, i128mem>;
6884 let ExeDomain = SSEPackedSingle in
6885 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
6886 VR128, memopv4f32, f128mem>;
6887 let ExeDomain = SSEPackedDouble in
6888 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
6889 VR128, memopv2f64, f128mem>;
6892 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
6893 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
6894 RegisterClass RC, X86MemOperand x86memop,
6895 PatFrag mem_frag, Intrinsic IntId> {
6896 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
6897 (ins RC:$src1, RC:$src2, RC:$src3),
6898 !strconcat(OpcodeStr,
6899 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6900 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
6901 NoItinerary, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6903 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
6904 (ins RC:$src1, x86memop:$src2, RC:$src3),
6905 !strconcat(OpcodeStr,
6906 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6908 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
6910 NoItinerary, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6913 let Predicates = [HasAVX] in {
6914 let ExeDomain = SSEPackedDouble in {
6915 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, f128mem,
6916 memopv2f64, int_x86_sse41_blendvpd>;
6917 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, f256mem,
6918 memopv4f64, int_x86_avx_blendv_pd_256>, VEX_L;
6919 } // ExeDomain = SSEPackedDouble
6920 let ExeDomain = SSEPackedSingle in {
6921 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, f128mem,
6922 memopv4f32, int_x86_sse41_blendvps>;
6923 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, f256mem,
6924 memopv8f32, int_x86_avx_blendv_ps_256>, VEX_L;
6925 } // ExeDomain = SSEPackedSingle
6926 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
6927 memopv2i64, int_x86_sse41_pblendvb>;
6930 let Predicates = [HasAVX2] in {
6931 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
6932 memopv4i64, int_x86_avx2_pblendvb>, VEX_L;
6935 let Predicates = [HasAVX] in {
6936 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
6937 (v16i8 VR128:$src2))),
6938 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6939 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
6940 (v4i32 VR128:$src2))),
6941 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6942 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
6943 (v4f32 VR128:$src2))),
6944 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6945 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
6946 (v2i64 VR128:$src2))),
6947 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6948 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
6949 (v2f64 VR128:$src2))),
6950 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6951 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
6952 (v8i32 VR256:$src2))),
6953 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6954 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
6955 (v8f32 VR256:$src2))),
6956 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6957 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
6958 (v4i64 VR256:$src2))),
6959 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6960 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
6961 (v4f64 VR256:$src2))),
6962 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6964 def : Pat<(v8f32 (X86Blendi (v8f32 VR256:$src1), (v8f32 VR256:$src2),
6966 (VBLENDPSYrri VR256:$src1, VR256:$src2, imm:$mask)>;
6967 def : Pat<(v4f64 (X86Blendi (v4f64 VR256:$src1), (v4f64 VR256:$src2),
6969 (VBLENDPDYrri VR256:$src1, VR256:$src2, imm:$mask)>;
6971 def : Pat<(v8i16 (X86Blendi (v8i16 VR128:$src1), (v8i16 VR128:$src2),
6973 (VPBLENDWrri VR128:$src1, VR128:$src2, imm:$mask)>;
6974 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$src1), (v4f32 VR128:$src2),
6976 (VBLENDPSrri VR128:$src1, VR128:$src2, imm:$mask)>;
6977 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$src1), (v2f64 VR128:$src2),
6979 (VBLENDPDrri VR128:$src1, VR128:$src2, imm:$mask)>;
6982 let Predicates = [HasAVX2] in {
6983 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
6984 (v32i8 VR256:$src2))),
6985 (VPBLENDVBYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
6986 def : Pat<(v16i16 (X86Blendi (v16i16 VR256:$src1), (v16i16 VR256:$src2),
6988 (VPBLENDWYrri VR256:$src1, VR256:$src2, imm:$mask)>;
6991 /// SS41I_ternary_int - SSE 4.1 ternary operator
6992 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
6993 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
6994 X86MemOperand x86memop, Intrinsic IntId> {
6995 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6996 (ins VR128:$src1, VR128:$src2),
6997 !strconcat(OpcodeStr,
6998 "\t{$src2, $dst|$dst, $src2}"),
6999 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
7002 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
7003 (ins VR128:$src1, x86memop:$src2),
7004 !strconcat(OpcodeStr,
7005 "\t{$src2, $dst|$dst, $src2}"),
7008 (bitconvert (mem_frag addr:$src2)), XMM0))]>, OpSize;
7012 let ExeDomain = SSEPackedDouble in
7013 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64, f128mem,
7014 int_x86_sse41_blendvpd>;
7015 let ExeDomain = SSEPackedSingle in
7016 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32, f128mem,
7017 int_x86_sse41_blendvps>;
7018 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64, i128mem,
7019 int_x86_sse41_pblendvb>;
7021 // Aliases with the implicit xmm0 argument
7022 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
7023 (BLENDVPDrr0 VR128:$dst, VR128:$src2)>;
7024 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
7025 (BLENDVPDrm0 VR128:$dst, f128mem:$src2)>;
7026 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
7027 (BLENDVPSrr0 VR128:$dst, VR128:$src2)>;
7028 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
7029 (BLENDVPSrm0 VR128:$dst, f128mem:$src2)>;
7030 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
7031 (PBLENDVBrr0 VR128:$dst, VR128:$src2)>;
7032 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
7033 (PBLENDVBrm0 VR128:$dst, i128mem:$src2)>;
7035 let Predicates = [UseSSE41] in {
7036 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
7037 (v16i8 VR128:$src2))),
7038 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
7039 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
7040 (v4i32 VR128:$src2))),
7041 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7042 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
7043 (v4f32 VR128:$src2))),
7044 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7045 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
7046 (v2i64 VR128:$src2))),
7047 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7048 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
7049 (v2f64 VR128:$src2))),
7050 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7052 def : Pat<(v8i16 (X86Blendi (v8i16 VR128:$src1), (v8i16 VR128:$src2),
7054 (PBLENDWrri VR128:$src1, VR128:$src2, imm:$mask)>;
7055 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$src1), (v4f32 VR128:$src2),
7057 (BLENDPSrri VR128:$src1, VR128:$src2, imm:$mask)>;
7058 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$src1), (v2f64 VR128:$src2),
7060 (BLENDPDrri VR128:$src1, VR128:$src2, imm:$mask)>;
7064 let Predicates = [HasAVX] in
7065 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7066 "vmovntdqa\t{$src, $dst|$dst, $src}",
7067 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
7069 let Predicates = [HasAVX2] in
7070 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
7071 "vmovntdqa\t{$src, $dst|$dst, $src}",
7072 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
7074 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7075 "movntdqa\t{$src, $dst|$dst, $src}",
7076 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
7079 //===----------------------------------------------------------------------===//
7080 // SSE4.2 - Compare Instructions
7081 //===----------------------------------------------------------------------===//
7083 /// SS42I_binop_rm - Simple SSE 4.2 binary operator
7084 multiclass SS42I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7085 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
7086 X86MemOperand x86memop, bit Is2Addr = 1> {
7087 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
7088 (ins RC:$src1, RC:$src2),
7090 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7091 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7092 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
7094 def rm : SS428I<opc, MRMSrcMem, (outs RC:$dst),
7095 (ins RC:$src1, x86memop:$src2),
7097 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7098 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7100 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>, OpSize;
7103 let Predicates = [HasAVX] in
7104 defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128,
7105 memopv2i64, i128mem, 0>, VEX_4V;
7107 let Predicates = [HasAVX2] in
7108 defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256,
7109 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
7111 let Constraints = "$src1 = $dst" in
7112 defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128,
7113 memopv2i64, i128mem>;
7115 //===----------------------------------------------------------------------===//
7116 // SSE4.2 - String/text Processing Instructions
7117 //===----------------------------------------------------------------------===//
7119 // Packed Compare Implicit Length Strings, Return Mask
7120 multiclass pseudo_pcmpistrm<string asm> {
7121 def REG : PseudoI<(outs VR128:$dst),
7122 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7123 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
7125 def MEM : PseudoI<(outs VR128:$dst),
7126 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7127 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1,
7128 (bc_v16i8 (memopv2i64 addr:$src2)), imm:$src3))]>;
7131 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7132 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
7133 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[UseSSE42]>;
7136 multiclass pcmpistrm_SS42AI<string asm> {
7137 def rr : SS42AI<0x62, MRMSrcReg, (outs),
7138 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7139 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7142 def rm :SS42AI<0x62, MRMSrcMem, (outs),
7143 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7144 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7148 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1 in {
7149 let Predicates = [HasAVX] in
7150 defm VPCMPISTRM128 : pcmpistrm_SS42AI<"vpcmpistrm">, VEX;
7151 defm PCMPISTRM128 : pcmpistrm_SS42AI<"pcmpistrm"> ;
7154 // Packed Compare Explicit Length Strings, Return Mask
7155 multiclass pseudo_pcmpestrm<string asm> {
7156 def REG : PseudoI<(outs VR128:$dst),
7157 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7158 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
7159 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7160 def MEM : PseudoI<(outs VR128:$dst),
7161 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7162 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128 VR128:$src1, EAX,
7163 (bc_v16i8 (memopv2i64 addr:$src3)), EDX, imm:$src5))]>;
7166 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7167 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
7168 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[UseSSE42]>;
7171 multiclass SS42AI_pcmpestrm<string asm> {
7172 def rr : SS42AI<0x60, MRMSrcReg, (outs),
7173 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7174 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7177 def rm : SS42AI<0x60, MRMSrcMem, (outs),
7178 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7179 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7183 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
7184 let Predicates = [HasAVX] in
7185 defm VPCMPESTRM128 : SS42AI_pcmpestrm<"vpcmpestrm">, VEX;
7186 defm PCMPESTRM128 : SS42AI_pcmpestrm<"pcmpestrm">;
7189 // Packed Compare Implicit Length Strings, Return Index
7190 multiclass pseudo_pcmpistri<string asm> {
7191 def REG : PseudoI<(outs GR32:$dst),
7192 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7193 [(set GR32:$dst, EFLAGS,
7194 (X86pcmpistri VR128:$src1, VR128:$src2, imm:$src3))]>;
7195 def MEM : PseudoI<(outs GR32:$dst),
7196 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7197 [(set GR32:$dst, EFLAGS, (X86pcmpistri VR128:$src1,
7198 (bc_v16i8 (memopv2i64 addr:$src2)), imm:$src3))]>;
7201 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7202 defm VPCMPISTRI : pseudo_pcmpistri<"#VPCMPISTRI">, Requires<[HasAVX]>;
7203 defm PCMPISTRI : pseudo_pcmpistri<"#PCMPISTRI">, Requires<[UseSSE42]>;
7206 multiclass SS42AI_pcmpistri<string asm> {
7207 def rr : SS42AI<0x63, MRMSrcReg, (outs),
7208 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7209 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7212 def rm : SS42AI<0x63, MRMSrcMem, (outs),
7213 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7214 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7218 let Defs = [ECX, EFLAGS], neverHasSideEffects = 1 in {
7219 let Predicates = [HasAVX] in
7220 defm VPCMPISTRI : SS42AI_pcmpistri<"vpcmpistri">, VEX;
7221 defm PCMPISTRI : SS42AI_pcmpistri<"pcmpistri">;
7224 // Packed Compare Explicit Length Strings, Return Index
7225 multiclass pseudo_pcmpestri<string asm> {
7226 def REG : PseudoI<(outs GR32:$dst),
7227 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7228 [(set GR32:$dst, EFLAGS,
7229 (X86pcmpestri VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7230 def MEM : PseudoI<(outs GR32:$dst),
7231 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7232 [(set GR32:$dst, EFLAGS,
7233 (X86pcmpestri VR128:$src1, EAX, (bc_v16i8 (memopv2i64 addr:$src3)), EDX,
7237 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7238 defm VPCMPESTRI : pseudo_pcmpestri<"#VPCMPESTRI">, Requires<[HasAVX]>;
7239 defm PCMPESTRI : pseudo_pcmpestri<"#PCMPESTRI">, Requires<[UseSSE42]>;
7242 multiclass SS42AI_pcmpestri<string asm> {
7243 def rr : SS42AI<0x61, MRMSrcReg, (outs),
7244 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7245 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7248 def rm : SS42AI<0x61, MRMSrcMem, (outs),
7249 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7250 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7254 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
7255 let Predicates = [HasAVX] in
7256 defm VPCMPESTRI : SS42AI_pcmpestri<"vpcmpestri">, VEX;
7257 defm PCMPESTRI : SS42AI_pcmpestri<"pcmpestri">;
7260 //===----------------------------------------------------------------------===//
7261 // SSE4.2 - CRC Instructions
7262 //===----------------------------------------------------------------------===//
7264 // No CRC instructions have AVX equivalents
7266 // crc intrinsic instruction
7267 // This set of instructions are only rm, the only difference is the size
7269 let Constraints = "$src1 = $dst" in {
7270 def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
7271 (ins GR32:$src1, i8mem:$src2),
7272 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7274 (int_x86_sse42_crc32_32_8 GR32:$src1,
7275 (load addr:$src2)))]>;
7276 def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
7277 (ins GR32:$src1, GR8:$src2),
7278 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7280 (int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))]>;
7281 def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
7282 (ins GR32:$src1, i16mem:$src2),
7283 "crc32{w} \t{$src2, $src1|$src1, $src2}",
7285 (int_x86_sse42_crc32_32_16 GR32:$src1,
7286 (load addr:$src2)))]>,
7288 def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
7289 (ins GR32:$src1, GR16:$src2),
7290 "crc32{w} \t{$src2, $src1|$src1, $src2}",
7292 (int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))]>,
7294 def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
7295 (ins GR32:$src1, i32mem:$src2),
7296 "crc32{l} \t{$src2, $src1|$src1, $src2}",
7298 (int_x86_sse42_crc32_32_32 GR32:$src1,
7299 (load addr:$src2)))]>;
7300 def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
7301 (ins GR32:$src1, GR32:$src2),
7302 "crc32{l} \t{$src2, $src1|$src1, $src2}",
7304 (int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))]>;
7305 def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
7306 (ins GR64:$src1, i8mem:$src2),
7307 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7309 (int_x86_sse42_crc32_64_8 GR64:$src1,
7310 (load addr:$src2)))]>,
7312 def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
7313 (ins GR64:$src1, GR8:$src2),
7314 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7316 (int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))]>,
7318 def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
7319 (ins GR64:$src1, i64mem:$src2),
7320 "crc32{q} \t{$src2, $src1|$src1, $src2}",
7322 (int_x86_sse42_crc32_64_64 GR64:$src1,
7323 (load addr:$src2)))]>,
7325 def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
7326 (ins GR64:$src1, GR64:$src2),
7327 "crc32{q} \t{$src2, $src1|$src1, $src2}",
7329 (int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))]>,
7333 //===----------------------------------------------------------------------===//
7334 // AES-NI Instructions
7335 //===----------------------------------------------------------------------===//
7337 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
7338 Intrinsic IntId128, bit Is2Addr = 1> {
7339 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
7340 (ins VR128:$src1, VR128:$src2),
7342 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7343 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7344 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
7346 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
7347 (ins VR128:$src1, i128mem:$src2),
7349 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7350 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7352 (IntId128 VR128:$src1, (memopv2i64 addr:$src2)))]>, OpSize;
7355 // Perform One Round of an AES Encryption/Decryption Flow
7356 let Predicates = [HasAVX, HasAES] in {
7357 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
7358 int_x86_aesni_aesenc, 0>, VEX_4V;
7359 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
7360 int_x86_aesni_aesenclast, 0>, VEX_4V;
7361 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
7362 int_x86_aesni_aesdec, 0>, VEX_4V;
7363 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
7364 int_x86_aesni_aesdeclast, 0>, VEX_4V;
7367 let Constraints = "$src1 = $dst" in {
7368 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
7369 int_x86_aesni_aesenc>;
7370 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
7371 int_x86_aesni_aesenclast>;
7372 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
7373 int_x86_aesni_aesdec>;
7374 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
7375 int_x86_aesni_aesdeclast>;
7378 // Perform the AES InvMixColumn Transformation
7379 let Predicates = [HasAVX, HasAES] in {
7380 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7382 "vaesimc\t{$src1, $dst|$dst, $src1}",
7384 (int_x86_aesni_aesimc VR128:$src1))]>,
7386 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7387 (ins i128mem:$src1),
7388 "vaesimc\t{$src1, $dst|$dst, $src1}",
7389 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7392 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7394 "aesimc\t{$src1, $dst|$dst, $src1}",
7396 (int_x86_aesni_aesimc VR128:$src1))]>,
7398 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7399 (ins i128mem:$src1),
7400 "aesimc\t{$src1, $dst|$dst, $src1}",
7401 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7404 // AES Round Key Generation Assist
7405 let Predicates = [HasAVX, HasAES] in {
7406 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7407 (ins VR128:$src1, i8imm:$src2),
7408 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7410 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7412 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7413 (ins i128mem:$src1, i8imm:$src2),
7414 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7416 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7419 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7420 (ins VR128:$src1, i8imm:$src2),
7421 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7423 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7425 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7426 (ins i128mem:$src1, i8imm:$src2),
7427 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7429 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7432 //===----------------------------------------------------------------------===//
7433 // PCLMUL Instructions
7434 //===----------------------------------------------------------------------===//
7436 // AVX carry-less Multiplication instructions
7437 def VPCLMULQDQrr : AVXPCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7438 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7439 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7441 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>;
7443 def VPCLMULQDQrm : AVXPCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7444 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7445 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7446 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7447 (memopv2i64 addr:$src2), imm:$src3))]>;
7449 // Carry-less Multiplication instructions
7450 let Constraints = "$src1 = $dst" in {
7451 def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7452 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7453 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7455 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>;
7457 def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7458 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7459 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7460 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7461 (memopv2i64 addr:$src2), imm:$src3))]>;
7462 } // Constraints = "$src1 = $dst"
7465 multiclass pclmul_alias<string asm, int immop> {
7466 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7467 (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
7469 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7470 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
7472 def : InstAlias<!strconcat("vpclmul", asm,
7473 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7474 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
7476 def : InstAlias<!strconcat("vpclmul", asm,
7477 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7478 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
7480 defm : pclmul_alias<"hqhq", 0x11>;
7481 defm : pclmul_alias<"hqlq", 0x01>;
7482 defm : pclmul_alias<"lqhq", 0x10>;
7483 defm : pclmul_alias<"lqlq", 0x00>;
7485 //===----------------------------------------------------------------------===//
7486 // SSE4A Instructions
7487 //===----------------------------------------------------------------------===//
7489 let Predicates = [HasSSE4A] in {
7491 let Constraints = "$src = $dst" in {
7492 def EXTRQI : Ii8<0x78, MRM0r, (outs VR128:$dst),
7493 (ins VR128:$src, i8imm:$len, i8imm:$idx),
7494 "extrq\t{$idx, $len, $src|$src, $len, $idx}",
7495 [(set VR128:$dst, (int_x86_sse4a_extrqi VR128:$src, imm:$len,
7496 imm:$idx))]>, TB, OpSize;
7497 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7498 (ins VR128:$src, VR128:$mask),
7499 "extrq\t{$mask, $src|$src, $mask}",
7500 [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src,
7501 VR128:$mask))]>, TB, OpSize;
7503 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
7504 (ins VR128:$src, VR128:$src2, i8imm:$len, i8imm:$idx),
7505 "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}",
7506 [(set VR128:$dst, (int_x86_sse4a_insertqi VR128:$src,
7507 VR128:$src2, imm:$len, imm:$idx))]>, XD;
7508 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7509 (ins VR128:$src, VR128:$mask),
7510 "insertq\t{$mask, $src|$src, $mask}",
7511 [(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src,
7512 VR128:$mask))]>, XD;
7515 def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
7516 "movntss\t{$src, $dst|$dst, $src}",
7517 [(int_x86_sse4a_movnt_ss addr:$dst, VR128:$src)]>, XS;
7519 def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
7520 "movntsd\t{$src, $dst|$dst, $src}",
7521 [(int_x86_sse4a_movnt_sd addr:$dst, VR128:$src)]>, XD;
7524 //===----------------------------------------------------------------------===//
7526 //===----------------------------------------------------------------------===//
7528 //===----------------------------------------------------------------------===//
7529 // VBROADCAST - Load from memory and broadcast to all elements of the
7530 // destination operand
7532 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
7533 X86MemOperand x86memop, Intrinsic Int> :
7534 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7535 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7536 [(set RC:$dst, (Int addr:$src))]>, VEX;
7538 // AVX2 adds register forms
7539 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
7541 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7542 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7543 [(set RC:$dst, (Int VR128:$src))]>, VEX;
7545 let ExeDomain = SSEPackedSingle in {
7546 def VBROADCASTSSrm : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
7547 int_x86_avx_vbroadcast_ss>;
7548 def VBROADCASTSSYrm : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
7549 int_x86_avx_vbroadcast_ss_256>, VEX_L;
7551 let ExeDomain = SSEPackedDouble in
7552 def VBROADCASTSDYrm : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
7553 int_x86_avx_vbroadcast_sd_256>, VEX_L;
7554 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
7555 int_x86_avx_vbroadcastf128_pd_256>, VEX_L;
7557 let ExeDomain = SSEPackedSingle in {
7558 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
7559 int_x86_avx2_vbroadcast_ss_ps>;
7560 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
7561 int_x86_avx2_vbroadcast_ss_ps_256>, VEX_L;
7563 let ExeDomain = SSEPackedDouble in
7564 def VBROADCASTSDYrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
7565 int_x86_avx2_vbroadcast_sd_pd_256>, VEX_L;
7567 let Predicates = [HasAVX2] in
7568 def VBROADCASTI128 : avx_broadcast<0x5A, "vbroadcasti128", VR256, i128mem,
7569 int_x86_avx2_vbroadcasti128>, VEX_L;
7571 let Predicates = [HasAVX] in
7572 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
7573 (VBROADCASTF128 addr:$src)>;
7576 //===----------------------------------------------------------------------===//
7577 // VINSERTF128 - Insert packed floating-point values
7579 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7580 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
7581 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7582 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7585 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
7586 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
7587 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7591 let Predicates = [HasAVX] in {
7592 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
7594 (VINSERTF128rr VR256:$src1, VR128:$src2,
7595 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7596 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
7598 (VINSERTF128rr VR256:$src1, VR128:$src2,
7599 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7601 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (memopv4f32 addr:$src2),
7603 (VINSERTF128rm VR256:$src1, addr:$src2,
7604 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7605 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (memopv2f64 addr:$src2),
7607 (VINSERTF128rm VR256:$src1, addr:$src2,
7608 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7611 let Predicates = [HasAVX1Only] in {
7612 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7614 (VINSERTF128rr VR256:$src1, VR128:$src2,
7615 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7616 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7618 (VINSERTF128rr VR256:$src1, VR128:$src2,
7619 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7620 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7622 (VINSERTF128rr VR256:$src1, VR128:$src2,
7623 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7624 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7626 (VINSERTF128rr VR256:$src1, VR128:$src2,
7627 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7629 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (memopv2i64 addr:$src2),
7631 (VINSERTF128rm VR256:$src1, addr:$src2,
7632 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7633 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1),
7634 (bc_v4i32 (memopv2i64 addr:$src2)),
7636 (VINSERTF128rm VR256:$src1, addr:$src2,
7637 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7638 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1),
7639 (bc_v16i8 (memopv2i64 addr:$src2)),
7641 (VINSERTF128rm VR256:$src1, addr:$src2,
7642 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7643 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1),
7644 (bc_v8i16 (memopv2i64 addr:$src2)),
7646 (VINSERTF128rm VR256:$src1, addr:$src2,
7647 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7650 //===----------------------------------------------------------------------===//
7651 // VEXTRACTF128 - Extract packed floating-point values
7653 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7654 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
7655 (ins VR256:$src1, i8imm:$src2),
7656 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7659 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
7660 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
7661 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7666 let Predicates = [HasAVX] in {
7667 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7668 (v4f32 (VEXTRACTF128rr
7669 (v8f32 VR256:$src1),
7670 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7671 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7672 (v2f64 (VEXTRACTF128rr
7673 (v4f64 VR256:$src1),
7674 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7676 def : Pat<(alignedstore (v4f32 (vextractf128_extract:$ext (v8f32 VR256:$src1),
7677 (iPTR imm))), addr:$dst),
7678 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7679 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7680 def : Pat<(alignedstore (v2f64 (vextractf128_extract:$ext (v4f64 VR256:$src1),
7681 (iPTR imm))), addr:$dst),
7682 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7683 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7686 let Predicates = [HasAVX1Only] in {
7687 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7688 (v2i64 (VEXTRACTF128rr
7689 (v4i64 VR256:$src1),
7690 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7691 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7692 (v4i32 (VEXTRACTF128rr
7693 (v8i32 VR256:$src1),
7694 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7695 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7696 (v8i16 (VEXTRACTF128rr
7697 (v16i16 VR256:$src1),
7698 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7699 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7700 (v16i8 (VEXTRACTF128rr
7701 (v32i8 VR256:$src1),
7702 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7704 def : Pat<(alignedstore (v2i64 (vextractf128_extract:$ext (v4i64 VR256:$src1),
7705 (iPTR imm))), addr:$dst),
7706 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7707 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7708 def : Pat<(alignedstore (v4i32 (vextractf128_extract:$ext (v8i32 VR256:$src1),
7709 (iPTR imm))), addr:$dst),
7710 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7711 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7712 def : Pat<(alignedstore (v8i16 (vextractf128_extract:$ext (v16i16 VR256:$src1),
7713 (iPTR imm))), addr:$dst),
7714 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7715 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7716 def : Pat<(alignedstore (v16i8 (vextractf128_extract:$ext (v32i8 VR256:$src1),
7717 (iPTR imm))), addr:$dst),
7718 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7719 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7722 //===----------------------------------------------------------------------===//
7723 // VMASKMOV - Conditional SIMD Packed Loads and Stores
7725 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
7726 Intrinsic IntLd, Intrinsic IntLd256,
7727 Intrinsic IntSt, Intrinsic IntSt256> {
7728 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
7729 (ins VR128:$src1, f128mem:$src2),
7730 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7731 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
7733 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
7734 (ins VR256:$src1, f256mem:$src2),
7735 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7736 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
7738 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
7739 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
7740 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7741 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
7742 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
7743 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
7744 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7745 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
7748 let ExeDomain = SSEPackedSingle in
7749 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
7750 int_x86_avx_maskload_ps,
7751 int_x86_avx_maskload_ps_256,
7752 int_x86_avx_maskstore_ps,
7753 int_x86_avx_maskstore_ps_256>;
7754 let ExeDomain = SSEPackedDouble in
7755 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
7756 int_x86_avx_maskload_pd,
7757 int_x86_avx_maskload_pd_256,
7758 int_x86_avx_maskstore_pd,
7759 int_x86_avx_maskstore_pd_256>;
7761 //===----------------------------------------------------------------------===//
7762 // VPERMIL - Permute Single and Double Floating-Point Values
7764 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
7765 RegisterClass RC, X86MemOperand x86memop_f,
7766 X86MemOperand x86memop_i, PatFrag i_frag,
7767 Intrinsic IntVar, ValueType vt> {
7768 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
7769 (ins RC:$src1, RC:$src2),
7770 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7771 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
7772 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
7773 (ins RC:$src1, x86memop_i:$src2),
7774 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7775 [(set RC:$dst, (IntVar RC:$src1,
7776 (bitconvert (i_frag addr:$src2))))]>, VEX_4V;
7778 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
7779 (ins RC:$src1, i8imm:$src2),
7780 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7781 [(set RC:$dst, (vt (X86VPermilp RC:$src1, (i8 imm:$src2))))]>, VEX;
7782 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
7783 (ins x86memop_f:$src1, i8imm:$src2),
7784 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7786 (vt (X86VPermilp (memop addr:$src1), (i8 imm:$src2))))]>, VEX;
7789 let ExeDomain = SSEPackedSingle in {
7790 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
7791 memopv2i64, int_x86_avx_vpermilvar_ps, v4f32>;
7792 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
7793 memopv4i64, int_x86_avx_vpermilvar_ps_256, v8f32>, VEX_L;
7795 let ExeDomain = SSEPackedDouble in {
7796 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
7797 memopv2i64, int_x86_avx_vpermilvar_pd, v2f64>;
7798 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
7799 memopv4i64, int_x86_avx_vpermilvar_pd_256, v4f64>, VEX_L;
7802 let Predicates = [HasAVX] in {
7803 def : Pat<(v8i32 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7804 (VPERMILPSYri VR256:$src1, imm:$imm)>;
7805 def : Pat<(v4i64 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7806 (VPERMILPDYri VR256:$src1, imm:$imm)>;
7807 def : Pat<(v8i32 (X86VPermilp (bc_v8i32 (memopv4i64 addr:$src1)),
7809 (VPERMILPSYmi addr:$src1, imm:$imm)>;
7810 def : Pat<(v4i64 (X86VPermilp (memopv4i64 addr:$src1), (i8 imm:$imm))),
7811 (VPERMILPDYmi addr:$src1, imm:$imm)>;
7813 def : Pat<(v2i64 (X86VPermilp VR128:$src1, (i8 imm:$imm))),
7814 (VPERMILPDri VR128:$src1, imm:$imm)>;
7815 def : Pat<(v2i64 (X86VPermilp (memopv2i64 addr:$src1), (i8 imm:$imm))),
7816 (VPERMILPDmi addr:$src1, imm:$imm)>;
7819 //===----------------------------------------------------------------------===//
7820 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
7822 let ExeDomain = SSEPackedSingle in {
7823 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
7824 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7825 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7826 [(set VR256:$dst, (v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2,
7827 (i8 imm:$src3))))]>, VEX_4V, VEX_L;
7828 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
7829 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7830 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7831 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv8f32 addr:$src2),
7832 (i8 imm:$src3)))]>, VEX_4V, VEX_L;
7835 let Predicates = [HasAVX] in {
7836 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7837 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7838 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
7839 (memopv4f64 addr:$src2), (i8 imm:$imm))),
7840 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7843 let Predicates = [HasAVX1Only] in {
7844 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7845 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7846 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7847 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7848 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7849 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7850 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7851 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7853 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
7854 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7855 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7856 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
7857 (memopv4i64 addr:$src2), (i8 imm:$imm))),
7858 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7859 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
7860 (bc_v32i8 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7861 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7862 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
7863 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7864 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7867 //===----------------------------------------------------------------------===//
7868 // VZERO - Zero YMM registers
7870 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
7871 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
7872 // Zero All YMM registers
7873 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
7874 [(int_x86_avx_vzeroall)]>, TB, VEX, VEX_L, Requires<[HasAVX]>;
7876 // Zero Upper bits of YMM registers
7877 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
7878 [(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>;
7881 //===----------------------------------------------------------------------===//
7882 // Half precision conversion instructions
7883 //===----------------------------------------------------------------------===//
7884 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7885 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7886 "vcvtph2ps\t{$src, $dst|$dst, $src}",
7887 [(set RC:$dst, (Int VR128:$src))]>,
7889 let neverHasSideEffects = 1, mayLoad = 1 in
7890 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7891 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8, OpSize, VEX;
7894 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7895 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
7896 (ins RC:$src1, i32i8imm:$src2),
7897 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7898 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
7900 let neverHasSideEffects = 1, mayStore = 1 in
7901 def mr : Ii8<0x1D, MRMDestMem, (outs),
7902 (ins x86memop:$dst, RC:$src1, i32i8imm:$src2),
7903 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
7907 let Predicates = [HasAVX, HasF16C] in {
7908 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
7909 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>, VEX_L;
7910 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
7911 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>, VEX_L;
7914 //===----------------------------------------------------------------------===//
7915 // AVX2 Instructions
7916 //===----------------------------------------------------------------------===//
7918 /// AVX2_binop_rmi_int - AVX2 binary operator with 8-bit immediate
7919 multiclass AVX2_binop_rmi_int<bits<8> opc, string OpcodeStr,
7920 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
7921 X86MemOperand x86memop> {
7922 let isCommutable = 1 in
7923 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
7924 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
7925 !strconcat(OpcodeStr,
7926 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7927 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
7929 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
7930 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
7931 !strconcat(OpcodeStr,
7932 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7935 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
7939 let isCommutable = 0 in {
7940 defm VPBLENDD : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_128,
7941 VR128, memopv2i64, i128mem>;
7942 defm VPBLENDDY : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_256,
7943 VR256, memopv4i64, i256mem>, VEX_L;
7946 def : Pat<(v4i32 (X86Blendi (v4i32 VR128:$src1), (v4i32 VR128:$src2),
7948 (VPBLENDDrri VR128:$src1, VR128:$src2, imm:$mask)>;
7949 def : Pat<(v8i32 (X86Blendi (v8i32 VR256:$src1), (v8i32 VR256:$src2),
7951 (VPBLENDDYrri VR256:$src1, VR256:$src2, imm:$mask)>;
7953 //===----------------------------------------------------------------------===//
7954 // VPBROADCAST - Load from memory and broadcast to all elements of the
7955 // destination operand
7957 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
7958 X86MemOperand x86memop, PatFrag ld_frag,
7959 Intrinsic Int128, Intrinsic Int256> {
7960 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
7961 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7962 [(set VR128:$dst, (Int128 VR128:$src))]>, VEX;
7963 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
7964 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7966 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
7967 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
7968 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7969 [(set VR256:$dst, (Int256 VR128:$src))]>, VEX, VEX_L;
7970 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
7971 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7973 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>,
7977 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
7978 int_x86_avx2_pbroadcastb_128,
7979 int_x86_avx2_pbroadcastb_256>;
7980 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
7981 int_x86_avx2_pbroadcastw_128,
7982 int_x86_avx2_pbroadcastw_256>;
7983 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
7984 int_x86_avx2_pbroadcastd_128,
7985 int_x86_avx2_pbroadcastd_256>;
7986 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
7987 int_x86_avx2_pbroadcastq_128,
7988 int_x86_avx2_pbroadcastq_256>;
7990 let Predicates = [HasAVX2] in {
7991 def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
7992 (VPBROADCASTBrm addr:$src)>;
7993 def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
7994 (VPBROADCASTBYrm addr:$src)>;
7995 def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
7996 (VPBROADCASTWrm addr:$src)>;
7997 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
7998 (VPBROADCASTWYrm addr:$src)>;
7999 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8000 (VPBROADCASTDrm addr:$src)>;
8001 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8002 (VPBROADCASTDYrm addr:$src)>;
8003 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
8004 (VPBROADCASTQrm addr:$src)>;
8005 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8006 (VPBROADCASTQYrm addr:$src)>;
8008 def : Pat<(v16i8 (X86VBroadcast (v16i8 VR128:$src))),
8009 (VPBROADCASTBrr VR128:$src)>;
8010 def : Pat<(v32i8 (X86VBroadcast (v16i8 VR128:$src))),
8011 (VPBROADCASTBYrr VR128:$src)>;
8012 def : Pat<(v8i16 (X86VBroadcast (v8i16 VR128:$src))),
8013 (VPBROADCASTWrr VR128:$src)>;
8014 def : Pat<(v16i16 (X86VBroadcast (v8i16 VR128:$src))),
8015 (VPBROADCASTWYrr VR128:$src)>;
8016 def : Pat<(v4i32 (X86VBroadcast (v4i32 VR128:$src))),
8017 (VPBROADCASTDrr VR128:$src)>;
8018 def : Pat<(v8i32 (X86VBroadcast (v4i32 VR128:$src))),
8019 (VPBROADCASTDYrr VR128:$src)>;
8020 def : Pat<(v2i64 (X86VBroadcast (v2i64 VR128:$src))),
8021 (VPBROADCASTQrr VR128:$src)>;
8022 def : Pat<(v4i64 (X86VBroadcast (v2i64 VR128:$src))),
8023 (VPBROADCASTQYrr VR128:$src)>;
8024 def : Pat<(v4f32 (X86VBroadcast (v4f32 VR128:$src))),
8025 (VBROADCASTSSrr VR128:$src)>;
8026 def : Pat<(v8f32 (X86VBroadcast (v4f32 VR128:$src))),
8027 (VBROADCASTSSYrr VR128:$src)>;
8028 def : Pat<(v2f64 (X86VBroadcast (v2f64 VR128:$src))),
8029 (VPBROADCASTQrr VR128:$src)>;
8030 def : Pat<(v4f64 (X86VBroadcast (v2f64 VR128:$src))),
8031 (VBROADCASTSDYrr VR128:$src)>;
8033 // Provide fallback in case the load node that is used in the patterns above
8034 // is used by additional users, which prevents the pattern selection.
8035 let AddedComplexity = 20 in {
8036 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8037 (VBROADCASTSSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8038 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8039 (VBROADCASTSSYrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8040 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8041 (VBROADCASTSDYrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
8043 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8044 (VBROADCASTSSrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8045 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8046 (VBROADCASTSSYrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8047 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8048 (VBROADCASTSDYrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8052 // AVX1 broadcast patterns
8053 let Predicates = [HasAVX1Only] in {
8054 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8055 (VBROADCASTSSYrm addr:$src)>;
8056 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8057 (VBROADCASTSDYrm addr:$src)>;
8058 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8059 (VBROADCASTSSrm addr:$src)>;
8062 let Predicates = [HasAVX] in {
8063 def : Pat<(v8f32 (X86VBroadcast (loadf32 addr:$src))),
8064 (VBROADCASTSSYrm addr:$src)>;
8065 def : Pat<(v4f64 (X86VBroadcast (loadf64 addr:$src))),
8066 (VBROADCASTSDYrm addr:$src)>;
8067 def : Pat<(v4f32 (X86VBroadcast (loadf32 addr:$src))),
8068 (VBROADCASTSSrm addr:$src)>;
8070 // Provide fallback in case the load node that is used in the patterns above
8071 // is used by additional users, which prevents the pattern selection.
8072 let AddedComplexity = 20 in {
8073 // 128bit broadcasts:
8074 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8075 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0)>;
8076 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8077 (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
8078 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), sub_xmm),
8079 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), 1)>;
8080 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8081 (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
8082 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), sub_xmm),
8083 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), 1)>;
8085 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8086 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0)>;
8087 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8088 (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)),
8089 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), sub_xmm),
8090 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), 1)>;
8091 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8092 (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)),
8093 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), sub_xmm),
8094 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), 1)>;
8098 //===----------------------------------------------------------------------===//
8099 // VPERM - Permute instructions
8102 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8104 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8105 (ins VR256:$src1, VR256:$src2),
8106 !strconcat(OpcodeStr,
8107 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8109 (OpVT (X86VPermv VR256:$src1, VR256:$src2)))]>,
8111 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8112 (ins VR256:$src1, i256mem:$src2),
8113 !strconcat(OpcodeStr,
8114 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8116 (OpVT (X86VPermv VR256:$src1,
8117 (bitconvert (mem_frag addr:$src2)))))]>,
8121 defm VPERMD : avx2_perm<0x36, "vpermd", memopv4i64, v8i32>;
8122 let ExeDomain = SSEPackedSingle in
8123 defm VPERMPS : avx2_perm<0x16, "vpermps", memopv8f32, v8f32>;
8125 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8127 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
8128 (ins VR256:$src1, i8imm:$src2),
8129 !strconcat(OpcodeStr,
8130 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8132 (OpVT (X86VPermi VR256:$src1, (i8 imm:$src2))))]>,
8134 def Ymi : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
8135 (ins i256mem:$src1, i8imm:$src2),
8136 !strconcat(OpcodeStr,
8137 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8139 (OpVT (X86VPermi (mem_frag addr:$src1),
8140 (i8 imm:$src2))))]>, VEX, VEX_L;
8143 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", memopv4i64, v4i64>, VEX_W;
8144 let ExeDomain = SSEPackedDouble in
8145 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", memopv4f64, v4f64>, VEX_W;
8147 //===----------------------------------------------------------------------===//
8148 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
8150 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
8151 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
8152 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8153 [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8154 (i8 imm:$src3))))]>, VEX_4V, VEX_L;
8155 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
8156 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
8157 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8158 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv4i64 addr:$src2),
8159 (i8 imm:$src3)))]>, VEX_4V, VEX_L;
8161 let Predicates = [HasAVX2] in {
8162 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8163 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8164 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8165 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8166 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8167 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8169 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (memopv4i64 addr:$src2)),
8171 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8172 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8173 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
8174 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8175 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)),
8177 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8181 //===----------------------------------------------------------------------===//
8182 // VINSERTI128 - Insert packed integer values
8184 let neverHasSideEffects = 1 in {
8185 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
8186 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
8187 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8190 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
8191 (ins VR256:$src1, i128mem:$src2, i8imm:$src3),
8192 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8196 let Predicates = [HasAVX2] in {
8197 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
8199 (VINSERTI128rr VR256:$src1, VR128:$src2,
8200 (INSERT_get_vinsertf128_imm VR256:$ins))>;
8201 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
8203 (VINSERTI128rr VR256:$src1, VR128:$src2,
8204 (INSERT_get_vinsertf128_imm VR256:$ins))>;
8205 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
8207 (VINSERTI128rr VR256:$src1, VR128:$src2,
8208 (INSERT_get_vinsertf128_imm VR256:$ins))>;
8209 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
8211 (VINSERTI128rr VR256:$src1, VR128:$src2,
8212 (INSERT_get_vinsertf128_imm VR256:$ins))>;
8214 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (memopv2i64 addr:$src2),
8216 (VINSERTI128rm VR256:$src1, addr:$src2,
8217 (INSERT_get_vinsertf128_imm VR256:$ins))>;
8218 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1),
8219 (bc_v4i32 (memopv2i64 addr:$src2)),
8221 (VINSERTI128rm VR256:$src1, addr:$src2,
8222 (INSERT_get_vinsertf128_imm VR256:$ins))>;
8223 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1),
8224 (bc_v16i8 (memopv2i64 addr:$src2)),
8226 (VINSERTI128rm VR256:$src1, addr:$src2,
8227 (INSERT_get_vinsertf128_imm VR256:$ins))>;
8228 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1),
8229 (bc_v8i16 (memopv2i64 addr:$src2)),
8231 (VINSERTI128rm VR256:$src1, addr:$src2,
8232 (INSERT_get_vinsertf128_imm VR256:$ins))>;
8235 //===----------------------------------------------------------------------===//
8236 // VEXTRACTI128 - Extract packed integer values
8238 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
8239 (ins VR256:$src1, i8imm:$src2),
8240 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8242 (int_x86_avx2_vextracti128 VR256:$src1, imm:$src2))]>,
8244 let neverHasSideEffects = 1, mayStore = 1 in
8245 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
8246 (ins i128mem:$dst, VR256:$src1, i8imm:$src2),
8247 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8250 let Predicates = [HasAVX2] in {
8251 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
8252 (v2i64 (VEXTRACTI128rr
8253 (v4i64 VR256:$src1),
8254 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
8255 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
8256 (v4i32 (VEXTRACTI128rr
8257 (v8i32 VR256:$src1),
8258 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
8259 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
8260 (v8i16 (VEXTRACTI128rr
8261 (v16i16 VR256:$src1),
8262 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
8263 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
8264 (v16i8 (VEXTRACTI128rr
8265 (v32i8 VR256:$src1),
8266 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
8268 def : Pat<(alignedstore (v2i64 (vextractf128_extract:$ext (v4i64 VR256:$src1),
8269 (iPTR imm))), addr:$dst),
8270 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8271 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
8272 def : Pat<(alignedstore (v4i32 (vextractf128_extract:$ext (v8i32 VR256:$src1),
8273 (iPTR imm))), addr:$dst),
8274 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8275 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
8276 def : Pat<(alignedstore (v8i16 (vextractf128_extract:$ext (v16i16 VR256:$src1),
8277 (iPTR imm))), addr:$dst),
8278 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8279 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
8280 def : Pat<(alignedstore (v16i8 (vextractf128_extract:$ext (v32i8 VR256:$src1),
8281 (iPTR imm))), addr:$dst),
8282 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8283 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
8286 //===----------------------------------------------------------------------===//
8287 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
8289 multiclass avx2_pmovmask<string OpcodeStr,
8290 Intrinsic IntLd128, Intrinsic IntLd256,
8291 Intrinsic IntSt128, Intrinsic IntSt256> {
8292 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
8293 (ins VR128:$src1, i128mem:$src2),
8294 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8295 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
8296 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
8297 (ins VR256:$src1, i256mem:$src2),
8298 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8299 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8301 def mr : AVX28I<0x8e, MRMDestMem, (outs),
8302 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
8303 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8304 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8305 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
8306 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
8307 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8308 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8311 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
8312 int_x86_avx2_maskload_d,
8313 int_x86_avx2_maskload_d_256,
8314 int_x86_avx2_maskstore_d,
8315 int_x86_avx2_maskstore_d_256>;
8316 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
8317 int_x86_avx2_maskload_q,
8318 int_x86_avx2_maskload_q_256,
8319 int_x86_avx2_maskstore_q,
8320 int_x86_avx2_maskstore_q_256>, VEX_W;
8323 //===----------------------------------------------------------------------===//
8324 // Variable Bit Shifts
8326 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
8327 ValueType vt128, ValueType vt256> {
8328 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
8329 (ins VR128:$src1, VR128:$src2),
8330 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8332 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
8334 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
8335 (ins VR128:$src1, i128mem:$src2),
8336 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8338 (vt128 (OpNode VR128:$src1,
8339 (vt128 (bitconvert (memopv2i64 addr:$src2))))))]>,
8341 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8342 (ins VR256:$src1, VR256:$src2),
8343 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8345 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
8347 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8348 (ins VR256:$src1, i256mem:$src2),
8349 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8351 (vt256 (OpNode VR256:$src1,
8352 (vt256 (bitconvert (memopv4i64 addr:$src2))))))]>,
8356 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
8357 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
8358 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
8359 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
8360 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;
8362 //===----------------------------------------------------------------------===//
8363 // VGATHER - GATHER Operations
8364 multiclass avx2_gather<bits<8> opc, string OpcodeStr, RegisterClass RC256,
8365 X86MemOperand memop128, X86MemOperand memop256> {
8366 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst, VR128:$mask_wb),
8367 (ins VR128:$src1, memop128:$src2, VR128:$mask),
8368 !strconcat(OpcodeStr,
8369 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8371 def Yrm : AVX28I<opc, MRMSrcMem, (outs RC256:$dst, RC256:$mask_wb),
8372 (ins RC256:$src1, memop256:$src2, RC256:$mask),
8373 !strconcat(OpcodeStr,
8374 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8375 []>, VEX_4VOp3, VEX_L;
8378 let mayLoad = 1, Constraints = "$src1 = $dst, $mask = $mask_wb" in {
8379 defm VGATHERDPD : avx2_gather<0x92, "vgatherdpd", VR256, vx64mem, vx64mem>, VEX_W;
8380 defm VGATHERQPD : avx2_gather<0x93, "vgatherqpd", VR256, vx64mem, vy64mem>, VEX_W;
8381 defm VGATHERDPS : avx2_gather<0x92, "vgatherdps", VR256, vx32mem, vy32mem>;
8382 defm VGATHERQPS : avx2_gather<0x93, "vgatherqps", VR128, vx32mem, vy32mem>;
8383 defm VPGATHERDQ : avx2_gather<0x90, "vpgatherdq", VR256, vx64mem, vx64mem>, VEX_W;
8384 defm VPGATHERQQ : avx2_gather<0x91, "vpgatherqq", VR256, vx64mem, vy64mem>, VEX_W;
8385 defm VPGATHERDD : avx2_gather<0x90, "vpgatherdd", VR256, vx32mem, vy32mem>;
8386 defm VPGATHERQD : avx2_gather<0x91, "vpgatherqd", VR128, vx32mem, vy32mem>;