1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE 1 & 2 Instructions Classes
19 //===----------------------------------------------------------------------===//
21 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
22 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
23 RegisterClass RC, X86MemOperand x86memop,
25 let isCommutable = 1 in {
26 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
28 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
29 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
30 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>;
32 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
34 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
35 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
36 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))]>;
39 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
40 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
41 string asm, string SSEVer, string FPSizeStr,
42 Operand memopr, ComplexPattern mem_cpat,
44 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
46 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
47 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
48 [(set RC:$dst, (!cast<Intrinsic>(
49 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
50 RC:$src1, RC:$src2))]>;
51 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
53 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
54 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
55 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
56 SSEVer, "_", OpcodeStr, FPSizeStr))
57 RC:$src1, mem_cpat:$src2))]>;
60 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
61 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
62 RegisterClass RC, ValueType vt,
63 X86MemOperand x86memop, PatFrag mem_frag,
64 Domain d, bit Is2Addr = 1> {
65 let isCommutable = 1 in
66 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
68 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
69 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
70 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], d>;
72 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
74 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
75 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
76 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))], d>;
79 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
80 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
81 string OpcodeStr, X86MemOperand x86memop,
82 list<dag> pat_rr, list<dag> pat_rm,
84 let isCommutable = 1 in
85 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
87 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
88 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
90 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
92 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
93 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
97 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
98 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
99 string asm, string SSEVer, string FPSizeStr,
100 X86MemOperand x86memop, PatFrag mem_frag,
101 Domain d, bit Is2Addr = 1> {
102 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
104 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
105 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
106 [(set RC:$dst, (!cast<Intrinsic>(
107 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
108 RC:$src1, RC:$src2))], d>;
109 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1,x86memop:$src2),
111 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
112 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
113 [(set RC:$dst, (!cast<Intrinsic>(
114 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
115 RC:$src1, (mem_frag addr:$src2)))], d>;
118 //===----------------------------------------------------------------------===//
119 // SSE 1 & 2 - Move Instructions
120 //===----------------------------------------------------------------------===//
122 class sse12_move_rr<RegisterClass RC, ValueType vt, string asm> :
123 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
124 [(set (vt VR128:$dst), (movl VR128:$src1, (scalar_to_vector RC:$src2)))]>;
126 // Loading from memory automatically zeroing upper bits.
127 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
128 PatFrag mem_pat, string OpcodeStr> :
129 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
130 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
131 [(set RC:$dst, (mem_pat addr:$src))]>;
133 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
134 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
135 // is used instead. Register-to-register movss/movsd is not modeled as an
136 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
137 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
138 def VMOVSSrr : sse12_move_rr<FR32, v4f32,
139 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V;
140 def VMOVSDrr : sse12_move_rr<FR64, v2f64,
141 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V;
143 let canFoldAsLoad = 1, isReMaterializable = 1 in {
144 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX;
146 let AddedComplexity = 20 in
147 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX;
150 let Constraints = "$src1 = $dst" in {
151 def MOVSSrr : sse12_move_rr<FR32, v4f32,
152 "movss\t{$src2, $dst|$dst, $src2}">, XS;
153 def MOVSDrr : sse12_move_rr<FR64, v2f64,
154 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
157 let canFoldAsLoad = 1, isReMaterializable = 1 in {
158 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
160 let AddedComplexity = 20 in
161 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
164 let AddedComplexity = 15 in {
165 // Extract the low 32-bit value from one vector and insert it into another.
166 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
167 (MOVSSrr (v4f32 VR128:$src1),
168 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
169 // Extract the low 64-bit value from one vector and insert it into another.
170 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
171 (MOVSDrr (v2f64 VR128:$src1),
172 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
175 // Implicitly promote a 32-bit scalar to a vector.
176 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
177 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
178 // Implicitly promote a 64-bit scalar to a vector.
179 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
180 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
181 // Implicitly promote a 32-bit scalar to a vector.
182 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
183 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
184 // Implicitly promote a 64-bit scalar to a vector.
185 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
186 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
188 let AddedComplexity = 20 in {
189 // MOVSSrm zeros the high parts of the register; represent this
190 // with SUBREG_TO_REG.
191 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
192 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
193 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
194 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
195 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
196 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
197 // MOVSDrm zeros the high parts of the register; represent this
198 // with SUBREG_TO_REG.
199 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
200 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
201 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
202 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
203 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
204 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
205 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
206 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
207 def : Pat<(v2f64 (X86vzload addr:$src)),
208 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
211 // Store scalar value to memory.
212 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
213 "movss\t{$src, $dst|$dst, $src}",
214 [(store FR32:$src, addr:$dst)]>;
215 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
216 "movsd\t{$src, $dst|$dst, $src}",
217 [(store FR64:$src, addr:$dst)]>;
219 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
220 "movss\t{$src, $dst|$dst, $src}",
221 [(store FR32:$src, addr:$dst)]>, XS, VEX;
222 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
223 "movsd\t{$src, $dst|$dst, $src}",
224 [(store FR64:$src, addr:$dst)]>, XD, VEX;
226 // Extract and store.
227 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
230 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
231 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
234 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
236 // Move Aligned/Unaligned floating point values
237 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
238 X86MemOperand x86memop, PatFrag ld_frag,
239 string asm, Domain d,
240 bit IsReMaterializable = 1> {
241 let neverHasSideEffects = 1 in
242 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
243 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>;
244 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
245 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
246 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
247 [(set RC:$dst, (ld_frag addr:$src))], d>;
250 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
251 "movaps", SSEPackedSingle>, VEX;
252 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
253 "movapd", SSEPackedDouble>, OpSize, VEX;
254 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
255 "movups", SSEPackedSingle>, VEX;
256 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
257 "movupd", SSEPackedDouble, 0>, OpSize, VEX;
259 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
260 "movaps", SSEPackedSingle>, VEX;
261 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
262 "movapd", SSEPackedDouble>, OpSize, VEX;
263 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
264 "movups", SSEPackedSingle>, VEX;
265 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
266 "movupd", SSEPackedDouble, 0>, OpSize, VEX;
267 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
268 "movaps", SSEPackedSingle>, TB;
269 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
270 "movapd", SSEPackedDouble>, TB, OpSize;
271 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
272 "movups", SSEPackedSingle>, TB;
273 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
274 "movupd", SSEPackedDouble, 0>, TB, OpSize;
276 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
277 "movaps\t{$src, $dst|$dst, $src}",
278 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>, VEX;
279 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
280 "movapd\t{$src, $dst|$dst, $src}",
281 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>, VEX;
282 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
283 "movups\t{$src, $dst|$dst, $src}",
284 [(store (v4f32 VR128:$src), addr:$dst)]>, VEX;
285 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
286 "movupd\t{$src, $dst|$dst, $src}",
287 [(store (v2f64 VR128:$src), addr:$dst)]>, VEX;
288 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
289 "movaps\t{$src, $dst|$dst, $src}",
290 [(alignedstore (v8f32 VR256:$src), addr:$dst)]>, VEX;
291 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
292 "movapd\t{$src, $dst|$dst, $src}",
293 [(alignedstore (v4f64 VR256:$src), addr:$dst)]>, VEX;
294 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
295 "movups\t{$src, $dst|$dst, $src}",
296 [(store (v8f32 VR256:$src), addr:$dst)]>, VEX;
297 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
298 "movupd\t{$src, $dst|$dst, $src}",
299 [(store (v4f64 VR256:$src), addr:$dst)]>, VEX;
301 def : Pat<(int_x86_avx_loadu_ps_256 addr:$src), (VMOVUPSYrm addr:$src)>;
302 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
303 (VMOVUPSYmr addr:$dst, VR256:$src)>;
305 def : Pat<(int_x86_avx_loadu_pd_256 addr:$src), (VMOVUPDYrm addr:$src)>;
306 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
307 (VMOVUPDYmr addr:$dst, VR256:$src)>;
309 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
310 "movaps\t{$src, $dst|$dst, $src}",
311 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
312 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
313 "movapd\t{$src, $dst|$dst, $src}",
314 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
315 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
316 "movups\t{$src, $dst|$dst, $src}",
317 [(store (v4f32 VR128:$src), addr:$dst)]>;
318 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
319 "movupd\t{$src, $dst|$dst, $src}",
320 [(store (v2f64 VR128:$src), addr:$dst)]>;
322 // Intrinsic forms of MOVUPS/D load and store
323 def VMOVUPSmr_Int : VPSI<0x11, MRMDestMem, (outs),
324 (ins f128mem:$dst, VR128:$src),
325 "movups\t{$src, $dst|$dst, $src}",
326 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>, VEX;
327 def VMOVUPDmr_Int : VPDI<0x11, MRMDestMem, (outs),
328 (ins f128mem:$dst, VR128:$src),
329 "movupd\t{$src, $dst|$dst, $src}",
330 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>, VEX;
332 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
333 "movups\t{$src, $dst|$dst, $src}",
334 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
335 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
336 "movupd\t{$src, $dst|$dst, $src}",
337 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
339 // Move Low/High packed floating point values
340 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
341 PatFrag mov_frag, string base_opc,
343 def PSrm : PI<opc, MRMSrcMem,
344 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
345 !strconcat(base_opc, "s", asm_opr),
348 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
349 SSEPackedSingle>, TB;
351 def PDrm : PI<opc, MRMSrcMem,
352 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
353 !strconcat(base_opc, "d", asm_opr),
354 [(set RC:$dst, (v2f64 (mov_frag RC:$src1,
355 (scalar_to_vector (loadf64 addr:$src2)))))],
356 SSEPackedDouble>, TB, OpSize;
359 let AddedComplexity = 20 in {
360 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
361 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
362 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
363 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
365 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
366 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
367 "\t{$src2, $dst|$dst, $src2}">;
368 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
369 "\t{$src2, $dst|$dst, $src2}">;
372 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
373 "movlps\t{$src, $dst|$dst, $src}",
374 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
375 (iPTR 0))), addr:$dst)]>, VEX;
376 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
377 "movlpd\t{$src, $dst|$dst, $src}",
378 [(store (f64 (vector_extract (v2f64 VR128:$src),
379 (iPTR 0))), addr:$dst)]>, VEX;
380 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
381 "movlps\t{$src, $dst|$dst, $src}",
382 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
383 (iPTR 0))), addr:$dst)]>;
384 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
385 "movlpd\t{$src, $dst|$dst, $src}",
386 [(store (f64 (vector_extract (v2f64 VR128:$src),
387 (iPTR 0))), addr:$dst)]>;
389 // v2f64 extract element 1 is always custom lowered to unpack high to low
390 // and extract element 0 so the non-store version isn't too horrible.
391 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
392 "movhps\t{$src, $dst|$dst, $src}",
393 [(store (f64 (vector_extract
394 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
395 (undef)), (iPTR 0))), addr:$dst)]>,
397 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
398 "movhpd\t{$src, $dst|$dst, $src}",
399 [(store (f64 (vector_extract
400 (v2f64 (unpckh VR128:$src, (undef))),
401 (iPTR 0))), addr:$dst)]>,
403 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
404 "movhps\t{$src, $dst|$dst, $src}",
405 [(store (f64 (vector_extract
406 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
407 (undef)), (iPTR 0))), addr:$dst)]>;
408 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
409 "movhpd\t{$src, $dst|$dst, $src}",
410 [(store (f64 (vector_extract
411 (v2f64 (unpckh VR128:$src, (undef))),
412 (iPTR 0))), addr:$dst)]>;
414 let AddedComplexity = 20 in {
415 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
416 (ins VR128:$src1, VR128:$src2),
417 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
419 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>,
421 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
422 (ins VR128:$src1, VR128:$src2),
423 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
425 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>,
428 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
429 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
430 (ins VR128:$src1, VR128:$src2),
431 "movlhps\t{$src2, $dst|$dst, $src2}",
433 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>;
434 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
435 (ins VR128:$src1, VR128:$src2),
436 "movhlps\t{$src2, $dst|$dst, $src2}",
438 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
441 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
442 (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
443 let AddedComplexity = 20 in {
444 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
445 (MOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
446 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
447 (MOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
450 //===----------------------------------------------------------------------===//
451 // SSE 1 & 2 - Conversion Instructions
452 //===----------------------------------------------------------------------===//
454 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
455 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
457 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
458 [(set DstRC:$dst, (OpNode SrcRC:$src))]>;
459 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
460 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>;
463 multiclass sse12_cvt_s_np<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
464 X86MemOperand x86memop, string asm> {
465 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
467 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
471 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
472 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
473 string asm, Domain d> {
474 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
475 [(set DstRC:$dst, (OpNode SrcRC:$src))], d>;
476 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
477 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))], d>;
480 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
481 X86MemOperand x86memop, string asm> {
482 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
483 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
484 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
485 (ins DstRC:$src1, x86memop:$src),
486 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
489 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
490 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX;
491 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
492 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
494 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
495 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
496 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
497 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD,
500 // The assembler can recognize rr 64-bit instructions by seeing a rxx
501 // register, but the same isn't true when only using memory operands,
502 // provide other assembly "l" and "q" forms to address this explicitly
503 // where appropriate to do so.
504 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss">, XS,
506 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">, XS,
508 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">, XD,
510 defm VCVTSI2SDL : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">, XD,
512 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">, XD,
515 let Predicates = [HasAVX] in {
516 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
517 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
518 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
519 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
520 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
521 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
522 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
523 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
525 def : Pat<(f32 (sint_to_fp GR32:$src)),
526 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
527 def : Pat<(f32 (sint_to_fp GR64:$src)),
528 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
529 def : Pat<(f64 (sint_to_fp GR32:$src)),
530 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
531 def : Pat<(f64 (sint_to_fp GR64:$src)),
532 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
535 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
536 "cvttss2si\t{$src, $dst|$dst, $src}">, XS;
537 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
538 "cvttss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
539 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
540 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD;
541 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
542 "cvttsd2si{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
543 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
544 "cvtsi2ss\t{$src, $dst|$dst, $src}">, XS;
545 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
546 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
547 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
548 "cvtsi2sd\t{$src, $dst|$dst, $src}">, XD;
549 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
550 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
552 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
553 // and/or XMM operand(s).
555 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
556 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
558 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
559 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
560 [(set DstRC:$dst, (Int SrcRC:$src))]>;
561 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
562 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
563 [(set DstRC:$dst, (Int (ld_frag addr:$src)))]>;
566 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
567 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
568 PatFrag ld_frag, string asm, bit Is2Addr = 1> {
569 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
571 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
572 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
573 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))]>;
574 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
575 (ins DstRC:$src1, x86memop:$src2),
577 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
578 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
579 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))]>;
582 defm Int_VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
583 f32mem, load, "cvtss2si">, XS, VEX;
584 defm Int_VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
585 int_x86_sse_cvtss2si64, f32mem, load, "cvtss2si">,
587 defm Int_VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
588 f128mem, load, "cvtsd2si">, XD, VEX;
589 defm Int_VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
590 int_x86_sse2_cvtsd2si64, f128mem, load, "cvtsd2si">,
593 // FIXME: The asm matcher has a hack to ignore instructions with _Int and Int_
594 // Get rid of this hack or rename the intrinsics, there are several
595 // intructions that only match with the intrinsic form, why create duplicates
596 // to let them be recognized by the assembler?
597 defm VCVTSD2SI_alt : sse12_cvt_s_np<0x2D, FR64, GR32, f64mem,
598 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
599 defm VCVTSD2SI64 : sse12_cvt_s_np<0x2D, FR64, GR64, f64mem,
600 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX, VEX_W;
601 defm Int_CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
602 f32mem, load, "cvtss2si">, XS;
603 defm Int_CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
604 f32mem, load, "cvtss2si{q}">, XS, REX_W;
605 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
606 f128mem, load, "cvtsd2si{l}">, XD;
607 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
608 f128mem, load, "cvtsd2si{q}">, XD, REX_W;
611 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
612 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss", 0>, XS, VEX_4V;
613 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
614 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss", 0>, XS, VEX_4V,
616 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
617 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd", 0>, XD, VEX_4V;
618 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
619 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd", 0>, XD,
622 let Constraints = "$src1 = $dst" in {
623 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
624 int_x86_sse_cvtsi2ss, i32mem, loadi32,
626 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
627 int_x86_sse_cvtsi642ss, i64mem, loadi64,
628 "cvtsi2ss{q}">, XS, REX_W;
629 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
630 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
632 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
633 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
634 "cvtsi2sd">, XD, REX_W;
639 // Aliases for intrinsics
640 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
641 f32mem, load, "cvttss2si">, XS, VEX;
642 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
643 int_x86_sse_cvttss2si64, f32mem, load,
644 "cvttss2si">, XS, VEX, VEX_W;
645 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
646 f128mem, load, "cvttsd2si">, XD, VEX;
647 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
648 int_x86_sse2_cvttsd2si64, f128mem, load,
649 "cvttsd2si">, XD, VEX, VEX_W;
650 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
651 f32mem, load, "cvttss2si">, XS;
652 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
653 int_x86_sse_cvttss2si64, f32mem, load,
654 "cvttss2si{q}">, XS, REX_W;
655 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
656 f128mem, load, "cvttsd2si">, XD;
657 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
658 int_x86_sse2_cvttsd2si64, f128mem, load,
659 "cvttsd2si{q}">, XD, REX_W;
661 let Pattern = []<dag> in {
662 defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load,
663 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS, VEX;
664 defm VCVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load,
665 "cvtss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
667 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load,
668 "cvtdq2ps\t{$src, $dst|$dst, $src}",
669 SSEPackedSingle>, TB, VEX;
670 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, undef, i256mem, load,
671 "cvtdq2ps\t{$src, $dst|$dst, $src}",
672 SSEPackedSingle>, TB, VEX;
674 let Pattern = []<dag> in {
675 defm CVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load /*dummy*/,
676 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS;
677 defm CVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load /*dummy*/,
678 "cvtss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
679 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load /*dummy*/,
680 "cvtdq2ps\t{$src, $dst|$dst, $src}",
681 SSEPackedSingle>, TB; /* PD SSE3 form is avaiable */
686 // Convert scalar double to scalar single
687 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
688 (ins FR64:$src1, FR64:$src2),
689 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
691 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
692 (ins FR64:$src1, f64mem:$src2),
693 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
694 []>, XD, Requires<[HasAVX, OptForSize]>, VEX_4V;
695 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
698 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
699 "cvtsd2ss\t{$src, $dst|$dst, $src}",
700 [(set FR32:$dst, (fround FR64:$src))]>;
701 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
702 "cvtsd2ss\t{$src, $dst|$dst, $src}",
703 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
704 Requires<[HasSSE2, OptForSize]>;
706 defm Int_VCVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
707 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss", 0>,
709 let Constraints = "$src1 = $dst" in
710 defm Int_CVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
711 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss">, XS;
713 // Convert scalar single to scalar double
714 // SSE2 instructions with XS prefix
715 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
716 (ins FR32:$src1, FR32:$src2),
717 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
718 []>, XS, Requires<[HasAVX]>, VEX_4V;
719 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
720 (ins FR32:$src1, f32mem:$src2),
721 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
722 []>, XS, VEX_4V, Requires<[HasAVX, OptForSize]>;
724 let Predicates = [HasAVX] in {
725 def : Pat<(f64 (fextend FR32:$src)),
726 (VCVTSS2SDrr FR32:$src, FR32:$src)>;
727 def : Pat<(fextend (loadf32 addr:$src)),
728 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
729 def : Pat<(extloadf32 addr:$src),
730 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
733 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
734 "cvtss2sd\t{$src, $dst|$dst, $src}",
735 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
737 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
738 "cvtss2sd\t{$src, $dst|$dst, $src}",
739 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
740 Requires<[HasSSE2, OptForSize]>;
742 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
743 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
744 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
745 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
746 VR128:$src2))]>, XS, VEX_4V,
748 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
749 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
750 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
751 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
752 (load addr:$src2)))]>, XS, VEX_4V,
754 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
755 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
756 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
757 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
758 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
761 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
762 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
763 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
764 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
765 (load addr:$src2)))]>, XS,
769 def : Pat<(extloadf32 addr:$src),
770 (CVTSS2SDrr (MOVSSrm addr:$src))>,
771 Requires<[HasSSE2, OptForSpeed]>;
773 // Convert doubleword to packed single/double fp
774 // SSE2 instructions without OpSize prefix
775 def Int_VCVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
776 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
777 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
778 TB, VEX, Requires<[HasAVX]>;
779 def Int_VCVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
780 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
781 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
782 (bitconvert (memopv2i64 addr:$src))))]>,
783 TB, VEX, Requires<[HasAVX]>;
784 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
785 "cvtdq2ps\t{$src, $dst|$dst, $src}",
786 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
787 TB, Requires<[HasSSE2]>;
788 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
789 "cvtdq2ps\t{$src, $dst|$dst, $src}",
790 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
791 (bitconvert (memopv2i64 addr:$src))))]>,
792 TB, Requires<[HasSSE2]>;
794 // FIXME: why the non-intrinsic version is described as SSE3?
795 // SSE2 instructions with XS prefix
796 def Int_VCVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
797 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
798 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
799 XS, VEX, Requires<[HasAVX]>;
800 def Int_VCVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
801 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
802 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
803 (bitconvert (memopv2i64 addr:$src))))]>,
804 XS, VEX, Requires<[HasAVX]>;
805 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
806 "cvtdq2pd\t{$src, $dst|$dst, $src}",
807 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
808 XS, Requires<[HasSSE2]>;
809 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
810 "cvtdq2pd\t{$src, $dst|$dst, $src}",
811 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
812 (bitconvert (memopv2i64 addr:$src))))]>,
813 XS, Requires<[HasSSE2]>;
816 // Convert packed single/double fp to doubleword
817 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
818 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
819 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
820 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
821 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
822 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
823 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
824 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
825 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
826 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
827 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
828 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
830 def Int_VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
831 "cvtps2dq\t{$src, $dst|$dst, $src}",
832 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>,
834 def Int_VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst),
836 "cvtps2dq\t{$src, $dst|$dst, $src}",
837 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
838 (memop addr:$src)))]>, VEX;
839 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
840 "cvtps2dq\t{$src, $dst|$dst, $src}",
841 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
842 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
843 "cvtps2dq\t{$src, $dst|$dst, $src}",
844 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
845 (memop addr:$src)))]>;
847 // SSE2 packed instructions with XD prefix
848 def Int_VCVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
849 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
850 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
851 XD, VEX, Requires<[HasAVX]>;
852 def Int_VCVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
853 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
854 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
855 (memop addr:$src)))]>,
856 XD, VEX, Requires<[HasAVX]>;
857 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
858 "cvtpd2dq\t{$src, $dst|$dst, $src}",
859 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
860 XD, Requires<[HasSSE2]>;
861 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
862 "cvtpd2dq\t{$src, $dst|$dst, $src}",
863 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
864 (memop addr:$src)))]>,
865 XD, Requires<[HasSSE2]>;
868 // Convert with truncation packed single/double fp to doubleword
869 // SSE2 packed instructions with XS prefix
870 def VCVTTPS2DQrr : VSSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
871 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
872 def VCVTTPS2DQrm : VSSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
873 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
874 def VCVTTPS2DQYrr : VSSI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
875 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
876 def VCVTTPS2DQYrm : VSSI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
877 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
878 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
879 "cvttps2dq\t{$src, $dst|$dst, $src}",
881 (int_x86_sse2_cvttps2dq VR128:$src))]>;
882 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
883 "cvttps2dq\t{$src, $dst|$dst, $src}",
885 (int_x86_sse2_cvttps2dq (memop addr:$src)))]>;
888 def Int_VCVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
889 "vcvttps2dq\t{$src, $dst|$dst, $src}",
891 (int_x86_sse2_cvttps2dq VR128:$src))]>,
892 XS, VEX, Requires<[HasAVX]>;
893 def Int_VCVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
894 "vcvttps2dq\t{$src, $dst|$dst, $src}",
895 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
896 (memop addr:$src)))]>,
897 XS, VEX, Requires<[HasAVX]>;
899 def Int_VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst),
901 "cvttpd2dq\t{$src, $dst|$dst, $src}",
902 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>,
904 def Int_VCVTTPD2DQrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst),
906 "cvttpd2dq\t{$src, $dst|$dst, $src}",
907 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
908 (memop addr:$src)))]>, VEX;
909 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
910 "cvttpd2dq\t{$src, $dst|$dst, $src}",
911 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
912 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
913 "cvttpd2dq\t{$src, $dst|$dst, $src}",
914 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
915 (memop addr:$src)))]>;
917 // The assembler can recognize rr 256-bit instructions by seeing a ymm
918 // register, but the same isn't true when using memory operands instead.
919 // Provide other assembly rr and rm forms to address this explicitly.
920 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
921 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
922 def VCVTTPD2DQXrYr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
923 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
926 def VCVTTPD2DQXrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
927 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
928 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
929 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
932 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
933 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
934 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
935 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
937 // Convert packed single to packed double
938 let Predicates = [HasAVX] in {
939 // SSE2 instructions without OpSize prefix
940 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
941 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
942 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
943 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
944 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
945 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
946 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
947 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
949 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
950 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
951 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
952 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
954 def Int_VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
955 "vcvtps2pd\t{$src, $dst|$dst, $src}",
956 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
957 VEX, Requires<[HasAVX]>;
958 def Int_VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
959 "vcvtps2pd\t{$src, $dst|$dst, $src}",
960 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
961 (load addr:$src)))]>,
962 VEX, Requires<[HasAVX]>;
963 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
964 "cvtps2pd\t{$src, $dst|$dst, $src}",
965 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
966 TB, Requires<[HasSSE2]>;
967 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
968 "cvtps2pd\t{$src, $dst|$dst, $src}",
969 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
970 (load addr:$src)))]>,
971 TB, Requires<[HasSSE2]>;
973 // Convert packed double to packed single
974 // The assembler can recognize rr 256-bit instructions by seeing a ymm
975 // register, but the same isn't true when using memory operands instead.
976 // Provide other assembly rr and rm forms to address this explicitly.
977 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
978 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
979 def VCVTPD2PSXrYr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
980 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
983 def VCVTPD2PSXrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
984 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
985 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
986 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
989 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
990 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX;
991 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
992 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
993 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
994 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
995 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
996 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
999 def Int_VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1000 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1001 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1002 def Int_VCVTPD2PSrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst),
1004 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1005 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1006 (memop addr:$src)))]>;
1007 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1008 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1009 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1010 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1011 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1012 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1013 (memop addr:$src)))]>;
1015 // AVX 256-bit register conversion intrinsics
1016 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
1017 // whenever possible to avoid declaring two versions of each one.
1018 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
1019 (VCVTDQ2PSYrr VR256:$src)>;
1020 def : Pat<(int_x86_avx_cvtdq2_ps_256 (memopv8i32 addr:$src)),
1021 (VCVTDQ2PSYrm addr:$src)>;
1023 def : Pat<(int_x86_avx_cvt_pd2_ps_256 VR256:$src),
1024 (VCVTPD2PSYrr VR256:$src)>;
1025 def : Pat<(int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)),
1026 (VCVTPD2PSYrm addr:$src)>;
1028 def : Pat<(int_x86_avx_cvt_ps2dq_256 VR256:$src),
1029 (VCVTPS2DQYrr VR256:$src)>;
1030 def : Pat<(int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)),
1031 (VCVTPS2DQYrm addr:$src)>;
1033 def : Pat<(int_x86_avx_cvt_ps2_pd_256 VR128:$src),
1034 (VCVTPS2PDYrr VR128:$src)>;
1035 def : Pat<(int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)),
1036 (VCVTPS2PDYrm addr:$src)>;
1038 def : Pat<(int_x86_avx_cvtt_pd2dq_256 VR256:$src),
1039 (VCVTTPD2DQYrr VR256:$src)>;
1040 def : Pat<(int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)),
1041 (VCVTTPD2DQYrm addr:$src)>;
1043 def : Pat<(int_x86_avx_cvtt_ps2dq_256 VR256:$src),
1044 (VCVTTPS2DQYrr VR256:$src)>;
1045 def : Pat<(int_x86_avx_cvtt_ps2dq_256 (memopv8f32 addr:$src)),
1046 (VCVTTPS2DQYrm addr:$src)>;
1048 //===----------------------------------------------------------------------===//
1049 // SSE 1 & 2 - Compare Instructions
1050 //===----------------------------------------------------------------------===//
1052 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
1053 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1054 string asm, string asm_alt> {
1055 let isAsmParserOnly = 1 in {
1056 def rr : SIi8<0xC2, MRMSrcReg,
1057 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc),
1060 def rm : SIi8<0xC2, MRMSrcMem,
1061 (outs RC:$dst), (ins RC:$src1, x86memop:$src, SSECC:$cc),
1065 // Accept explicit immediate argument form instead of comparison code.
1066 def rr_alt : SIi8<0xC2, MRMSrcReg,
1067 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
1070 def rm_alt : SIi8<0xC2, MRMSrcMem,
1071 (outs RC:$dst), (ins RC:$src1, x86memop:$src, i8imm:$src2),
1075 let neverHasSideEffects = 1 in {
1076 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem,
1077 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1078 "cmpss\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1080 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem,
1081 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1082 "cmpsd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1086 let Constraints = "$src1 = $dst" in {
1087 def CMPSSrr : SIi8<0xC2, MRMSrcReg,
1088 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, SSECC:$cc),
1089 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
1090 [(set FR32:$dst, (X86cmpss (f32 FR32:$src1), FR32:$src2, imm:$cc))]>, XS;
1091 def CMPSSrm : SIi8<0xC2, MRMSrcMem,
1092 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2, SSECC:$cc),
1093 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
1094 [(set FR32:$dst, (X86cmpss (f32 FR32:$src1), (loadf32 addr:$src2), imm:$cc))]>, XS;
1095 def CMPSDrr : SIi8<0xC2, MRMSrcReg,
1096 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, SSECC:$cc),
1097 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
1098 [(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), FR64:$src2, imm:$cc))]>, XD;
1099 def CMPSDrm : SIi8<0xC2, MRMSrcMem,
1100 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src2, SSECC:$cc),
1101 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
1102 [(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), (loadf64 addr:$src2), imm:$cc))]>, XD;
1104 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1105 def CMPSSrr_alt : SIi8<0xC2, MRMSrcReg,
1106 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, i8imm:$src2),
1107 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XS;
1108 def CMPSSrm_alt : SIi8<0xC2, MRMSrcMem,
1109 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, i8imm:$src2),
1110 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XS;
1111 def CMPSDrr_alt : SIi8<0xC2, MRMSrcReg,
1112 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, i8imm:$src2),
1113 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XD;
1114 def CMPSDrm_alt : SIi8<0xC2, MRMSrcMem,
1115 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, i8imm:$src2),
1116 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XD;
1119 multiclass sse12_cmp_scalar_int<RegisterClass RC, X86MemOperand x86memop,
1120 Intrinsic Int, string asm> {
1121 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
1122 (ins VR128:$src1, VR128:$src, SSECC:$cc), asm,
1123 [(set VR128:$dst, (Int VR128:$src1,
1124 VR128:$src, imm:$cc))]>;
1125 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
1126 (ins VR128:$src1, f32mem:$src, SSECC:$cc), asm,
1127 [(set VR128:$dst, (Int VR128:$src1,
1128 (load addr:$src), imm:$cc))]>;
1131 // Aliases to match intrinsics which expect XMM operand(s).
1132 defm Int_VCMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
1133 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}">,
1135 defm Int_VCMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
1136 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}">,
1138 let Constraints = "$src1 = $dst" in {
1139 defm Int_CMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
1140 "cmp${cc}ss\t{$src, $dst|$dst, $src}">, XS;
1141 defm Int_CMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
1142 "cmp${cc}sd\t{$src, $dst|$dst, $src}">, XD;
1146 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
1147 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
1148 ValueType vt, X86MemOperand x86memop,
1149 PatFrag ld_frag, string OpcodeStr, Domain d> {
1150 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
1151 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1152 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))], d>;
1153 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
1154 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1155 [(set EFLAGS, (OpNode (vt RC:$src1),
1156 (ld_frag addr:$src2)))], d>;
1159 let Defs = [EFLAGS] in {
1160 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
1161 "ucomiss", SSEPackedSingle>, VEX;
1162 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
1163 "ucomisd", SSEPackedDouble>, OpSize, VEX;
1164 let Pattern = []<dag> in {
1165 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
1166 "comiss", SSEPackedSingle>, VEX;
1167 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
1168 "comisd", SSEPackedDouble>, OpSize, VEX;
1171 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
1172 load, "ucomiss", SSEPackedSingle>, VEX;
1173 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
1174 load, "ucomisd", SSEPackedDouble>, OpSize, VEX;
1176 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
1177 load, "comiss", SSEPackedSingle>, VEX;
1178 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
1179 load, "comisd", SSEPackedDouble>, OpSize, VEX;
1180 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
1181 "ucomiss", SSEPackedSingle>, TB;
1182 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
1183 "ucomisd", SSEPackedDouble>, TB, OpSize;
1185 let Pattern = []<dag> in {
1186 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
1187 "comiss", SSEPackedSingle>, TB;
1188 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
1189 "comisd", SSEPackedDouble>, TB, OpSize;
1192 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
1193 load, "ucomiss", SSEPackedSingle>, TB;
1194 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
1195 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
1197 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
1198 "comiss", SSEPackedSingle>, TB;
1199 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
1200 "comisd", SSEPackedDouble>, TB, OpSize;
1201 } // Defs = [EFLAGS]
1203 // sse12_cmp_packed - sse 1 & 2 compared packed instructions
1204 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
1205 Intrinsic Int, string asm, string asm_alt,
1207 let isAsmParserOnly = 1 in {
1208 def rri : PIi8<0xC2, MRMSrcReg,
1209 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc), asm,
1210 [(set RC:$dst, (Int RC:$src1, RC:$src, imm:$cc))], d>;
1211 def rmi : PIi8<0xC2, MRMSrcMem,
1212 (outs RC:$dst), (ins RC:$src1, f128mem:$src, SSECC:$cc), asm,
1213 [(set RC:$dst, (Int RC:$src1, (memop addr:$src), imm:$cc))], d>;
1216 // Accept explicit immediate argument form instead of comparison code.
1217 def rri_alt : PIi8<0xC2, MRMSrcReg,
1218 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
1220 def rmi_alt : PIi8<0xC2, MRMSrcMem,
1221 (outs RC:$dst), (ins RC:$src1, f128mem:$src, i8imm:$src2),
1225 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
1226 "cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
1227 "cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1228 SSEPackedSingle>, VEX_4V;
1229 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
1230 "cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
1231 "cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1232 SSEPackedDouble>, OpSize, VEX_4V;
1233 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_ps_256,
1234 "cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
1235 "cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1236 SSEPackedSingle>, VEX_4V;
1237 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_pd_256,
1238 "cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
1239 "cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1240 SSEPackedDouble>, OpSize, VEX_4V;
1241 let Constraints = "$src1 = $dst" in {
1242 defm CMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
1243 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
1244 "cmpps\t{$src2, $src, $dst|$dst, $src, $src2}",
1245 SSEPackedSingle>, TB;
1246 defm CMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
1247 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1248 "cmppd\t{$src2, $src, $dst|$dst, $src, $src2}",
1249 SSEPackedDouble>, TB, OpSize;
1252 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
1253 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
1254 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
1255 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
1256 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1257 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1258 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1259 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1261 //===----------------------------------------------------------------------===//
1262 // SSE 1 & 2 - Shuffle Instructions
1263 //===----------------------------------------------------------------------===//
1265 /// sse12_shuffle - sse 1 & 2 shuffle instructions
1266 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
1267 ValueType vt, string asm, PatFrag mem_frag,
1268 Domain d, bit IsConvertibleToThreeAddress = 0> {
1269 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
1270 (ins RC:$src1, f128mem:$src2, i8imm:$src3), asm,
1271 [(set RC:$dst, (vt (shufp:$src3
1272 RC:$src1, (mem_frag addr:$src2))))], d>;
1273 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
1274 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
1275 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
1277 (vt (shufp:$src3 RC:$src1, RC:$src2)))], d>;
1280 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
1281 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
1282 memopv4f32, SSEPackedSingle>, TB, VEX_4V;
1283 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
1284 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
1285 memopv8f32, SSEPackedSingle>, TB, VEX_4V;
1286 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
1287 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
1288 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
1289 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
1290 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
1291 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
1293 let Constraints = "$src1 = $dst" in {
1294 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
1295 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1296 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
1298 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
1299 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1300 memopv2f64, SSEPackedDouble>, TB, OpSize;
1303 //===----------------------------------------------------------------------===//
1304 // SSE 1 & 2 - Unpack Instructions
1305 //===----------------------------------------------------------------------===//
1307 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
1308 multiclass sse12_unpack_interleave<bits<8> opc, PatFrag OpNode, ValueType vt,
1309 PatFrag mem_frag, RegisterClass RC,
1310 X86MemOperand x86memop, string asm,
1312 def rr : PI<opc, MRMSrcReg,
1313 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1315 (vt (OpNode RC:$src1, RC:$src2)))], d>;
1316 def rm : PI<opc, MRMSrcMem,
1317 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1319 (vt (OpNode RC:$src1,
1320 (mem_frag addr:$src2))))], d>;
1323 let AddedComplexity = 10 in {
1324 defm VUNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
1325 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1326 SSEPackedSingle>, VEX_4V;
1327 defm VUNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
1328 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1329 SSEPackedDouble>, OpSize, VEX_4V;
1330 defm VUNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
1331 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1332 SSEPackedSingle>, VEX_4V;
1333 defm VUNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
1334 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1335 SSEPackedDouble>, OpSize, VEX_4V;
1337 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, unpckh, v8f32, memopv8f32,
1338 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1339 SSEPackedSingle>, VEX_4V;
1340 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, unpckh, v4f64, memopv4f64,
1341 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1342 SSEPackedDouble>, OpSize, VEX_4V;
1343 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, unpckl, v8f32, memopv8f32,
1344 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1345 SSEPackedSingle>, VEX_4V;
1346 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, unpckl, v4f64, memopv4f64,
1347 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1348 SSEPackedDouble>, OpSize, VEX_4V;
1350 let Constraints = "$src1 = $dst" in {
1351 defm UNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
1352 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
1353 SSEPackedSingle>, TB;
1354 defm UNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
1355 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
1356 SSEPackedDouble>, TB, OpSize;
1357 defm UNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
1358 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
1359 SSEPackedSingle>, TB;
1360 defm UNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
1361 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
1362 SSEPackedDouble>, TB, OpSize;
1363 } // Constraints = "$src1 = $dst"
1364 } // AddedComplexity
1366 //===----------------------------------------------------------------------===//
1367 // SSE 1 & 2 - Extract Floating-Point Sign mask
1368 //===----------------------------------------------------------------------===//
1370 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
1371 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
1373 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
1374 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1375 [(set GR32:$dst, (Int RC:$src))], d>;
1376 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
1377 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>, REX_W;
1381 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
1382 "movmskps", SSEPackedSingle>, VEX;
1383 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
1384 "movmskpd", SSEPackedDouble>, OpSize,
1386 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
1387 "movmskps", SSEPackedSingle>, VEX;
1388 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
1389 "movmskpd", SSEPackedDouble>, OpSize,
1391 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
1392 SSEPackedSingle>, TB;
1393 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
1394 SSEPackedDouble>, TB, OpSize;
1397 def MOVMSKPDrr32_alt : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins FR64:$src),
1398 "movmskpd\t{$src, $dst|$dst, $src}",
1399 [(set GR32:$dst, (X86fgetsign FR64:$src))], SSEPackedDouble>, TB, OpSize;
1400 def MOVMSKPDrr64_alt : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src),
1401 "movmskpd\t{$src, $dst|$dst, $src}",
1402 [(set GR64:$dst, (X86fgetsign FR64:$src))], SSEPackedDouble>, TB, OpSize;
1403 def MOVMSKPSrr32_alt : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
1404 "movmskps\t{$src, $dst|$dst, $src}",
1405 [(set GR32:$dst, (X86fgetsign FR32:$src))], SSEPackedSingle>, TB;
1406 def MOVMSKPSrr64_alt : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src),
1407 "movmskps\t{$src, $dst|$dst, $src}",
1408 [(set GR64:$dst, (X86fgetsign FR32:$src))], SSEPackedSingle>, TB;
1411 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1412 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX;
1413 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1414 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize,
1416 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
1417 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX;
1418 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
1419 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize,
1422 //===----------------------------------------------------------------------===//
1423 // SSE 1 & 2 - Misc aliasing of packed SSE 1 & 2 instructions
1424 //===----------------------------------------------------------------------===//
1426 // Aliases of packed SSE1 & SSE2 instructions for scalar use. These all have
1427 // names that start with 'Fs'.
1429 // Alias instructions that map fld0 to pxor for sse.
1430 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
1431 canFoldAsLoad = 1 in {
1432 // FIXME: Set encoding to pseudo!
1433 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
1434 [(set FR32:$dst, fp32imm0)]>,
1435 Requires<[HasSSE1]>, TB, OpSize;
1436 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
1437 [(set FR64:$dst, fpimm0)]>,
1438 Requires<[HasSSE2]>, TB, OpSize;
1439 def VFsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
1440 [(set FR32:$dst, fp32imm0)]>,
1441 Requires<[HasAVX]>, TB, OpSize, VEX_4V;
1442 def VFsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
1443 [(set FR64:$dst, fpimm0)]>,
1444 Requires<[HasAVX]>, TB, OpSize, VEX_4V;
1447 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
1448 // bits are disregarded.
1449 let neverHasSideEffects = 1 in {
1450 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1451 "movaps\t{$src, $dst|$dst, $src}", []>;
1452 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1453 "movapd\t{$src, $dst|$dst, $src}", []>;
1456 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1457 // bits are disregarded.
1458 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1459 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1460 "movaps\t{$src, $dst|$dst, $src}",
1461 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
1462 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1463 "movapd\t{$src, $dst|$dst, $src}",
1464 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1467 //===----------------------------------------------------------------------===//
1468 // SSE 1 & 2 - Logical Instructions
1469 //===----------------------------------------------------------------------===//
1471 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
1473 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
1475 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
1476 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, 0>, VEX_4V;
1478 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
1479 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, 0>, OpSize, VEX_4V;
1481 let Constraints = "$src1 = $dst" in {
1482 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
1483 f32, f128mem, memopfsf32, SSEPackedSingle>, TB;
1485 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
1486 f64, f128mem, memopfsf64, SSEPackedDouble>, TB, OpSize;
1490 // Alias bitwise logical operations using SSE logical ops on packed FP values.
1491 let mayLoad = 0 in {
1492 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand>;
1493 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for>;
1494 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>;
1497 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
1498 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef>;
1500 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
1502 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
1504 let Pattern = []<dag> in {
1505 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
1506 !strconcat(OpcodeStr, "ps"), f128mem,
1507 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
1508 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
1509 (memopv2i64 addr:$src2)))], 0>, VEX_4V;
1511 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
1512 !strconcat(OpcodeStr, "pd"), f128mem,
1513 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1514 (bc_v2i64 (v2f64 VR128:$src2))))],
1515 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1516 (memopv2i64 addr:$src2)))], 0>,
1519 let Constraints = "$src1 = $dst" in {
1520 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
1521 !strconcat(OpcodeStr, "ps"), f128mem,
1522 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
1523 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
1524 (memopv2i64 addr:$src2)))]>, TB;
1526 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
1527 !strconcat(OpcodeStr, "pd"), f128mem,
1528 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1529 (bc_v2i64 (v2f64 VR128:$src2))))],
1530 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1531 (memopv2i64 addr:$src2)))]>, TB, OpSize;
1535 /// sse12_fp_packed_logical_y - AVX 256-bit SSE 1 & 2 logical ops forms
1537 multiclass sse12_fp_packed_logical_y<bits<8> opc, string OpcodeStr,
1539 defm PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
1540 !strconcat(OpcodeStr, "ps"), f256mem,
1541 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
1542 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
1543 (memopv4i64 addr:$src2)))], 0>, VEX_4V;
1545 defm PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
1546 !strconcat(OpcodeStr, "pd"), f256mem,
1547 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
1548 (bc_v4i64 (v4f64 VR256:$src2))))],
1549 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
1550 (memopv4i64 addr:$src2)))], 0>,
1554 // AVX 256-bit packed logical ops forms
1555 defm VAND : sse12_fp_packed_logical_y<0x54, "and", and>;
1556 defm VOR : sse12_fp_packed_logical_y<0x56, "or", or>;
1557 defm VXOR : sse12_fp_packed_logical_y<0x57, "xor", xor>;
1558 defm VANDN : sse12_fp_packed_logical_y<0x55, "andn", X86andnp>;
1560 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
1561 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
1562 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
1563 let isCommutable = 0 in
1564 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
1566 //===----------------------------------------------------------------------===//
1567 // SSE 1 & 2 - Arithmetic Instructions
1568 //===----------------------------------------------------------------------===//
1570 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
1573 /// In addition, we also have a special variant of the scalar form here to
1574 /// represent the associated intrinsic operation. This form is unlike the
1575 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
1576 /// and leaves the top elements unmodified (therefore these cannot be commuted).
1578 /// These three forms can each be reg+reg or reg+mem.
1581 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
1583 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
1585 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
1586 OpNode, FR32, f32mem, Is2Addr>, XS;
1587 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
1588 OpNode, FR64, f64mem, Is2Addr>, XD;
1591 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
1593 let mayLoad = 0 in {
1594 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
1595 v4f32, f128mem, memopv4f32, SSEPackedSingle, Is2Addr>, TB;
1596 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
1597 v2f64, f128mem, memopv2f64, SSEPackedDouble, Is2Addr>, TB, OpSize;
1601 multiclass basic_sse12_fp_binop_p_y<bits<8> opc, string OpcodeStr,
1603 let mayLoad = 0 in {
1604 defm PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR256,
1605 v8f32, f256mem, memopv8f32, SSEPackedSingle, 0>, TB;
1606 defm PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR256,
1607 v4f64, f256mem, memopv4f64, SSEPackedDouble, 0>, TB, OpSize;
1611 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
1613 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1614 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32, Is2Addr>, XS;
1615 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1616 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64, Is2Addr>, XD;
1619 multiclass basic_sse12_fp_binop_p_int<bits<8> opc, string OpcodeStr,
1621 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
1622 !strconcat(OpcodeStr, "ps"), "sse", "_ps", f128mem, memopv4f32,
1623 SSEPackedSingle, Is2Addr>, TB;
1625 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
1626 !strconcat(OpcodeStr, "pd"), "sse2", "_pd", f128mem, memopv2f64,
1627 SSEPackedDouble, Is2Addr>, TB, OpSize;
1630 multiclass basic_sse12_fp_binop_p_y_int<bits<8> opc, string OpcodeStr> {
1631 defm PSY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
1632 !strconcat(OpcodeStr, "ps"), "avx", "_ps_256", f256mem, memopv8f32,
1633 SSEPackedSingle, 0>, TB;
1635 defm PDY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
1636 !strconcat(OpcodeStr, "pd"), "avx", "_pd_256", f256mem, memopv4f64,
1637 SSEPackedDouble, 0>, TB, OpSize;
1640 // Binary Arithmetic instructions
1641 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, 0>,
1642 basic_sse12_fp_binop_s_int<0x58, "add", 0>,
1643 basic_sse12_fp_binop_p<0x58, "add", fadd, 0>,
1644 basic_sse12_fp_binop_p_y<0x58, "add", fadd>, VEX_4V;
1645 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, 0>,
1646 basic_sse12_fp_binop_s_int<0x59, "mul", 0>,
1647 basic_sse12_fp_binop_p<0x59, "mul", fmul, 0>,
1648 basic_sse12_fp_binop_p_y<0x59, "mul", fmul>, VEX_4V;
1650 let isCommutable = 0 in {
1651 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, 0>,
1652 basic_sse12_fp_binop_s_int<0x5C, "sub", 0>,
1653 basic_sse12_fp_binop_p<0x5C, "sub", fsub, 0>,
1654 basic_sse12_fp_binop_p_y<0x5C, "sub", fsub>, VEX_4V;
1655 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, 0>,
1656 basic_sse12_fp_binop_s_int<0x5E, "div", 0>,
1657 basic_sse12_fp_binop_p<0x5E, "div", fdiv, 0>,
1658 basic_sse12_fp_binop_p_y<0x5E, "div", fdiv>, VEX_4V;
1659 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, 0>,
1660 basic_sse12_fp_binop_s_int<0x5F, "max", 0>,
1661 basic_sse12_fp_binop_p<0x5F, "max", X86fmax, 0>,
1662 basic_sse12_fp_binop_p_int<0x5F, "max", 0>,
1663 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax>,
1664 basic_sse12_fp_binop_p_y_int<0x5F, "max">, VEX_4V;
1665 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, 0>,
1666 basic_sse12_fp_binop_s_int<0x5D, "min", 0>,
1667 basic_sse12_fp_binop_p<0x5D, "min", X86fmin, 0>,
1668 basic_sse12_fp_binop_p_int<0x5D, "min", 0>,
1669 basic_sse12_fp_binop_p_y_int<0x5D, "min">,
1670 basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin>, VEX_4V;
1673 let Constraints = "$src1 = $dst" in {
1674 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd>,
1675 basic_sse12_fp_binop_p<0x58, "add", fadd>,
1676 basic_sse12_fp_binop_s_int<0x58, "add">;
1677 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul>,
1678 basic_sse12_fp_binop_p<0x59, "mul", fmul>,
1679 basic_sse12_fp_binop_s_int<0x59, "mul">;
1681 let isCommutable = 0 in {
1682 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub>,
1683 basic_sse12_fp_binop_p<0x5C, "sub", fsub>,
1684 basic_sse12_fp_binop_s_int<0x5C, "sub">;
1685 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv>,
1686 basic_sse12_fp_binop_p<0x5E, "div", fdiv>,
1687 basic_sse12_fp_binop_s_int<0x5E, "div">;
1688 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax>,
1689 basic_sse12_fp_binop_p<0x5F, "max", X86fmax>,
1690 basic_sse12_fp_binop_s_int<0x5F, "max">,
1691 basic_sse12_fp_binop_p_int<0x5F, "max">;
1692 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin>,
1693 basic_sse12_fp_binop_p<0x5D, "min", X86fmin>,
1694 basic_sse12_fp_binop_s_int<0x5D, "min">,
1695 basic_sse12_fp_binop_p_int<0x5D, "min">;
1700 /// In addition, we also have a special variant of the scalar form here to
1701 /// represent the associated intrinsic operation. This form is unlike the
1702 /// plain scalar form, in that it takes an entire vector (instead of a
1703 /// scalar) and leaves the top elements undefined.
1705 /// And, we have a special variant form for a full-vector intrinsic form.
1707 /// sse1_fp_unop_s - SSE1 unops in scalar form.
1708 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
1709 SDNode OpNode, Intrinsic F32Int> {
1710 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1711 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1712 [(set FR32:$dst, (OpNode FR32:$src))]>;
1713 // For scalar unary operations, fold a load into the operation
1714 // only in OptForSize mode. It eliminates an instruction, but it also
1715 // eliminates a whole-register clobber (the load), so it introduces a
1716 // partial register update condition.
1717 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
1718 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1719 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
1720 Requires<[HasSSE1, OptForSize]>;
1721 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1722 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1723 [(set VR128:$dst, (F32Int VR128:$src))]>;
1724 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
1725 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1726 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
1729 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
1730 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr,
1731 SDNode OpNode, Intrinsic F32Int> {
1732 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
1733 !strconcat(OpcodeStr,
1734 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1735 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2),
1736 !strconcat(OpcodeStr,
1737 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1738 []>, XS, Requires<[HasAVX, OptForSize]>;
1739 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1740 !strconcat(OpcodeStr,
1741 "ss\t{$src, $dst, $dst|$dst, $dst, $src}"),
1742 [(set VR128:$dst, (F32Int VR128:$src))]>;
1743 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
1744 !strconcat(OpcodeStr,
1745 "ss\t{$src, $dst, $dst|$dst, $dst, $src}"),
1746 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
1749 /// sse1_fp_unop_p - SSE1 unops in packed form.
1750 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1751 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1752 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1753 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]>;
1754 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1755 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1756 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
1759 /// sse1_fp_unop_p_y - AVX 256-bit SSE1 unops in packed form.
1760 multiclass sse1_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1761 def PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1762 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1763 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))]>;
1764 def PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1765 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1766 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))]>;
1769 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
1770 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
1771 Intrinsic V4F32Int> {
1772 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1773 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1774 [(set VR128:$dst, (V4F32Int VR128:$src))]>;
1775 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1776 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1777 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
1780 /// sse1_fp_unop_p_y_int - AVX 256-bit intrinsics unops in packed forms.
1781 multiclass sse1_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
1782 Intrinsic V4F32Int> {
1783 def PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1784 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1785 [(set VR256:$dst, (V4F32Int VR256:$src))]>;
1786 def PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1787 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1788 [(set VR256:$dst, (V4F32Int (memopv8f32 addr:$src)))]>;
1791 /// sse2_fp_unop_s - SSE2 unops in scalar form.
1792 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
1793 SDNode OpNode, Intrinsic F64Int> {
1794 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1795 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1796 [(set FR64:$dst, (OpNode FR64:$src))]>;
1797 // See the comments in sse1_fp_unop_s for why this is OptForSize.
1798 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1799 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1800 [(set FR64:$dst, (OpNode (load addr:$src)))]>, XD,
1801 Requires<[HasSSE2, OptForSize]>;
1802 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1803 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1804 [(set VR128:$dst, (F64Int VR128:$src))]>;
1805 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1806 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1807 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1810 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
1811 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr,
1812 SDNode OpNode, Intrinsic F64Int> {
1813 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1814 !strconcat(OpcodeStr,
1815 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1816 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
1817 (ins FR64:$src1, f64mem:$src2),
1818 !strconcat(OpcodeStr,
1819 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1820 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1821 !strconcat(OpcodeStr, "sd\t{$src, $dst, $dst|$dst, $dst, $src}"),
1822 [(set VR128:$dst, (F64Int VR128:$src))]>;
1823 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1824 !strconcat(OpcodeStr, "sd\t{$src, $dst, $dst|$dst, $dst, $src}"),
1825 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1828 /// sse2_fp_unop_p - SSE2 unops in vector forms.
1829 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
1831 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1832 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1833 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]>;
1834 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1835 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1836 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1839 /// sse2_fp_unop_p_y - AVX SSE2 256-bit unops in vector forms.
1840 multiclass sse2_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1841 def PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1842 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1843 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))]>;
1844 def PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1845 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1846 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))]>;
1849 /// sse2_fp_unop_p_int - SSE2 intrinsic unops in vector forms.
1850 multiclass sse2_fp_unop_p_int<bits<8> opc, string OpcodeStr,
1851 Intrinsic V2F64Int> {
1852 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1853 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1854 [(set VR128:$dst, (V2F64Int VR128:$src))]>;
1855 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1856 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1857 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
1860 /// sse2_fp_unop_p_y_int - AVX 256-bit intrinsic unops in vector forms.
1861 multiclass sse2_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
1862 Intrinsic V2F64Int> {
1863 def PDYr_Int : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1864 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1865 [(set VR256:$dst, (V2F64Int VR256:$src))]>;
1866 def PDYm_Int : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1867 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1868 [(set VR256:$dst, (V2F64Int (memopv4f64 addr:$src)))]>;
1871 let Predicates = [HasAVX] in {
1873 defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt", fsqrt, int_x86_sse_sqrt_ss>,
1874 sse2_fp_unop_s_avx<0x51, "vsqrt", fsqrt, int_x86_sse2_sqrt_sd>,
1877 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt>,
1878 sse2_fp_unop_p<0x51, "vsqrt", fsqrt>,
1879 sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
1880 sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
1881 sse1_fp_unop_p_int<0x51, "vsqrt", int_x86_sse_sqrt_ps>,
1882 sse2_fp_unop_p_int<0x51, "vsqrt", int_x86_sse2_sqrt_pd>,
1883 sse1_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_ps_256>,
1884 sse2_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_pd_256>,
1887 // Reciprocal approximations. Note that these typically require refinement
1888 // in order to obtain suitable precision.
1889 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt", X86frsqrt,
1890 int_x86_sse_rsqrt_ss>, VEX_4V;
1891 defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt>,
1892 sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt>,
1893 sse1_fp_unop_p_y_int<0x52, "vrsqrt", int_x86_avx_rsqrt_ps_256>,
1894 sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps>, VEX;
1896 defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp", X86frcp, int_x86_sse_rcp_ss>,
1898 defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp>,
1899 sse1_fp_unop_p_y<0x53, "vrcp", X86frcp>,
1900 sse1_fp_unop_p_y_int<0x53, "vrcp", int_x86_avx_rcp_ps_256>,
1901 sse1_fp_unop_p_int<0x53, "vrcp", int_x86_sse_rcp_ps>, VEX;
1904 def : Pat<(f32 (fsqrt FR32:$src)),
1905 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
1906 def : Pat<(f64 (fsqrt FR64:$src)),
1907 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
1908 def : Pat<(f64 (fsqrt (load addr:$src))),
1909 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
1910 Requires<[HasAVX, OptForSize]>;
1911 def : Pat<(f32 (fsqrt (load addr:$src))),
1912 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
1913 Requires<[HasAVX, OptForSize]>;
1916 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss>,
1917 sse1_fp_unop_p<0x51, "sqrt", fsqrt>,
1918 sse1_fp_unop_p_int<0x51, "sqrt", int_x86_sse_sqrt_ps>,
1919 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd>,
1920 sse2_fp_unop_p<0x51, "sqrt", fsqrt>,
1921 sse2_fp_unop_p_int<0x51, "sqrt", int_x86_sse2_sqrt_pd>;
1923 // Reciprocal approximations. Note that these typically require refinement
1924 // in order to obtain suitable precision.
1925 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss>,
1926 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt>,
1927 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps>;
1928 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>,
1929 sse1_fp_unop_p<0x53, "rcp", X86frcp>,
1930 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps>;
1932 // There is no f64 version of the reciprocal approximation instructions.
1934 //===----------------------------------------------------------------------===//
1935 // SSE 1 & 2 - Non-temporal stores
1936 //===----------------------------------------------------------------------===//
1938 let AddedComplexity = 400 in { // Prefer non-temporal versions
1939 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
1940 (ins f128mem:$dst, VR128:$src),
1941 "movntps\t{$src, $dst|$dst, $src}",
1942 [(alignednontemporalstore (v4f32 VR128:$src),
1944 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
1945 (ins f128mem:$dst, VR128:$src),
1946 "movntpd\t{$src, $dst|$dst, $src}",
1947 [(alignednontemporalstore (v2f64 VR128:$src),
1949 def VMOVNTDQ_64mr : VPDI<0xE7, MRMDestMem, (outs),
1950 (ins f128mem:$dst, VR128:$src),
1951 "movntdq\t{$src, $dst|$dst, $src}",
1952 [(alignednontemporalstore (v2f64 VR128:$src),
1955 let ExeDomain = SSEPackedInt in
1956 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
1957 (ins f128mem:$dst, VR128:$src),
1958 "movntdq\t{$src, $dst|$dst, $src}",
1959 [(alignednontemporalstore (v4f32 VR128:$src),
1962 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
1963 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
1965 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
1966 (ins f256mem:$dst, VR256:$src),
1967 "movntps\t{$src, $dst|$dst, $src}",
1968 [(alignednontemporalstore (v8f32 VR256:$src),
1970 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
1971 (ins f256mem:$dst, VR256:$src),
1972 "movntpd\t{$src, $dst|$dst, $src}",
1973 [(alignednontemporalstore (v4f64 VR256:$src),
1975 def VMOVNTDQY_64mr : VPDI<0xE7, MRMDestMem, (outs),
1976 (ins f256mem:$dst, VR256:$src),
1977 "movntdq\t{$src, $dst|$dst, $src}",
1978 [(alignednontemporalstore (v4f64 VR256:$src),
1980 let ExeDomain = SSEPackedInt in
1981 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
1982 (ins f256mem:$dst, VR256:$src),
1983 "movntdq\t{$src, $dst|$dst, $src}",
1984 [(alignednontemporalstore (v8f32 VR256:$src),
1988 def : Pat<(int_x86_avx_movnt_dq_256 addr:$dst, VR256:$src),
1989 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
1990 def : Pat<(int_x86_avx_movnt_pd_256 addr:$dst, VR256:$src),
1991 (VMOVNTPDYmr addr:$dst, VR256:$src)>;
1992 def : Pat<(int_x86_avx_movnt_ps_256 addr:$dst, VR256:$src),
1993 (VMOVNTPSYmr addr:$dst, VR256:$src)>;
1995 let AddedComplexity = 400 in { // Prefer non-temporal versions
1996 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1997 "movntps\t{$src, $dst|$dst, $src}",
1998 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
1999 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2000 "movntpd\t{$src, $dst|$dst, $src}",
2001 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
2003 def MOVNTDQ_64mr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2004 "movntdq\t{$src, $dst|$dst, $src}",
2005 [(alignednontemporalstore (v2f64 VR128:$src), addr:$dst)]>;
2007 let ExeDomain = SSEPackedInt in
2008 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2009 "movntdq\t{$src, $dst|$dst, $src}",
2010 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
2012 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
2013 (MOVNTDQmr addr:$dst, VR128:$src)>;
2015 // There is no AVX form for instructions below this point
2016 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2017 "movnti{l}\t{$src, $dst|$dst, $src}",
2018 [(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
2019 TB, Requires<[HasSSE2]>;
2020 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
2021 "movnti{q}\t{$src, $dst|$dst, $src}",
2022 [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
2023 TB, Requires<[HasSSE2]>;
2026 //===----------------------------------------------------------------------===//
2027 // SSE 1 & 2 - Misc Instructions (No AVX form)
2028 //===----------------------------------------------------------------------===//
2030 // Prefetch intrinsic.
2031 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
2032 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))]>;
2033 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
2034 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))]>;
2035 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
2036 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))]>;
2037 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
2038 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))]>;
2040 // Load, store, and memory fence
2041 def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>,
2042 TB, Requires<[HasSSE1]>;
2043 def : Pat<(X86SFence), (SFENCE)>;
2045 // Alias instructions that map zero vector to pxor / xorp* for sse.
2046 // We set canFoldAsLoad because this can be converted to a constant-pool
2047 // load of an all-zeros value if folding it would be beneficial.
2048 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
2049 // JIT implementation, it does not expand the instructions below like
2050 // X86MCInstLower does.
2051 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
2052 isCodeGenOnly = 1 in {
2053 def V_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2054 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
2055 def V_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2056 [(set VR128:$dst, (v2f64 immAllZerosV))]>;
2057 let ExeDomain = SSEPackedInt in
2058 def V_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
2059 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
2062 // The same as done above but for AVX. The 128-bit versions are the
2063 // same, but re-encoded. The 256-bit does not support PI version, and
2064 // doesn't need it because on sandy bridge the register is set to zero
2065 // at the rename stage without using any execution unit, so SET0PSY
2066 // and SET0PDY can be used for vector int instructions without penalty
2067 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
2068 // JIT implementatioan, it does not expand the instructions below like
2069 // X86MCInstLower does.
2070 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
2071 isCodeGenOnly = 1, Predicates = [HasAVX] in {
2072 def AVX_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2073 [(set VR128:$dst, (v4f32 immAllZerosV))]>, VEX_4V;
2074 def AVX_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2075 [(set VR128:$dst, (v2f64 immAllZerosV))]>, VEX_4V;
2076 def AVX_SET0PSY : PSI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
2077 [(set VR256:$dst, (v8f32 immAllZerosV))]>, VEX_4V;
2078 def AVX_SET0PDY : PDI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
2079 [(set VR256:$dst, (v4f64 immAllZerosV))]>, VEX_4V;
2080 let ExeDomain = SSEPackedInt in
2081 def AVX_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
2082 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
2085 def : Pat<(v2i64 immAllZerosV), (V_SET0PI)>;
2086 def : Pat<(v8i16 immAllZerosV), (V_SET0PI)>;
2087 def : Pat<(v16i8 immAllZerosV), (V_SET0PI)>;
2089 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
2090 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
2092 //===----------------------------------------------------------------------===//
2093 // SSE 1 & 2 - Load/Store XCSR register
2094 //===----------------------------------------------------------------------===//
2096 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
2097 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>, VEX;
2098 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
2099 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>, VEX;
2101 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
2102 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
2103 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
2104 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
2106 //===---------------------------------------------------------------------===//
2107 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
2108 //===---------------------------------------------------------------------===//
2110 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2112 let neverHasSideEffects = 1 in {
2113 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2114 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2115 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2116 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2118 def VMOVDQUrr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2119 "movdqu\t{$src, $dst|$dst, $src}", []>, XS, VEX;
2120 def VMOVDQUYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2121 "movdqu\t{$src, $dst|$dst, $src}", []>, XS, VEX;
2123 let canFoldAsLoad = 1, mayLoad = 1 in {
2124 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2125 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2126 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
2127 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2128 let Predicates = [HasAVX] in {
2129 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2130 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2131 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
2132 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2136 let mayStore = 1 in {
2137 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
2138 (ins i128mem:$dst, VR128:$src),
2139 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2140 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
2141 (ins i256mem:$dst, VR256:$src),
2142 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2143 let Predicates = [HasAVX] in {
2144 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2145 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2146 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
2147 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2151 let neverHasSideEffects = 1 in
2152 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2153 "movdqa\t{$src, $dst|$dst, $src}", []>;
2155 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2156 "movdqu\t{$src, $dst|$dst, $src}",
2157 []>, XS, Requires<[HasSSE2]>;
2159 let canFoldAsLoad = 1, mayLoad = 1 in {
2160 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2161 "movdqa\t{$src, $dst|$dst, $src}",
2162 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
2163 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2164 "movdqu\t{$src, $dst|$dst, $src}",
2165 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
2166 XS, Requires<[HasSSE2]>;
2169 let mayStore = 1 in {
2170 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2171 "movdqa\t{$src, $dst|$dst, $src}",
2172 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
2173 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2174 "movdqu\t{$src, $dst|$dst, $src}",
2175 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
2176 XS, Requires<[HasSSE2]>;
2179 // Intrinsic forms of MOVDQU load and store
2180 def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2181 "vmovdqu\t{$src, $dst|$dst, $src}",
2182 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
2183 XS, VEX, Requires<[HasAVX]>;
2185 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2186 "movdqu\t{$src, $dst|$dst, $src}",
2187 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
2188 XS, Requires<[HasSSE2]>;
2190 } // ExeDomain = SSEPackedInt
2192 def : Pat<(int_x86_avx_loadu_dq_256 addr:$src), (VMOVDQUYrm addr:$src)>;
2193 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
2194 (VMOVDQUYmr addr:$dst, VR256:$src)>;
2196 //===---------------------------------------------------------------------===//
2197 // SSE2 - Packed Integer Arithmetic Instructions
2198 //===---------------------------------------------------------------------===//
2200 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2202 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
2203 bit IsCommutable = 0, bit Is2Addr = 1> {
2204 let isCommutable = IsCommutable in
2205 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2206 (ins VR128:$src1, VR128:$src2),
2208 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2209 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2210 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2211 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2212 (ins VR128:$src1, i128mem:$src2),
2214 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2215 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2216 [(set VR128:$dst, (IntId VR128:$src1,
2217 (bitconvert (memopv2i64 addr:$src2))))]>;
2220 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
2221 string OpcodeStr, Intrinsic IntId,
2222 Intrinsic IntId2, bit Is2Addr = 1> {
2223 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2224 (ins VR128:$src1, VR128:$src2),
2226 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2227 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2228 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2229 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2230 (ins VR128:$src1, i128mem:$src2),
2232 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2233 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2234 [(set VR128:$dst, (IntId VR128:$src1,
2235 (bitconvert (memopv2i64 addr:$src2))))]>;
2236 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst),
2237 (ins VR128:$src1, i32i8imm:$src2),
2239 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2240 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2241 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
2244 /// PDI_binop_rm - Simple SSE2 binary operator.
2245 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2246 ValueType OpVT, bit IsCommutable = 0, bit Is2Addr = 1> {
2247 let isCommutable = IsCommutable in
2248 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2249 (ins VR128:$src1, VR128:$src2),
2251 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2252 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2253 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>;
2254 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2255 (ins VR128:$src1, i128mem:$src2),
2257 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2258 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2259 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
2260 (bitconvert (memopv2i64 addr:$src2)))))]>;
2263 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
2265 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
2266 /// to collapse (bitconvert VT to VT) into its operand.
2268 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
2269 bit IsCommutable = 0, bit Is2Addr = 1> {
2270 let isCommutable = IsCommutable in
2271 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2272 (ins VR128:$src1, VR128:$src2),
2274 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2275 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2276 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]>;
2277 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2278 (ins VR128:$src1, i128mem:$src2),
2280 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2281 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2282 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2i64 addr:$src2)))]>;
2285 } // ExeDomain = SSEPackedInt
2287 // 128-bit Integer Arithmetic
2289 let Predicates = [HasAVX] in {
2290 defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, 1, 0 /*3addr*/>, VEX_4V;
2291 defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, 1, 0>, VEX_4V;
2292 defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, 1, 0>, VEX_4V;
2293 defm VPADDQ : PDI_binop_rm_v2i64<0xD4, "vpaddq", add, 1, 0>, VEX_4V;
2294 defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, 1, 0>, VEX_4V;
2295 defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, 0, 0>, VEX_4V;
2296 defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, 0, 0>, VEX_4V;
2297 defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, 0, 0>, VEX_4V;
2298 defm VPSUBQ : PDI_binop_rm_v2i64<0xFB, "vpsubq", sub, 0, 0>, VEX_4V;
2301 defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b, 0, 0>,
2303 defm VPSUBSW : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w, 0, 0>,
2305 defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b, 0, 0>,
2307 defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w, 0, 0>,
2309 defm VPADDSB : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b, 1, 0>,
2311 defm VPADDSW : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w, 1, 0>,
2313 defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b, 1, 0>,
2315 defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w, 1, 0>,
2317 defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w, 1, 0>,
2319 defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w, 1, 0>,
2321 defm VPMULUDQ : PDI_binop_rm_int<0xF4, "vpmuludq", int_x86_sse2_pmulu_dq, 1, 0>,
2323 defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd, 1, 0>,
2325 defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b, 1, 0>,
2327 defm VPAVGW : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w, 1, 0>,
2329 defm VPMINUB : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b, 1, 0>,
2331 defm VPMINSW : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w, 1, 0>,
2333 defm VPMAXUB : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b, 1, 0>,
2335 defm VPMAXSW : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w, 1, 0>,
2337 defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw, 1, 0>,
2341 let Constraints = "$src1 = $dst" in {
2342 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
2343 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
2344 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
2345 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
2346 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
2347 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
2348 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
2349 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
2350 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
2353 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
2354 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
2355 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
2356 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
2357 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
2358 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
2359 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
2360 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
2361 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
2362 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w, 1>;
2363 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
2364 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
2365 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
2366 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
2367 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
2368 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
2369 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
2370 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
2371 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw, 1>;
2373 } // Constraints = "$src1 = $dst"
2375 //===---------------------------------------------------------------------===//
2376 // SSE2 - Packed Integer Logical Instructions
2377 //===---------------------------------------------------------------------===//
2379 let Predicates = [HasAVX] in {
2380 defm VPSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "vpsllw",
2381 int_x86_sse2_psll_w, int_x86_sse2_pslli_w, 0>,
2383 defm VPSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "vpslld",
2384 int_x86_sse2_psll_d, int_x86_sse2_pslli_d, 0>,
2386 defm VPSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "vpsllq",
2387 int_x86_sse2_psll_q, int_x86_sse2_pslli_q, 0>,
2390 defm VPSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "vpsrlw",
2391 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w, 0>,
2393 defm VPSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "vpsrld",
2394 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d, 0>,
2396 defm VPSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "vpsrlq",
2397 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q, 0>,
2400 defm VPSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "vpsraw",
2401 int_x86_sse2_psra_w, int_x86_sse2_psrai_w, 0>,
2403 defm VPSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "vpsrad",
2404 int_x86_sse2_psra_d, int_x86_sse2_psrai_d, 0>,
2407 defm VPAND : PDI_binop_rm_v2i64<0xDB, "vpand", and, 1, 0>, VEX_4V;
2408 defm VPOR : PDI_binop_rm_v2i64<0xEB, "vpor" , or, 1, 0>, VEX_4V;
2409 defm VPXOR : PDI_binop_rm_v2i64<0xEF, "vpxor", xor, 1, 0>, VEX_4V;
2411 let ExeDomain = SSEPackedInt in {
2412 let neverHasSideEffects = 1 in {
2413 // 128-bit logical shifts.
2414 def VPSLLDQri : PDIi8<0x73, MRM7r,
2415 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2416 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2418 def VPSRLDQri : PDIi8<0x73, MRM3r,
2419 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2420 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2422 // PSRADQri doesn't exist in SSE[1-3].
2424 def VPANDNrr : PDI<0xDF, MRMSrcReg,
2425 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2426 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2427 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2428 VR128:$src2)))]>, VEX_4V;
2430 def VPANDNrm : PDI<0xDF, MRMSrcMem,
2431 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2432 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2433 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2434 (memopv2i64 addr:$src2))))]>,
2439 let Constraints = "$src1 = $dst" in {
2440 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
2441 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
2442 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
2443 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
2444 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
2445 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
2447 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
2448 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
2449 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
2450 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
2451 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
2452 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
2454 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
2455 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
2456 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
2457 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
2459 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
2460 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or, 1>;
2461 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
2463 let ExeDomain = SSEPackedInt in {
2464 let neverHasSideEffects = 1 in {
2465 // 128-bit logical shifts.
2466 def PSLLDQri : PDIi8<0x73, MRM7r,
2467 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2468 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
2469 def PSRLDQri : PDIi8<0x73, MRM3r,
2470 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2471 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
2472 // PSRADQri doesn't exist in SSE[1-3].
2474 def PANDNrr : PDI<0xDF, MRMSrcReg,
2475 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2476 "pandn\t{$src2, $dst|$dst, $src2}", []>;
2478 def PANDNrm : PDI<0xDF, MRMSrcMem,
2479 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2480 "pandn\t{$src2, $dst|$dst, $src2}", []>;
2482 } // Constraints = "$src1 = $dst"
2484 let Predicates = [HasAVX] in {
2485 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2486 (v2i64 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2487 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2488 (v2i64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2489 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
2490 (v2i64 (VPSLLDQri VR128:$src1, imm:$src2))>;
2491 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
2492 (v2i64 (VPSRLDQri VR128:$src1, imm:$src2))>;
2493 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
2494 (v2f64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2496 // Shift up / down and insert zero's.
2497 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
2498 (v2i64 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2499 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
2500 (v2i64 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2503 let Predicates = [HasSSE2] in {
2504 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2505 (v2i64 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2506 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2507 (v2i64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2508 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
2509 (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
2510 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
2511 (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
2512 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
2513 (v2f64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2515 // Shift up / down and insert zero's.
2516 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
2517 (v2i64 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2518 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
2519 (v2i64 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2522 //===---------------------------------------------------------------------===//
2523 // SSE2 - Packed Integer Comparison Instructions
2524 //===---------------------------------------------------------------------===//
2526 let Predicates = [HasAVX] in {
2527 defm VPCMPEQB : PDI_binop_rm_int<0x74, "vpcmpeqb", int_x86_sse2_pcmpeq_b, 1,
2529 defm VPCMPEQW : PDI_binop_rm_int<0x75, "vpcmpeqw", int_x86_sse2_pcmpeq_w, 1,
2531 defm VPCMPEQD : PDI_binop_rm_int<0x76, "vpcmpeqd", int_x86_sse2_pcmpeq_d, 1,
2533 defm VPCMPGTB : PDI_binop_rm_int<0x64, "vpcmpgtb", int_x86_sse2_pcmpgt_b, 0,
2535 defm VPCMPGTW : PDI_binop_rm_int<0x65, "vpcmpgtw", int_x86_sse2_pcmpgt_w, 0,
2537 defm VPCMPGTD : PDI_binop_rm_int<0x66, "vpcmpgtd", int_x86_sse2_pcmpgt_d, 0,
2541 let Constraints = "$src1 = $dst" in {
2542 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b, 1>;
2543 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w, 1>;
2544 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d, 1>;
2545 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
2546 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
2547 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
2548 } // Constraints = "$src1 = $dst"
2550 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
2551 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
2552 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
2553 (PCMPEQBrm VR128:$src1, addr:$src2)>;
2554 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
2555 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
2556 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
2557 (PCMPEQWrm VR128:$src1, addr:$src2)>;
2558 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
2559 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
2560 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
2561 (PCMPEQDrm VR128:$src1, addr:$src2)>;
2563 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
2564 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
2565 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
2566 (PCMPGTBrm VR128:$src1, addr:$src2)>;
2567 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
2568 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
2569 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
2570 (PCMPGTWrm VR128:$src1, addr:$src2)>;
2571 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
2572 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
2573 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
2574 (PCMPGTDrm VR128:$src1, addr:$src2)>;
2576 //===---------------------------------------------------------------------===//
2577 // SSE2 - Packed Integer Pack Instructions
2578 //===---------------------------------------------------------------------===//
2580 let Predicates = [HasAVX] in {
2581 defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
2583 defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
2585 defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
2589 let Constraints = "$src1 = $dst" in {
2590 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
2591 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
2592 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
2593 } // Constraints = "$src1 = $dst"
2595 //===---------------------------------------------------------------------===//
2596 // SSE2 - Packed Integer Shuffle Instructions
2597 //===---------------------------------------------------------------------===//
2599 let ExeDomain = SSEPackedInt in {
2600 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, PatFrag pshuf_frag,
2602 def ri : Ii8<0x70, MRMSrcReg,
2603 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2604 !strconcat(OpcodeStr,
2605 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2606 [(set VR128:$dst, (vt (pshuf_frag:$src2 VR128:$src1,
2608 def mi : Ii8<0x70, MRMSrcMem,
2609 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2610 !strconcat(OpcodeStr,
2611 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2612 [(set VR128:$dst, (vt (pshuf_frag:$src2
2613 (bc_frag (memopv2i64 addr:$src1)),
2616 } // ExeDomain = SSEPackedInt
2618 let Predicates = [HasAVX] in {
2619 let AddedComplexity = 5 in
2620 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, pshufd, bc_v4i32>, OpSize,
2623 // SSE2 with ImmT == Imm8 and XS prefix.
2624 defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, pshufhw, bc_v8i16>, XS,
2627 // SSE2 with ImmT == Imm8 and XD prefix.
2628 defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, pshuflw, bc_v8i16>, XD,
2632 let Predicates = [HasSSE2] in {
2633 let AddedComplexity = 5 in
2634 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize;
2636 // SSE2 with ImmT == Imm8 and XS prefix.
2637 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, pshufhw, bc_v8i16>, XS;
2639 // SSE2 with ImmT == Imm8 and XD prefix.
2640 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, pshuflw, bc_v8i16>, XD;
2643 //===---------------------------------------------------------------------===//
2644 // SSE2 - Packed Integer Unpack Instructions
2645 //===---------------------------------------------------------------------===//
2647 let ExeDomain = SSEPackedInt in {
2648 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
2649 PatFrag unp_frag, PatFrag bc_frag, bit Is2Addr = 1> {
2650 def rr : PDI<opc, MRMSrcReg,
2651 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2653 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2654 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2655 [(set VR128:$dst, (vt (unp_frag VR128:$src1, VR128:$src2)))]>;
2656 def rm : PDI<opc, MRMSrcMem,
2657 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2659 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2660 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2661 [(set VR128:$dst, (unp_frag VR128:$src1,
2662 (bc_frag (memopv2i64
2666 let Predicates = [HasAVX] in {
2667 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, unpckl, bc_v16i8,
2669 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, unpckl, bc_v8i16,
2671 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, unpckl, bc_v4i32,
2674 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2675 /// knew to collapse (bitconvert VT to VT) into its operand.
2676 def VPUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2677 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2678 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2680 (v2i64 (unpckl VR128:$src1, VR128:$src2)))]>, VEX_4V;
2681 def VPUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2682 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2683 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2685 (v2i64 (unpckl VR128:$src1,
2686 (memopv2i64 addr:$src2))))]>, VEX_4V;
2688 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, unpckh, bc_v16i8,
2690 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, unpckh, bc_v8i16,
2692 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, unpckh, bc_v4i32,
2695 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2696 /// knew to collapse (bitconvert VT to VT) into its operand.
2697 def VPUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2698 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2699 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2701 (v2i64 (unpckh VR128:$src1, VR128:$src2)))]>, VEX_4V;
2702 def VPUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2703 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2704 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2706 (v2i64 (unpckh VR128:$src1,
2707 (memopv2i64 addr:$src2))))]>, VEX_4V;
2710 let Constraints = "$src1 = $dst" in {
2711 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, unpckl, bc_v16i8>;
2712 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, unpckl, bc_v8i16>;
2713 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, unpckl, bc_v4i32>;
2715 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2716 /// knew to collapse (bitconvert VT to VT) into its operand.
2717 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2718 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2719 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2721 (v2i64 (unpckl VR128:$src1, VR128:$src2)))]>;
2722 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2723 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2724 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2726 (v2i64 (unpckl VR128:$src1,
2727 (memopv2i64 addr:$src2))))]>;
2729 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, unpckh, bc_v16i8>;
2730 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, unpckh, bc_v8i16>;
2731 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, unpckh, bc_v4i32>;
2733 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2734 /// knew to collapse (bitconvert VT to VT) into its operand.
2735 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2736 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2737 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2739 (v2i64 (unpckh VR128:$src1, VR128:$src2)))]>;
2740 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2741 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2742 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2744 (v2i64 (unpckh VR128:$src1,
2745 (memopv2i64 addr:$src2))))]>;
2748 } // ExeDomain = SSEPackedInt
2750 //===---------------------------------------------------------------------===//
2751 // SSE2 - Packed Integer Extract and Insert
2752 //===---------------------------------------------------------------------===//
2754 let ExeDomain = SSEPackedInt in {
2755 multiclass sse2_pinsrw<bit Is2Addr = 1> {
2756 def rri : Ii8<0xC4, MRMSrcReg,
2757 (outs VR128:$dst), (ins VR128:$src1,
2758 GR32:$src2, i32i8imm:$src3),
2760 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2761 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2763 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
2764 def rmi : Ii8<0xC4, MRMSrcMem,
2765 (outs VR128:$dst), (ins VR128:$src1,
2766 i16mem:$src2, i32i8imm:$src3),
2768 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2769 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2771 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
2776 let Predicates = [HasAVX] in
2777 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
2778 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2779 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2780 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2781 imm:$src2))]>, OpSize, VEX;
2782 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2783 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2784 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2785 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2789 let Predicates = [HasAVX] in {
2790 defm VPINSRW : sse2_pinsrw<0>, OpSize, VEX_4V;
2791 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
2792 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
2793 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2794 []>, OpSize, VEX_4V;
2797 let Constraints = "$src1 = $dst" in
2798 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[HasSSE2]>;
2800 } // ExeDomain = SSEPackedInt
2802 //===---------------------------------------------------------------------===//
2803 // SSE2 - Packed Mask Creation
2804 //===---------------------------------------------------------------------===//
2806 let ExeDomain = SSEPackedInt in {
2808 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2809 "pmovmskb\t{$src, $dst|$dst, $src}",
2810 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>, VEX;
2811 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2812 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX;
2813 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2814 "pmovmskb\t{$src, $dst|$dst, $src}",
2815 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2817 } // ExeDomain = SSEPackedInt
2819 //===---------------------------------------------------------------------===//
2820 // SSE2 - Conditional Store
2821 //===---------------------------------------------------------------------===//
2823 let ExeDomain = SSEPackedInt in {
2826 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
2827 (ins VR128:$src, VR128:$mask),
2828 "maskmovdqu\t{$mask, $src|$src, $mask}",
2829 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>, VEX;
2831 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
2832 (ins VR128:$src, VR128:$mask),
2833 "maskmovdqu\t{$mask, $src|$src, $mask}",
2834 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>, VEX;
2837 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2838 "maskmovdqu\t{$mask, $src|$src, $mask}",
2839 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
2841 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2842 "maskmovdqu\t{$mask, $src|$src, $mask}",
2843 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
2845 } // ExeDomain = SSEPackedInt
2847 //===---------------------------------------------------------------------===//
2848 // SSE2 - Move Doubleword
2849 //===---------------------------------------------------------------------===//
2851 // Move Int Doubleword to Packed Double Int
2852 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2853 "movd\t{$src, $dst|$dst, $src}",
2855 (v4i32 (scalar_to_vector GR32:$src)))]>, VEX;
2856 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2857 "movd\t{$src, $dst|$dst, $src}",
2859 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>,
2861 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2862 "movd\t{$src, $dst|$dst, $src}",
2864 (v4i32 (scalar_to_vector GR32:$src)))]>;
2865 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2866 "movd\t{$src, $dst|$dst, $src}",
2868 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2869 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2870 "mov{d|q}\t{$src, $dst|$dst, $src}",
2872 (v2i64 (scalar_to_vector GR64:$src)))]>;
2873 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2874 "mov{d|q}\t{$src, $dst|$dst, $src}",
2875 [(set FR64:$dst, (bitconvert GR64:$src))]>;
2878 // Move Int Doubleword to Single Scalar
2879 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2880 "movd\t{$src, $dst|$dst, $src}",
2881 [(set FR32:$dst, (bitconvert GR32:$src))]>, VEX;
2883 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2884 "movd\t{$src, $dst|$dst, $src}",
2885 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>,
2887 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2888 "movd\t{$src, $dst|$dst, $src}",
2889 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2891 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2892 "movd\t{$src, $dst|$dst, $src}",
2893 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2895 // Move Packed Doubleword Int to Packed Double Int
2896 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2897 "movd\t{$src, $dst|$dst, $src}",
2898 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2900 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
2901 (ins i32mem:$dst, VR128:$src),
2902 "movd\t{$src, $dst|$dst, $src}",
2903 [(store (i32 (vector_extract (v4i32 VR128:$src),
2904 (iPTR 0))), addr:$dst)]>, VEX;
2905 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2906 "movd\t{$src, $dst|$dst, $src}",
2907 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2909 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
2910 "movd\t{$src, $dst|$dst, $src}",
2911 [(store (i32 (vector_extract (v4i32 VR128:$src),
2912 (iPTR 0))), addr:$dst)]>;
2914 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
2915 "mov{d|q}\t{$src, $dst|$dst, $src}",
2916 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
2918 def MOV64toSDrm : S3SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
2919 "movq\t{$src, $dst|$dst, $src}",
2920 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
2922 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2923 "mov{d|q}\t{$src, $dst|$dst, $src}",
2924 [(set GR64:$dst, (bitconvert FR64:$src))]>;
2925 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2926 "movq\t{$src, $dst|$dst, $src}",
2927 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
2929 // Move Scalar Single to Double Int
2930 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2931 "movd\t{$src, $dst|$dst, $src}",
2932 [(set GR32:$dst, (bitconvert FR32:$src))]>, VEX;
2933 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2934 "movd\t{$src, $dst|$dst, $src}",
2935 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>, VEX;
2936 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2937 "movd\t{$src, $dst|$dst, $src}",
2938 [(set GR32:$dst, (bitconvert FR32:$src))]>;
2939 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2940 "movd\t{$src, $dst|$dst, $src}",
2941 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
2943 // movd / movq to XMM register zero-extends
2944 let AddedComplexity = 15 in {
2945 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2946 "movd\t{$src, $dst|$dst, $src}",
2947 [(set VR128:$dst, (v4i32 (X86vzmovl
2948 (v4i32 (scalar_to_vector GR32:$src)))))]>,
2950 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2951 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
2952 [(set VR128:$dst, (v2i64 (X86vzmovl
2953 (v2i64 (scalar_to_vector GR64:$src)))))]>,
2956 let AddedComplexity = 15 in {
2957 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2958 "movd\t{$src, $dst|$dst, $src}",
2959 [(set VR128:$dst, (v4i32 (X86vzmovl
2960 (v4i32 (scalar_to_vector GR32:$src)))))]>;
2961 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2962 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
2963 [(set VR128:$dst, (v2i64 (X86vzmovl
2964 (v2i64 (scalar_to_vector GR64:$src)))))]>;
2967 let AddedComplexity = 20 in {
2968 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2969 "movd\t{$src, $dst|$dst, $src}",
2971 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
2972 (loadi32 addr:$src))))))]>,
2974 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2975 "movd\t{$src, $dst|$dst, $src}",
2977 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
2978 (loadi32 addr:$src))))))]>;
2980 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
2981 (MOVZDI2PDIrm addr:$src)>;
2982 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2983 (MOVZDI2PDIrm addr:$src)>;
2984 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2985 (MOVZDI2PDIrm addr:$src)>;
2988 // These are the correct encodings of the instructions so that we know how to
2989 // read correct assembly, even though we continue to emit the wrong ones for
2990 // compatibility with Darwin's buggy assembler.
2991 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
2992 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
2993 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
2994 (MOV64toSDrr FR64:$dst, GR64:$src), 0>;
2995 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
2996 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
2997 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
2998 (MOVSDto64rr GR64:$dst, FR64:$src), 0>;
2999 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3000 (VMOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
3001 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3002 (MOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
3004 //===---------------------------------------------------------------------===//
3005 // SSE2 - Move Quadword
3006 //===---------------------------------------------------------------------===//
3008 // Move Quadword Int to Packed Quadword Int
3009 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3010 "vmovq\t{$src, $dst|$dst, $src}",
3012 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
3013 VEX, Requires<[HasAVX]>;
3014 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3015 "movq\t{$src, $dst|$dst, $src}",
3017 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
3018 Requires<[HasSSE2]>; // SSE2 instruction with XS Prefix
3020 // Move Packed Quadword Int to Quadword Int
3021 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3022 "movq\t{$src, $dst|$dst, $src}",
3023 [(store (i64 (vector_extract (v2i64 VR128:$src),
3024 (iPTR 0))), addr:$dst)]>, VEX;
3025 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3026 "movq\t{$src, $dst|$dst, $src}",
3027 [(store (i64 (vector_extract (v2i64 VR128:$src),
3028 (iPTR 0))), addr:$dst)]>;
3030 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
3031 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
3033 // Store / copy lower 64-bits of a XMM register.
3034 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3035 "movq\t{$src, $dst|$dst, $src}",
3036 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
3037 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3038 "movq\t{$src, $dst|$dst, $src}",
3039 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
3041 let AddedComplexity = 20 in
3042 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3043 "vmovq\t{$src, $dst|$dst, $src}",
3045 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
3046 (loadi64 addr:$src))))))]>,
3047 XS, VEX, Requires<[HasAVX]>;
3049 let AddedComplexity = 20 in {
3050 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3051 "movq\t{$src, $dst|$dst, $src}",
3053 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
3054 (loadi64 addr:$src))))))]>,
3055 XS, Requires<[HasSSE2]>;
3057 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
3058 (MOVZQI2PQIrm addr:$src)>;
3059 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
3060 (MOVZQI2PQIrm addr:$src)>;
3061 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
3064 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
3065 // IA32 document. movq xmm1, xmm2 does clear the high bits.
3066 let AddedComplexity = 15 in
3067 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3068 "vmovq\t{$src, $dst|$dst, $src}",
3069 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
3070 XS, VEX, Requires<[HasAVX]>;
3071 let AddedComplexity = 15 in
3072 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3073 "movq\t{$src, $dst|$dst, $src}",
3074 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
3075 XS, Requires<[HasSSE2]>;
3077 let AddedComplexity = 20 in
3078 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3079 "vmovq\t{$src, $dst|$dst, $src}",
3080 [(set VR128:$dst, (v2i64 (X86vzmovl
3081 (loadv2i64 addr:$src))))]>,
3082 XS, VEX, Requires<[HasAVX]>;
3083 let AddedComplexity = 20 in {
3084 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3085 "movq\t{$src, $dst|$dst, $src}",
3086 [(set VR128:$dst, (v2i64 (X86vzmovl
3087 (loadv2i64 addr:$src))))]>,
3088 XS, Requires<[HasSSE2]>;
3090 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
3091 (MOVZPQILo2PQIrm addr:$src)>;
3094 // Instructions to match in the assembler
3095 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3096 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3097 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
3098 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3099 // Recognize "movd" with GR64 destination, but encode as a "movq"
3100 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
3101 "movd\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3103 // Instructions for the disassembler
3104 // xr = XMM register
3107 let Predicates = [HasAVX] in
3108 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3109 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
3110 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3111 "movq\t{$src, $dst|$dst, $src}", []>, XS;
3113 //===---------------------------------------------------------------------===//
3114 // SSE2 - Misc Instructions
3115 //===---------------------------------------------------------------------===//
3118 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3119 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
3120 TB, Requires<[HasSSE2]>;
3122 // Load, store, and memory fence
3123 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3124 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
3125 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3126 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
3127 def : Pat<(X86LFence), (LFENCE)>;
3128 def : Pat<(X86MFence), (MFENCE)>;
3131 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3132 // was introduced with SSE2, it's backward compatible.
3133 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
3135 // Alias instructions that map zero vector to pxor / xorp* for sse.
3136 // We set canFoldAsLoad because this can be converted to a constant-pool
3137 // load of an all-ones value if folding it would be beneficial.
3138 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
3139 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in
3140 // FIXME: Change encoding to pseudo.
3141 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
3142 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
3144 //===---------------------------------------------------------------------===//
3145 // SSE3 - Conversion Instructions
3146 //===---------------------------------------------------------------------===//
3148 // Convert Packed Double FP to Packed DW Integers
3149 let Predicates = [HasAVX] in {
3150 // The assembler can recognize rr 256-bit instructions by seeing a ymm
3151 // register, but the same isn't true when using memory operands instead.
3152 // Provide other assembly rr and rm forms to address this explicitly.
3153 def VCVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3154 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
3155 def VCVTPD2DQXrYr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
3156 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
3159 def VCVTPD2DQXrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3160 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
3161 def VCVTPD2DQXrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3162 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
3165 def VCVTPD2DQYrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
3166 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
3167 def VCVTPD2DQYrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
3168 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
3171 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3172 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
3173 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3174 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
3176 // Convert Packed DW Integers to Packed Double FP
3177 let Predicates = [HasAVX] in {
3178 def VCVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3179 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3180 def VCVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3181 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3182 def VCVTDQ2PDYrm : S3SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
3183 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3184 def VCVTDQ2PDYrr : S3SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
3185 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3188 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3189 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
3190 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3191 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
3193 // AVX 256-bit register conversion intrinsics
3194 def : Pat<(int_x86_avx_cvtdq2_pd_256 VR128:$src),
3195 (VCVTDQ2PDYrr VR128:$src)>;
3196 def : Pat<(int_x86_avx_cvtdq2_pd_256 (memopv4i32 addr:$src)),
3197 (VCVTDQ2PDYrm addr:$src)>;
3199 def : Pat<(int_x86_avx_cvt_pd2dq_256 VR256:$src),
3200 (VCVTPD2DQYrr VR256:$src)>;
3201 def : Pat<(int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)),
3202 (VCVTPD2DQYrm addr:$src)>;
3204 //===---------------------------------------------------------------------===//
3205 // SSE3 - Move Instructions
3206 //===---------------------------------------------------------------------===//
3208 // Replicate Single FP
3209 multiclass sse3_replicate_sfp<bits<8> op, PatFrag rep_frag, string OpcodeStr> {
3210 def rr : S3SI<op, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3211 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3212 [(set VR128:$dst, (v4f32 (rep_frag
3213 VR128:$src, (undef))))]>;
3214 def rm : S3SI<op, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3215 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3216 [(set VR128:$dst, (rep_frag
3217 (memopv4f32 addr:$src), (undef)))]>;
3220 multiclass sse3_replicate_sfp_y<bits<8> op, PatFrag rep_frag,
3222 def rr : S3SI<op, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3223 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
3224 def rm : S3SI<op, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3225 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
3228 let Predicates = [HasAVX] in {
3229 // FIXME: Merge above classes when we have patterns for the ymm version
3230 defm VMOVSHDUP : sse3_replicate_sfp<0x16, movshdup, "vmovshdup">, VEX;
3231 defm VMOVSLDUP : sse3_replicate_sfp<0x12, movsldup, "vmovsldup">, VEX;
3232 defm VMOVSHDUPY : sse3_replicate_sfp_y<0x16, movshdup, "vmovshdup">, VEX;
3233 defm VMOVSLDUPY : sse3_replicate_sfp_y<0x12, movsldup, "vmovsldup">, VEX;
3235 defm MOVSHDUP : sse3_replicate_sfp<0x16, movshdup, "movshdup">;
3236 defm MOVSLDUP : sse3_replicate_sfp<0x12, movsldup, "movsldup">;
3238 // Replicate Double FP
3239 multiclass sse3_replicate_dfp<string OpcodeStr> {
3240 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3241 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3242 [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
3243 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
3244 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3246 (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
3250 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
3251 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3252 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3254 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3255 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3259 let Predicates = [HasAVX] in {
3260 // FIXME: Merge above classes when we have patterns for the ymm version
3261 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
3262 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX;
3264 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
3266 // Move Unaligned Integer
3267 let Predicates = [HasAVX] in {
3268 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3269 "vlddqu\t{$src, $dst|$dst, $src}",
3270 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
3271 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3272 "vlddqu\t{$src, $dst|$dst, $src}",
3273 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>, VEX;
3275 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3276 "lddqu\t{$src, $dst|$dst, $src}",
3277 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
3279 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
3281 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3283 // Several Move patterns
3284 let AddedComplexity = 5 in {
3285 def : Pat<(movddup (memopv2f64 addr:$src), (undef)),
3286 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3287 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
3288 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3289 def : Pat<(movddup (memopv2i64 addr:$src), (undef)),
3290 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3291 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
3292 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3295 // vector_shuffle v1, <undef> <1, 1, 3, 3>
3296 let AddedComplexity = 15 in
3297 def : Pat<(v4i32 (movshdup VR128:$src, (undef))),
3298 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
3299 let AddedComplexity = 20 in
3300 def : Pat<(v4i32 (movshdup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
3301 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
3303 // vector_shuffle v1, <undef> <0, 0, 2, 2>
3304 let AddedComplexity = 15 in
3305 def : Pat<(v4i32 (movsldup VR128:$src, (undef))),
3306 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
3307 let AddedComplexity = 20 in
3308 def : Pat<(v4i32 (movsldup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
3309 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
3311 //===---------------------------------------------------------------------===//
3312 // SSE3 - Arithmetic
3313 //===---------------------------------------------------------------------===//
3315 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
3316 X86MemOperand x86memop, bit Is2Addr = 1> {
3317 def rr : I<0xD0, MRMSrcReg,
3318 (outs RC:$dst), (ins RC:$src1, RC:$src2),
3320 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3321 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3322 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>;
3323 def rm : I<0xD0, MRMSrcMem,
3324 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3326 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3327 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3328 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))]>;
3331 let Predicates = [HasAVX],
3332 ExeDomain = SSEPackedDouble in {
3333 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
3334 f128mem, 0>, TB, XD, VEX_4V;
3335 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
3336 f128mem, 0>, TB, OpSize, VEX_4V;
3337 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
3338 f256mem, 0>, TB, XD, VEX_4V;
3339 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
3340 f256mem, 0>, TB, OpSize, VEX_4V;
3342 let Constraints = "$src1 = $dst", Predicates = [HasSSE3],
3343 ExeDomain = SSEPackedDouble in {
3344 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
3346 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
3347 f128mem>, TB, OpSize;
3350 //===---------------------------------------------------------------------===//
3351 // SSE3 Instructions
3352 //===---------------------------------------------------------------------===//
3355 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
3356 X86MemOperand x86memop, Intrinsic IntId, bit Is2Addr = 1> {
3357 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
3359 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3360 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3361 [(set RC:$dst, (vt (IntId RC:$src1, RC:$src2)))]>;
3363 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3365 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3366 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3367 [(set RC:$dst, (vt (IntId RC:$src1, (memop addr:$src2))))]>;
3369 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
3370 X86MemOperand x86memop, Intrinsic IntId, bit Is2Addr = 1> {
3371 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
3373 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3374 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3375 [(set RC:$dst, (vt (IntId RC:$src1, RC:$src2)))]>;
3377 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3379 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3380 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3381 [(set RC:$dst, (vt (IntId RC:$src1, (memop addr:$src2))))]>;
3384 let Predicates = [HasAVX] in {
3385 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
3386 int_x86_sse3_hadd_ps, 0>, VEX_4V;
3387 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
3388 int_x86_sse3_hadd_pd, 0>, VEX_4V;
3389 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
3390 int_x86_sse3_hsub_ps, 0>, VEX_4V;
3391 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
3392 int_x86_sse3_hsub_pd, 0>, VEX_4V;
3393 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
3394 int_x86_avx_hadd_ps_256, 0>, VEX_4V;
3395 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
3396 int_x86_avx_hadd_pd_256, 0>, VEX_4V;
3397 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
3398 int_x86_avx_hsub_ps_256, 0>, VEX_4V;
3399 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
3400 int_x86_avx_hsub_pd_256, 0>, VEX_4V;
3403 let Constraints = "$src1 = $dst" in {
3404 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem,
3405 int_x86_sse3_hadd_ps>;
3406 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem,
3407 int_x86_sse3_hadd_pd>;
3408 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem,
3409 int_x86_sse3_hsub_ps>;
3410 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem,
3411 int_x86_sse3_hsub_pd>;
3414 //===---------------------------------------------------------------------===//
3415 // SSSE3 - Packed Absolute Instructions
3416 //===---------------------------------------------------------------------===//
3419 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
3420 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
3421 PatFrag mem_frag128, Intrinsic IntId128> {
3422 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
3424 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3425 [(set VR128:$dst, (IntId128 VR128:$src))]>,
3428 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
3430 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3433 (bitconvert (mem_frag128 addr:$src))))]>, OpSize;
3436 let Predicates = [HasAVX] in {
3437 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb", memopv16i8,
3438 int_x86_ssse3_pabs_b_128>, VEX;
3439 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", memopv8i16,
3440 int_x86_ssse3_pabs_w_128>, VEX;
3441 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd", memopv4i32,
3442 int_x86_ssse3_pabs_d_128>, VEX;
3445 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", memopv16i8,
3446 int_x86_ssse3_pabs_b_128>;
3447 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw", memopv8i16,
3448 int_x86_ssse3_pabs_w_128>;
3449 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", memopv4i32,
3450 int_x86_ssse3_pabs_d_128>;
3452 //===---------------------------------------------------------------------===//
3453 // SSSE3 - Packed Binary Operator Instructions
3454 //===---------------------------------------------------------------------===//
3456 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
3457 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
3458 PatFrag mem_frag128, Intrinsic IntId128,
3460 let isCommutable = 1 in
3461 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
3462 (ins VR128:$src1, VR128:$src2),
3464 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3465 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3466 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3468 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
3469 (ins VR128:$src1, i128mem:$src2),
3471 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3472 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3474 (IntId128 VR128:$src1,
3475 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3478 let Predicates = [HasAVX] in {
3479 let isCommutable = 0 in {
3480 defm VPHADDW : SS3I_binop_rm_int<0x01, "vphaddw", memopv8i16,
3481 int_x86_ssse3_phadd_w_128, 0>, VEX_4V;
3482 defm VPHADDD : SS3I_binop_rm_int<0x02, "vphaddd", memopv4i32,
3483 int_x86_ssse3_phadd_d_128, 0>, VEX_4V;
3484 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw", memopv8i16,
3485 int_x86_ssse3_phadd_sw_128, 0>, VEX_4V;
3486 defm VPHSUBW : SS3I_binop_rm_int<0x05, "vphsubw", memopv8i16,
3487 int_x86_ssse3_phsub_w_128, 0>, VEX_4V;
3488 defm VPHSUBD : SS3I_binop_rm_int<0x06, "vphsubd", memopv4i32,
3489 int_x86_ssse3_phsub_d_128, 0>, VEX_4V;
3490 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw", memopv8i16,
3491 int_x86_ssse3_phsub_sw_128, 0>, VEX_4V;
3492 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw", memopv16i8,
3493 int_x86_ssse3_pmadd_ub_sw_128, 0>, VEX_4V;
3494 defm VPSHUFB : SS3I_binop_rm_int<0x00, "vpshufb", memopv16i8,
3495 int_x86_ssse3_pshuf_b_128, 0>, VEX_4V;
3496 defm VPSIGNB : SS3I_binop_rm_int<0x08, "vpsignb", memopv16i8,
3497 int_x86_ssse3_psign_b_128, 0>, VEX_4V;
3498 defm VPSIGNW : SS3I_binop_rm_int<0x09, "vpsignw", memopv8i16,
3499 int_x86_ssse3_psign_w_128, 0>, VEX_4V;
3500 defm VPSIGND : SS3I_binop_rm_int<0x0A, "vpsignd", memopv4i32,
3501 int_x86_ssse3_psign_d_128, 0>, VEX_4V;
3503 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw", memopv8i16,
3504 int_x86_ssse3_pmul_hr_sw_128, 0>, VEX_4V;
3507 // None of these have i8 immediate fields.
3508 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
3509 let isCommutable = 0 in {
3510 defm PHADDW : SS3I_binop_rm_int<0x01, "phaddw", memopv8i16,
3511 int_x86_ssse3_phadd_w_128>;
3512 defm PHADDD : SS3I_binop_rm_int<0x02, "phaddd", memopv4i32,
3513 int_x86_ssse3_phadd_d_128>;
3514 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw", memopv8i16,
3515 int_x86_ssse3_phadd_sw_128>;
3516 defm PHSUBW : SS3I_binop_rm_int<0x05, "phsubw", memopv8i16,
3517 int_x86_ssse3_phsub_w_128>;
3518 defm PHSUBD : SS3I_binop_rm_int<0x06, "phsubd", memopv4i32,
3519 int_x86_ssse3_phsub_d_128>;
3520 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw", memopv8i16,
3521 int_x86_ssse3_phsub_sw_128>;
3522 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw", memopv16i8,
3523 int_x86_ssse3_pmadd_ub_sw_128>;
3524 defm PSHUFB : SS3I_binop_rm_int<0x00, "pshufb", memopv16i8,
3525 int_x86_ssse3_pshuf_b_128>;
3526 defm PSIGNB : SS3I_binop_rm_int<0x08, "psignb", memopv16i8,
3527 int_x86_ssse3_psign_b_128>;
3528 defm PSIGNW : SS3I_binop_rm_int<0x09, "psignw", memopv8i16,
3529 int_x86_ssse3_psign_w_128>;
3530 defm PSIGND : SS3I_binop_rm_int<0x0A, "psignd", memopv4i32,
3531 int_x86_ssse3_psign_d_128>;
3533 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw", memopv8i16,
3534 int_x86_ssse3_pmul_hr_sw_128>;
3537 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
3538 (PSHUFBrr128 VR128:$src, VR128:$mask)>, Requires<[HasSSSE3]>;
3539 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
3540 (PSHUFBrm128 VR128:$src, addr:$mask)>, Requires<[HasSSSE3]>;
3542 def : Pat<(X86psignb VR128:$src1, VR128:$src2),
3543 (PSIGNBrr128 VR128:$src1, VR128:$src2)>, Requires<[HasSSSE3]>;
3544 def : Pat<(X86psignw VR128:$src1, VR128:$src2),
3545 (PSIGNWrr128 VR128:$src1, VR128:$src2)>, Requires<[HasSSSE3]>;
3546 def : Pat<(X86psignd VR128:$src1, VR128:$src2),
3547 (PSIGNDrr128 VR128:$src1, VR128:$src2)>, Requires<[HasSSSE3]>;
3549 //===---------------------------------------------------------------------===//
3550 // SSSE3 - Packed Align Instruction Patterns
3551 //===---------------------------------------------------------------------===//
3553 multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
3554 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
3555 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3557 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3559 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3561 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
3562 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3564 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3566 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3570 let Predicates = [HasAVX] in
3571 defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
3572 let Constraints = "$src1 = $dst" in
3573 defm PALIGN : ssse3_palign<"palignr">;
3575 let AddedComplexity = 5 in {
3576 def : Pat<(v4i32 (palign:$src3 VR128:$src1, VR128:$src2)),
3577 (PALIGNR128rr VR128:$src2, VR128:$src1,
3578 (SHUFFLE_get_palign_imm VR128:$src3))>,
3579 Requires<[HasSSSE3]>;
3580 def : Pat<(v4f32 (palign:$src3 VR128:$src1, VR128:$src2)),
3581 (PALIGNR128rr VR128:$src2, VR128:$src1,
3582 (SHUFFLE_get_palign_imm VR128:$src3))>,
3583 Requires<[HasSSSE3]>;
3584 def : Pat<(v8i16 (palign:$src3 VR128:$src1, VR128:$src2)),
3585 (PALIGNR128rr VR128:$src2, VR128:$src1,
3586 (SHUFFLE_get_palign_imm VR128:$src3))>,
3587 Requires<[HasSSSE3]>;
3588 def : Pat<(v16i8 (palign:$src3 VR128:$src1, VR128:$src2)),
3589 (PALIGNR128rr VR128:$src2, VR128:$src1,
3590 (SHUFFLE_get_palign_imm VR128:$src3))>,
3591 Requires<[HasSSSE3]>;
3594 //===---------------------------------------------------------------------===//
3595 // SSSE3 Misc Instructions
3596 //===---------------------------------------------------------------------===//
3598 // Thread synchronization
3599 let usesCustomInserter = 1 in {
3600 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
3601 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>;
3602 def MWAIT : PseudoI<(outs), (ins GR32:$src1, GR32:$src2),
3603 [(int_x86_sse3_mwait GR32:$src1, GR32:$src2)]>;
3606 let Uses = [EAX, ECX, EDX] in
3607 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", []>, TB,
3608 Requires<[HasSSE3]>;
3609 let Uses = [ECX, EAX] in
3610 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait", []>, TB,
3611 Requires<[HasSSE3]>;
3613 def : InstAlias<"mwait %eax, %ecx", (MWAITrr)>, Requires<[In32BitMode]>;
3614 def : InstAlias<"mwait %rax, %rcx", (MWAITrr)>, Requires<[In64BitMode]>;
3616 def : InstAlias<"monitor %eax, %ecx, %edx", (MONITORrrr)>,
3617 Requires<[In32BitMode]>;
3618 def : InstAlias<"monitor %rax, %rcx, %rdx", (MONITORrrr)>,
3619 Requires<[In64BitMode]>;
3621 //===---------------------------------------------------------------------===//
3622 // Non-Instruction Patterns
3623 //===---------------------------------------------------------------------===//
3625 // extload f32 -> f64. This matches load+fextend because we have a hack in
3626 // the isel (PreprocessForFPConvert) that can introduce loads after dag
3628 // Since these loads aren't folded into the fextend, we have to match it
3630 let Predicates = [HasSSE2] in
3631 def : Pat<(fextend (loadf32 addr:$src)),
3632 (CVTSS2SDrm addr:$src)>;
3637 let Predicates = [HasXMMInt] in {
3638 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
3639 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
3640 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
3641 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
3642 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
3643 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
3644 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
3645 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
3646 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
3647 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
3648 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
3649 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
3650 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
3651 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
3652 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
3653 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
3654 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
3655 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
3656 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
3657 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
3658 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
3659 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
3660 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
3661 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
3662 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
3663 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
3664 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
3665 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
3666 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
3667 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
3670 let Predicates = [HasAVX] in {
3671 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
3672 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
3673 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
3674 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
3675 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
3676 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
3677 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
3678 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
3679 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
3680 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
3681 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
3682 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
3683 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
3684 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
3687 // Move scalar to XMM zero-extended
3688 // movd to XMM register zero-extends
3689 let AddedComplexity = 15 in {
3690 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
3691 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
3692 (MOVSDrr (v2f64 (V_SET0PS)), FR64:$src)>;
3693 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
3694 (MOVSSrr (v4f32 (V_SET0PS)), FR32:$src)>;
3695 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
3696 (MOVSSrr (v4f32 (V_SET0PS)),
3697 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
3698 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
3699 (MOVSSrr (v4i32 (V_SET0PI)),
3700 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
3703 // Splat v2f64 / v2i64
3704 let AddedComplexity = 10 in {
3705 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
3706 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3707 def : Pat<(unpckh (v2f64 VR128:$src), (undef)),
3708 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3709 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
3710 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3711 def : Pat<(unpckh (v2i64 VR128:$src), (undef)),
3712 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3715 // Special unary SHUFPSrri case.
3716 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
3717 (SHUFPSrri VR128:$src1, VR128:$src1,
3718 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3719 let AddedComplexity = 5 in
3720 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
3721 (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3722 Requires<[HasSSE2]>;
3723 // Special unary SHUFPDrri case.
3724 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
3725 (SHUFPDrri VR128:$src1, VR128:$src1,
3726 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3727 Requires<[HasSSE2]>;
3728 // Special unary SHUFPDrri case.
3729 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
3730 (SHUFPDrri VR128:$src1, VR128:$src1,
3731 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3732 Requires<[HasSSE2]>;
3733 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
3734 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
3735 (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3736 Requires<[HasSSE2]>;
3738 // Special binary v4i32 shuffle cases with SHUFPS.
3739 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
3740 (SHUFPSrri VR128:$src1, VR128:$src2,
3741 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3742 Requires<[HasSSE2]>;
3743 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)))),
3744 (SHUFPSrmi VR128:$src1, addr:$src2,
3745 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3746 Requires<[HasSSE2]>;
3747 // Special binary v2i64 shuffle cases using SHUFPDrri.
3748 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
3749 (SHUFPDrri VR128:$src1, VR128:$src2,
3750 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3751 Requires<[HasSSE2]>;
3753 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
3754 let AddedComplexity = 15 in {
3755 def : Pat<(v4i32 (unpckl_undef:$src2 VR128:$src, (undef))),
3756 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3757 Requires<[OptForSpeed, HasSSE2]>;
3758 def : Pat<(v4f32 (unpckl_undef:$src2 VR128:$src, (undef))),
3759 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3760 Requires<[OptForSpeed, HasSSE2]>;
3762 let AddedComplexity = 10 in {
3763 def : Pat<(v4f32 (unpckl_undef VR128:$src, (undef))),
3764 (UNPCKLPSrr VR128:$src, VR128:$src)>;
3765 def : Pat<(v16i8 (unpckl_undef VR128:$src, (undef))),
3766 (PUNPCKLBWrr VR128:$src, VR128:$src)>;
3767 def : Pat<(v8i16 (unpckl_undef VR128:$src, (undef))),
3768 (PUNPCKLWDrr VR128:$src, VR128:$src)>;
3769 def : Pat<(v4i32 (unpckl_undef VR128:$src, (undef))),
3770 (PUNPCKLDQrr VR128:$src, VR128:$src)>;
3773 // vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
3774 let AddedComplexity = 15 in {
3775 def : Pat<(v4i32 (unpckh_undef:$src2 VR128:$src, (undef))),
3776 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3777 Requires<[OptForSpeed, HasSSE2]>;
3778 def : Pat<(v4f32 (unpckh_undef:$src2 VR128:$src, (undef))),
3779 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3780 Requires<[OptForSpeed, HasSSE2]>;
3782 let AddedComplexity = 10 in {
3783 def : Pat<(v4f32 (unpckh_undef VR128:$src, (undef))),
3784 (UNPCKHPSrr VR128:$src, VR128:$src)>;
3785 def : Pat<(v16i8 (unpckh_undef VR128:$src, (undef))),
3786 (PUNPCKHBWrr VR128:$src, VR128:$src)>;
3787 def : Pat<(v8i16 (unpckh_undef VR128:$src, (undef))),
3788 (PUNPCKHWDrr VR128:$src, VR128:$src)>;
3789 def : Pat<(v4i32 (unpckh_undef VR128:$src, (undef))),
3790 (PUNPCKHDQrr VR128:$src, VR128:$src)>;
3793 let AddedComplexity = 20 in {
3794 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
3795 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
3796 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
3798 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
3799 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
3800 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
3802 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
3803 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
3804 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3805 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
3806 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3809 let AddedComplexity = 20 in {
3810 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
3811 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
3812 (MOVLPSrm VR128:$src1, addr:$src2)>;
3813 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
3814 (MOVLPDrm VR128:$src1, addr:$src2)>;
3815 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
3816 (MOVLPSrm VR128:$src1, addr:$src2)>;
3817 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
3818 (MOVLPDrm VR128:$src1, addr:$src2)>;
3821 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
3822 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3823 (MOVLPSmr addr:$src1, VR128:$src2)>;
3824 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3825 (MOVLPDmr addr:$src1, VR128:$src2)>;
3826 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
3828 (MOVLPSmr addr:$src1, VR128:$src2)>;
3829 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3830 (MOVLPDmr addr:$src1, VR128:$src2)>;
3832 let AddedComplexity = 15 in {
3833 // Setting the lowest element in the vector.
3834 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
3835 (MOVSSrr (v4i32 VR128:$src1),
3836 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
3837 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
3838 (MOVSDrr (v2i64 VR128:$src1),
3839 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
3841 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
3842 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
3843 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
3844 Requires<[HasSSE2]>;
3845 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
3846 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
3847 Requires<[HasSSE2]>;
3850 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
3851 // fall back to this for SSE1)
3852 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
3853 (SHUFPSrri VR128:$src2, VR128:$src1,
3854 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3856 // Set lowest element and zero upper elements.
3857 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
3858 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3860 // vector -> vector casts
3861 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
3862 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
3863 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
3864 (CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
3866 // Use movaps / movups for SSE integer load / store (one byte shorter).
3867 // The instructions selected below are then converted to MOVDQA/MOVDQU
3868 // during the SSE domain pass.
3869 let Predicates = [HasSSE1] in {
3870 def : Pat<(alignedloadv4i32 addr:$src),
3871 (MOVAPSrm addr:$src)>;
3872 def : Pat<(loadv4i32 addr:$src),
3873 (MOVUPSrm addr:$src)>;
3874 def : Pat<(alignedloadv2i64 addr:$src),
3875 (MOVAPSrm addr:$src)>;
3876 def : Pat<(loadv2i64 addr:$src),
3877 (MOVUPSrm addr:$src)>;
3879 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3880 (MOVAPSmr addr:$dst, VR128:$src)>;
3881 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3882 (MOVAPSmr addr:$dst, VR128:$src)>;
3883 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3884 (MOVAPSmr addr:$dst, VR128:$src)>;
3885 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3886 (MOVAPSmr addr:$dst, VR128:$src)>;
3887 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3888 (MOVUPSmr addr:$dst, VR128:$src)>;
3889 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3890 (MOVUPSmr addr:$dst, VR128:$src)>;
3891 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3892 (MOVUPSmr addr:$dst, VR128:$src)>;
3893 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3894 (MOVUPSmr addr:$dst, VR128:$src)>;
3897 // Use vmovaps/vmovups for AVX integer load/store.
3898 let Predicates = [HasAVX] in {
3899 // 128-bit load/store
3900 def : Pat<(alignedloadv4i32 addr:$src),
3901 (VMOVAPSrm addr:$src)>;
3902 def : Pat<(loadv4i32 addr:$src),
3903 (VMOVUPSrm addr:$src)>;
3904 def : Pat<(alignedloadv2i64 addr:$src),
3905 (VMOVAPSrm addr:$src)>;
3906 def : Pat<(loadv2i64 addr:$src),
3907 (VMOVUPSrm addr:$src)>;
3909 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3910 (VMOVAPSmr addr:$dst, VR128:$src)>;
3911 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3912 (VMOVAPSmr addr:$dst, VR128:$src)>;
3913 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3914 (VMOVAPSmr addr:$dst, VR128:$src)>;
3915 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3916 (VMOVAPSmr addr:$dst, VR128:$src)>;
3917 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3918 (VMOVUPSmr addr:$dst, VR128:$src)>;
3919 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3920 (VMOVUPSmr addr:$dst, VR128:$src)>;
3921 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3922 (VMOVUPSmr addr:$dst, VR128:$src)>;
3923 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3924 (VMOVUPSmr addr:$dst, VR128:$src)>;
3926 // 256-bit load/store
3927 def : Pat<(alignedloadv4i64 addr:$src),
3928 (VMOVAPSYrm addr:$src)>;
3929 def : Pat<(loadv4i64 addr:$src),
3930 (VMOVUPSYrm addr:$src)>;
3931 def : Pat<(alignedloadv8i32 addr:$src),
3932 (VMOVAPSYrm addr:$src)>;
3933 def : Pat<(loadv8i32 addr:$src),
3934 (VMOVUPSYrm addr:$src)>;
3935 def : Pat<(alignedstore (v4i64 VR256:$src), addr:$dst),
3936 (VMOVAPSYmr addr:$dst, VR256:$src)>;
3937 def : Pat<(alignedstore (v8i32 VR256:$src), addr:$dst),
3938 (VMOVAPSYmr addr:$dst, VR256:$src)>;
3939 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
3940 (VMOVUPSYmr addr:$dst, VR256:$src)>;
3941 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
3942 (VMOVUPSYmr addr:$dst, VR256:$src)>;
3945 //===----------------------------------------------------------------------===//
3946 // SSE4.1 - Packed Move with Sign/Zero Extend
3947 //===----------------------------------------------------------------------===//
3949 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3950 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3951 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3952 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3954 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3955 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3957 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
3961 let Predicates = [HasAVX] in {
3962 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
3964 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
3966 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
3968 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
3970 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
3972 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
3976 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
3977 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
3978 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
3979 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
3980 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
3981 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
3983 // Common patterns involving scalar load.
3984 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
3985 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3986 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
3987 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3989 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
3990 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3991 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
3992 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3994 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
3995 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3996 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
3997 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3999 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
4000 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
4001 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
4002 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
4004 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
4005 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
4006 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
4007 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
4009 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
4010 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
4011 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
4012 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
4015 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4016 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4017 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4018 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
4020 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4021 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4023 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
4027 let Predicates = [HasAVX] in {
4028 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
4030 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
4032 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
4034 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
4038 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
4039 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
4040 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
4041 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
4043 // Common patterns involving scalar load
4044 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
4045 (PMOVSXBDrm addr:$src)>, Requires<[HasSSE41]>;
4046 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
4047 (PMOVSXWQrm addr:$src)>, Requires<[HasSSE41]>;
4049 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
4050 (PMOVZXBDrm addr:$src)>, Requires<[HasSSE41]>;
4051 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
4052 (PMOVZXWQrm addr:$src)>, Requires<[HasSSE41]>;
4055 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4056 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4057 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4058 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
4060 // Expecting a i16 load any extended to i32 value.
4061 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
4062 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4063 [(set VR128:$dst, (IntId (bitconvert
4064 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
4068 let Predicates = [HasAVX] in {
4069 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
4071 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
4074 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
4075 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
4077 // Common patterns involving scalar load
4078 def : Pat<(int_x86_sse41_pmovsxbq
4079 (bitconvert (v4i32 (X86vzmovl
4080 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
4081 (PMOVSXBQrm addr:$src)>, Requires<[HasSSE41]>;
4083 def : Pat<(int_x86_sse41_pmovzxbq
4084 (bitconvert (v4i32 (X86vzmovl
4085 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
4086 (PMOVZXBQrm addr:$src)>, Requires<[HasSSE41]>;
4088 //===----------------------------------------------------------------------===//
4089 // SSE4.1 - Extract Instructions
4090 //===----------------------------------------------------------------------===//
4092 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
4093 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
4094 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4095 (ins VR128:$src1, i32i8imm:$src2),
4096 !strconcat(OpcodeStr,
4097 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4098 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
4100 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4101 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
4102 !strconcat(OpcodeStr,
4103 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4106 // There's an AssertZext in the way of writing the store pattern
4107 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
4110 let Predicates = [HasAVX] in {
4111 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
4112 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
4113 (ins VR128:$src1, i32i8imm:$src2),
4114 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
4117 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
4120 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
4121 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
4122 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4123 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
4124 !strconcat(OpcodeStr,
4125 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4128 // There's an AssertZext in the way of writing the store pattern
4129 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
4132 let Predicates = [HasAVX] in
4133 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
4135 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
4138 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
4139 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
4140 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4141 (ins VR128:$src1, i32i8imm:$src2),
4142 !strconcat(OpcodeStr,
4143 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4145 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
4146 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4147 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
4148 !strconcat(OpcodeStr,
4149 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4150 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
4151 addr:$dst)]>, OpSize;
4154 let Predicates = [HasAVX] in
4155 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
4157 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
4159 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
4160 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
4161 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
4162 (ins VR128:$src1, i32i8imm:$src2),
4163 !strconcat(OpcodeStr,
4164 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4166 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
4167 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4168 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
4169 !strconcat(OpcodeStr,
4170 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4171 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
4172 addr:$dst)]>, OpSize, REX_W;
4175 let Predicates = [HasAVX] in
4176 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
4178 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
4180 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
4182 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
4183 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4184 (ins VR128:$src1, i32i8imm:$src2),
4185 !strconcat(OpcodeStr,
4186 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4188 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
4190 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4191 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
4192 !strconcat(OpcodeStr,
4193 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4194 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
4195 addr:$dst)]>, OpSize;
4198 let Predicates = [HasAVX] in {
4199 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
4200 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
4201 (ins VR128:$src1, i32i8imm:$src2),
4202 "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
4205 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
4207 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
4208 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
4211 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
4212 Requires<[HasSSE41]>;
4214 //===----------------------------------------------------------------------===//
4215 // SSE4.1 - Insert Instructions
4216 //===----------------------------------------------------------------------===//
4218 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
4219 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4220 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
4222 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4224 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4226 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
4227 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4228 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
4230 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4232 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4234 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
4235 imm:$src3))]>, OpSize;
4238 let Predicates = [HasAVX] in
4239 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
4240 let Constraints = "$src1 = $dst" in
4241 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
4243 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
4244 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4245 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
4247 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4249 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4251 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
4253 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4254 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
4256 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4258 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4260 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
4261 imm:$src3)))]>, OpSize;
4264 let Predicates = [HasAVX] in
4265 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
4266 let Constraints = "$src1 = $dst" in
4267 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
4269 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
4270 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4271 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4273 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4275 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4277 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
4279 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4280 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
4282 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4284 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4286 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
4287 imm:$src3)))]>, OpSize;
4290 let Predicates = [HasAVX] in
4291 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
4292 let Constraints = "$src1 = $dst" in
4293 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
4295 // insertps has a few different modes, there's the first two here below which
4296 // are optimized inserts that won't zero arbitrary elements in the destination
4297 // vector. The next one matches the intrinsic and could zero arbitrary elements
4298 // in the target vector.
4299 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
4300 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4301 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4303 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4305 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4307 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
4309 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4310 (ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
4312 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4314 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4316 (X86insrtps VR128:$src1,
4317 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
4318 imm:$src3))]>, OpSize;
4321 let Constraints = "$src1 = $dst" in
4322 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
4323 let Predicates = [HasAVX] in
4324 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
4326 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
4327 (VINSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
4329 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
4330 (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
4331 Requires<[HasSSE41]>;
4333 //===----------------------------------------------------------------------===//
4334 // SSE4.1 - Round Instructions
4335 //===----------------------------------------------------------------------===//
4337 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
4338 X86MemOperand x86memop, RegisterClass RC,
4339 PatFrag mem_frag32, PatFrag mem_frag64,
4340 Intrinsic V4F32Int, Intrinsic V2F64Int> {
4341 // Intrinsic operation, reg.
4342 // Vector intrinsic operation, reg
4343 def PSr : SS4AIi8<opcps, MRMSrcReg,
4344 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4345 !strconcat(OpcodeStr,
4346 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4347 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
4350 // Vector intrinsic operation, mem
4351 def PSm : Ii8<opcps, MRMSrcMem,
4352 (outs RC:$dst), (ins f256mem:$src1, i32i8imm:$src2),
4353 !strconcat(OpcodeStr,
4354 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4356 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
4358 Requires<[HasSSE41]>;
4360 // Vector intrinsic operation, reg
4361 def PDr : SS4AIi8<opcpd, MRMSrcReg,
4362 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4363 !strconcat(OpcodeStr,
4364 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4365 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
4368 // Vector intrinsic operation, mem
4369 def PDm : SS4AIi8<opcpd, MRMSrcMem,
4370 (outs RC:$dst), (ins f256mem:$src1, i32i8imm:$src2),
4371 !strconcat(OpcodeStr,
4372 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4374 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
4378 multiclass sse41_fp_unop_rm_avx_p<bits<8> opcps, bits<8> opcpd,
4379 RegisterClass RC, X86MemOperand x86memop, string OpcodeStr> {
4380 // Intrinsic operation, reg.
4381 // Vector intrinsic operation, reg
4382 def PSr_AVX : SS4AIi8<opcps, MRMSrcReg,
4383 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4384 !strconcat(OpcodeStr,
4385 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4388 // Vector intrinsic operation, mem
4389 def PSm_AVX : Ii8<opcps, MRMSrcMem,
4390 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4391 !strconcat(OpcodeStr,
4392 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4393 []>, TA, OpSize, Requires<[HasSSE41]>;
4395 // Vector intrinsic operation, reg
4396 def PDr_AVX : SS4AIi8<opcpd, MRMSrcReg,
4397 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4398 !strconcat(OpcodeStr,
4399 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4402 // Vector intrinsic operation, mem
4403 def PDm_AVX : SS4AIi8<opcpd, MRMSrcMem,
4404 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4405 !strconcat(OpcodeStr,
4406 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4410 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
4413 Intrinsic F64Int, bit Is2Addr = 1> {
4414 // Intrinsic operation, reg.
4415 def SSr : SS4AIi8<opcss, MRMSrcReg,
4416 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4418 !strconcat(OpcodeStr,
4419 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4420 !strconcat(OpcodeStr,
4421 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4422 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
4425 // Intrinsic operation, mem.
4426 def SSm : SS4AIi8<opcss, MRMSrcMem,
4427 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
4429 !strconcat(OpcodeStr,
4430 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4431 !strconcat(OpcodeStr,
4432 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4434 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
4437 // Intrinsic operation, reg.
4438 def SDr : SS4AIi8<opcsd, MRMSrcReg,
4439 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4441 !strconcat(OpcodeStr,
4442 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4443 !strconcat(OpcodeStr,
4444 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4445 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
4448 // Intrinsic operation, mem.
4449 def SDm : SS4AIi8<opcsd, MRMSrcMem,
4450 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
4452 !strconcat(OpcodeStr,
4453 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4454 !strconcat(OpcodeStr,
4455 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4457 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
4461 multiclass sse41_fp_binop_rm_avx_s<bits<8> opcss, bits<8> opcsd,
4463 // Intrinsic operation, reg.
4464 def SSr_AVX : SS4AIi8<opcss, MRMSrcReg,
4465 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4466 !strconcat(OpcodeStr,
4467 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4470 // Intrinsic operation, mem.
4471 def SSm_AVX : SS4AIi8<opcss, MRMSrcMem,
4472 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
4473 !strconcat(OpcodeStr,
4474 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4477 // Intrinsic operation, reg.
4478 def SDr_AVX : SS4AIi8<opcsd, MRMSrcReg,
4479 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4480 !strconcat(OpcodeStr,
4481 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4484 // Intrinsic operation, mem.
4485 def SDm_AVX : SS4AIi8<opcsd, MRMSrcMem,
4486 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
4487 !strconcat(OpcodeStr,
4488 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4492 // FP round - roundss, roundps, roundsd, roundpd
4493 let Predicates = [HasAVX] in {
4495 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
4496 memopv4f32, memopv2f64,
4497 int_x86_sse41_round_ps,
4498 int_x86_sse41_round_pd>, VEX;
4499 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
4500 memopv8f32, memopv4f64,
4501 int_x86_avx_round_ps_256,
4502 int_x86_avx_round_pd_256>, VEX;
4503 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
4504 int_x86_sse41_round_ss,
4505 int_x86_sse41_round_sd, 0>, VEX_4V;
4507 // Instructions for the assembler
4508 defm VROUND : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR128, f128mem, "vround">,
4510 defm VROUNDY : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR256, f256mem, "vround">,
4512 defm VROUND : sse41_fp_binop_rm_avx_s<0x0A, 0x0B, "vround">, VEX_4V;
4515 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
4516 memopv4f32, memopv2f64,
4517 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
4518 let Constraints = "$src1 = $dst" in
4519 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
4520 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
4522 //===----------------------------------------------------------------------===//
4523 // SSE4.1 - Packed Bit Test
4524 //===----------------------------------------------------------------------===//
4526 // ptest instruction we'll lower to this in X86ISelLowering primarily from
4527 // the intel intrinsic that corresponds to this.
4528 let Defs = [EFLAGS], Predicates = [HasAVX] in {
4529 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
4530 "vptest\t{$src2, $src1|$src1, $src2}",
4531 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
4533 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
4534 "vptest\t{$src2, $src1|$src1, $src2}",
4535 [(set EFLAGS,(X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
4538 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
4539 "vptest\t{$src2, $src1|$src1, $src2}",
4540 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
4542 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
4543 "vptest\t{$src2, $src1|$src1, $src2}",
4544 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
4548 let Defs = [EFLAGS] in {
4549 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
4550 "ptest \t{$src2, $src1|$src1, $src2}",
4551 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
4553 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
4554 "ptest \t{$src2, $src1|$src1, $src2}",
4555 [(set EFLAGS, (X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
4559 // The bit test instructions below are AVX only
4560 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
4561 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
4562 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
4563 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
4564 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
4565 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
4566 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
4567 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
4571 let Defs = [EFLAGS], Predicates = [HasAVX] in {
4572 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
4573 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>;
4574 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
4575 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>;
4578 //===----------------------------------------------------------------------===//
4579 // SSE4.1 - Misc Instructions
4580 //===----------------------------------------------------------------------===//
4582 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4583 "popcnt{w}\t{$src, $dst|$dst, $src}",
4584 [(set GR16:$dst, (ctpop GR16:$src))]>, OpSize, XS;
4585 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4586 "popcnt{w}\t{$src, $dst|$dst, $src}",
4587 [(set GR16:$dst, (ctpop (loadi16 addr:$src)))]>, OpSize, XS;
4589 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4590 "popcnt{l}\t{$src, $dst|$dst, $src}",
4591 [(set GR32:$dst, (ctpop GR32:$src))]>, XS;
4592 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4593 "popcnt{l}\t{$src, $dst|$dst, $src}",
4594 [(set GR32:$dst, (ctpop (loadi32 addr:$src)))]>, XS;
4596 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
4597 "popcnt{q}\t{$src, $dst|$dst, $src}",
4598 [(set GR64:$dst, (ctpop GR64:$src))]>, XS;
4599 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
4600 "popcnt{q}\t{$src, $dst|$dst, $src}",
4601 [(set GR64:$dst, (ctpop (loadi64 addr:$src)))]>, XS;
4605 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
4606 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
4607 Intrinsic IntId128> {
4608 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4610 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4611 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
4612 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4614 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4617 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
4620 let Predicates = [HasAVX] in
4621 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
4622 int_x86_sse41_phminposuw>, VEX;
4623 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
4624 int_x86_sse41_phminposuw>;
4626 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
4627 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
4628 Intrinsic IntId128, bit Is2Addr = 1> {
4629 let isCommutable = 1 in
4630 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4631 (ins VR128:$src1, VR128:$src2),
4633 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4634 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4635 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
4636 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4637 (ins VR128:$src1, i128mem:$src2),
4639 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4640 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4642 (IntId128 VR128:$src1,
4643 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
4646 let Predicates = [HasAVX] in {
4647 let isCommutable = 0 in
4648 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
4650 defm VPCMPEQQ : SS41I_binop_rm_int<0x29, "vpcmpeqq", int_x86_sse41_pcmpeqq,
4652 defm VPMINSB : SS41I_binop_rm_int<0x38, "vpminsb", int_x86_sse41_pminsb,
4654 defm VPMINSD : SS41I_binop_rm_int<0x39, "vpminsd", int_x86_sse41_pminsd,
4656 defm VPMINUD : SS41I_binop_rm_int<0x3B, "vpminud", int_x86_sse41_pminud,
4658 defm VPMINUW : SS41I_binop_rm_int<0x3A, "vpminuw", int_x86_sse41_pminuw,
4660 defm VPMAXSB : SS41I_binop_rm_int<0x3C, "vpmaxsb", int_x86_sse41_pmaxsb,
4662 defm VPMAXSD : SS41I_binop_rm_int<0x3D, "vpmaxsd", int_x86_sse41_pmaxsd,
4664 defm VPMAXUD : SS41I_binop_rm_int<0x3F, "vpmaxud", int_x86_sse41_pmaxud,
4666 defm VPMAXUW : SS41I_binop_rm_int<0x3E, "vpmaxuw", int_x86_sse41_pmaxuw,
4668 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
4672 let Constraints = "$src1 = $dst" in {
4673 let isCommutable = 0 in
4674 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
4675 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq", int_x86_sse41_pcmpeqq>;
4676 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb", int_x86_sse41_pminsb>;
4677 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd", int_x86_sse41_pminsd>;
4678 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud", int_x86_sse41_pminud>;
4679 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw", int_x86_sse41_pminuw>;
4680 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb", int_x86_sse41_pmaxsb>;
4681 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd", int_x86_sse41_pmaxsd>;
4682 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud", int_x86_sse41_pmaxud>;
4683 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw", int_x86_sse41_pmaxuw>;
4684 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
4687 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
4688 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
4689 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
4690 (PCMPEQQrm VR128:$src1, addr:$src2)>;
4692 /// SS48I_binop_rm - Simple SSE41 binary operator.
4693 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4694 ValueType OpVT, bit Is2Addr = 1> {
4695 let isCommutable = 1 in
4696 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4697 (ins VR128:$src1, VR128:$src2),
4699 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4700 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4701 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
4703 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4704 (ins VR128:$src1, i128mem:$src2),
4706 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4707 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4708 [(set VR128:$dst, (OpNode VR128:$src1,
4709 (bc_v4i32 (memopv2i64 addr:$src2))))]>,
4713 let Predicates = [HasAVX] in
4714 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, 0>, VEX_4V;
4715 let Constraints = "$src1 = $dst" in
4716 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32>;
4718 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
4719 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
4720 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
4721 X86MemOperand x86memop, bit Is2Addr = 1> {
4722 let isCommutable = 1 in
4723 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
4724 (ins RC:$src1, RC:$src2, i32i8imm:$src3),
4726 !strconcat(OpcodeStr,
4727 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4728 !strconcat(OpcodeStr,
4729 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4730 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
4732 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
4733 (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
4735 !strconcat(OpcodeStr,
4736 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4737 !strconcat(OpcodeStr,
4738 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4741 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
4745 let Predicates = [HasAVX] in {
4746 let isCommutable = 0 in {
4747 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
4748 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4749 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
4750 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4751 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
4752 int_x86_avx_blend_ps_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
4753 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
4754 int_x86_avx_blend_pd_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
4755 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
4756 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4757 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
4758 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4760 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
4761 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4762 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
4763 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4764 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
4765 VR256, memopv32i8, i256mem, 0>, VEX_4V;
4768 let Constraints = "$src1 = $dst" in {
4769 let isCommutable = 0 in {
4770 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
4771 VR128, memopv16i8, i128mem>;
4772 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
4773 VR128, memopv16i8, i128mem>;
4774 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
4775 VR128, memopv16i8, i128mem>;
4776 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
4777 VR128, memopv16i8, i128mem>;
4779 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
4780 VR128, memopv16i8, i128mem>;
4781 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
4782 VR128, memopv16i8, i128mem>;
4785 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
4786 let Predicates = [HasAVX] in {
4787 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
4788 RegisterClass RC, X86MemOperand x86memop,
4789 PatFrag mem_frag, Intrinsic IntId> {
4790 def rr : I<opc, MRMSrcReg, (outs RC:$dst),
4791 (ins RC:$src1, RC:$src2, RC:$src3),
4792 !strconcat(OpcodeStr,
4793 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4794 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
4795 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
4797 def rm : I<opc, MRMSrcMem, (outs RC:$dst),
4798 (ins RC:$src1, x86memop:$src2, RC:$src3),
4799 !strconcat(OpcodeStr,
4800 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4802 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
4804 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
4808 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, i128mem,
4809 memopv16i8, int_x86_sse41_blendvpd>;
4810 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, i128mem,
4811 memopv16i8, int_x86_sse41_blendvps>;
4812 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
4813 memopv16i8, int_x86_sse41_pblendvb>;
4814 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, i256mem,
4815 memopv32i8, int_x86_avx_blendv_pd_256>;
4816 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem,
4817 memopv32i8, int_x86_avx_blendv_ps_256>;
4819 /// SS41I_ternary_int - SSE 4.1 ternary operator
4820 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
4821 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4822 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4823 (ins VR128:$src1, VR128:$src2),
4824 !strconcat(OpcodeStr,
4825 "\t{$src2, $dst|$dst, $src2}"),
4826 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
4829 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4830 (ins VR128:$src1, i128mem:$src2),
4831 !strconcat(OpcodeStr,
4832 "\t{$src2, $dst|$dst, $src2}"),
4835 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
4839 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
4840 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
4841 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
4843 def : Pat<(X86pblendv VR128:$src1, VR128:$src2, XMM0),
4844 (PBLENDVBrr0 VR128:$src1, VR128:$src2)>;
4846 let Predicates = [HasAVX] in
4847 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4848 "vmovntdqa\t{$src, $dst|$dst, $src}",
4849 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
4851 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4852 "movntdqa\t{$src, $dst|$dst, $src}",
4853 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
4856 //===----------------------------------------------------------------------===//
4857 // SSE4.2 - Compare Instructions
4858 //===----------------------------------------------------------------------===//
4860 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
4861 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
4862 Intrinsic IntId128, bit Is2Addr = 1> {
4863 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
4864 (ins VR128:$src1, VR128:$src2),
4866 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4867 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4868 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
4870 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
4871 (ins VR128:$src1, i128mem:$src2),
4873 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4874 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4876 (IntId128 VR128:$src1,
4877 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
4880 let Predicates = [HasAVX] in
4881 defm VPCMPGTQ : SS42I_binop_rm_int<0x37, "vpcmpgtq", int_x86_sse42_pcmpgtq,
4883 let Constraints = "$src1 = $dst" in
4884 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
4886 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
4887 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
4888 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
4889 (PCMPGTQrm VR128:$src1, addr:$src2)>;
4891 //===----------------------------------------------------------------------===//
4892 // SSE4.2 - String/text Processing Instructions
4893 //===----------------------------------------------------------------------===//
4895 // Packed Compare Implicit Length Strings, Return Mask
4896 multiclass pseudo_pcmpistrm<string asm> {
4897 def REG : PseudoI<(outs VR128:$dst),
4898 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4899 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
4901 def MEM : PseudoI<(outs VR128:$dst),
4902 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4903 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128
4904 VR128:$src1, (load addr:$src2), imm:$src3))]>;
4907 let Defs = [EFLAGS], usesCustomInserter = 1 in {
4908 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[HasSSE42]>;
4909 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
4912 let Defs = [XMM0, EFLAGS], Predicates = [HasAVX] in {
4913 def VPCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
4914 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4915 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
4916 def VPCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
4917 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4918 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
4921 let Defs = [XMM0, EFLAGS] in {
4922 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
4923 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4924 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
4925 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
4926 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4927 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
4930 // Packed Compare Explicit Length Strings, Return Mask
4931 multiclass pseudo_pcmpestrm<string asm> {
4932 def REG : PseudoI<(outs VR128:$dst),
4933 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
4934 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
4935 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
4936 def MEM : PseudoI<(outs VR128:$dst),
4937 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
4938 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
4939 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>;
4942 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
4943 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[HasSSE42]>;
4944 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
4947 let Predicates = [HasAVX],
4948 Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
4949 def VPCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
4950 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
4951 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
4952 def VPCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
4953 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
4954 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
4957 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
4958 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
4959 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
4960 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
4961 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
4962 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
4963 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
4966 // Packed Compare Implicit Length Strings, Return Index
4967 let Defs = [ECX, EFLAGS] in {
4968 multiclass SS42AI_pcmpistri<Intrinsic IntId128, string asm = "pcmpistri"> {
4969 def rr : SS42AI<0x63, MRMSrcReg, (outs),
4970 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4971 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
4972 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
4973 (implicit EFLAGS)]>, OpSize;
4974 def rm : SS42AI<0x63, MRMSrcMem, (outs),
4975 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4976 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
4977 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
4978 (implicit EFLAGS)]>, OpSize;
4982 let Predicates = [HasAVX] in {
4983 defm VPCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128, "vpcmpistri">,
4985 defm VPCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128, "vpcmpistri">,
4987 defm VPCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128, "vpcmpistri">,
4989 defm VPCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128, "vpcmpistri">,
4991 defm VPCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128, "vpcmpistri">,
4993 defm VPCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128, "vpcmpistri">,
4997 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
4998 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
4999 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
5000 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
5001 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
5002 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
5004 // Packed Compare Explicit Length Strings, Return Index
5005 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX] in {
5006 multiclass SS42AI_pcmpestri<Intrinsic IntId128, string asm = "pcmpestri"> {
5007 def rr : SS42AI<0x61, MRMSrcReg, (outs),
5008 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
5009 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
5010 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
5011 (implicit EFLAGS)]>, OpSize;
5012 def rm : SS42AI<0x61, MRMSrcMem, (outs),
5013 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
5014 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
5016 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
5017 (implicit EFLAGS)]>, OpSize;
5021 let Predicates = [HasAVX] in {
5022 defm VPCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128, "vpcmpestri">,
5024 defm VPCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128, "vpcmpestri">,
5026 defm VPCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128, "vpcmpestri">,
5028 defm VPCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128, "vpcmpestri">,
5030 defm VPCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128, "vpcmpestri">,
5032 defm VPCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128, "vpcmpestri">,
5036 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
5037 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
5038 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
5039 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
5040 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
5041 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
5043 //===----------------------------------------------------------------------===//
5044 // SSE4.2 - CRC Instructions
5045 //===----------------------------------------------------------------------===//
5047 // No CRC instructions have AVX equivalents
5049 // crc intrinsic instruction
5050 // This set of instructions are only rm, the only difference is the size
5052 let Constraints = "$src1 = $dst" in {
5053 def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
5054 (ins GR32:$src1, i8mem:$src2),
5055 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5057 (int_x86_sse42_crc32_32_8 GR32:$src1,
5058 (load addr:$src2)))]>;
5059 def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
5060 (ins GR32:$src1, GR8:$src2),
5061 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5063 (int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))]>;
5064 def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
5065 (ins GR32:$src1, i16mem:$src2),
5066 "crc32{w} \t{$src2, $src1|$src1, $src2}",
5068 (int_x86_sse42_crc32_32_16 GR32:$src1,
5069 (load addr:$src2)))]>,
5071 def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
5072 (ins GR32:$src1, GR16:$src2),
5073 "crc32{w} \t{$src2, $src1|$src1, $src2}",
5075 (int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))]>,
5077 def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
5078 (ins GR32:$src1, i32mem:$src2),
5079 "crc32{l} \t{$src2, $src1|$src1, $src2}",
5081 (int_x86_sse42_crc32_32_32 GR32:$src1,
5082 (load addr:$src2)))]>;
5083 def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
5084 (ins GR32:$src1, GR32:$src2),
5085 "crc32{l} \t{$src2, $src1|$src1, $src2}",
5087 (int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))]>;
5088 def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
5089 (ins GR64:$src1, i8mem:$src2),
5090 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5092 (int_x86_sse42_crc32_64_8 GR64:$src1,
5093 (load addr:$src2)))]>,
5095 def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
5096 (ins GR64:$src1, GR8:$src2),
5097 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5099 (int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))]>,
5101 def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
5102 (ins GR64:$src1, i64mem:$src2),
5103 "crc32{q} \t{$src2, $src1|$src1, $src2}",
5105 (int_x86_sse42_crc32_64_64 GR64:$src1,
5106 (load addr:$src2)))]>,
5108 def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
5109 (ins GR64:$src1, GR64:$src2),
5110 "crc32{q} \t{$src2, $src1|$src1, $src2}",
5112 (int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))]>,
5116 //===----------------------------------------------------------------------===//
5117 // AES-NI Instructions
5118 //===----------------------------------------------------------------------===//
5120 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
5121 Intrinsic IntId128, bit Is2Addr = 1> {
5122 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
5123 (ins VR128:$src1, VR128:$src2),
5125 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5126 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5127 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5129 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
5130 (ins VR128:$src1, i128mem:$src2),
5132 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5133 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5135 (IntId128 VR128:$src1,
5136 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
5139 // Perform One Round of an AES Encryption/Decryption Flow
5140 let Predicates = [HasAVX, HasAES] in {
5141 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
5142 int_x86_aesni_aesenc, 0>, VEX_4V;
5143 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
5144 int_x86_aesni_aesenclast, 0>, VEX_4V;
5145 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
5146 int_x86_aesni_aesdec, 0>, VEX_4V;
5147 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
5148 int_x86_aesni_aesdeclast, 0>, VEX_4V;
5151 let Constraints = "$src1 = $dst" in {
5152 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
5153 int_x86_aesni_aesenc>;
5154 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
5155 int_x86_aesni_aesenclast>;
5156 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
5157 int_x86_aesni_aesdec>;
5158 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
5159 int_x86_aesni_aesdeclast>;
5162 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, VR128:$src2)),
5163 (AESENCrr VR128:$src1, VR128:$src2)>;
5164 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, (memop addr:$src2))),
5165 (AESENCrm VR128:$src1, addr:$src2)>;
5166 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, VR128:$src2)),
5167 (AESENCLASTrr VR128:$src1, VR128:$src2)>;
5168 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, (memop addr:$src2))),
5169 (AESENCLASTrm VR128:$src1, addr:$src2)>;
5170 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, VR128:$src2)),
5171 (AESDECrr VR128:$src1, VR128:$src2)>;
5172 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, (memop addr:$src2))),
5173 (AESDECrm VR128:$src1, addr:$src2)>;
5174 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, VR128:$src2)),
5175 (AESDECLASTrr VR128:$src1, VR128:$src2)>;
5176 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, (memop addr:$src2))),
5177 (AESDECLASTrm VR128:$src1, addr:$src2)>;
5179 // Perform the AES InvMixColumn Transformation
5180 let Predicates = [HasAVX, HasAES] in {
5181 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
5183 "vaesimc\t{$src1, $dst|$dst, $src1}",
5185 (int_x86_aesni_aesimc VR128:$src1))]>,
5187 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
5188 (ins i128mem:$src1),
5189 "vaesimc\t{$src1, $dst|$dst, $src1}",
5191 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
5194 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
5196 "aesimc\t{$src1, $dst|$dst, $src1}",
5198 (int_x86_aesni_aesimc VR128:$src1))]>,
5200 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
5201 (ins i128mem:$src1),
5202 "aesimc\t{$src1, $dst|$dst, $src1}",
5204 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
5207 // AES Round Key Generation Assist
5208 let Predicates = [HasAVX, HasAES] in {
5209 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
5210 (ins VR128:$src1, i8imm:$src2),
5211 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5213 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
5215 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
5216 (ins i128mem:$src1, i8imm:$src2),
5217 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5219 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
5223 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
5224 (ins VR128:$src1, i8imm:$src2),
5225 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5227 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
5229 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
5230 (ins i128mem:$src1, i8imm:$src2),
5231 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5233 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
5237 //===----------------------------------------------------------------------===//
5238 // CLMUL Instructions
5239 //===----------------------------------------------------------------------===//
5241 // Carry-less Multiplication instructions
5242 let Constraints = "$src1 = $dst" in {
5243 def PCLMULQDQrr : CLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
5244 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5245 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
5248 def PCLMULQDQrm : CLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
5249 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5250 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
5254 // AVX carry-less Multiplication instructions
5255 def VPCLMULQDQrr : AVXCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
5256 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5257 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5260 def VPCLMULQDQrm : AVXCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
5261 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5262 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5266 multiclass pclmul_alias<string asm, int immop> {
5267 def : InstAlias<!strconcat("pclmul", asm,
5268 "dq {$src, $dst|$dst, $src}"),
5269 (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
5271 def : InstAlias<!strconcat("pclmul", asm,
5272 "dq {$src, $dst|$dst, $src}"),
5273 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
5275 def : InstAlias<!strconcat("vpclmul", asm,
5276 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
5277 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
5279 def : InstAlias<!strconcat("vpclmul", asm,
5280 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
5281 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
5283 defm : pclmul_alias<"hqhq", 0x11>;
5284 defm : pclmul_alias<"hqlq", 0x01>;
5285 defm : pclmul_alias<"lqhq", 0x10>;
5286 defm : pclmul_alias<"lqlq", 0x00>;
5288 //===----------------------------------------------------------------------===//
5290 //===----------------------------------------------------------------------===//
5292 //===----------------------------------------------------------------------===//
5293 // VBROADCAST - Load from memory and broadcast to all elements of the
5294 // destination operand
5296 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
5297 X86MemOperand x86memop, Intrinsic Int> :
5298 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
5299 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5300 [(set RC:$dst, (Int addr:$src))]>, VEX;
5302 def VBROADCASTSS : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
5303 int_x86_avx_vbroadcastss>;
5304 def VBROADCASTSSY : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
5305 int_x86_avx_vbroadcastss_256>;
5306 def VBROADCASTSD : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
5307 int_x86_avx_vbroadcast_sd_256>;
5308 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
5309 int_x86_avx_vbroadcastf128_pd_256>;
5311 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
5312 (VBROADCASTF128 addr:$src)>;
5314 //===----------------------------------------------------------------------===//
5315 // VINSERTF128 - Insert packed floating-point values
5317 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
5318 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
5319 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5321 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
5322 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
5323 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5326 def : Pat<(int_x86_avx_vinsertf128_pd_256 VR256:$src1, VR128:$src2, imm:$src3),
5327 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
5328 def : Pat<(int_x86_avx_vinsertf128_ps_256 VR256:$src1, VR128:$src2, imm:$src3),
5329 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
5330 def : Pat<(int_x86_avx_vinsertf128_si_256 VR256:$src1, VR128:$src2, imm:$src3),
5331 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
5333 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
5335 (VINSERTF128rr VR256:$src1, VR128:$src2,
5336 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5337 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
5339 (VINSERTF128rr VR256:$src1, VR128:$src2,
5340 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5341 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
5343 (VINSERTF128rr VR256:$src1, VR128:$src2,
5344 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5345 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
5347 (VINSERTF128rr VR256:$src1, VR128:$src2,
5348 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5349 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
5351 (VINSERTF128rr VR256:$src1, VR128:$src2,
5352 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5353 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
5355 (VINSERTF128rr VR256:$src1, VR128:$src2,
5356 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5358 //===----------------------------------------------------------------------===//
5359 // VEXTRACTF128 - Extract packed floating-point values
5361 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
5362 (ins VR256:$src1, i8imm:$src2),
5363 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5365 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
5366 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
5367 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5370 def : Pat<(int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2),
5371 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
5372 def : Pat<(int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2),
5373 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
5374 def : Pat<(int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2),
5375 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
5377 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5378 (v4f32 (VEXTRACTF128rr
5379 (v8f32 VR256:$src1),
5380 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5381 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5382 (v2f64 (VEXTRACTF128rr
5383 (v4f64 VR256:$src1),
5384 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5385 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5386 (v4i32 (VEXTRACTF128rr
5387 (v8i32 VR256:$src1),
5388 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5389 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5390 (v2i64 (VEXTRACTF128rr
5391 (v4i64 VR256:$src1),
5392 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5393 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5394 (v8i16 (VEXTRACTF128rr
5395 (v16i16 VR256:$src1),
5396 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5397 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5398 (v16i8 (VEXTRACTF128rr
5399 (v32i8 VR256:$src1),
5400 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5402 //===----------------------------------------------------------------------===//
5403 // VMASKMOV - Conditional SIMD Packed Loads and Stores
5405 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
5406 Intrinsic IntLd, Intrinsic IntLd256,
5407 Intrinsic IntSt, Intrinsic IntSt256,
5408 PatFrag pf128, PatFrag pf256> {
5409 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
5410 (ins VR128:$src1, f128mem:$src2),
5411 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5412 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
5414 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
5415 (ins VR256:$src1, f256mem:$src2),
5416 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5417 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
5419 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
5420 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
5421 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5422 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
5423 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
5424 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
5425 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5426 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
5429 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
5430 int_x86_avx_maskload_ps,
5431 int_x86_avx_maskload_ps_256,
5432 int_x86_avx_maskstore_ps,
5433 int_x86_avx_maskstore_ps_256,
5434 memopv4f32, memopv8f32>;
5435 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
5436 int_x86_avx_maskload_pd,
5437 int_x86_avx_maskload_pd_256,
5438 int_x86_avx_maskstore_pd,
5439 int_x86_avx_maskstore_pd_256,
5440 memopv2f64, memopv4f64>;
5442 //===----------------------------------------------------------------------===//
5443 // VPERM - Permute Floating-Point Values
5445 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
5446 RegisterClass RC, X86MemOperand x86memop_f,
5447 X86MemOperand x86memop_i, PatFrag f_frag, PatFrag i_frag,
5448 Intrinsic IntVar, Intrinsic IntImm> {
5449 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
5450 (ins RC:$src1, RC:$src2),
5451 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5452 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
5453 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
5454 (ins RC:$src1, x86memop_i:$src2),
5455 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5456 [(set RC:$dst, (IntVar RC:$src1, (i_frag addr:$src2)))]>, VEX_4V;
5458 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
5459 (ins RC:$src1, i8imm:$src2),
5460 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5461 [(set RC:$dst, (IntImm RC:$src1, imm:$src2))]>, VEX;
5462 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
5463 (ins x86memop_f:$src1, i8imm:$src2),
5464 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5465 [(set RC:$dst, (IntImm (f_frag addr:$src1), imm:$src2))]>, VEX;
5468 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
5469 memopv4f32, memopv4i32,
5470 int_x86_avx_vpermilvar_ps,
5471 int_x86_avx_vpermil_ps>;
5472 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
5473 memopv8f32, memopv8i32,
5474 int_x86_avx_vpermilvar_ps_256,
5475 int_x86_avx_vpermil_ps_256>;
5476 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
5477 memopv2f64, memopv2i64,
5478 int_x86_avx_vpermilvar_pd,
5479 int_x86_avx_vpermil_pd>;
5480 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
5481 memopv4f64, memopv4i64,
5482 int_x86_avx_vpermilvar_pd_256,
5483 int_x86_avx_vpermil_pd_256>;
5485 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
5486 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5487 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5489 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
5490 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
5491 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5494 def : Pat<(int_x86_avx_vperm2f128_ps_256 VR256:$src1, VR256:$src2, imm:$src3),
5495 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
5496 def : Pat<(int_x86_avx_vperm2f128_pd_256 VR256:$src1, VR256:$src2, imm:$src3),
5497 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
5498 def : Pat<(int_x86_avx_vperm2f128_si_256 VR256:$src1, VR256:$src2, imm:$src3),
5499 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
5501 def : Pat<(int_x86_avx_vperm2f128_ps_256
5502 VR256:$src1, (memopv8f32 addr:$src2), imm:$src3),
5503 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
5504 def : Pat<(int_x86_avx_vperm2f128_pd_256
5505 VR256:$src1, (memopv4f64 addr:$src2), imm:$src3),
5506 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
5507 def : Pat<(int_x86_avx_vperm2f128_si_256
5508 VR256:$src1, (memopv8i32 addr:$src2), imm:$src3),
5509 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
5511 //===----------------------------------------------------------------------===//
5512 // VZERO - Zero YMM registers
5514 // Zero All YMM registers
5515 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
5516 [(int_x86_avx_vzeroall)]>, VEX, VEX_L, Requires<[HasAVX]>;
5518 // Zero Upper bits of YMM registers
5519 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
5520 [(int_x86_avx_vzeroupper)]>, VEX, Requires<[HasAVX]>;
5522 //===----------------------------------------------------------------------===//
5523 // SSE Shuffle pattern fragments
5524 //===----------------------------------------------------------------------===//
5526 // This is part of a "work in progress" refactoring. The idea is that all
5527 // vector shuffles are going to be translated into target specific nodes and
5528 // directly matched by the patterns below (which can be changed along the way)
5529 // The AVX version of some but not all of them are described here, and more
5530 // should come in a near future.
5532 // Shuffle with PSHUFD instruction folding loads. The first two patterns match
5533 // SSE2 loads, which are always promoted to v2i64. The last one should match
5534 // the SSE1 case, where the only legal load is v4f32, but there is no PSHUFD
5535 // in SSE2, how does it ever worked? Anyway, the pattern will remain here until
5536 // we investigate further.
5537 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
5539 (VPSHUFDmi addr:$src1, imm:$imm)>, Requires<[HasAVX]>;
5540 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
5542 (PSHUFDmi addr:$src1, imm:$imm)>;
5543 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv4f32 addr:$src1)),
5545 (PSHUFDmi addr:$src1, imm:$imm)>; // FIXME: has this ever worked?
5547 // Shuffle with PSHUFD instruction.
5548 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
5549 (VPSHUFDri VR128:$src1, imm:$imm)>, Requires<[HasAVX]>;
5550 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
5551 (PSHUFDri VR128:$src1, imm:$imm)>;
5553 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
5554 (VPSHUFDri VR128:$src1, imm:$imm)>, Requires<[HasAVX]>;
5555 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
5556 (PSHUFDri VR128:$src1, imm:$imm)>;
5558 // Shuffle with SHUFPD instruction.
5559 def : Pat<(v2f64 (X86Shufps VR128:$src1,
5560 (memopv2f64 addr:$src2), (i8 imm:$imm))),
5561 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>, Requires<[HasAVX]>;
5562 def : Pat<(v2f64 (X86Shufps VR128:$src1,
5563 (memopv2f64 addr:$src2), (i8 imm:$imm))),
5564 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
5566 def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5567 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>;
5568 def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5569 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
5571 def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5572 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>;
5573 def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5574 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
5576 // Shuffle with SHUFPS instruction.
5577 def : Pat<(v4f32 (X86Shufps VR128:$src1,
5578 (memopv4f32 addr:$src2), (i8 imm:$imm))),
5579 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>, Requires<[HasAVX]>;
5580 def : Pat<(v4f32 (X86Shufps VR128:$src1,
5581 (memopv4f32 addr:$src2), (i8 imm:$imm))),
5582 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
5584 def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5585 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>;
5586 def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5587 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
5589 def : Pat<(v4i32 (X86Shufps VR128:$src1,
5590 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
5591 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>, Requires<[HasAVX]>;
5592 def : Pat<(v4i32 (X86Shufps VR128:$src1,
5593 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
5594 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
5596 def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5597 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>;
5598 def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5599 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
5601 // Shuffle with MOVHLPS instruction
5602 def : Pat<(v4f32 (X86Movhlps VR128:$src1, VR128:$src2)),
5603 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
5604 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
5605 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
5607 // Shuffle with MOVDDUP instruction
5608 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5609 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5610 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5611 (MOVDDUPrm addr:$src)>;
5613 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5614 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5615 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5616 (MOVDDUPrm addr:$src)>;
5618 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5619 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5620 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5621 (MOVDDUPrm addr:$src)>;
5623 def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))),
5624 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5625 def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))),
5626 (MOVDDUPrm addr:$src)>;
5628 def : Pat<(X86Movddup (bc_v2f64
5629 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5630 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5631 def : Pat<(X86Movddup (bc_v2f64
5632 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5633 (MOVDDUPrm addr:$src)>;
5636 // Shuffle with UNPCKLPS
5637 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
5638 (VUNPCKLPSrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
5639 def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, (memopv8f32 addr:$src2))),
5640 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
5641 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
5642 (UNPCKLPSrm VR128:$src1, addr:$src2)>;
5644 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
5645 (VUNPCKLPSrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
5646 def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, VR256:$src2)),
5647 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
5648 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
5649 (UNPCKLPSrr VR128:$src1, VR128:$src2)>;
5651 // Shuffle with UNPCKHPS
5652 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))),
5653 (VUNPCKHPSrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
5654 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))),
5655 (UNPCKHPSrm VR128:$src1, addr:$src2)>;
5657 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
5658 (VUNPCKHPSrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
5659 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
5660 (UNPCKHPSrr VR128:$src1, VR128:$src2)>;
5662 // Shuffle with UNPCKLPD
5663 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
5664 (VUNPCKLPDrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
5665 def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, (memopv4f64 addr:$src2))),
5666 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
5667 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
5668 (UNPCKLPDrm VR128:$src1, addr:$src2)>;
5670 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
5671 (VUNPCKLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
5672 def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, VR256:$src2)),
5673 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
5674 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
5675 (UNPCKLPDrr VR128:$src1, VR128:$src2)>;
5677 // Shuffle with UNPCKHPD
5678 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))),
5679 (VUNPCKHPDrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
5680 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))),
5681 (UNPCKHPDrm VR128:$src1, addr:$src2)>;
5683 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
5684 (VUNPCKHPDrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
5685 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
5686 (UNPCKHPDrr VR128:$src1, VR128:$src2)>;
5688 // Shuffle with PUNPCKLBW
5689 def : Pat<(v16i8 (X86Punpcklbw VR128:$src1,
5690 (bc_v16i8 (memopv2i64 addr:$src2)))),
5691 (PUNPCKLBWrm VR128:$src1, addr:$src2)>;
5692 def : Pat<(v16i8 (X86Punpcklbw VR128:$src1, VR128:$src2)),
5693 (PUNPCKLBWrr VR128:$src1, VR128:$src2)>;
5695 // Shuffle with PUNPCKLWD
5696 def : Pat<(v8i16 (X86Punpcklwd VR128:$src1,
5697 (bc_v8i16 (memopv2i64 addr:$src2)))),
5698 (PUNPCKLWDrm VR128:$src1, addr:$src2)>;
5699 def : Pat<(v8i16 (X86Punpcklwd VR128:$src1, VR128:$src2)),
5700 (PUNPCKLWDrr VR128:$src1, VR128:$src2)>;
5702 // Shuffle with PUNPCKLDQ
5703 def : Pat<(v4i32 (X86Punpckldq VR128:$src1,
5704 (bc_v4i32 (memopv2i64 addr:$src2)))),
5705 (PUNPCKLDQrm VR128:$src1, addr:$src2)>;
5706 def : Pat<(v4i32 (X86Punpckldq VR128:$src1, VR128:$src2)),
5707 (PUNPCKLDQrr VR128:$src1, VR128:$src2)>;
5709 // Shuffle with PUNPCKLQDQ
5710 def : Pat<(v2i64 (X86Punpcklqdq VR128:$src1, (memopv2i64 addr:$src2))),
5711 (PUNPCKLQDQrm VR128:$src1, addr:$src2)>;
5712 def : Pat<(v2i64 (X86Punpcklqdq VR128:$src1, VR128:$src2)),
5713 (PUNPCKLQDQrr VR128:$src1, VR128:$src2)>;
5715 // Shuffle with PUNPCKHBW
5716 def : Pat<(v16i8 (X86Punpckhbw VR128:$src1,
5717 (bc_v16i8 (memopv2i64 addr:$src2)))),
5718 (PUNPCKHBWrm VR128:$src1, addr:$src2)>;
5719 def : Pat<(v16i8 (X86Punpckhbw VR128:$src1, VR128:$src2)),
5720 (PUNPCKHBWrr VR128:$src1, VR128:$src2)>;
5722 // Shuffle with PUNPCKHWD
5723 def : Pat<(v8i16 (X86Punpckhwd VR128:$src1,
5724 (bc_v8i16 (memopv2i64 addr:$src2)))),
5725 (PUNPCKHWDrm VR128:$src1, addr:$src2)>;
5726 def : Pat<(v8i16 (X86Punpckhwd VR128:$src1, VR128:$src2)),
5727 (PUNPCKHWDrr VR128:$src1, VR128:$src2)>;
5729 // Shuffle with PUNPCKHDQ
5730 def : Pat<(v4i32 (X86Punpckhdq VR128:$src1,
5731 (bc_v4i32 (memopv2i64 addr:$src2)))),
5732 (PUNPCKHDQrm VR128:$src1, addr:$src2)>;
5733 def : Pat<(v4i32 (X86Punpckhdq VR128:$src1, VR128:$src2)),
5734 (PUNPCKHDQrr VR128:$src1, VR128:$src2)>;
5736 // Shuffle with PUNPCKHQDQ
5737 def : Pat<(v2i64 (X86Punpckhqdq VR128:$src1, (memopv2i64 addr:$src2))),
5738 (PUNPCKHQDQrm VR128:$src1, addr:$src2)>;
5739 def : Pat<(v2i64 (X86Punpckhqdq VR128:$src1, VR128:$src2)),
5740 (PUNPCKHQDQrr VR128:$src1, VR128:$src2)>;
5742 // Shuffle with MOVLHPS
5743 def : Pat<(X86Movlhps VR128:$src1,
5744 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
5745 (MOVHPSrm VR128:$src1, addr:$src2)>;
5746 def : Pat<(X86Movlhps VR128:$src1,
5747 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
5748 (MOVHPSrm VR128:$src1, addr:$src2)>;
5749 def : Pat<(v4f32 (X86Movlhps VR128:$src1, VR128:$src2)),
5750 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
5751 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
5752 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
5753 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
5754 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
5756 // FIXME: Instead of X86Movddup, there should be a X86Unpcklpd here, the problem
5757 // is during lowering, where it's not possible to recognize the load fold cause
5758 // it has two uses through a bitcast. One use disappears at isel time and the
5759 // fold opportunity reappears.
5760 def : Pat<(v2f64 (X86Movddup VR128:$src)),
5761 (UNPCKLPDrr VR128:$src, VR128:$src)>;
5763 // Shuffle with MOVLHPD
5764 def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
5765 (scalar_to_vector (loadf64 addr:$src2)))),
5766 (MOVHPDrm VR128:$src1, addr:$src2)>;
5768 // FIXME: Instead of X86Unpcklpd, there should be a X86Movlhpd here, the problem
5769 // is during lowering, where it's not possible to recognize the load fold cause
5770 // it has two uses through a bitcast. One use disappears at isel time and the
5771 // fold opportunity reappears.
5772 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1,
5773 (scalar_to_vector (loadf64 addr:$src2)))),
5774 (MOVHPDrm VR128:$src1, addr:$src2)>;
5776 // Shuffle with MOVSS
5777 def : Pat<(v4f32 (X86Movss VR128:$src1, (scalar_to_vector FR32:$src2))),
5778 (MOVSSrr VR128:$src1, FR32:$src2)>;
5779 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
5780 (MOVSSrr (v4i32 VR128:$src1),
5781 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
5782 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
5783 (MOVSSrr (v4f32 VR128:$src1),
5784 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
5785 // FIXME: Instead of a X86Movss there should be a X86Movlps here, the problem
5786 // is during lowering, where it's not possible to recognize the load fold cause
5787 // it has two uses through a bitcast. One use disappears at isel time and the
5788 // fold opportunity reappears.
5789 def : Pat<(X86Movss VR128:$src1,
5790 (bc_v4i32 (v2i64 (load addr:$src2)))),
5791 (MOVLPSrm VR128:$src1, addr:$src2)>;
5793 // Shuffle with MOVSD
5794 def : Pat<(v2f64 (X86Movsd VR128:$src1, (scalar_to_vector FR64:$src2))),
5795 (MOVSDrr VR128:$src1, FR64:$src2)>;
5796 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
5797 (MOVSDrr (v2i64 VR128:$src1),
5798 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
5799 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
5800 (MOVSDrr (v2f64 VR128:$src1),
5801 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
5802 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
5803 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_sd))>;
5804 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
5805 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_sd))>;
5807 // Shuffle with MOVSHDUP
5808 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5809 (MOVSHDUPrr VR128:$src)>;
5810 def : Pat<(X86Movshdup (bc_v4i32 (memopv2i64 addr:$src))),
5811 (MOVSHDUPrm addr:$src)>;
5813 def : Pat<(v4f32 (X86Movshdup VR128:$src)),
5814 (MOVSHDUPrr VR128:$src)>;
5815 def : Pat<(X86Movshdup (memopv4f32 addr:$src)),
5816 (MOVSHDUPrm addr:$src)>;
5818 // Shuffle with MOVSLDUP
5819 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5820 (MOVSLDUPrr VR128:$src)>;
5821 def : Pat<(X86Movsldup (bc_v4i32 (memopv2i64 addr:$src))),
5822 (MOVSLDUPrm addr:$src)>;
5824 def : Pat<(v4f32 (X86Movsldup VR128:$src)),
5825 (MOVSLDUPrr VR128:$src)>;
5826 def : Pat<(X86Movsldup (memopv4f32 addr:$src)),
5827 (MOVSLDUPrm addr:$src)>;
5829 // Shuffle with PSHUFHW
5830 def : Pat<(v8i16 (X86PShufhw VR128:$src, (i8 imm:$imm))),
5831 (PSHUFHWri VR128:$src, imm:$imm)>;
5832 def : Pat<(v8i16 (X86PShufhw (bc_v8i16 (memopv2i64 addr:$src)), (i8 imm:$imm))),
5833 (PSHUFHWmi addr:$src, imm:$imm)>;
5835 // Shuffle with PSHUFLW
5836 def : Pat<(v8i16 (X86PShuflw VR128:$src, (i8 imm:$imm))),
5837 (PSHUFLWri VR128:$src, imm:$imm)>;
5838 def : Pat<(v8i16 (X86PShuflw (bc_v8i16 (memopv2i64 addr:$src)), (i8 imm:$imm))),
5839 (PSHUFLWmi addr:$src, imm:$imm)>;
5841 // Shuffle with PALIGN
5842 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5843 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5844 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5845 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5846 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5847 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5848 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5849 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5851 // Shuffle with MOVLPS
5852 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
5853 (MOVLPSrm VR128:$src1, addr:$src2)>;
5854 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
5855 (MOVLPSrm VR128:$src1, addr:$src2)>;
5856 def : Pat<(X86Movlps VR128:$src1,
5857 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
5858 (MOVLPSrm VR128:$src1, addr:$src2)>;
5859 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
5860 // is during lowering, where it's not possible to recognize the load fold cause
5861 // it has two uses through a bitcast. One use disappears at isel time and the
5862 // fold opportunity reappears.
5863 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
5864 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_sd))>;
5866 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
5867 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_sd))>;
5869 // Shuffle with MOVLPD
5870 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
5871 (MOVLPDrm VR128:$src1, addr:$src2)>;
5872 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
5873 (MOVLPDrm VR128:$src1, addr:$src2)>;
5874 def : Pat<(v2f64 (X86Movlpd VR128:$src1,
5875 (scalar_to_vector (loadf64 addr:$src2)))),
5876 (MOVLPDrm VR128:$src1, addr:$src2)>;
5878 // Extra patterns to match stores with MOVHPS/PD and MOVLPS/PD
5879 def : Pat<(store (f64 (vector_extract
5880 (v2f64 (X86Unpckhps VR128:$src, (undef))), (iPTR 0))),addr:$dst),
5881 (MOVHPSmr addr:$dst, VR128:$src)>;
5882 def : Pat<(store (f64 (vector_extract
5883 (v2f64 (X86Unpckhpd VR128:$src, (undef))), (iPTR 0))),addr:$dst),
5884 (MOVHPDmr addr:$dst, VR128:$src)>;
5886 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),addr:$src1),
5887 (MOVLPSmr addr:$src1, VR128:$src2)>;
5888 def : Pat<(store (v4i32 (X86Movlps
5889 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
5890 (MOVLPSmr addr:$src1, VR128:$src2)>;
5892 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),addr:$src1),
5893 (MOVLPDmr addr:$src1, VR128:$src2)>;
5894 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),addr:$src1),
5895 (MOVLPDmr addr:$src1, VR128:$src2)>;