1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE 1 & 2 Instructions Classes
19 //===----------------------------------------------------------------------===//
21 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
22 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
23 RegisterClass RC, X86MemOperand x86memop,
25 let isCommutable = 1 in {
26 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
28 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
29 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
30 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>;
32 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
34 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
35 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
36 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))]>;
39 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
40 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
41 string asm, string SSEVer, string FPSizeStr,
42 Operand memopr, ComplexPattern mem_cpat,
44 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
46 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
47 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
48 [(set RC:$dst, (!cast<Intrinsic>(
49 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
50 RC:$src1, RC:$src2))]>;
51 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
53 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
54 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
55 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
56 SSEVer, "_", OpcodeStr, FPSizeStr))
57 RC:$src1, mem_cpat:$src2))]>;
60 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
61 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
62 RegisterClass RC, ValueType vt,
63 X86MemOperand x86memop, PatFrag mem_frag,
64 Domain d, bit Is2Addr = 1> {
65 let isCommutable = 1 in
66 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
68 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
69 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
70 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], d>;
72 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
74 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
75 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
76 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))], d>;
79 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
80 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
81 string OpcodeStr, X86MemOperand x86memop,
82 list<dag> pat_rr, list<dag> pat_rm,
84 let isCommutable = 1 in
85 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
87 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
88 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
90 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
92 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
93 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
97 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
98 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
99 string asm, string SSEVer, string FPSizeStr,
100 X86MemOperand x86memop, PatFrag mem_frag,
101 Domain d, bit Is2Addr = 1> {
102 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
104 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
105 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
106 [(set RC:$dst, (!cast<Intrinsic>(
107 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
108 RC:$src1, RC:$src2))], d>;
109 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1,x86memop:$src2),
111 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
112 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
113 [(set RC:$dst, (!cast<Intrinsic>(
114 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
115 RC:$src1, (mem_frag addr:$src2)))], d>;
118 //===----------------------------------------------------------------------===//
119 // SSE 1 & 2 - Move Instructions
120 //===----------------------------------------------------------------------===//
122 class sse12_move_rr<RegisterClass RC, ValueType vt, string asm> :
123 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
124 [(set (vt VR128:$dst), (movl VR128:$src1, (scalar_to_vector RC:$src2)))]>;
126 // Loading from memory automatically zeroing upper bits.
127 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
128 PatFrag mem_pat, string OpcodeStr> :
129 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
130 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
131 [(set RC:$dst, (mem_pat addr:$src))]>;
133 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
134 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
135 // is used instead. Register-to-register movss/movsd is not modeled as an
136 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
137 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
138 def VMOVSSrr : sse12_move_rr<FR32, v4f32,
139 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V;
140 def VMOVSDrr : sse12_move_rr<FR64, v2f64,
141 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V;
143 let canFoldAsLoad = 1, isReMaterializable = 1 in {
144 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX;
146 let AddedComplexity = 20 in
147 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX;
150 let Constraints = "$src1 = $dst" in {
151 def MOVSSrr : sse12_move_rr<FR32, v4f32,
152 "movss\t{$src2, $dst|$dst, $src2}">, XS;
153 def MOVSDrr : sse12_move_rr<FR64, v2f64,
154 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
157 let canFoldAsLoad = 1, isReMaterializable = 1 in {
158 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
160 let AddedComplexity = 20 in
161 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
164 let AddedComplexity = 15 in {
165 // Extract the low 32-bit value from one vector and insert it into another.
166 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
167 (MOVSSrr (v4f32 VR128:$src1),
168 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
169 // Extract the low 64-bit value from one vector and insert it into another.
170 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
171 (MOVSDrr (v2f64 VR128:$src1),
172 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
175 // Implicitly promote a 32-bit scalar to a vector.
176 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
177 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
178 // Implicitly promote a 64-bit scalar to a vector.
179 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
180 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
181 // Implicitly promote a 32-bit scalar to a vector.
182 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
183 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
184 // Implicitly promote a 64-bit scalar to a vector.
185 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
186 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
188 let AddedComplexity = 20 in {
189 let Predicates = [HasSSE1] in {
190 // MOVSSrm zeros the high parts of the register; represent this
191 // with SUBREG_TO_REG.
192 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
193 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
194 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
195 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
196 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
197 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
199 let Predicates = [HasSSE2] in {
200 // MOVSDrm zeros the high parts of the register; represent this
201 // with SUBREG_TO_REG.
202 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
203 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
204 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
205 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
206 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
207 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
208 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
209 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
210 def : Pat<(v2f64 (X86vzload addr:$src)),
211 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
215 let AddedComplexity = 20, Predicates = [HasAVX] in {
216 // MOVSSrm zeros the high parts of the register; represent this
217 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
218 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
219 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
220 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
221 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
222 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
223 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
224 // MOVSDrm zeros the high parts of the register; represent this
225 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
226 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
227 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
228 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
229 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
230 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
231 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
232 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
233 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
234 def : Pat<(v2f64 (X86vzload addr:$src)),
235 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
236 // Represent the same patterns above but in the form they appear for
238 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
239 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (i32 0)))),
240 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
241 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
242 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (i32 0)))),
243 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_sd)>;
246 // Store scalar value to memory.
247 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
248 "movss\t{$src, $dst|$dst, $src}",
249 [(store FR32:$src, addr:$dst)]>;
250 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
251 "movsd\t{$src, $dst|$dst, $src}",
252 [(store FR64:$src, addr:$dst)]>;
254 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
255 "movss\t{$src, $dst|$dst, $src}",
256 [(store FR32:$src, addr:$dst)]>, XS, VEX;
257 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
258 "movsd\t{$src, $dst|$dst, $src}",
259 [(store FR64:$src, addr:$dst)]>, XD, VEX;
261 // Extract and store.
262 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
265 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
266 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
269 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
271 // Move Aligned/Unaligned floating point values
272 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
273 X86MemOperand x86memop, PatFrag ld_frag,
274 string asm, Domain d,
275 bit IsReMaterializable = 1> {
276 let neverHasSideEffects = 1 in
277 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
278 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>;
279 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
280 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
281 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
282 [(set RC:$dst, (ld_frag addr:$src))], d>;
285 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
286 "movaps", SSEPackedSingle>, VEX;
287 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
288 "movapd", SSEPackedDouble>, OpSize, VEX;
289 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
290 "movups", SSEPackedSingle>, VEX;
291 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
292 "movupd", SSEPackedDouble, 0>, OpSize, VEX;
294 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
295 "movaps", SSEPackedSingle>, VEX;
296 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
297 "movapd", SSEPackedDouble>, OpSize, VEX;
298 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
299 "movups", SSEPackedSingle>, VEX;
300 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
301 "movupd", SSEPackedDouble, 0>, OpSize, VEX;
302 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
303 "movaps", SSEPackedSingle>, TB;
304 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
305 "movapd", SSEPackedDouble>, TB, OpSize;
306 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
307 "movups", SSEPackedSingle>, TB;
308 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
309 "movupd", SSEPackedDouble, 0>, TB, OpSize;
311 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
312 "movaps\t{$src, $dst|$dst, $src}",
313 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>, VEX;
314 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
315 "movapd\t{$src, $dst|$dst, $src}",
316 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>, VEX;
317 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
318 "movups\t{$src, $dst|$dst, $src}",
319 [(store (v4f32 VR128:$src), addr:$dst)]>, VEX;
320 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
321 "movupd\t{$src, $dst|$dst, $src}",
322 [(store (v2f64 VR128:$src), addr:$dst)]>, VEX;
323 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
324 "movaps\t{$src, $dst|$dst, $src}",
325 [(alignedstore (v8f32 VR256:$src), addr:$dst)]>, VEX;
326 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
327 "movapd\t{$src, $dst|$dst, $src}",
328 [(alignedstore (v4f64 VR256:$src), addr:$dst)]>, VEX;
329 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
330 "movups\t{$src, $dst|$dst, $src}",
331 [(store (v8f32 VR256:$src), addr:$dst)]>, VEX;
332 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
333 "movupd\t{$src, $dst|$dst, $src}",
334 [(store (v4f64 VR256:$src), addr:$dst)]>, VEX;
336 def : Pat<(int_x86_avx_loadu_ps_256 addr:$src), (VMOVUPSYrm addr:$src)>;
337 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
338 (VMOVUPSYmr addr:$dst, VR256:$src)>;
340 def : Pat<(int_x86_avx_loadu_pd_256 addr:$src), (VMOVUPDYrm addr:$src)>;
341 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
342 (VMOVUPDYmr addr:$dst, VR256:$src)>;
344 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
345 "movaps\t{$src, $dst|$dst, $src}",
346 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
347 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
348 "movapd\t{$src, $dst|$dst, $src}",
349 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
350 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
351 "movups\t{$src, $dst|$dst, $src}",
352 [(store (v4f32 VR128:$src), addr:$dst)]>;
353 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
354 "movupd\t{$src, $dst|$dst, $src}",
355 [(store (v2f64 VR128:$src), addr:$dst)]>;
357 // Intrinsic forms of MOVUPS/D load and store
358 def VMOVUPSmr_Int : VPSI<0x11, MRMDestMem, (outs),
359 (ins f128mem:$dst, VR128:$src),
360 "movups\t{$src, $dst|$dst, $src}",
361 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>, VEX;
362 def VMOVUPDmr_Int : VPDI<0x11, MRMDestMem, (outs),
363 (ins f128mem:$dst, VR128:$src),
364 "movupd\t{$src, $dst|$dst, $src}",
365 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>, VEX;
367 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
368 "movups\t{$src, $dst|$dst, $src}",
369 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
370 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
371 "movupd\t{$src, $dst|$dst, $src}",
372 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
374 // Move Low/High packed floating point values
375 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
376 PatFrag mov_frag, string base_opc,
378 def PSrm : PI<opc, MRMSrcMem,
379 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
380 !strconcat(base_opc, "s", asm_opr),
383 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
384 SSEPackedSingle>, TB;
386 def PDrm : PI<opc, MRMSrcMem,
387 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
388 !strconcat(base_opc, "d", asm_opr),
389 [(set RC:$dst, (v2f64 (mov_frag RC:$src1,
390 (scalar_to_vector (loadf64 addr:$src2)))))],
391 SSEPackedDouble>, TB, OpSize;
394 let AddedComplexity = 20 in {
395 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
396 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
397 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
398 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
400 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
401 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
402 "\t{$src2, $dst|$dst, $src2}">;
403 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
404 "\t{$src2, $dst|$dst, $src2}">;
407 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
408 "movlps\t{$src, $dst|$dst, $src}",
409 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
410 (iPTR 0))), addr:$dst)]>, VEX;
411 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
412 "movlpd\t{$src, $dst|$dst, $src}",
413 [(store (f64 (vector_extract (v2f64 VR128:$src),
414 (iPTR 0))), addr:$dst)]>, VEX;
415 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
416 "movlps\t{$src, $dst|$dst, $src}",
417 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
418 (iPTR 0))), addr:$dst)]>;
419 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
420 "movlpd\t{$src, $dst|$dst, $src}",
421 [(store (f64 (vector_extract (v2f64 VR128:$src),
422 (iPTR 0))), addr:$dst)]>;
424 // v2f64 extract element 1 is always custom lowered to unpack high to low
425 // and extract element 0 so the non-store version isn't too horrible.
426 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
427 "movhps\t{$src, $dst|$dst, $src}",
428 [(store (f64 (vector_extract
429 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
430 (undef)), (iPTR 0))), addr:$dst)]>,
432 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
433 "movhpd\t{$src, $dst|$dst, $src}",
434 [(store (f64 (vector_extract
435 (v2f64 (unpckh VR128:$src, (undef))),
436 (iPTR 0))), addr:$dst)]>,
438 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
439 "movhps\t{$src, $dst|$dst, $src}",
440 [(store (f64 (vector_extract
441 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
442 (undef)), (iPTR 0))), addr:$dst)]>;
443 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
444 "movhpd\t{$src, $dst|$dst, $src}",
445 [(store (f64 (vector_extract
446 (v2f64 (unpckh VR128:$src, (undef))),
447 (iPTR 0))), addr:$dst)]>;
449 let AddedComplexity = 20 in {
450 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
451 (ins VR128:$src1, VR128:$src2),
452 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
454 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>,
456 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
457 (ins VR128:$src1, VR128:$src2),
458 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
460 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>,
463 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
464 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
465 (ins VR128:$src1, VR128:$src2),
466 "movlhps\t{$src2, $dst|$dst, $src2}",
468 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>;
469 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
470 (ins VR128:$src1, VR128:$src2),
471 "movhlps\t{$src2, $dst|$dst, $src2}",
473 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
476 let Predicates = [HasAVX] in {
478 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
479 (VMOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
480 def : Pat<(X86Movlhps VR128:$src1,
481 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
482 (VMOVHPSrm VR128:$src1, addr:$src2)>;
483 def : Pat<(X86Movlhps VR128:$src1,
484 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
485 (VMOVHPSrm VR128:$src1, addr:$src2)>;
488 let AddedComplexity = 20 in {
489 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
490 (VMOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
491 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
492 (VMOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
494 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
495 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
496 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
498 def : Pat<(v4f32 (X86Movlhps VR128:$src1, VR128:$src2)),
499 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
500 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
501 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
502 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
503 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
506 let AddedComplexity = 20 in {
507 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
508 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
509 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
511 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
512 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
513 (VMOVHLPSrr VR128:$src1, VR128:$src1)>;
514 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
515 (VMOVHLPSrr VR128:$src1, VR128:$src1)>;
519 let Predicates = [HasSSE1] in {
521 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
522 (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
523 def : Pat<(X86Movlhps VR128:$src1,
524 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
525 (MOVHPSrm VR128:$src1, addr:$src2)>;
526 def : Pat<(X86Movlhps VR128:$src1,
527 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
528 (MOVHPSrm VR128:$src1, addr:$src2)>;
531 let AddedComplexity = 20 in {
532 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
533 (MOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
534 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
535 (MOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
537 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
538 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
539 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
541 def : Pat<(v4f32 (X86Movlhps VR128:$src1, VR128:$src2)),
542 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
543 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
544 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
545 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
546 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
549 let AddedComplexity = 20 in {
550 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
551 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
552 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
554 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
555 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
556 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
557 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
558 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
562 //===----------------------------------------------------------------------===//
563 // SSE 1 & 2 - Conversion Instructions
564 //===----------------------------------------------------------------------===//
566 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
567 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
569 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
570 [(set DstRC:$dst, (OpNode SrcRC:$src))]>;
571 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
572 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>;
575 multiclass sse12_cvt_s_np<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
576 X86MemOperand x86memop, string asm> {
577 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
579 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
583 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
584 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
585 string asm, Domain d> {
586 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
587 [(set DstRC:$dst, (OpNode SrcRC:$src))], d>;
588 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
589 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))], d>;
592 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
593 X86MemOperand x86memop, string asm> {
594 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
595 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
596 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
597 (ins DstRC:$src1, x86memop:$src),
598 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
601 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
602 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX;
603 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
604 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
606 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
607 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
608 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
609 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD,
612 // The assembler can recognize rr 64-bit instructions by seeing a rxx
613 // register, but the same isn't true when only using memory operands,
614 // provide other assembly "l" and "q" forms to address this explicitly
615 // where appropriate to do so.
616 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss">, XS,
618 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">, XS,
620 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">, XD,
622 defm VCVTSI2SDL : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">, XD,
624 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">, XD,
627 let Predicates = [HasAVX] in {
628 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
629 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
630 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
631 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
632 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
633 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
634 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
635 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
637 def : Pat<(f32 (sint_to_fp GR32:$src)),
638 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
639 def : Pat<(f32 (sint_to_fp GR64:$src)),
640 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
641 def : Pat<(f64 (sint_to_fp GR32:$src)),
642 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
643 def : Pat<(f64 (sint_to_fp GR64:$src)),
644 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
647 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
648 "cvttss2si\t{$src, $dst|$dst, $src}">, XS;
649 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
650 "cvttss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
651 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
652 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD;
653 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
654 "cvttsd2si{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
655 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
656 "cvtsi2ss\t{$src, $dst|$dst, $src}">, XS;
657 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
658 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
659 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
660 "cvtsi2sd\t{$src, $dst|$dst, $src}">, XD;
661 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
662 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
664 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
665 // and/or XMM operand(s).
667 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
668 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
670 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
671 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
672 [(set DstRC:$dst, (Int SrcRC:$src))]>;
673 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
674 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
675 [(set DstRC:$dst, (Int (ld_frag addr:$src)))]>;
678 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
679 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
680 PatFrag ld_frag, string asm, bit Is2Addr = 1> {
681 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
683 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
684 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
685 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))]>;
686 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
687 (ins DstRC:$src1, x86memop:$src2),
689 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
690 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
691 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))]>;
694 defm Int_VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
695 f128mem, load, "cvtsd2si">, XD, VEX;
696 defm Int_VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
697 int_x86_sse2_cvtsd2si64, f128mem, load, "cvtsd2si">,
700 // FIXME: The asm matcher has a hack to ignore instructions with _Int and Int_
701 // Get rid of this hack or rename the intrinsics, there are several
702 // intructions that only match with the intrinsic form, why create duplicates
703 // to let them be recognized by the assembler?
704 defm VCVTSD2SI_alt : sse12_cvt_s_np<0x2D, FR64, GR32, f64mem,
705 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
706 defm VCVTSD2SI64 : sse12_cvt_s_np<0x2D, FR64, GR64, f64mem,
707 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX, VEX_W;
708 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
709 f128mem, load, "cvtsd2si{l}">, XD;
710 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
711 f128mem, load, "cvtsd2si{q}">, XD, REX_W;
714 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
715 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss", 0>, XS, VEX_4V;
716 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
717 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss", 0>, XS, VEX_4V,
719 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
720 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd", 0>, XD, VEX_4V;
721 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
722 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd", 0>, XD,
725 let Constraints = "$src1 = $dst" in {
726 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
727 int_x86_sse_cvtsi2ss, i32mem, loadi32,
729 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
730 int_x86_sse_cvtsi642ss, i64mem, loadi64,
731 "cvtsi2ss{q}">, XS, REX_W;
732 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
733 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
735 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
736 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
737 "cvtsi2sd">, XD, REX_W;
742 // Aliases for intrinsics
743 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
744 f32mem, load, "cvttss2si">, XS, VEX;
745 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
746 int_x86_sse_cvttss2si64, f32mem, load,
747 "cvttss2si">, XS, VEX, VEX_W;
748 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
749 f128mem, load, "cvttsd2si">, XD, VEX;
750 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
751 int_x86_sse2_cvttsd2si64, f128mem, load,
752 "cvttsd2si">, XD, VEX, VEX_W;
753 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
754 f32mem, load, "cvttss2si">, XS;
755 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
756 int_x86_sse_cvttss2si64, f32mem, load,
757 "cvttss2si{q}">, XS, REX_W;
758 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
759 f128mem, load, "cvttsd2si">, XD;
760 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
761 int_x86_sse2_cvttsd2si64, f128mem, load,
762 "cvttsd2si{q}">, XD, REX_W;
764 let Pattern = []<dag> in {
765 defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load,
766 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS, VEX;
767 defm VCVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load,
768 "cvtss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
770 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load,
771 "cvtdq2ps\t{$src, $dst|$dst, $src}",
772 SSEPackedSingle>, TB, VEX;
773 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, undef, i256mem, load,
774 "cvtdq2ps\t{$src, $dst|$dst, $src}",
775 SSEPackedSingle>, TB, VEX;
778 let Pattern = []<dag> in {
779 defm CVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load /*dummy*/,
780 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS;
781 defm CVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load /*dummy*/,
782 "cvtss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
783 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load /*dummy*/,
784 "cvtdq2ps\t{$src, $dst|$dst, $src}",
785 SSEPackedSingle>, TB; /* PD SSE3 form is avaiable */
788 let Predicates = [HasSSE1] in {
789 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
790 (CVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
791 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
792 (CVTSS2SIrm addr:$src)>;
793 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
794 (CVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
795 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
796 (CVTSS2SI64rm addr:$src)>;
799 let Predicates = [HasAVX] in {
800 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
801 (VCVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
802 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
803 (VCVTSS2SIrm addr:$src)>;
804 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
805 (VCVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
806 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
807 (VCVTSS2SI64rm addr:$src)>;
812 // Convert scalar double to scalar single
813 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
814 (ins FR64:$src1, FR64:$src2),
815 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
817 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
818 (ins FR64:$src1, f64mem:$src2),
819 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
820 []>, XD, Requires<[HasAVX, OptForSize]>, VEX_4V;
821 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
824 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
825 "cvtsd2ss\t{$src, $dst|$dst, $src}",
826 [(set FR32:$dst, (fround FR64:$src))]>;
827 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
828 "cvtsd2ss\t{$src, $dst|$dst, $src}",
829 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
830 Requires<[HasSSE2, OptForSize]>;
832 defm Int_VCVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
833 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss", 0>,
835 let Constraints = "$src1 = $dst" in
836 defm Int_CVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
837 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss">, XS;
839 // Convert scalar single to scalar double
840 // SSE2 instructions with XS prefix
841 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
842 (ins FR32:$src1, FR32:$src2),
843 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
844 []>, XS, Requires<[HasAVX]>, VEX_4V;
845 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
846 (ins FR32:$src1, f32mem:$src2),
847 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
848 []>, XS, VEX_4V, Requires<[HasAVX, OptForSize]>;
850 let Predicates = [HasAVX] in {
851 def : Pat<(f64 (fextend FR32:$src)),
852 (VCVTSS2SDrr FR32:$src, FR32:$src)>;
853 def : Pat<(fextend (loadf32 addr:$src)),
854 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
855 def : Pat<(extloadf32 addr:$src),
856 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
859 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
860 "cvtss2sd\t{$src, $dst|$dst, $src}",
861 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
863 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
864 "cvtss2sd\t{$src, $dst|$dst, $src}",
865 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
866 Requires<[HasSSE2, OptForSize]>;
868 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
869 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
870 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
871 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
872 VR128:$src2))]>, XS, VEX_4V,
874 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
875 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
876 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
877 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
878 (load addr:$src2)))]>, XS, VEX_4V,
880 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
881 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
882 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
883 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
884 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
887 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
888 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
889 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
890 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
891 (load addr:$src2)))]>, XS,
895 def : Pat<(extloadf32 addr:$src),
896 (CVTSS2SDrr (MOVSSrm addr:$src))>,
897 Requires<[HasSSE2, OptForSpeed]>;
899 // Convert doubleword to packed single/double fp
900 // SSE2 instructions without OpSize prefix
901 def Int_VCVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
902 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
903 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
904 TB, VEX, Requires<[HasAVX]>;
905 def Int_VCVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
906 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
907 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
908 (bitconvert (memopv2i64 addr:$src))))]>,
909 TB, VEX, Requires<[HasAVX]>;
910 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
911 "cvtdq2ps\t{$src, $dst|$dst, $src}",
912 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
913 TB, Requires<[HasSSE2]>;
914 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
915 "cvtdq2ps\t{$src, $dst|$dst, $src}",
916 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
917 (bitconvert (memopv2i64 addr:$src))))]>,
918 TB, Requires<[HasSSE2]>;
920 // FIXME: why the non-intrinsic version is described as SSE3?
921 // SSE2 instructions with XS prefix
922 def Int_VCVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
923 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
924 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
925 XS, VEX, Requires<[HasAVX]>;
926 def Int_VCVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
927 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
928 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
929 (bitconvert (memopv2i64 addr:$src))))]>,
930 XS, VEX, Requires<[HasAVX]>;
931 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
932 "cvtdq2pd\t{$src, $dst|$dst, $src}",
933 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
934 XS, Requires<[HasSSE2]>;
935 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
936 "cvtdq2pd\t{$src, $dst|$dst, $src}",
937 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
938 (bitconvert (memopv2i64 addr:$src))))]>,
939 XS, Requires<[HasSSE2]>;
942 // Convert packed single/double fp to doubleword
943 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
944 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
945 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
946 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
947 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
948 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
949 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
950 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
951 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
952 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
953 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
954 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
956 def Int_VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
957 "cvtps2dq\t{$src, $dst|$dst, $src}",
958 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>,
960 def Int_VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst),
962 "cvtps2dq\t{$src, $dst|$dst, $src}",
963 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
964 (memop addr:$src)))]>, VEX;
965 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
966 "cvtps2dq\t{$src, $dst|$dst, $src}",
967 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
968 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
969 "cvtps2dq\t{$src, $dst|$dst, $src}",
970 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
971 (memop addr:$src)))]>;
973 // SSE2 packed instructions with XD prefix
974 def Int_VCVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
975 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
976 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
977 XD, VEX, Requires<[HasAVX]>;
978 def Int_VCVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
979 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
980 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
981 (memop addr:$src)))]>,
982 XD, VEX, Requires<[HasAVX]>;
983 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
984 "cvtpd2dq\t{$src, $dst|$dst, $src}",
985 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
986 XD, Requires<[HasSSE2]>;
987 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
988 "cvtpd2dq\t{$src, $dst|$dst, $src}",
989 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
990 (memop addr:$src)))]>,
991 XD, Requires<[HasSSE2]>;
994 // Convert with truncation packed single/double fp to doubleword
995 // SSE2 packed instructions with XS prefix
996 def VCVTTPS2DQrr : VSSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
997 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
998 def VCVTTPS2DQrm : VSSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
999 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1000 def VCVTTPS2DQYrr : VSSI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1001 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1002 def VCVTTPS2DQYrm : VSSI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1003 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1004 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1005 "cvttps2dq\t{$src, $dst|$dst, $src}",
1007 (int_x86_sse2_cvttps2dq VR128:$src))]>;
1008 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1009 "cvttps2dq\t{$src, $dst|$dst, $src}",
1011 (int_x86_sse2_cvttps2dq (memop addr:$src)))]>;
1013 def Int_VCVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1014 "vcvttps2dq\t{$src, $dst|$dst, $src}",
1016 (int_x86_sse2_cvttps2dq VR128:$src))]>,
1017 XS, VEX, Requires<[HasAVX]>;
1018 def Int_VCVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1019 "vcvttps2dq\t{$src, $dst|$dst, $src}",
1020 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1021 (memop addr:$src)))]>,
1022 XS, VEX, Requires<[HasAVX]>;
1024 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1025 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
1026 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1027 (CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
1029 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1030 (Int_VCVTDQ2PSrr VR128:$src)>, Requires<[HasAVX]>;
1031 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1032 (VCVTTPS2DQrr VR128:$src)>, Requires<[HasAVX]>;
1033 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
1034 (VCVTDQ2PSYrr VR256:$src)>, Requires<[HasAVX]>;
1035 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
1036 (VCVTTPS2DQYrr VR256:$src)>, Requires<[HasAVX]>;
1038 def Int_VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst),
1040 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1041 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>,
1043 def Int_VCVTTPD2DQrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst),
1045 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1046 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1047 (memop addr:$src)))]>, VEX;
1048 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1049 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1050 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1051 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1052 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1053 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1054 (memop addr:$src)))]>;
1056 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1057 // register, but the same isn't true when using memory operands instead.
1058 // Provide other assembly rr and rm forms to address this explicitly.
1059 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1060 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1061 def VCVTTPD2DQXrYr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1062 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1065 def VCVTTPD2DQXrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1066 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
1067 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1068 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
1071 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1072 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
1073 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1074 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
1076 // Convert packed single to packed double
1077 let Predicates = [HasAVX] in {
1078 // SSE2 instructions without OpSize prefix
1079 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1080 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
1081 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1082 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
1083 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
1084 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
1085 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
1086 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
1088 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1089 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1090 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1091 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1093 def Int_VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1094 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1095 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1096 VEX, Requires<[HasAVX]>;
1097 def Int_VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1098 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1099 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1100 (load addr:$src)))]>,
1101 VEX, Requires<[HasAVX]>;
1102 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1103 "cvtps2pd\t{$src, $dst|$dst, $src}",
1104 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1105 TB, Requires<[HasSSE2]>;
1106 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1107 "cvtps2pd\t{$src, $dst|$dst, $src}",
1108 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1109 (load addr:$src)))]>,
1110 TB, Requires<[HasSSE2]>;
1112 // Convert packed double to packed single
1113 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1114 // register, but the same isn't true when using memory operands instead.
1115 // Provide other assembly rr and rm forms to address this explicitly.
1116 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1117 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1118 def VCVTPD2PSXrYr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1119 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1122 def VCVTPD2PSXrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1123 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
1124 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1125 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
1128 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1129 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX;
1130 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1131 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
1132 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1133 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1134 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1135 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1138 def Int_VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1139 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1140 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1141 def Int_VCVTPD2PSrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst),
1143 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1144 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1145 (memop addr:$src)))]>;
1146 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1147 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1148 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1149 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1150 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1151 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1152 (memop addr:$src)))]>;
1154 // AVX 256-bit register conversion intrinsics
1155 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
1156 // whenever possible to avoid declaring two versions of each one.
1157 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
1158 (VCVTDQ2PSYrr VR256:$src)>;
1159 def : Pat<(int_x86_avx_cvtdq2_ps_256 (memopv8i32 addr:$src)),
1160 (VCVTDQ2PSYrm addr:$src)>;
1162 def : Pat<(int_x86_avx_cvt_pd2_ps_256 VR256:$src),
1163 (VCVTPD2PSYrr VR256:$src)>;
1164 def : Pat<(int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)),
1165 (VCVTPD2PSYrm addr:$src)>;
1167 def : Pat<(int_x86_avx_cvt_ps2dq_256 VR256:$src),
1168 (VCVTPS2DQYrr VR256:$src)>;
1169 def : Pat<(int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)),
1170 (VCVTPS2DQYrm addr:$src)>;
1172 def : Pat<(int_x86_avx_cvt_ps2_pd_256 VR128:$src),
1173 (VCVTPS2PDYrr VR128:$src)>;
1174 def : Pat<(int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)),
1175 (VCVTPS2PDYrm addr:$src)>;
1177 def : Pat<(int_x86_avx_cvtt_pd2dq_256 VR256:$src),
1178 (VCVTTPD2DQYrr VR256:$src)>;
1179 def : Pat<(int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)),
1180 (VCVTTPD2DQYrm addr:$src)>;
1182 def : Pat<(int_x86_avx_cvtt_ps2dq_256 VR256:$src),
1183 (VCVTTPS2DQYrr VR256:$src)>;
1184 def : Pat<(int_x86_avx_cvtt_ps2dq_256 (memopv8f32 addr:$src)),
1185 (VCVTTPS2DQYrm addr:$src)>;
1187 // Match fround and fextend for 128/256-bit conversions
1188 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
1189 (VCVTPD2PSYrr VR256:$src)>;
1190 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
1191 (VCVTPD2PSYrm addr:$src)>;
1193 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
1194 (VCVTPS2PDYrr VR128:$src)>;
1195 def : Pat<(v4f64 (fextend (loadv4f32 addr:$src))),
1196 (VCVTPS2PDYrm addr:$src)>;
1198 //===----------------------------------------------------------------------===//
1199 // SSE 1 & 2 - Compare Instructions
1200 //===----------------------------------------------------------------------===//
1202 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
1203 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1204 string asm, string asm_alt> {
1205 let isAsmParserOnly = 1 in {
1206 def rr : SIi8<0xC2, MRMSrcReg,
1207 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc),
1210 def rm : SIi8<0xC2, MRMSrcMem,
1211 (outs RC:$dst), (ins RC:$src1, x86memop:$src, SSECC:$cc),
1215 // Accept explicit immediate argument form instead of comparison code.
1216 def rr_alt : SIi8<0xC2, MRMSrcReg,
1217 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
1220 def rm_alt : SIi8<0xC2, MRMSrcMem,
1221 (outs RC:$dst), (ins RC:$src1, x86memop:$src, i8imm:$src2),
1225 let neverHasSideEffects = 1 in {
1226 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem,
1227 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1228 "cmpss\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1230 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem,
1231 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1232 "cmpsd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1236 let Constraints = "$src1 = $dst" in {
1237 def CMPSSrr : SIi8<0xC2, MRMSrcReg,
1238 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, SSECC:$cc),
1239 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
1240 [(set FR32:$dst, (X86cmpss (f32 FR32:$src1), FR32:$src2, imm:$cc))]>, XS;
1241 def CMPSSrm : SIi8<0xC2, MRMSrcMem,
1242 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2, SSECC:$cc),
1243 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
1244 [(set FR32:$dst, (X86cmpss (f32 FR32:$src1), (loadf32 addr:$src2), imm:$cc))]>, XS;
1245 def CMPSDrr : SIi8<0xC2, MRMSrcReg,
1246 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, SSECC:$cc),
1247 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
1248 [(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), FR64:$src2, imm:$cc))]>, XD;
1249 def CMPSDrm : SIi8<0xC2, MRMSrcMem,
1250 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src2, SSECC:$cc),
1251 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
1252 [(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), (loadf64 addr:$src2), imm:$cc))]>, XD;
1254 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1255 def CMPSSrr_alt : SIi8<0xC2, MRMSrcReg,
1256 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, i8imm:$src2),
1257 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XS;
1258 def CMPSSrm_alt : SIi8<0xC2, MRMSrcMem,
1259 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, i8imm:$src2),
1260 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XS;
1261 def CMPSDrr_alt : SIi8<0xC2, MRMSrcReg,
1262 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, i8imm:$src2),
1263 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XD;
1264 def CMPSDrm_alt : SIi8<0xC2, MRMSrcMem,
1265 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, i8imm:$src2),
1266 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XD;
1269 multiclass sse12_cmp_scalar_int<RegisterClass RC, X86MemOperand x86memop,
1270 Intrinsic Int, string asm> {
1271 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
1272 (ins VR128:$src1, VR128:$src, SSECC:$cc), asm,
1273 [(set VR128:$dst, (Int VR128:$src1,
1274 VR128:$src, imm:$cc))]>;
1275 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
1276 (ins VR128:$src1, f32mem:$src, SSECC:$cc), asm,
1277 [(set VR128:$dst, (Int VR128:$src1,
1278 (load addr:$src), imm:$cc))]>;
1281 // Aliases to match intrinsics which expect XMM operand(s).
1282 defm Int_VCMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
1283 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}">,
1285 defm Int_VCMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
1286 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}">,
1288 let Constraints = "$src1 = $dst" in {
1289 defm Int_CMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
1290 "cmp${cc}ss\t{$src, $dst|$dst, $src}">, XS;
1291 defm Int_CMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
1292 "cmp${cc}sd\t{$src, $dst|$dst, $src}">, XD;
1296 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
1297 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
1298 ValueType vt, X86MemOperand x86memop,
1299 PatFrag ld_frag, string OpcodeStr, Domain d> {
1300 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
1301 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1302 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))], d>;
1303 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
1304 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1305 [(set EFLAGS, (OpNode (vt RC:$src1),
1306 (ld_frag addr:$src2)))], d>;
1309 let Defs = [EFLAGS] in {
1310 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
1311 "ucomiss", SSEPackedSingle>, VEX;
1312 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
1313 "ucomisd", SSEPackedDouble>, OpSize, VEX;
1314 let Pattern = []<dag> in {
1315 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
1316 "comiss", SSEPackedSingle>, VEX;
1317 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
1318 "comisd", SSEPackedDouble>, OpSize, VEX;
1321 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
1322 load, "ucomiss", SSEPackedSingle>, VEX;
1323 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
1324 load, "ucomisd", SSEPackedDouble>, OpSize, VEX;
1326 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
1327 load, "comiss", SSEPackedSingle>, VEX;
1328 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
1329 load, "comisd", SSEPackedDouble>, OpSize, VEX;
1330 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
1331 "ucomiss", SSEPackedSingle>, TB;
1332 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
1333 "ucomisd", SSEPackedDouble>, TB, OpSize;
1335 let Pattern = []<dag> in {
1336 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
1337 "comiss", SSEPackedSingle>, TB;
1338 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
1339 "comisd", SSEPackedDouble>, TB, OpSize;
1342 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
1343 load, "ucomiss", SSEPackedSingle>, TB;
1344 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
1345 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
1347 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
1348 "comiss", SSEPackedSingle>, TB;
1349 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
1350 "comisd", SSEPackedDouble>, TB, OpSize;
1351 } // Defs = [EFLAGS]
1353 // sse12_cmp_packed - sse 1 & 2 compared packed instructions
1354 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
1355 Intrinsic Int, string asm, string asm_alt,
1357 let isAsmParserOnly = 1 in {
1358 def rri : PIi8<0xC2, MRMSrcReg,
1359 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc), asm,
1360 [(set RC:$dst, (Int RC:$src1, RC:$src, imm:$cc))], d>;
1361 def rmi : PIi8<0xC2, MRMSrcMem,
1362 (outs RC:$dst), (ins RC:$src1, f128mem:$src, SSECC:$cc), asm,
1363 [(set RC:$dst, (Int RC:$src1, (memop addr:$src), imm:$cc))], d>;
1366 // Accept explicit immediate argument form instead of comparison code.
1367 def rri_alt : PIi8<0xC2, MRMSrcReg,
1368 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
1370 def rmi_alt : PIi8<0xC2, MRMSrcMem,
1371 (outs RC:$dst), (ins RC:$src1, f128mem:$src, i8imm:$src2),
1375 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
1376 "cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
1377 "cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1378 SSEPackedSingle>, VEX_4V;
1379 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
1380 "cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
1381 "cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1382 SSEPackedDouble>, OpSize, VEX_4V;
1383 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_ps_256,
1384 "cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
1385 "cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1386 SSEPackedSingle>, VEX_4V;
1387 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_pd_256,
1388 "cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
1389 "cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1390 SSEPackedDouble>, OpSize, VEX_4V;
1391 let Constraints = "$src1 = $dst" in {
1392 defm CMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
1393 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
1394 "cmpps\t{$src2, $src, $dst|$dst, $src, $src2}",
1395 SSEPackedSingle>, TB;
1396 defm CMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
1397 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1398 "cmppd\t{$src2, $src, $dst|$dst, $src, $src2}",
1399 SSEPackedDouble>, TB, OpSize;
1402 let Predicates = [HasSSE1] in {
1403 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
1404 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
1405 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
1406 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
1409 let Predicates = [HasSSE2] in {
1410 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1411 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1412 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1413 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1416 let Predicates = [HasAVX] in {
1417 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
1418 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
1419 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
1420 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
1421 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1422 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1423 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1424 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1426 def : Pat<(v8i32 (X86cmpps (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
1427 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
1428 def : Pat<(v8i32 (X86cmpps (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
1429 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
1430 def : Pat<(v4i64 (X86cmppd (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
1431 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
1432 def : Pat<(v4i64 (X86cmppd (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
1433 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
1436 //===----------------------------------------------------------------------===//
1437 // SSE 1 & 2 - Shuffle Instructions
1438 //===----------------------------------------------------------------------===//
1440 /// sse12_shuffle - sse 1 & 2 shuffle instructions
1441 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
1442 ValueType vt, string asm, PatFrag mem_frag,
1443 Domain d, bit IsConvertibleToThreeAddress = 0> {
1444 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
1445 (ins RC:$src1, f128mem:$src2, i8imm:$src3), asm,
1446 [(set RC:$dst, (vt (shufp:$src3
1447 RC:$src1, (mem_frag addr:$src2))))], d>;
1448 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
1449 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
1450 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
1452 (vt (shufp:$src3 RC:$src1, RC:$src2)))], d>;
1455 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
1456 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
1457 memopv4f32, SSEPackedSingle>, TB, VEX_4V;
1458 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
1459 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
1460 memopv8f32, SSEPackedSingle>, TB, VEX_4V;
1461 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
1462 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
1463 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
1464 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
1465 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
1466 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
1468 let Constraints = "$src1 = $dst" in {
1469 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
1470 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1471 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
1473 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
1474 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1475 memopv2f64, SSEPackedDouble>, TB, OpSize;
1478 //===----------------------------------------------------------------------===//
1479 // SSE 1 & 2 - Unpack Instructions
1480 //===----------------------------------------------------------------------===//
1482 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
1483 multiclass sse12_unpack_interleave<bits<8> opc, PatFrag OpNode, ValueType vt,
1484 PatFrag mem_frag, RegisterClass RC,
1485 X86MemOperand x86memop, string asm,
1487 def rr : PI<opc, MRMSrcReg,
1488 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1490 (vt (OpNode RC:$src1, RC:$src2)))], d>;
1491 def rm : PI<opc, MRMSrcMem,
1492 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1494 (vt (OpNode RC:$src1,
1495 (mem_frag addr:$src2))))], d>;
1498 let AddedComplexity = 10 in {
1499 defm VUNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
1500 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1501 SSEPackedSingle>, VEX_4V;
1502 defm VUNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
1503 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1504 SSEPackedDouble>, OpSize, VEX_4V;
1505 defm VUNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
1506 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1507 SSEPackedSingle>, VEX_4V;
1508 defm VUNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
1509 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1510 SSEPackedDouble>, OpSize, VEX_4V;
1512 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, unpckh, v8f32, memopv8f32,
1513 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1514 SSEPackedSingle>, VEX_4V;
1515 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, unpckh, v4f64, memopv4f64,
1516 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1517 SSEPackedDouble>, OpSize, VEX_4V;
1518 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, unpckl, v8f32, memopv8f32,
1519 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1520 SSEPackedSingle>, VEX_4V;
1521 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, unpckl, v4f64, memopv4f64,
1522 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1523 SSEPackedDouble>, OpSize, VEX_4V;
1525 let Constraints = "$src1 = $dst" in {
1526 defm UNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
1527 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
1528 SSEPackedSingle>, TB;
1529 defm UNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
1530 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
1531 SSEPackedDouble>, TB, OpSize;
1532 defm UNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
1533 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
1534 SSEPackedSingle>, TB;
1535 defm UNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
1536 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
1537 SSEPackedDouble>, TB, OpSize;
1538 } // Constraints = "$src1 = $dst"
1539 } // AddedComplexity
1541 //===----------------------------------------------------------------------===//
1542 // SSE 1 & 2 - Extract Floating-Point Sign mask
1543 //===----------------------------------------------------------------------===//
1545 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
1546 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
1548 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
1549 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1550 [(set GR32:$dst, (Int RC:$src))], d>;
1551 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
1552 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>, REX_W;
1555 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
1556 SSEPackedSingle>, TB;
1557 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
1558 SSEPackedDouble>, TB, OpSize;
1560 def : Pat<(i32 (X86fgetsign FR32:$src)),
1561 (MOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
1562 sub_ss))>, Requires<[HasSSE1]>;
1563 def : Pat<(i64 (X86fgetsign FR32:$src)),
1564 (MOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
1565 sub_ss))>, Requires<[HasSSE1]>;
1566 def : Pat<(i32 (X86fgetsign FR64:$src)),
1567 (MOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
1568 sub_sd))>, Requires<[HasSSE2]>;
1569 def : Pat<(i64 (X86fgetsign FR64:$src)),
1570 (MOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
1571 sub_sd))>, Requires<[HasSSE2]>;
1573 let Predicates = [HasAVX] in {
1574 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
1575 "movmskps", SSEPackedSingle>, TB, VEX;
1576 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
1577 "movmskpd", SSEPackedDouble>, TB, OpSize,
1579 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
1580 "movmskps", SSEPackedSingle>, TB, VEX;
1581 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
1582 "movmskpd", SSEPackedDouble>, TB, OpSize,
1585 def : Pat<(i32 (X86fgetsign FR32:$src)),
1586 (VMOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
1588 def : Pat<(i64 (X86fgetsign FR32:$src)),
1589 (VMOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
1591 def : Pat<(i32 (X86fgetsign FR64:$src)),
1592 (VMOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
1594 def : Pat<(i64 (X86fgetsign FR64:$src)),
1595 (VMOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
1599 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1600 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX;
1601 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1602 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize,
1604 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
1605 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX;
1606 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
1607 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize,
1611 //===----------------------------------------------------------------------===//
1612 // SSE 1 & 2 - Misc aliasing of packed SSE 1 & 2 instructions
1613 //===----------------------------------------------------------------------===//
1615 // Aliases of packed SSE1 & SSE2 instructions for scalar use. These all have
1616 // names that start with 'Fs'.
1618 // Alias instructions that map fld0 to pxor for sse.
1619 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
1620 canFoldAsLoad = 1 in {
1621 // FIXME: Set encoding to pseudo!
1622 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
1623 [(set FR32:$dst, fp32imm0)]>,
1624 Requires<[HasSSE1]>, TB, OpSize;
1625 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
1626 [(set FR64:$dst, fpimm0)]>,
1627 Requires<[HasSSE2]>, TB, OpSize;
1628 def VFsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
1629 [(set FR32:$dst, fp32imm0)]>,
1630 Requires<[HasAVX]>, TB, OpSize, VEX_4V;
1631 def VFsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
1632 [(set FR64:$dst, fpimm0)]>,
1633 Requires<[HasAVX]>, TB, OpSize, VEX_4V;
1636 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
1637 // bits are disregarded.
1638 let neverHasSideEffects = 1 in {
1639 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1640 "movaps\t{$src, $dst|$dst, $src}", []>;
1641 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1642 "movapd\t{$src, $dst|$dst, $src}", []>;
1645 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1646 // bits are disregarded.
1647 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1648 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1649 "movaps\t{$src, $dst|$dst, $src}",
1650 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
1651 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1652 "movapd\t{$src, $dst|$dst, $src}",
1653 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1656 //===----------------------------------------------------------------------===//
1657 // SSE 1 & 2 - Logical Instructions
1658 //===----------------------------------------------------------------------===//
1660 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
1662 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
1664 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
1665 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, 0>, TB, VEX_4V;
1667 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
1668 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, 0>, TB, OpSize, VEX_4V;
1670 let Constraints = "$src1 = $dst" in {
1671 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
1672 f32, f128mem, memopfsf32, SSEPackedSingle>, TB;
1674 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
1675 f64, f128mem, memopfsf64, SSEPackedDouble>, TB, OpSize;
1679 // Alias bitwise logical operations using SSE logical ops on packed FP values.
1680 let mayLoad = 0 in {
1681 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand>;
1682 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for>;
1683 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>;
1686 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
1687 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef>;
1689 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
1691 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
1693 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
1694 // are all promoted to v2i64, and the patterns are covered by the int
1695 // version. This is needed in SSE only, because v2i64 isn't supported on
1696 // SSE1, but only on SSE2.
1697 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
1698 !strconcat(OpcodeStr, "ps"), f128mem, [],
1699 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
1700 (memopv2i64 addr:$src2)))], 0>, TB, VEX_4V;
1702 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
1703 !strconcat(OpcodeStr, "pd"), f128mem,
1704 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1705 (bc_v2i64 (v2f64 VR128:$src2))))],
1706 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1707 (memopv2i64 addr:$src2)))], 0>,
1709 let Constraints = "$src1 = $dst" in {
1710 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
1711 !strconcat(OpcodeStr, "ps"), f128mem,
1712 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
1713 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
1714 (memopv2i64 addr:$src2)))]>, TB;
1716 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
1717 !strconcat(OpcodeStr, "pd"), f128mem,
1718 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1719 (bc_v2i64 (v2f64 VR128:$src2))))],
1720 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1721 (memopv2i64 addr:$src2)))]>, TB, OpSize;
1725 /// sse12_fp_packed_logical_y - AVX 256-bit SSE 1 & 2 logical ops forms
1727 multiclass sse12_fp_packed_logical_y<bits<8> opc, string OpcodeStr,
1729 defm PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
1730 !strconcat(OpcodeStr, "ps"), f256mem,
1731 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
1732 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
1733 (memopv4i64 addr:$src2)))], 0>, TB, VEX_4V;
1735 defm PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
1736 !strconcat(OpcodeStr, "pd"), f256mem,
1737 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
1738 (bc_v4i64 (v4f64 VR256:$src2))))],
1739 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
1740 (memopv4i64 addr:$src2)))], 0>,
1744 // AVX 256-bit packed logical ops forms
1745 defm VAND : sse12_fp_packed_logical_y<0x54, "and", and>;
1746 defm VOR : sse12_fp_packed_logical_y<0x56, "or", or>;
1747 defm VXOR : sse12_fp_packed_logical_y<0x57, "xor", xor>;
1748 defm VANDN : sse12_fp_packed_logical_y<0x55, "andn", X86andnp>;
1750 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
1751 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
1752 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
1753 let isCommutable = 0 in
1754 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
1756 //===----------------------------------------------------------------------===//
1757 // SSE 1 & 2 - Arithmetic Instructions
1758 //===----------------------------------------------------------------------===//
1760 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
1763 /// In addition, we also have a special variant of the scalar form here to
1764 /// represent the associated intrinsic operation. This form is unlike the
1765 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
1766 /// and leaves the top elements unmodified (therefore these cannot be commuted).
1768 /// These three forms can each be reg+reg or reg+mem.
1771 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
1773 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
1775 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
1776 OpNode, FR32, f32mem, Is2Addr>, XS;
1777 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
1778 OpNode, FR64, f64mem, Is2Addr>, XD;
1781 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
1783 let mayLoad = 0 in {
1784 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
1785 v4f32, f128mem, memopv4f32, SSEPackedSingle, Is2Addr>, TB;
1786 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
1787 v2f64, f128mem, memopv2f64, SSEPackedDouble, Is2Addr>, TB, OpSize;
1791 multiclass basic_sse12_fp_binop_p_y<bits<8> opc, string OpcodeStr,
1793 let mayLoad = 0 in {
1794 defm PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR256,
1795 v8f32, f256mem, memopv8f32, SSEPackedSingle, 0>, TB;
1796 defm PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR256,
1797 v4f64, f256mem, memopv4f64, SSEPackedDouble, 0>, TB, OpSize;
1801 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
1803 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1804 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32, Is2Addr>, XS;
1805 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1806 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64, Is2Addr>, XD;
1809 multiclass basic_sse12_fp_binop_p_int<bits<8> opc, string OpcodeStr,
1811 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
1812 !strconcat(OpcodeStr, "ps"), "sse", "_ps", f128mem, memopv4f32,
1813 SSEPackedSingle, Is2Addr>, TB;
1815 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
1816 !strconcat(OpcodeStr, "pd"), "sse2", "_pd", f128mem, memopv2f64,
1817 SSEPackedDouble, Is2Addr>, TB, OpSize;
1820 multiclass basic_sse12_fp_binop_p_y_int<bits<8> opc, string OpcodeStr> {
1821 defm PSY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
1822 !strconcat(OpcodeStr, "ps"), "avx", "_ps_256", f256mem, memopv8f32,
1823 SSEPackedSingle, 0>, TB;
1825 defm PDY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
1826 !strconcat(OpcodeStr, "pd"), "avx", "_pd_256", f256mem, memopv4f64,
1827 SSEPackedDouble, 0>, TB, OpSize;
1830 // Binary Arithmetic instructions
1831 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, 0>,
1832 basic_sse12_fp_binop_s_int<0x58, "add", 0>,
1833 basic_sse12_fp_binop_p<0x58, "add", fadd, 0>,
1834 basic_sse12_fp_binop_p_y<0x58, "add", fadd>, VEX_4V;
1835 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, 0>,
1836 basic_sse12_fp_binop_s_int<0x59, "mul", 0>,
1837 basic_sse12_fp_binop_p<0x59, "mul", fmul, 0>,
1838 basic_sse12_fp_binop_p_y<0x59, "mul", fmul>, VEX_4V;
1840 let isCommutable = 0 in {
1841 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, 0>,
1842 basic_sse12_fp_binop_s_int<0x5C, "sub", 0>,
1843 basic_sse12_fp_binop_p<0x5C, "sub", fsub, 0>,
1844 basic_sse12_fp_binop_p_y<0x5C, "sub", fsub>, VEX_4V;
1845 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, 0>,
1846 basic_sse12_fp_binop_s_int<0x5E, "div", 0>,
1847 basic_sse12_fp_binop_p<0x5E, "div", fdiv, 0>,
1848 basic_sse12_fp_binop_p_y<0x5E, "div", fdiv>, VEX_4V;
1849 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, 0>,
1850 basic_sse12_fp_binop_s_int<0x5F, "max", 0>,
1851 basic_sse12_fp_binop_p<0x5F, "max", X86fmax, 0>,
1852 basic_sse12_fp_binop_p_int<0x5F, "max", 0>,
1853 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax>,
1854 basic_sse12_fp_binop_p_y_int<0x5F, "max">, VEX_4V;
1855 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, 0>,
1856 basic_sse12_fp_binop_s_int<0x5D, "min", 0>,
1857 basic_sse12_fp_binop_p<0x5D, "min", X86fmin, 0>,
1858 basic_sse12_fp_binop_p_int<0x5D, "min", 0>,
1859 basic_sse12_fp_binop_p_y_int<0x5D, "min">,
1860 basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin>, VEX_4V;
1863 let Constraints = "$src1 = $dst" in {
1864 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd>,
1865 basic_sse12_fp_binop_p<0x58, "add", fadd>,
1866 basic_sse12_fp_binop_s_int<0x58, "add">;
1867 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul>,
1868 basic_sse12_fp_binop_p<0x59, "mul", fmul>,
1869 basic_sse12_fp_binop_s_int<0x59, "mul">;
1871 let isCommutable = 0 in {
1872 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub>,
1873 basic_sse12_fp_binop_p<0x5C, "sub", fsub>,
1874 basic_sse12_fp_binop_s_int<0x5C, "sub">;
1875 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv>,
1876 basic_sse12_fp_binop_p<0x5E, "div", fdiv>,
1877 basic_sse12_fp_binop_s_int<0x5E, "div">;
1878 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax>,
1879 basic_sse12_fp_binop_p<0x5F, "max", X86fmax>,
1880 basic_sse12_fp_binop_s_int<0x5F, "max">,
1881 basic_sse12_fp_binop_p_int<0x5F, "max">;
1882 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin>,
1883 basic_sse12_fp_binop_p<0x5D, "min", X86fmin>,
1884 basic_sse12_fp_binop_s_int<0x5D, "min">,
1885 basic_sse12_fp_binop_p_int<0x5D, "min">;
1890 /// In addition, we also have a special variant of the scalar form here to
1891 /// represent the associated intrinsic operation. This form is unlike the
1892 /// plain scalar form, in that it takes an entire vector (instead of a
1893 /// scalar) and leaves the top elements undefined.
1895 /// And, we have a special variant form for a full-vector intrinsic form.
1897 /// sse1_fp_unop_s - SSE1 unops in scalar form.
1898 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
1899 SDNode OpNode, Intrinsic F32Int> {
1900 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1901 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1902 [(set FR32:$dst, (OpNode FR32:$src))]>;
1903 // For scalar unary operations, fold a load into the operation
1904 // only in OptForSize mode. It eliminates an instruction, but it also
1905 // eliminates a whole-register clobber (the load), so it introduces a
1906 // partial register update condition.
1907 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
1908 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1909 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
1910 Requires<[HasSSE1, OptForSize]>;
1911 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1912 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1913 [(set VR128:$dst, (F32Int VR128:$src))]>;
1914 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
1915 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1916 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
1919 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
1920 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
1921 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
1922 !strconcat(OpcodeStr,
1923 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1924 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1,f32mem:$src2),
1925 !strconcat(OpcodeStr,
1926 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1927 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
1928 (ins ssmem:$src1, VR128:$src2),
1929 !strconcat(OpcodeStr,
1930 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1933 /// sse1_fp_unop_p - SSE1 unops in packed form.
1934 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1935 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1936 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1937 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]>;
1938 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1939 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1940 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
1943 /// sse1_fp_unop_p_y - AVX 256-bit SSE1 unops in packed form.
1944 multiclass sse1_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1945 def PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1946 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1947 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))]>;
1948 def PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1949 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1950 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))]>;
1953 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
1954 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
1955 Intrinsic V4F32Int> {
1956 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1957 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1958 [(set VR128:$dst, (V4F32Int VR128:$src))]>;
1959 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1960 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1961 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
1964 /// sse1_fp_unop_p_y_int - AVX 256-bit intrinsics unops in packed forms.
1965 multiclass sse1_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
1966 Intrinsic V4F32Int> {
1967 def PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1968 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1969 [(set VR256:$dst, (V4F32Int VR256:$src))]>;
1970 def PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1971 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1972 [(set VR256:$dst, (V4F32Int (memopv8f32 addr:$src)))]>;
1975 /// sse2_fp_unop_s - SSE2 unops in scalar form.
1976 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
1977 SDNode OpNode, Intrinsic F64Int> {
1978 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1979 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1980 [(set FR64:$dst, (OpNode FR64:$src))]>;
1981 // See the comments in sse1_fp_unop_s for why this is OptForSize.
1982 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1983 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1984 [(set FR64:$dst, (OpNode (load addr:$src)))]>, XD,
1985 Requires<[HasSSE2, OptForSize]>;
1986 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1987 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1988 [(set VR128:$dst, (F64Int VR128:$src))]>;
1989 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1990 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1991 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1994 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
1995 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
1996 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1997 !strconcat(OpcodeStr,
1998 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1999 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1,f64mem:$src2),
2000 !strconcat(OpcodeStr,
2001 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2002 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
2003 (ins VR128:$src1, sdmem:$src2),
2004 !strconcat(OpcodeStr,
2005 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2008 /// sse2_fp_unop_p - SSE2 unops in vector forms.
2009 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
2011 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2012 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2013 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]>;
2014 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2015 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2016 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
2019 /// sse2_fp_unop_p_y - AVX SSE2 256-bit unops in vector forms.
2020 multiclass sse2_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2021 def PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2022 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2023 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))]>;
2024 def PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2025 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2026 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))]>;
2029 /// sse2_fp_unop_p_int - SSE2 intrinsic unops in vector forms.
2030 multiclass sse2_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2031 Intrinsic V2F64Int> {
2032 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2033 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2034 [(set VR128:$dst, (V2F64Int VR128:$src))]>;
2035 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2036 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2037 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
2040 /// sse2_fp_unop_p_y_int - AVX 256-bit intrinsic unops in vector forms.
2041 multiclass sse2_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
2042 Intrinsic V2F64Int> {
2043 def PDYr_Int : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2044 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2045 [(set VR256:$dst, (V2F64Int VR256:$src))]>;
2046 def PDYm_Int : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2047 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2048 [(set VR256:$dst, (V2F64Int (memopv4f64 addr:$src)))]>;
2051 let Predicates = [HasAVX] in {
2053 defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt">,
2054 sse2_fp_unop_s_avx<0x51, "vsqrt">, VEX_4V;
2056 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt>,
2057 sse2_fp_unop_p<0x51, "vsqrt", fsqrt>,
2058 sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
2059 sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
2060 sse1_fp_unop_p_int<0x51, "vsqrt", int_x86_sse_sqrt_ps>,
2061 sse2_fp_unop_p_int<0x51, "vsqrt", int_x86_sse2_sqrt_pd>,
2062 sse1_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_ps_256>,
2063 sse2_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_pd_256>,
2066 // Reciprocal approximations. Note that these typically require refinement
2067 // in order to obtain suitable precision.
2068 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt">, VEX_4V;
2069 defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt>,
2070 sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt>,
2071 sse1_fp_unop_p_y_int<0x52, "vrsqrt", int_x86_avx_rsqrt_ps_256>,
2072 sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps>, VEX;
2074 defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp">, VEX_4V;
2075 defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp>,
2076 sse1_fp_unop_p_y<0x53, "vrcp", X86frcp>,
2077 sse1_fp_unop_p_y_int<0x53, "vrcp", int_x86_avx_rcp_ps_256>,
2078 sse1_fp_unop_p_int<0x53, "vrcp", int_x86_sse_rcp_ps>, VEX;
2081 def : Pat<(f32 (fsqrt FR32:$src)),
2082 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
2083 def : Pat<(f32 (fsqrt (load addr:$src))),
2084 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
2085 Requires<[HasAVX, OptForSize]>;
2086 def : Pat<(f64 (fsqrt FR64:$src)),
2087 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
2088 def : Pat<(f64 (fsqrt (load addr:$src))),
2089 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
2090 Requires<[HasAVX, OptForSize]>;
2092 def : Pat<(f32 (X86frsqrt FR32:$src)),
2093 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
2094 def : Pat<(f32 (X86frsqrt (load addr:$src))),
2095 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
2096 Requires<[HasAVX, OptForSize]>;
2098 def : Pat<(f32 (X86frcp FR32:$src)),
2099 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
2100 def : Pat<(f32 (X86frcp (load addr:$src))),
2101 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
2102 Requires<[HasAVX, OptForSize]>;
2104 let Predicates = [HasAVX] in {
2105 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
2106 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
2107 (VSQRTSSr (f32 (IMPLICIT_DEF)),
2108 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
2110 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
2111 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2113 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
2114 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)),
2115 (VSQRTSDr (f64 (IMPLICIT_DEF)),
2116 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd)),
2118 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
2119 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
2121 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
2122 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
2123 (VRSQRTSSr (f32 (IMPLICIT_DEF)),
2124 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
2126 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
2127 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2129 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
2130 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
2131 (VRCPSSr (f32 (IMPLICIT_DEF)),
2132 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
2134 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
2135 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2139 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss>,
2140 sse1_fp_unop_p<0x51, "sqrt", fsqrt>,
2141 sse1_fp_unop_p_int<0x51, "sqrt", int_x86_sse_sqrt_ps>,
2142 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd>,
2143 sse2_fp_unop_p<0x51, "sqrt", fsqrt>,
2144 sse2_fp_unop_p_int<0x51, "sqrt", int_x86_sse2_sqrt_pd>;
2146 // Reciprocal approximations. Note that these typically require refinement
2147 // in order to obtain suitable precision.
2148 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss>,
2149 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt>,
2150 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps>;
2151 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>,
2152 sse1_fp_unop_p<0x53, "rcp", X86frcp>,
2153 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps>;
2155 // There is no f64 version of the reciprocal approximation instructions.
2157 //===----------------------------------------------------------------------===//
2158 // SSE 1 & 2 - Non-temporal stores
2159 //===----------------------------------------------------------------------===//
2161 let AddedComplexity = 400 in { // Prefer non-temporal versions
2162 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
2163 (ins f128mem:$dst, VR128:$src),
2164 "movntps\t{$src, $dst|$dst, $src}",
2165 [(alignednontemporalstore (v4f32 VR128:$src),
2167 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
2168 (ins f128mem:$dst, VR128:$src),
2169 "movntpd\t{$src, $dst|$dst, $src}",
2170 [(alignednontemporalstore (v2f64 VR128:$src),
2172 def VMOVNTDQ_64mr : VPDI<0xE7, MRMDestMem, (outs),
2173 (ins f128mem:$dst, VR128:$src),
2174 "movntdq\t{$src, $dst|$dst, $src}",
2175 [(alignednontemporalstore (v2f64 VR128:$src),
2178 let ExeDomain = SSEPackedInt in
2179 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
2180 (ins f128mem:$dst, VR128:$src),
2181 "movntdq\t{$src, $dst|$dst, $src}",
2182 [(alignednontemporalstore (v4f32 VR128:$src),
2185 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
2186 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
2188 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
2189 (ins f256mem:$dst, VR256:$src),
2190 "movntps\t{$src, $dst|$dst, $src}",
2191 [(alignednontemporalstore (v8f32 VR256:$src),
2193 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
2194 (ins f256mem:$dst, VR256:$src),
2195 "movntpd\t{$src, $dst|$dst, $src}",
2196 [(alignednontemporalstore (v4f64 VR256:$src),
2198 def VMOVNTDQY_64mr : VPDI<0xE7, MRMDestMem, (outs),
2199 (ins f256mem:$dst, VR256:$src),
2200 "movntdq\t{$src, $dst|$dst, $src}",
2201 [(alignednontemporalstore (v4f64 VR256:$src),
2203 let ExeDomain = SSEPackedInt in
2204 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
2205 (ins f256mem:$dst, VR256:$src),
2206 "movntdq\t{$src, $dst|$dst, $src}",
2207 [(alignednontemporalstore (v8f32 VR256:$src),
2211 def : Pat<(int_x86_avx_movnt_dq_256 addr:$dst, VR256:$src),
2212 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
2213 def : Pat<(int_x86_avx_movnt_pd_256 addr:$dst, VR256:$src),
2214 (VMOVNTPDYmr addr:$dst, VR256:$src)>;
2215 def : Pat<(int_x86_avx_movnt_ps_256 addr:$dst, VR256:$src),
2216 (VMOVNTPSYmr addr:$dst, VR256:$src)>;
2218 let AddedComplexity = 400 in { // Prefer non-temporal versions
2219 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2220 "movntps\t{$src, $dst|$dst, $src}",
2221 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
2222 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2223 "movntpd\t{$src, $dst|$dst, $src}",
2224 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
2226 def MOVNTDQ_64mr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2227 "movntdq\t{$src, $dst|$dst, $src}",
2228 [(alignednontemporalstore (v2f64 VR128:$src), addr:$dst)]>;
2230 let ExeDomain = SSEPackedInt in
2231 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2232 "movntdq\t{$src, $dst|$dst, $src}",
2233 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
2235 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
2236 (MOVNTDQmr addr:$dst, VR128:$src)>;
2238 // There is no AVX form for instructions below this point
2239 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2240 "movnti{l}\t{$src, $dst|$dst, $src}",
2241 [(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
2242 TB, Requires<[HasSSE2]>;
2243 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
2244 "movnti{q}\t{$src, $dst|$dst, $src}",
2245 [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
2246 TB, Requires<[HasSSE2]>;
2249 //===----------------------------------------------------------------------===//
2250 // SSE 1 & 2 - Misc Instructions (No AVX form)
2251 //===----------------------------------------------------------------------===//
2253 // Prefetch intrinsic.
2254 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
2255 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))]>;
2256 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
2257 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))]>;
2258 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
2259 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))]>;
2260 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
2261 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))]>;
2263 // Load, store, and memory fence
2264 def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>,
2265 TB, Requires<[HasSSE1]>;
2266 def : Pat<(X86SFence), (SFENCE)>;
2268 // Alias instructions that map zero vector to pxor / xorp* for sse.
2269 // We set canFoldAsLoad because this can be converted to a constant-pool
2270 // load of an all-zeros value if folding it would be beneficial.
2271 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
2272 // JIT implementation, it does not expand the instructions below like
2273 // X86MCInstLower does.
2274 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
2275 isCodeGenOnly = 1 in {
2276 def V_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2277 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
2278 def V_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2279 [(set VR128:$dst, (v2f64 immAllZerosV))]>;
2280 let ExeDomain = SSEPackedInt in
2281 def V_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
2282 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
2285 // The same as done above but for AVX. The 128-bit versions are the
2286 // same, but re-encoded. The 256-bit does not support PI version, and
2287 // doesn't need it because on sandy bridge the register is set to zero
2288 // at the rename stage without using any execution unit, so SET0PSY
2289 // and SET0PDY can be used for vector int instructions without penalty
2290 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
2291 // JIT implementatioan, it does not expand the instructions below like
2292 // X86MCInstLower does.
2293 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
2294 isCodeGenOnly = 1, Predicates = [HasAVX] in {
2295 def AVX_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2296 [(set VR128:$dst, (v4f32 immAllZerosV))]>, VEX_4V;
2297 def AVX_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2298 [(set VR128:$dst, (v2f64 immAllZerosV))]>, VEX_4V;
2299 def AVX_SET0PSY : PSI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
2300 [(set VR256:$dst, (v8f32 immAllZerosV))]>, VEX_4V;
2301 def AVX_SET0PDY : PDI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
2302 [(set VR256:$dst, (v4f64 immAllZerosV))]>, VEX_4V;
2303 let ExeDomain = SSEPackedInt in
2304 def AVX_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
2305 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
2308 def : Pat<(v2i64 immAllZerosV), (V_SET0PI)>;
2309 def : Pat<(v8i16 immAllZerosV), (V_SET0PI)>;
2310 def : Pat<(v16i8 immAllZerosV), (V_SET0PI)>;
2312 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
2313 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
2315 // AVX has no support for 256-bit integer instructions, but since the 128-bit
2316 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
2317 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (AVX_SET0PI), sub_xmm)>;
2318 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
2319 (SUBREG_TO_REG (i32 0), (AVX_SET0PI), sub_xmm)>;
2321 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (AVX_SET0PI), sub_xmm)>;
2322 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
2323 (SUBREG_TO_REG (i64 0), (AVX_SET0PI), sub_xmm)>;
2325 //===----------------------------------------------------------------------===//
2326 // SSE 1 & 2 - Load/Store XCSR register
2327 //===----------------------------------------------------------------------===//
2329 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
2330 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>, VEX;
2331 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
2332 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>, VEX;
2334 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
2335 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
2336 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
2337 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
2339 //===---------------------------------------------------------------------===//
2340 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
2341 //===---------------------------------------------------------------------===//
2343 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2345 let neverHasSideEffects = 1 in {
2346 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2347 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2348 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2349 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2351 def VMOVDQUrr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2352 "movdqu\t{$src, $dst|$dst, $src}", []>, XS, VEX;
2353 def VMOVDQUYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2354 "movdqu\t{$src, $dst|$dst, $src}", []>, XS, VEX;
2356 let canFoldAsLoad = 1, mayLoad = 1 in {
2357 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2358 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2359 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
2360 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2361 let Predicates = [HasAVX] in {
2362 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2363 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2364 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
2365 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2369 let mayStore = 1 in {
2370 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
2371 (ins i128mem:$dst, VR128:$src),
2372 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2373 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
2374 (ins i256mem:$dst, VR256:$src),
2375 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2376 let Predicates = [HasAVX] in {
2377 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2378 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2379 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
2380 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2384 let neverHasSideEffects = 1 in
2385 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2386 "movdqa\t{$src, $dst|$dst, $src}", []>;
2388 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2389 "movdqu\t{$src, $dst|$dst, $src}",
2390 []>, XS, Requires<[HasSSE2]>;
2392 let canFoldAsLoad = 1, mayLoad = 1 in {
2393 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2394 "movdqa\t{$src, $dst|$dst, $src}",
2395 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
2396 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2397 "movdqu\t{$src, $dst|$dst, $src}",
2398 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
2399 XS, Requires<[HasSSE2]>;
2402 let mayStore = 1 in {
2403 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2404 "movdqa\t{$src, $dst|$dst, $src}",
2405 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
2406 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2407 "movdqu\t{$src, $dst|$dst, $src}",
2408 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
2409 XS, Requires<[HasSSE2]>;
2412 // Intrinsic forms of MOVDQU load and store
2413 def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2414 "vmovdqu\t{$src, $dst|$dst, $src}",
2415 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
2416 XS, VEX, Requires<[HasAVX]>;
2418 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2419 "movdqu\t{$src, $dst|$dst, $src}",
2420 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
2421 XS, Requires<[HasSSE2]>;
2423 } // ExeDomain = SSEPackedInt
2425 def : Pat<(int_x86_avx_loadu_dq_256 addr:$src), (VMOVDQUYrm addr:$src)>;
2426 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
2427 (VMOVDQUYmr addr:$dst, VR256:$src)>;
2429 //===---------------------------------------------------------------------===//
2430 // SSE2 - Packed Integer Arithmetic Instructions
2431 //===---------------------------------------------------------------------===//
2433 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2435 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
2436 bit IsCommutable = 0, bit Is2Addr = 1> {
2437 let isCommutable = IsCommutable in
2438 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2439 (ins VR128:$src1, VR128:$src2),
2441 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2442 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2443 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2444 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2445 (ins VR128:$src1, i128mem:$src2),
2447 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2448 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2449 [(set VR128:$dst, (IntId VR128:$src1,
2450 (bitconvert (memopv2i64 addr:$src2))))]>;
2453 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
2454 string OpcodeStr, Intrinsic IntId,
2455 Intrinsic IntId2, bit Is2Addr = 1> {
2456 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2457 (ins VR128:$src1, VR128:$src2),
2459 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2460 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2461 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2462 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2463 (ins VR128:$src1, i128mem:$src2),
2465 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2466 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2467 [(set VR128:$dst, (IntId VR128:$src1,
2468 (bitconvert (memopv2i64 addr:$src2))))]>;
2469 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst),
2470 (ins VR128:$src1, i32i8imm:$src2),
2472 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2473 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2474 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
2477 /// PDI_binop_rm - Simple SSE2 binary operator.
2478 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2479 ValueType OpVT, bit IsCommutable = 0, bit Is2Addr = 1> {
2480 let isCommutable = IsCommutable in
2481 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2482 (ins VR128:$src1, VR128:$src2),
2484 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2485 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2486 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>;
2487 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2488 (ins VR128:$src1, i128mem:$src2),
2490 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2491 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2492 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
2493 (bitconvert (memopv2i64 addr:$src2)))))]>;
2496 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
2498 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
2499 /// to collapse (bitconvert VT to VT) into its operand.
2501 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
2502 bit IsCommutable = 0, bit Is2Addr = 1> {
2503 let isCommutable = IsCommutable in
2504 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2505 (ins VR128:$src1, VR128:$src2),
2507 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2508 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2509 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]>;
2510 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2511 (ins VR128:$src1, i128mem:$src2),
2513 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2514 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2515 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2i64 addr:$src2)))]>;
2518 } // ExeDomain = SSEPackedInt
2520 // 128-bit Integer Arithmetic
2522 let Predicates = [HasAVX] in {
2523 defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, 1, 0 /*3addr*/>, VEX_4V;
2524 defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, 1, 0>, VEX_4V;
2525 defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, 1, 0>, VEX_4V;
2526 defm VPADDQ : PDI_binop_rm_v2i64<0xD4, "vpaddq", add, 1, 0>, VEX_4V;
2527 defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, 1, 0>, VEX_4V;
2528 defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, 0, 0>, VEX_4V;
2529 defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, 0, 0>, VEX_4V;
2530 defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, 0, 0>, VEX_4V;
2531 defm VPSUBQ : PDI_binop_rm_v2i64<0xFB, "vpsubq", sub, 0, 0>, VEX_4V;
2534 defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b, 0, 0>,
2536 defm VPSUBSW : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w, 0, 0>,
2538 defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b, 0, 0>,
2540 defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w, 0, 0>,
2542 defm VPADDSB : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b, 1, 0>,
2544 defm VPADDSW : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w, 1, 0>,
2546 defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b, 1, 0>,
2548 defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w, 1, 0>,
2550 defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w, 1, 0>,
2552 defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w, 1, 0>,
2554 defm VPMULUDQ : PDI_binop_rm_int<0xF4, "vpmuludq", int_x86_sse2_pmulu_dq, 1, 0>,
2556 defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd, 1, 0>,
2558 defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b, 1, 0>,
2560 defm VPAVGW : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w, 1, 0>,
2562 defm VPMINUB : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b, 1, 0>,
2564 defm VPMINSW : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w, 1, 0>,
2566 defm VPMAXUB : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b, 1, 0>,
2568 defm VPMAXSW : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w, 1, 0>,
2570 defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw, 1, 0>,
2574 let Constraints = "$src1 = $dst" in {
2575 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
2576 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
2577 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
2578 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
2579 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
2580 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
2581 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
2582 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
2583 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
2586 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
2587 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
2588 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
2589 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
2590 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
2591 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
2592 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
2593 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
2594 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
2595 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w, 1>;
2596 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
2597 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
2598 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
2599 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
2600 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
2601 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
2602 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
2603 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
2604 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw, 1>;
2606 } // Constraints = "$src1 = $dst"
2608 //===---------------------------------------------------------------------===//
2609 // SSE2 - Packed Integer Logical Instructions
2610 //===---------------------------------------------------------------------===//
2612 let Predicates = [HasAVX] in {
2613 defm VPSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "vpsllw",
2614 int_x86_sse2_psll_w, int_x86_sse2_pslli_w, 0>,
2616 defm VPSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "vpslld",
2617 int_x86_sse2_psll_d, int_x86_sse2_pslli_d, 0>,
2619 defm VPSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "vpsllq",
2620 int_x86_sse2_psll_q, int_x86_sse2_pslli_q, 0>,
2623 defm VPSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "vpsrlw",
2624 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w, 0>,
2626 defm VPSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "vpsrld",
2627 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d, 0>,
2629 defm VPSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "vpsrlq",
2630 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q, 0>,
2633 defm VPSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "vpsraw",
2634 int_x86_sse2_psra_w, int_x86_sse2_psrai_w, 0>,
2636 defm VPSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "vpsrad",
2637 int_x86_sse2_psra_d, int_x86_sse2_psrai_d, 0>,
2640 defm VPAND : PDI_binop_rm_v2i64<0xDB, "vpand", and, 1, 0>, VEX_4V;
2641 defm VPOR : PDI_binop_rm_v2i64<0xEB, "vpor" , or, 1, 0>, VEX_4V;
2642 defm VPXOR : PDI_binop_rm_v2i64<0xEF, "vpxor", xor, 1, 0>, VEX_4V;
2644 let ExeDomain = SSEPackedInt in {
2645 let neverHasSideEffects = 1 in {
2646 // 128-bit logical shifts.
2647 def VPSLLDQri : PDIi8<0x73, MRM7r,
2648 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2649 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2651 def VPSRLDQri : PDIi8<0x73, MRM3r,
2652 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2653 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2655 // PSRADQri doesn't exist in SSE[1-3].
2657 def VPANDNrr : PDI<0xDF, MRMSrcReg,
2658 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2659 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2661 (v2i64 (X86andnp VR128:$src1, VR128:$src2)))]>,VEX_4V;
2663 def VPANDNrm : PDI<0xDF, MRMSrcMem,
2664 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2665 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2666 [(set VR128:$dst, (X86andnp VR128:$src1,
2667 (memopv2i64 addr:$src2)))]>, VEX_4V;
2671 let Constraints = "$src1 = $dst" in {
2672 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
2673 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
2674 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
2675 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
2676 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
2677 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
2679 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
2680 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
2681 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
2682 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
2683 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
2684 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
2686 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
2687 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
2688 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
2689 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
2691 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
2692 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or, 1>;
2693 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
2695 let ExeDomain = SSEPackedInt in {
2696 let neverHasSideEffects = 1 in {
2697 // 128-bit logical shifts.
2698 def PSLLDQri : PDIi8<0x73, MRM7r,
2699 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2700 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
2701 def PSRLDQri : PDIi8<0x73, MRM3r,
2702 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2703 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
2704 // PSRADQri doesn't exist in SSE[1-3].
2706 def PANDNrr : PDI<0xDF, MRMSrcReg,
2707 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2708 "pandn\t{$src2, $dst|$dst, $src2}", []>;
2710 def PANDNrm : PDI<0xDF, MRMSrcMem,
2711 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2712 "pandn\t{$src2, $dst|$dst, $src2}", []>;
2714 } // Constraints = "$src1 = $dst"
2716 let Predicates = [HasAVX] in {
2717 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2718 (v2i64 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2719 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2720 (v2i64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2721 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
2722 (v2i64 (VPSLLDQri VR128:$src1, imm:$src2))>;
2723 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
2724 (v2i64 (VPSRLDQri VR128:$src1, imm:$src2))>;
2725 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
2726 (v2f64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2728 // Shift up / down and insert zero's.
2729 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
2730 (v2i64 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2731 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
2732 (v2i64 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2735 let Predicates = [HasSSE2] in {
2736 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2737 (v2i64 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2738 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2739 (v2i64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2740 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
2741 (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
2742 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
2743 (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
2744 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
2745 (v2f64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2747 // Shift up / down and insert zero's.
2748 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
2749 (v2i64 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2750 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
2751 (v2i64 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2754 //===---------------------------------------------------------------------===//
2755 // SSE2 - Packed Integer Comparison Instructions
2756 //===---------------------------------------------------------------------===//
2758 let Predicates = [HasAVX] in {
2759 defm VPCMPEQB : PDI_binop_rm_int<0x74, "vpcmpeqb", int_x86_sse2_pcmpeq_b, 1,
2761 defm VPCMPEQW : PDI_binop_rm_int<0x75, "vpcmpeqw", int_x86_sse2_pcmpeq_w, 1,
2763 defm VPCMPEQD : PDI_binop_rm_int<0x76, "vpcmpeqd", int_x86_sse2_pcmpeq_d, 1,
2765 defm VPCMPGTB : PDI_binop_rm_int<0x64, "vpcmpgtb", int_x86_sse2_pcmpgt_b, 0,
2767 defm VPCMPGTW : PDI_binop_rm_int<0x65, "vpcmpgtw", int_x86_sse2_pcmpgt_w, 0,
2769 defm VPCMPGTD : PDI_binop_rm_int<0x66, "vpcmpgtd", int_x86_sse2_pcmpgt_d, 0,
2772 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
2773 (VPCMPEQBrr VR128:$src1, VR128:$src2)>;
2774 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
2775 (VPCMPEQBrm VR128:$src1, addr:$src2)>;
2776 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
2777 (VPCMPEQWrr VR128:$src1, VR128:$src2)>;
2778 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
2779 (VPCMPEQWrm VR128:$src1, addr:$src2)>;
2780 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
2781 (VPCMPEQDrr VR128:$src1, VR128:$src2)>;
2782 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
2783 (VPCMPEQDrm VR128:$src1, addr:$src2)>;
2785 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
2786 (VPCMPGTBrr VR128:$src1, VR128:$src2)>;
2787 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
2788 (VPCMPGTBrm VR128:$src1, addr:$src2)>;
2789 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
2790 (VPCMPGTWrr VR128:$src1, VR128:$src2)>;
2791 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
2792 (VPCMPGTWrm VR128:$src1, addr:$src2)>;
2793 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
2794 (VPCMPGTDrr VR128:$src1, VR128:$src2)>;
2795 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
2796 (VPCMPGTDrm VR128:$src1, addr:$src2)>;
2799 let Constraints = "$src1 = $dst" in {
2800 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b, 1>;
2801 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w, 1>;
2802 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d, 1>;
2803 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
2804 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
2805 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
2806 } // Constraints = "$src1 = $dst"
2808 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
2809 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
2810 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
2811 (PCMPEQBrm VR128:$src1, addr:$src2)>;
2812 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
2813 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
2814 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
2815 (PCMPEQWrm VR128:$src1, addr:$src2)>;
2816 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
2817 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
2818 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
2819 (PCMPEQDrm VR128:$src1, addr:$src2)>;
2821 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
2822 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
2823 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
2824 (PCMPGTBrm VR128:$src1, addr:$src2)>;
2825 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
2826 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
2827 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
2828 (PCMPGTWrm VR128:$src1, addr:$src2)>;
2829 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
2830 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
2831 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
2832 (PCMPGTDrm VR128:$src1, addr:$src2)>;
2834 //===---------------------------------------------------------------------===//
2835 // SSE2 - Packed Integer Pack Instructions
2836 //===---------------------------------------------------------------------===//
2838 let Predicates = [HasAVX] in {
2839 defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
2841 defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
2843 defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
2847 let Constraints = "$src1 = $dst" in {
2848 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
2849 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
2850 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
2851 } // Constraints = "$src1 = $dst"
2853 //===---------------------------------------------------------------------===//
2854 // SSE2 - Packed Integer Shuffle Instructions
2855 //===---------------------------------------------------------------------===//
2857 let ExeDomain = SSEPackedInt in {
2858 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, PatFrag pshuf_frag,
2860 def ri : Ii8<0x70, MRMSrcReg,
2861 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2862 !strconcat(OpcodeStr,
2863 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2864 [(set VR128:$dst, (vt (pshuf_frag:$src2 VR128:$src1,
2866 def mi : Ii8<0x70, MRMSrcMem,
2867 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2868 !strconcat(OpcodeStr,
2869 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2870 [(set VR128:$dst, (vt (pshuf_frag:$src2
2871 (bc_frag (memopv2i64 addr:$src1)),
2874 } // ExeDomain = SSEPackedInt
2876 let Predicates = [HasAVX] in {
2877 let AddedComplexity = 5 in
2878 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, pshufd, bc_v4i32>, OpSize,
2881 // SSE2 with ImmT == Imm8 and XS prefix.
2882 defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, pshufhw, bc_v8i16>, XS,
2885 // SSE2 with ImmT == Imm8 and XD prefix.
2886 defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, pshuflw, bc_v8i16>, XD,
2890 let Predicates = [HasSSE2] in {
2891 let AddedComplexity = 5 in
2892 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize;
2894 // SSE2 with ImmT == Imm8 and XS prefix.
2895 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, pshufhw, bc_v8i16>, XS;
2897 // SSE2 with ImmT == Imm8 and XD prefix.
2898 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, pshuflw, bc_v8i16>, XD;
2901 //===---------------------------------------------------------------------===//
2902 // SSE2 - Packed Integer Unpack Instructions
2903 //===---------------------------------------------------------------------===//
2905 let ExeDomain = SSEPackedInt in {
2906 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
2907 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
2908 def rr : PDI<opc, MRMSrcReg,
2909 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2911 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2912 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2913 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))]>;
2914 def rm : PDI<opc, MRMSrcMem,
2915 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2917 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2918 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2919 [(set VR128:$dst, (OpNode VR128:$src1,
2920 (bc_frag (memopv2i64
2924 let Predicates = [HasAVX] in {
2925 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Punpcklbw,
2926 bc_v16i8, 0>, VEX_4V;
2927 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Punpcklwd,
2928 bc_v8i16, 0>, VEX_4V;
2929 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Punpckldq,
2930 bc_v4i32, 0>, VEX_4V;
2932 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2933 /// knew to collapse (bitconvert VT to VT) into its operand.
2934 def VPUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2935 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2936 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2937 [(set VR128:$dst, (v2i64 (X86Punpcklqdq VR128:$src1,
2938 VR128:$src2)))]>, VEX_4V;
2939 def VPUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2940 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2941 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2942 [(set VR128:$dst, (v2i64 (X86Punpcklqdq VR128:$src1,
2943 (memopv2i64 addr:$src2))))]>, VEX_4V;
2945 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Punpckhbw,
2946 bc_v16i8, 0>, VEX_4V;
2947 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Punpckhwd,
2948 bc_v8i16, 0>, VEX_4V;
2949 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Punpckhdq,
2950 bc_v4i32, 0>, VEX_4V;
2952 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2953 /// knew to collapse (bitconvert VT to VT) into its operand.
2954 def VPUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2955 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2956 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2957 [(set VR128:$dst, (v2i64 (X86Punpckhqdq VR128:$src1,
2958 VR128:$src2)))]>, VEX_4V;
2959 def VPUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2960 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2961 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2962 [(set VR128:$dst, (v2i64 (X86Punpckhqdq VR128:$src1,
2963 (memopv2i64 addr:$src2))))]>, VEX_4V;
2966 let Constraints = "$src1 = $dst" in {
2967 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Punpcklbw, bc_v16i8>;
2968 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Punpcklwd, bc_v8i16>;
2969 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Punpckldq, bc_v4i32>;
2971 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2972 /// knew to collapse (bitconvert VT to VT) into its operand.
2973 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2974 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2975 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2977 (v2i64 (X86Punpcklqdq VR128:$src1, VR128:$src2)))]>;
2978 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2979 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2980 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2982 (v2i64 (X86Punpcklqdq VR128:$src1,
2983 (memopv2i64 addr:$src2))))]>;
2985 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Punpckhbw, bc_v16i8>;
2986 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Punpckhwd, bc_v8i16>;
2987 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Punpckhdq, bc_v4i32>;
2989 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2990 /// knew to collapse (bitconvert VT to VT) into its operand.
2991 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2992 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2993 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2995 (v2i64 (X86Punpckhqdq VR128:$src1, VR128:$src2)))]>;
2996 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2997 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2998 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
3000 (v2i64 (X86Punpckhqdq VR128:$src1,
3001 (memopv2i64 addr:$src2))))]>;
3004 } // ExeDomain = SSEPackedInt
3006 //===---------------------------------------------------------------------===//
3007 // SSE2 - Packed Integer Extract and Insert
3008 //===---------------------------------------------------------------------===//
3010 let ExeDomain = SSEPackedInt in {
3011 multiclass sse2_pinsrw<bit Is2Addr = 1> {
3012 def rri : Ii8<0xC4, MRMSrcReg,
3013 (outs VR128:$dst), (ins VR128:$src1,
3014 GR32:$src2, i32i8imm:$src3),
3016 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
3017 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3019 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
3020 def rmi : Ii8<0xC4, MRMSrcMem,
3021 (outs VR128:$dst), (ins VR128:$src1,
3022 i16mem:$src2, i32i8imm:$src3),
3024 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
3025 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3027 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
3032 let Predicates = [HasAVX] in
3033 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
3034 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
3035 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3036 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
3037 imm:$src2))]>, OpSize, VEX;
3038 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
3039 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
3040 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3041 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
3045 let Predicates = [HasAVX] in {
3046 defm VPINSRW : sse2_pinsrw<0>, OpSize, VEX_4V;
3047 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
3048 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
3049 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
3050 []>, OpSize, VEX_4V;
3053 let Constraints = "$src1 = $dst" in
3054 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[HasSSE2]>;
3056 } // ExeDomain = SSEPackedInt
3058 //===---------------------------------------------------------------------===//
3059 // SSE2 - Packed Mask Creation
3060 //===---------------------------------------------------------------------===//
3062 let ExeDomain = SSEPackedInt in {
3064 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
3065 "pmovmskb\t{$src, $dst|$dst, $src}",
3066 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>, VEX;
3067 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
3068 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX;
3069 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
3070 "pmovmskb\t{$src, $dst|$dst, $src}",
3071 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
3073 } // ExeDomain = SSEPackedInt
3075 //===---------------------------------------------------------------------===//
3076 // SSE2 - Conditional Store
3077 //===---------------------------------------------------------------------===//
3079 let ExeDomain = SSEPackedInt in {
3082 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
3083 (ins VR128:$src, VR128:$mask),
3084 "maskmovdqu\t{$mask, $src|$src, $mask}",
3085 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>, VEX;
3087 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
3088 (ins VR128:$src, VR128:$mask),
3089 "maskmovdqu\t{$mask, $src|$src, $mask}",
3090 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>, VEX;
3093 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
3094 "maskmovdqu\t{$mask, $src|$src, $mask}",
3095 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
3097 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
3098 "maskmovdqu\t{$mask, $src|$src, $mask}",
3099 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
3101 } // ExeDomain = SSEPackedInt
3103 //===---------------------------------------------------------------------===//
3104 // SSE2 - Move Doubleword
3105 //===---------------------------------------------------------------------===//
3107 //===---------------------------------------------------------------------===//
3108 // Move Int Doubleword to Packed Double Int
3110 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
3111 "movd\t{$src, $dst|$dst, $src}",
3113 (v4i32 (scalar_to_vector GR32:$src)))]>, VEX;
3114 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3115 "movd\t{$src, $dst|$dst, $src}",
3117 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>,
3119 def VMOV64toPQIrr : VRPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3120 "mov{d|q}\t{$src, $dst|$dst, $src}",
3122 (v2i64 (scalar_to_vector GR64:$src)))]>, VEX;
3123 def VMOV64toSDrr : VRPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
3124 "mov{d|q}\t{$src, $dst|$dst, $src}",
3125 [(set FR64:$dst, (bitconvert GR64:$src))]>, VEX;
3127 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
3128 "movd\t{$src, $dst|$dst, $src}",
3130 (v4i32 (scalar_to_vector GR32:$src)))]>;
3131 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3132 "movd\t{$src, $dst|$dst, $src}",
3134 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
3135 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3136 "mov{d|q}\t{$src, $dst|$dst, $src}",
3138 (v2i64 (scalar_to_vector GR64:$src)))]>;
3139 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
3140 "mov{d|q}\t{$src, $dst|$dst, $src}",
3141 [(set FR64:$dst, (bitconvert GR64:$src))]>;
3143 //===---------------------------------------------------------------------===//
3144 // Move Int Doubleword to Single Scalar
3146 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
3147 "movd\t{$src, $dst|$dst, $src}",
3148 [(set FR32:$dst, (bitconvert GR32:$src))]>, VEX;
3150 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
3151 "movd\t{$src, $dst|$dst, $src}",
3152 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>,
3154 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
3155 "movd\t{$src, $dst|$dst, $src}",
3156 [(set FR32:$dst, (bitconvert GR32:$src))]>;
3158 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
3159 "movd\t{$src, $dst|$dst, $src}",
3160 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
3162 //===---------------------------------------------------------------------===//
3163 // Move Packed Doubleword Int to Packed Double Int
3165 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
3166 "movd\t{$src, $dst|$dst, $src}",
3167 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
3169 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
3170 (ins i32mem:$dst, VR128:$src),
3171 "movd\t{$src, $dst|$dst, $src}",
3172 [(store (i32 (vector_extract (v4i32 VR128:$src),
3173 (iPTR 0))), addr:$dst)]>, VEX;
3174 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
3175 "movd\t{$src, $dst|$dst, $src}",
3176 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
3178 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
3179 "movd\t{$src, $dst|$dst, $src}",
3180 [(store (i32 (vector_extract (v4i32 VR128:$src),
3181 (iPTR 0))), addr:$dst)]>;
3183 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
3184 "mov{d|q}\t{$src, $dst|$dst, $src}",
3185 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
3187 def MOV64toSDrm : S3SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
3188 "movq\t{$src, $dst|$dst, $src}",
3189 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
3191 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
3192 "mov{d|q}\t{$src, $dst|$dst, $src}",
3193 [(set GR64:$dst, (bitconvert FR64:$src))]>;
3194 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
3195 "movq\t{$src, $dst|$dst, $src}",
3196 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
3198 //===---------------------------------------------------------------------===//
3199 // Move Scalar Single to Double Int
3201 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
3202 "movd\t{$src, $dst|$dst, $src}",
3203 [(set GR32:$dst, (bitconvert FR32:$src))]>, VEX;
3204 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
3205 "movd\t{$src, $dst|$dst, $src}",
3206 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>, VEX;
3207 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
3208 "movd\t{$src, $dst|$dst, $src}",
3209 [(set GR32:$dst, (bitconvert FR32:$src))]>;
3210 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
3211 "movd\t{$src, $dst|$dst, $src}",
3212 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
3214 //===---------------------------------------------------------------------===//
3215 // Patterns and instructions to describe movd/movq to XMM register zero-extends
3217 let AddedComplexity = 15 in {
3218 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
3219 "movd\t{$src, $dst|$dst, $src}",
3220 [(set VR128:$dst, (v4i32 (X86vzmovl
3221 (v4i32 (scalar_to_vector GR32:$src)))))]>,
3223 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3224 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
3225 [(set VR128:$dst, (v2i64 (X86vzmovl
3226 (v2i64 (scalar_to_vector GR64:$src)))))]>,
3229 let AddedComplexity = 15 in {
3230 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
3231 "movd\t{$src, $dst|$dst, $src}",
3232 [(set VR128:$dst, (v4i32 (X86vzmovl
3233 (v4i32 (scalar_to_vector GR32:$src)))))]>;
3234 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3235 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
3236 [(set VR128:$dst, (v2i64 (X86vzmovl
3237 (v2i64 (scalar_to_vector GR64:$src)))))]>;
3240 let AddedComplexity = 20 in {
3241 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3242 "movd\t{$src, $dst|$dst, $src}",
3244 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
3245 (loadi32 addr:$src))))))]>,
3247 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3248 "movd\t{$src, $dst|$dst, $src}",
3250 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
3251 (loadi32 addr:$src))))))]>;
3253 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
3254 (MOVZDI2PDIrm addr:$src)>;
3255 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
3256 (MOVZDI2PDIrm addr:$src)>;
3257 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
3258 (MOVZDI2PDIrm addr:$src)>;
3261 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
3262 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
3263 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
3264 (v4i32 (scalar_to_vector GR32:$src)), (i32 0)))),
3265 (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrr GR32:$src), sub_xmm)>;
3266 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
3267 (v2i64 (scalar_to_vector GR64:$src)), (i32 0)))),
3268 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
3270 // These are the correct encodings of the instructions so that we know how to
3271 // read correct assembly, even though we continue to emit the wrong ones for
3272 // compatibility with Darwin's buggy assembler.
3273 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3274 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
3275 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3276 (MOV64toSDrr FR64:$dst, GR64:$src), 0>;
3277 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3278 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
3279 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3280 (MOVSDto64rr GR64:$dst, FR64:$src), 0>;
3281 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3282 (VMOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
3283 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3284 (MOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
3286 //===---------------------------------------------------------------------===//
3287 // SSE2 - Move Quadword
3288 //===---------------------------------------------------------------------===//
3290 //===---------------------------------------------------------------------===//
3291 // Move Quadword Int to Packed Quadword Int
3293 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3294 "vmovq\t{$src, $dst|$dst, $src}",
3296 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
3297 VEX, Requires<[HasAVX]>;
3298 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3299 "movq\t{$src, $dst|$dst, $src}",
3301 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
3302 Requires<[HasSSE2]>; // SSE2 instruction with XS Prefix
3304 //===---------------------------------------------------------------------===//
3305 // Move Packed Quadword Int to Quadword Int
3307 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3308 "movq\t{$src, $dst|$dst, $src}",
3309 [(store (i64 (vector_extract (v2i64 VR128:$src),
3310 (iPTR 0))), addr:$dst)]>, VEX;
3311 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3312 "movq\t{$src, $dst|$dst, $src}",
3313 [(store (i64 (vector_extract (v2i64 VR128:$src),
3314 (iPTR 0))), addr:$dst)]>;
3316 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
3317 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
3319 //===---------------------------------------------------------------------===//
3320 // Store / copy lower 64-bits of a XMM register.
3322 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3323 "movq\t{$src, $dst|$dst, $src}",
3324 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
3325 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3326 "movq\t{$src, $dst|$dst, $src}",
3327 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
3329 let AddedComplexity = 20 in
3330 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3331 "vmovq\t{$src, $dst|$dst, $src}",
3333 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
3334 (loadi64 addr:$src))))))]>,
3335 XS, VEX, Requires<[HasAVX]>;
3337 let AddedComplexity = 20 in {
3338 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3339 "movq\t{$src, $dst|$dst, $src}",
3341 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
3342 (loadi64 addr:$src))))))]>,
3343 XS, Requires<[HasSSE2]>;
3345 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
3346 (MOVZQI2PQIrm addr:$src)>;
3347 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
3348 (MOVZQI2PQIrm addr:$src)>;
3349 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
3352 //===---------------------------------------------------------------------===//
3353 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
3354 // IA32 document. movq xmm1, xmm2 does clear the high bits.
3356 let AddedComplexity = 15 in
3357 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3358 "vmovq\t{$src, $dst|$dst, $src}",
3359 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
3360 XS, VEX, Requires<[HasAVX]>;
3361 let AddedComplexity = 15 in
3362 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3363 "movq\t{$src, $dst|$dst, $src}",
3364 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
3365 XS, Requires<[HasSSE2]>;
3367 let AddedComplexity = 20 in
3368 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3369 "vmovq\t{$src, $dst|$dst, $src}",
3370 [(set VR128:$dst, (v2i64 (X86vzmovl
3371 (loadv2i64 addr:$src))))]>,
3372 XS, VEX, Requires<[HasAVX]>;
3373 let AddedComplexity = 20 in {
3374 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3375 "movq\t{$src, $dst|$dst, $src}",
3376 [(set VR128:$dst, (v2i64 (X86vzmovl
3377 (loadv2i64 addr:$src))))]>,
3378 XS, Requires<[HasSSE2]>;
3380 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
3381 (MOVZPQILo2PQIrm addr:$src)>;
3384 // Instructions to match in the assembler
3385 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3386 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3387 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
3388 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3389 // Recognize "movd" with GR64 destination, but encode as a "movq"
3390 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
3391 "movd\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3393 // Instructions for the disassembler
3394 // xr = XMM register
3397 let Predicates = [HasAVX] in
3398 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3399 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
3400 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3401 "movq\t{$src, $dst|$dst, $src}", []>, XS;
3403 //===---------------------------------------------------------------------===//
3404 // SSE2 - Misc Instructions
3405 //===---------------------------------------------------------------------===//
3408 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3409 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
3410 TB, Requires<[HasSSE2]>;
3412 // Load, store, and memory fence
3413 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3414 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
3415 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3416 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
3417 def : Pat<(X86LFence), (LFENCE)>;
3418 def : Pat<(X86MFence), (MFENCE)>;
3421 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3422 // was introduced with SSE2, it's backward compatible.
3423 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
3425 // Alias instructions that map zero vector to pxor / xorp* for sse.
3426 // We set canFoldAsLoad because this can be converted to a constant-pool
3427 // load of an all-ones value if folding it would be beneficial.
3428 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
3429 // JIT implementation, it does not expand the instructions below like
3430 // X86MCInstLower does.
3431 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
3432 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in
3433 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
3434 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
3435 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
3436 isCodeGenOnly = 1, ExeDomain = SSEPackedInt, Predicates = [HasAVX] in
3437 def AVX_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
3438 [(set VR128:$dst, (v4i32 immAllOnesV))]>, VEX_4V;
3440 //===---------------------------------------------------------------------===//
3441 // SSE3 - Conversion Instructions
3442 //===---------------------------------------------------------------------===//
3444 // Convert Packed Double FP to Packed DW Integers
3445 let Predicates = [HasAVX] in {
3446 // The assembler can recognize rr 256-bit instructions by seeing a ymm
3447 // register, but the same isn't true when using memory operands instead.
3448 // Provide other assembly rr and rm forms to address this explicitly.
3449 def VCVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3450 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
3451 def VCVTPD2DQXrYr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
3452 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
3455 def VCVTPD2DQXrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3456 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
3457 def VCVTPD2DQXrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3458 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
3461 def VCVTPD2DQYrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
3462 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
3463 def VCVTPD2DQYrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
3464 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
3467 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3468 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
3469 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3470 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
3472 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
3473 (VCVTPD2DQYrr VR256:$src)>;
3474 def : Pat<(v4i32 (fp_to_sint (memopv4f64 addr:$src))),
3475 (VCVTPD2DQYrm addr:$src)>;
3477 // Convert Packed DW Integers to Packed Double FP
3478 let Predicates = [HasAVX] in {
3479 def VCVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3480 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3481 def VCVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3482 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3483 def VCVTDQ2PDYrm : S3SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
3484 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3485 def VCVTDQ2PDYrr : S3SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
3486 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3489 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3490 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
3491 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3492 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
3494 // AVX 256-bit register conversion intrinsics
3495 def : Pat<(int_x86_avx_cvtdq2_pd_256 VR128:$src),
3496 (VCVTDQ2PDYrr VR128:$src)>;
3497 def : Pat<(int_x86_avx_cvtdq2_pd_256 (memopv4i32 addr:$src)),
3498 (VCVTDQ2PDYrm addr:$src)>;
3500 def : Pat<(int_x86_avx_cvt_pd2dq_256 VR256:$src),
3501 (VCVTPD2DQYrr VR256:$src)>;
3502 def : Pat<(int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)),
3503 (VCVTPD2DQYrm addr:$src)>;
3505 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
3506 (VCVTDQ2PDYrr VR128:$src)>;
3507 def : Pat<(v4f64 (sint_to_fp (memopv4i32 addr:$src))),
3508 (VCVTDQ2PDYrm addr:$src)>;
3510 //===---------------------------------------------------------------------===//
3511 // SSE3 - Move Instructions
3512 //===---------------------------------------------------------------------===//
3514 //===---------------------------------------------------------------------===//
3515 // Replicate Single FP - MOVSHDUP and MOVSLDUP
3517 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3518 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3519 X86MemOperand x86memop> {
3520 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3521 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3522 [(set RC:$dst, (vt (OpNode RC:$src)))]>;
3523 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3524 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3525 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>;
3528 let Predicates = [HasAVX] in {
3529 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3530 v4f32, VR128, memopv4f32, f128mem>, VEX;
3531 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3532 v4f32, VR128, memopv4f32, f128mem>, VEX;
3533 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3534 v8f32, VR256, memopv8f32, f256mem>, VEX;
3535 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3536 v8f32, VR256, memopv8f32, f256mem>, VEX;
3538 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
3539 memopv4f32, f128mem>;
3540 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
3541 memopv4f32, f128mem>;
3543 let Predicates = [HasSSE3] in {
3544 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
3545 (MOVSHDUPrr VR128:$src)>;
3546 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
3547 (MOVSHDUPrm addr:$src)>;
3548 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
3549 (MOVSLDUPrr VR128:$src)>;
3550 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
3551 (MOVSLDUPrm addr:$src)>;
3554 let Predicates = [HasAVX] in {
3555 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
3556 (VMOVSHDUPrr VR128:$src)>;
3557 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
3558 (VMOVSHDUPrm addr:$src)>;
3559 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
3560 (VMOVSLDUPrr VR128:$src)>;
3561 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
3562 (VMOVSLDUPrm addr:$src)>;
3563 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
3564 (VMOVSHDUPYrr VR256:$src)>;
3565 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (memopv4i64 addr:$src)))),
3566 (VMOVSHDUPYrm addr:$src)>;
3567 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
3568 (VMOVSLDUPYrr VR256:$src)>;
3569 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (memopv4i64 addr:$src)))),
3570 (VMOVSLDUPYrm addr:$src)>;
3573 //===---------------------------------------------------------------------===//
3574 // Replicate Double FP - MOVDDUP
3576 multiclass sse3_replicate_dfp<string OpcodeStr> {
3577 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3578 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3579 [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
3580 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
3581 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3583 (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
3587 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
3588 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3589 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3591 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3592 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3596 let Predicates = [HasAVX] in {
3597 // FIXME: Merge above classes when we have patterns for the ymm version
3598 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
3599 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX;
3601 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
3603 // Move Unaligned Integer
3604 let Predicates = [HasAVX] in {
3605 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3606 "vlddqu\t{$src, $dst|$dst, $src}",
3607 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
3608 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3609 "vlddqu\t{$src, $dst|$dst, $src}",
3610 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>, VEX;
3612 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3613 "lddqu\t{$src, $dst|$dst, $src}",
3614 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
3616 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
3618 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3620 // Several Move patterns
3621 let AddedComplexity = 5 in {
3622 def : Pat<(movddup (memopv2f64 addr:$src), (undef)),
3623 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3624 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
3625 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3626 def : Pat<(movddup (memopv2i64 addr:$src), (undef)),
3627 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3628 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
3629 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3632 //===---------------------------------------------------------------------===//
3633 // SSE3 - Arithmetic
3634 //===---------------------------------------------------------------------===//
3636 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
3637 X86MemOperand x86memop, bit Is2Addr = 1> {
3638 def rr : I<0xD0, MRMSrcReg,
3639 (outs RC:$dst), (ins RC:$src1, RC:$src2),
3641 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3642 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3643 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>;
3644 def rm : I<0xD0, MRMSrcMem,
3645 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3647 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3648 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3649 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))]>;
3652 let Predicates = [HasAVX],
3653 ExeDomain = SSEPackedDouble in {
3654 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
3655 f128mem, 0>, TB, XD, VEX_4V;
3656 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
3657 f128mem, 0>, TB, OpSize, VEX_4V;
3658 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
3659 f256mem, 0>, TB, XD, VEX_4V;
3660 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
3661 f256mem, 0>, TB, OpSize, VEX_4V;
3663 let Constraints = "$src1 = $dst", Predicates = [HasSSE3],
3664 ExeDomain = SSEPackedDouble in {
3665 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
3667 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
3668 f128mem>, TB, OpSize;
3671 //===---------------------------------------------------------------------===//
3672 // SSE3 Instructions
3673 //===---------------------------------------------------------------------===//
3676 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
3677 X86MemOperand x86memop, Intrinsic IntId, bit Is2Addr = 1> {
3678 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
3680 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3681 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3682 [(set RC:$dst, (vt (IntId RC:$src1, RC:$src2)))]>;
3684 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3686 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3687 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3688 [(set RC:$dst, (vt (IntId RC:$src1, (memop addr:$src2))))]>;
3690 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
3691 X86MemOperand x86memop, Intrinsic IntId, bit Is2Addr = 1> {
3692 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
3694 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3695 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3696 [(set RC:$dst, (vt (IntId RC:$src1, RC:$src2)))]>;
3698 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3700 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3701 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3702 [(set RC:$dst, (vt (IntId RC:$src1, (memop addr:$src2))))]>;
3705 let Predicates = [HasAVX] in {
3706 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
3707 int_x86_sse3_hadd_ps, 0>, VEX_4V;
3708 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
3709 int_x86_sse3_hadd_pd, 0>, VEX_4V;
3710 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
3711 int_x86_sse3_hsub_ps, 0>, VEX_4V;
3712 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
3713 int_x86_sse3_hsub_pd, 0>, VEX_4V;
3714 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
3715 int_x86_avx_hadd_ps_256, 0>, VEX_4V;
3716 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
3717 int_x86_avx_hadd_pd_256, 0>, VEX_4V;
3718 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
3719 int_x86_avx_hsub_ps_256, 0>, VEX_4V;
3720 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
3721 int_x86_avx_hsub_pd_256, 0>, VEX_4V;
3724 let Constraints = "$src1 = $dst" in {
3725 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem,
3726 int_x86_sse3_hadd_ps>;
3727 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem,
3728 int_x86_sse3_hadd_pd>;
3729 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem,
3730 int_x86_sse3_hsub_ps>;
3731 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem,
3732 int_x86_sse3_hsub_pd>;
3735 //===---------------------------------------------------------------------===//
3736 // SSSE3 - Packed Absolute Instructions
3737 //===---------------------------------------------------------------------===//
3740 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
3741 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
3742 PatFrag mem_frag128, Intrinsic IntId128> {
3743 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
3745 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3746 [(set VR128:$dst, (IntId128 VR128:$src))]>,
3749 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
3751 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3754 (bitconvert (mem_frag128 addr:$src))))]>, OpSize;
3757 let Predicates = [HasAVX] in {
3758 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb", memopv16i8,
3759 int_x86_ssse3_pabs_b_128>, VEX;
3760 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", memopv8i16,
3761 int_x86_ssse3_pabs_w_128>, VEX;
3762 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd", memopv4i32,
3763 int_x86_ssse3_pabs_d_128>, VEX;
3766 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", memopv16i8,
3767 int_x86_ssse3_pabs_b_128>;
3768 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw", memopv8i16,
3769 int_x86_ssse3_pabs_w_128>;
3770 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", memopv4i32,
3771 int_x86_ssse3_pabs_d_128>;
3773 //===---------------------------------------------------------------------===//
3774 // SSSE3 - Packed Binary Operator Instructions
3775 //===---------------------------------------------------------------------===//
3777 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
3778 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
3779 PatFrag mem_frag128, Intrinsic IntId128,
3781 let isCommutable = 1 in
3782 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
3783 (ins VR128:$src1, VR128:$src2),
3785 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3786 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3787 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3789 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
3790 (ins VR128:$src1, i128mem:$src2),
3792 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3793 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3795 (IntId128 VR128:$src1,
3796 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3799 let Predicates = [HasAVX] in {
3800 let isCommutable = 0 in {
3801 defm VPHADDW : SS3I_binop_rm_int<0x01, "vphaddw", memopv8i16,
3802 int_x86_ssse3_phadd_w_128, 0>, VEX_4V;
3803 defm VPHADDD : SS3I_binop_rm_int<0x02, "vphaddd", memopv4i32,
3804 int_x86_ssse3_phadd_d_128, 0>, VEX_4V;
3805 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw", memopv8i16,
3806 int_x86_ssse3_phadd_sw_128, 0>, VEX_4V;
3807 defm VPHSUBW : SS3I_binop_rm_int<0x05, "vphsubw", memopv8i16,
3808 int_x86_ssse3_phsub_w_128, 0>, VEX_4V;
3809 defm VPHSUBD : SS3I_binop_rm_int<0x06, "vphsubd", memopv4i32,
3810 int_x86_ssse3_phsub_d_128, 0>, VEX_4V;
3811 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw", memopv8i16,
3812 int_x86_ssse3_phsub_sw_128, 0>, VEX_4V;
3813 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw", memopv16i8,
3814 int_x86_ssse3_pmadd_ub_sw_128, 0>, VEX_4V;
3815 defm VPSHUFB : SS3I_binop_rm_int<0x00, "vpshufb", memopv16i8,
3816 int_x86_ssse3_pshuf_b_128, 0>, VEX_4V;
3817 defm VPSIGNB : SS3I_binop_rm_int<0x08, "vpsignb", memopv16i8,
3818 int_x86_ssse3_psign_b_128, 0>, VEX_4V;
3819 defm VPSIGNW : SS3I_binop_rm_int<0x09, "vpsignw", memopv8i16,
3820 int_x86_ssse3_psign_w_128, 0>, VEX_4V;
3821 defm VPSIGND : SS3I_binop_rm_int<0x0A, "vpsignd", memopv4i32,
3822 int_x86_ssse3_psign_d_128, 0>, VEX_4V;
3824 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw", memopv8i16,
3825 int_x86_ssse3_pmul_hr_sw_128, 0>, VEX_4V;
3828 // None of these have i8 immediate fields.
3829 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
3830 let isCommutable = 0 in {
3831 defm PHADDW : SS3I_binop_rm_int<0x01, "phaddw", memopv8i16,
3832 int_x86_ssse3_phadd_w_128>;
3833 defm PHADDD : SS3I_binop_rm_int<0x02, "phaddd", memopv4i32,
3834 int_x86_ssse3_phadd_d_128>;
3835 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw", memopv8i16,
3836 int_x86_ssse3_phadd_sw_128>;
3837 defm PHSUBW : SS3I_binop_rm_int<0x05, "phsubw", memopv8i16,
3838 int_x86_ssse3_phsub_w_128>;
3839 defm PHSUBD : SS3I_binop_rm_int<0x06, "phsubd", memopv4i32,
3840 int_x86_ssse3_phsub_d_128>;
3841 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw", memopv8i16,
3842 int_x86_ssse3_phsub_sw_128>;
3843 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw", memopv16i8,
3844 int_x86_ssse3_pmadd_ub_sw_128>;
3845 defm PSHUFB : SS3I_binop_rm_int<0x00, "pshufb", memopv16i8,
3846 int_x86_ssse3_pshuf_b_128>;
3847 defm PSIGNB : SS3I_binop_rm_int<0x08, "psignb", memopv16i8,
3848 int_x86_ssse3_psign_b_128>;
3849 defm PSIGNW : SS3I_binop_rm_int<0x09, "psignw", memopv8i16,
3850 int_x86_ssse3_psign_w_128>;
3851 defm PSIGND : SS3I_binop_rm_int<0x0A, "psignd", memopv4i32,
3852 int_x86_ssse3_psign_d_128>;
3854 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw", memopv8i16,
3855 int_x86_ssse3_pmul_hr_sw_128>;
3858 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
3859 (PSHUFBrr128 VR128:$src, VR128:$mask)>, Requires<[HasSSSE3]>;
3860 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
3861 (PSHUFBrm128 VR128:$src, addr:$mask)>, Requires<[HasSSSE3]>;
3863 def : Pat<(X86psignb VR128:$src1, VR128:$src2),
3864 (PSIGNBrr128 VR128:$src1, VR128:$src2)>, Requires<[HasSSSE3]>;
3865 def : Pat<(X86psignw VR128:$src1, VR128:$src2),
3866 (PSIGNWrr128 VR128:$src1, VR128:$src2)>, Requires<[HasSSSE3]>;
3867 def : Pat<(X86psignd VR128:$src1, VR128:$src2),
3868 (PSIGNDrr128 VR128:$src1, VR128:$src2)>, Requires<[HasSSSE3]>;
3870 //===---------------------------------------------------------------------===//
3871 // SSSE3 - Packed Align Instruction Patterns
3872 //===---------------------------------------------------------------------===//
3874 multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
3875 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
3876 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3878 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3880 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3882 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
3883 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3885 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3887 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3891 let Predicates = [HasAVX] in
3892 defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
3893 let Constraints = "$src1 = $dst", Predicates = [HasSSSE3] in
3894 defm PALIGN : ssse3_palign<"palignr">;
3896 let Predicates = [HasSSSE3] in {
3897 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
3898 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
3899 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
3900 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
3901 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
3902 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
3903 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
3904 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
3907 let Predicates = [HasAVX] in {
3908 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
3909 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
3910 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
3911 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
3912 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
3913 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
3914 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
3915 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
3918 //===---------------------------------------------------------------------===//
3919 // SSSE3 Misc Instructions
3920 //===---------------------------------------------------------------------===//
3922 // Thread synchronization
3923 let usesCustomInserter = 1 in {
3924 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
3925 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>;
3926 def MWAIT : PseudoI<(outs), (ins GR32:$src1, GR32:$src2),
3927 [(int_x86_sse3_mwait GR32:$src1, GR32:$src2)]>;
3930 let Uses = [EAX, ECX, EDX] in
3931 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", []>, TB,
3932 Requires<[HasSSE3]>;
3933 let Uses = [ECX, EAX] in
3934 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait", []>, TB,
3935 Requires<[HasSSE3]>;
3937 def : InstAlias<"mwait %eax, %ecx", (MWAITrr)>, Requires<[In32BitMode]>;
3938 def : InstAlias<"mwait %rax, %rcx", (MWAITrr)>, Requires<[In64BitMode]>;
3940 def : InstAlias<"monitor %eax, %ecx, %edx", (MONITORrrr)>,
3941 Requires<[In32BitMode]>;
3942 def : InstAlias<"monitor %rax, %rcx, %rdx", (MONITORrrr)>,
3943 Requires<[In64BitMode]>;
3945 //===---------------------------------------------------------------------===//
3946 // Non-Instruction Patterns
3947 //===---------------------------------------------------------------------===//
3949 // extload f32 -> f64. This matches load+fextend because we have a hack in
3950 // the isel (PreprocessForFPConvert) that can introduce loads after dag
3952 // Since these loads aren't folded into the fextend, we have to match it
3954 let Predicates = [HasSSE2] in
3955 def : Pat<(fextend (loadf32 addr:$src)),
3956 (CVTSS2SDrm addr:$src)>;
3958 // Bitcasts between 128-bit vector types. Return the original type since
3959 // no instruction is needed for the conversion
3960 let Predicates = [HasXMMInt] in {
3961 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
3962 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
3963 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
3964 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
3965 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
3966 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
3967 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
3968 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
3969 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
3970 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
3971 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
3972 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
3973 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
3974 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
3975 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
3976 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
3977 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
3978 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
3979 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
3980 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
3981 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
3982 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
3983 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
3984 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
3985 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
3986 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
3987 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
3988 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
3989 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
3990 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
3993 // Bitcasts between 256-bit vector types. Return the original type since
3994 // no instruction is needed for the conversion
3995 let Predicates = [HasAVX] in {
3996 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
3997 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
3998 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
3999 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
4000 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
4001 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
4002 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
4003 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
4004 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
4005 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
4006 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
4007 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
4008 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
4009 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
4010 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
4011 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
4012 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
4013 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
4014 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
4015 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
4016 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
4017 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
4018 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
4019 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
4020 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
4021 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
4022 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
4023 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
4024 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
4025 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
4028 // Move scalar to XMM zero-extended
4029 // movd to XMM register zero-extends
4030 let AddedComplexity = 15 in {
4031 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
4032 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
4033 (MOVSDrr (v2f64 (V_SET0PS)), FR64:$src)>;
4034 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
4035 (MOVSSrr (v4f32 (V_SET0PS)), FR32:$src)>;
4036 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
4037 (MOVSSrr (v4f32 (V_SET0PS)),
4038 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
4039 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
4040 (MOVSSrr (v4i32 (V_SET0PI)),
4041 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
4044 // Splat v2f64 / v2i64
4045 let AddedComplexity = 10 in {
4046 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
4047 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
4048 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
4049 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
4052 // Special unary SHUFPSrri case.
4053 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
4054 (SHUFPSrri VR128:$src1, VR128:$src1,
4055 (SHUFFLE_get_shuf_imm VR128:$src3))>;
4056 let AddedComplexity = 5 in
4057 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
4058 (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
4059 Requires<[HasSSE2]>;
4060 // Special unary SHUFPDrri case.
4061 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
4062 (SHUFPDrri VR128:$src1, VR128:$src1,
4063 (SHUFFLE_get_shuf_imm VR128:$src3))>,
4064 Requires<[HasSSE2]>;
4065 // Special unary SHUFPDrri case.
4066 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
4067 (SHUFPDrri VR128:$src1, VR128:$src1,
4068 (SHUFFLE_get_shuf_imm VR128:$src3))>,
4069 Requires<[HasSSE2]>;
4070 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
4071 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
4072 (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
4073 Requires<[HasSSE2]>;
4075 // Special binary v4i32 shuffle cases with SHUFPS.
4076 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
4077 (SHUFPSrri VR128:$src1, VR128:$src2,
4078 (SHUFFLE_get_shuf_imm VR128:$src3))>,
4079 Requires<[HasSSE2]>;
4080 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)))),
4081 (SHUFPSrmi VR128:$src1, addr:$src2,
4082 (SHUFFLE_get_shuf_imm VR128:$src3))>,
4083 Requires<[HasSSE2]>;
4084 // Special binary v2i64 shuffle cases using SHUFPDrri.
4085 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
4086 (SHUFPDrri VR128:$src1, VR128:$src2,
4087 (SHUFFLE_get_shuf_imm VR128:$src3))>,
4088 Requires<[HasSSE2]>;
4090 let AddedComplexity = 20 in {
4091 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
4092 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
4093 (MOVLPSrm VR128:$src1, addr:$src2)>;
4094 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
4095 (MOVLPDrm VR128:$src1, addr:$src2)>;
4096 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
4097 (MOVLPSrm VR128:$src1, addr:$src2)>;
4098 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
4099 (MOVLPDrm VR128:$src1, addr:$src2)>;
4102 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
4103 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
4104 (MOVLPSmr addr:$src1, VR128:$src2)>;
4105 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
4106 (MOVLPDmr addr:$src1, VR128:$src2)>;
4107 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
4109 (MOVLPSmr addr:$src1, VR128:$src2)>;
4110 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
4111 (MOVLPDmr addr:$src1, VR128:$src2)>;
4113 let AddedComplexity = 15 in {
4114 // Setting the lowest element in the vector.
4115 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
4116 (MOVSSrr (v4i32 VR128:$src1),
4117 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
4118 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
4119 (MOVSDrr (v2i64 VR128:$src1),
4120 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
4122 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
4123 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
4124 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
4125 Requires<[HasSSE2]>;
4126 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
4127 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
4128 Requires<[HasSSE2]>;
4131 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
4132 // fall back to this for SSE1)
4133 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
4134 (SHUFPSrri VR128:$src2, VR128:$src1,
4135 (SHUFFLE_get_shuf_imm VR128:$src3))>;
4137 // Set lowest element and zero upper elements.
4138 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4139 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
4141 // Use movaps / movups for SSE integer load / store (one byte shorter).
4142 // The instructions selected below are then converted to MOVDQA/MOVDQU
4143 // during the SSE domain pass.
4144 let Predicates = [HasSSE1] in {
4145 def : Pat<(alignedloadv4i32 addr:$src),
4146 (MOVAPSrm addr:$src)>;
4147 def : Pat<(loadv4i32 addr:$src),
4148 (MOVUPSrm addr:$src)>;
4149 def : Pat<(alignedloadv2i64 addr:$src),
4150 (MOVAPSrm addr:$src)>;
4151 def : Pat<(loadv2i64 addr:$src),
4152 (MOVUPSrm addr:$src)>;
4154 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
4155 (MOVAPSmr addr:$dst, VR128:$src)>;
4156 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
4157 (MOVAPSmr addr:$dst, VR128:$src)>;
4158 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
4159 (MOVAPSmr addr:$dst, VR128:$src)>;
4160 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
4161 (MOVAPSmr addr:$dst, VR128:$src)>;
4162 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
4163 (MOVUPSmr addr:$dst, VR128:$src)>;
4164 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
4165 (MOVUPSmr addr:$dst, VR128:$src)>;
4166 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
4167 (MOVUPSmr addr:$dst, VR128:$src)>;
4168 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
4169 (MOVUPSmr addr:$dst, VR128:$src)>;
4172 // Use vmovaps/vmovups for AVX integer load/store.
4173 let Predicates = [HasAVX] in {
4174 // 128-bit load/store
4175 def : Pat<(alignedloadv4i32 addr:$src),
4176 (VMOVAPSrm addr:$src)>;
4177 def : Pat<(loadv4i32 addr:$src),
4178 (VMOVUPSrm addr:$src)>;
4179 def : Pat<(alignedloadv2i64 addr:$src),
4180 (VMOVAPSrm addr:$src)>;
4181 def : Pat<(loadv2i64 addr:$src),
4182 (VMOVUPSrm addr:$src)>;
4184 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
4185 (VMOVAPSmr addr:$dst, VR128:$src)>;
4186 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
4187 (VMOVAPSmr addr:$dst, VR128:$src)>;
4188 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
4189 (VMOVAPSmr addr:$dst, VR128:$src)>;
4190 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
4191 (VMOVAPSmr addr:$dst, VR128:$src)>;
4192 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
4193 (VMOVUPSmr addr:$dst, VR128:$src)>;
4194 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
4195 (VMOVUPSmr addr:$dst, VR128:$src)>;
4196 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
4197 (VMOVUPSmr addr:$dst, VR128:$src)>;
4198 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
4199 (VMOVUPSmr addr:$dst, VR128:$src)>;
4201 // 256-bit load/store
4202 def : Pat<(alignedloadv4i64 addr:$src),
4203 (VMOVAPSYrm addr:$src)>;
4204 def : Pat<(loadv4i64 addr:$src),
4205 (VMOVUPSYrm addr:$src)>;
4206 def : Pat<(alignedloadv8i32 addr:$src),
4207 (VMOVAPSYrm addr:$src)>;
4208 def : Pat<(loadv8i32 addr:$src),
4209 (VMOVUPSYrm addr:$src)>;
4210 def : Pat<(alignedstore (v4i64 VR256:$src), addr:$dst),
4211 (VMOVAPSYmr addr:$dst, VR256:$src)>;
4212 def : Pat<(alignedstore (v8i32 VR256:$src), addr:$dst),
4213 (VMOVAPSYmr addr:$dst, VR256:$src)>;
4214 def : Pat<(alignedstore (v16i16 VR256:$src), addr:$dst),
4215 (VMOVAPSYmr addr:$dst, VR256:$src)>;
4216 def : Pat<(alignedstore (v32i8 VR256:$src), addr:$dst),
4217 (VMOVAPSYmr addr:$dst, VR256:$src)>;
4218 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
4219 (VMOVUPSYmr addr:$dst, VR256:$src)>;
4220 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
4221 (VMOVUPSYmr addr:$dst, VR256:$src)>;
4222 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
4223 (VMOVUPSYmr addr:$dst, VR256:$src)>;
4224 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
4225 (VMOVUPSYmr addr:$dst, VR256:$src)>;
4228 //===----------------------------------------------------------------------===//
4229 // SSE4.1 - Packed Move with Sign/Zero Extend
4230 //===----------------------------------------------------------------------===//
4232 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4233 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4234 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4235 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
4237 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4238 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4240 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
4244 let Predicates = [HasAVX] in {
4245 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
4247 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
4249 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
4251 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
4253 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
4255 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
4259 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
4260 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
4261 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
4262 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
4263 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
4264 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
4266 // Common patterns involving scalar load.
4267 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
4268 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
4269 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
4270 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
4272 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
4273 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
4274 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
4275 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
4277 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
4278 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
4279 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
4280 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
4282 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
4283 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
4284 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
4285 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
4287 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
4288 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
4289 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
4290 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
4292 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
4293 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
4294 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
4295 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
4298 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4299 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4300 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4301 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
4303 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4304 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4306 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
4310 let Predicates = [HasAVX] in {
4311 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
4313 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
4315 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
4317 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
4321 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
4322 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
4323 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
4324 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
4326 // Common patterns involving scalar load
4327 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
4328 (PMOVSXBDrm addr:$src)>, Requires<[HasSSE41]>;
4329 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
4330 (PMOVSXWQrm addr:$src)>, Requires<[HasSSE41]>;
4332 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
4333 (PMOVZXBDrm addr:$src)>, Requires<[HasSSE41]>;
4334 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
4335 (PMOVZXWQrm addr:$src)>, Requires<[HasSSE41]>;
4338 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4339 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4340 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4341 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
4343 // Expecting a i16 load any extended to i32 value.
4344 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
4345 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4346 [(set VR128:$dst, (IntId (bitconvert
4347 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
4351 let Predicates = [HasAVX] in {
4352 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
4354 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
4357 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
4358 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
4360 // Common patterns involving scalar load
4361 def : Pat<(int_x86_sse41_pmovsxbq
4362 (bitconvert (v4i32 (X86vzmovl
4363 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
4364 (PMOVSXBQrm addr:$src)>, Requires<[HasSSE41]>;
4366 def : Pat<(int_x86_sse41_pmovzxbq
4367 (bitconvert (v4i32 (X86vzmovl
4368 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
4369 (PMOVZXBQrm addr:$src)>, Requires<[HasSSE41]>;
4371 //===----------------------------------------------------------------------===//
4372 // SSE4.1 - Extract Instructions
4373 //===----------------------------------------------------------------------===//
4375 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
4376 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
4377 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4378 (ins VR128:$src1, i32i8imm:$src2),
4379 !strconcat(OpcodeStr,
4380 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4381 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
4383 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4384 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
4385 !strconcat(OpcodeStr,
4386 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4389 // There's an AssertZext in the way of writing the store pattern
4390 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
4393 let Predicates = [HasAVX] in {
4394 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
4395 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
4396 (ins VR128:$src1, i32i8imm:$src2),
4397 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
4400 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
4403 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
4404 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
4405 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4406 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
4407 !strconcat(OpcodeStr,
4408 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4411 // There's an AssertZext in the way of writing the store pattern
4412 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
4415 let Predicates = [HasAVX] in
4416 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
4418 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
4421 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
4422 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
4423 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4424 (ins VR128:$src1, i32i8imm:$src2),
4425 !strconcat(OpcodeStr,
4426 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4428 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
4429 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4430 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
4431 !strconcat(OpcodeStr,
4432 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4433 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
4434 addr:$dst)]>, OpSize;
4437 let Predicates = [HasAVX] in
4438 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
4440 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
4442 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
4443 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
4444 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
4445 (ins VR128:$src1, i32i8imm:$src2),
4446 !strconcat(OpcodeStr,
4447 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4449 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
4450 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4451 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
4452 !strconcat(OpcodeStr,
4453 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4454 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
4455 addr:$dst)]>, OpSize, REX_W;
4458 let Predicates = [HasAVX] in
4459 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
4461 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
4463 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
4465 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
4466 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4467 (ins VR128:$src1, i32i8imm:$src2),
4468 !strconcat(OpcodeStr,
4469 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4471 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
4473 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4474 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
4475 !strconcat(OpcodeStr,
4476 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4477 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
4478 addr:$dst)]>, OpSize;
4481 let Predicates = [HasAVX] in {
4482 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
4483 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
4484 (ins VR128:$src1, i32i8imm:$src2),
4485 "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
4488 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
4490 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
4491 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
4494 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
4495 Requires<[HasSSE41]>;
4497 //===----------------------------------------------------------------------===//
4498 // SSE4.1 - Insert Instructions
4499 //===----------------------------------------------------------------------===//
4501 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
4502 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4503 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
4505 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4507 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4509 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
4510 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4511 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
4513 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4515 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4517 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
4518 imm:$src3))]>, OpSize;
4521 let Predicates = [HasAVX] in
4522 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
4523 let Constraints = "$src1 = $dst" in
4524 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
4526 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
4527 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4528 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
4530 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4532 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4534 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
4536 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4537 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
4539 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4541 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4543 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
4544 imm:$src3)))]>, OpSize;
4547 let Predicates = [HasAVX] in
4548 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
4549 let Constraints = "$src1 = $dst" in
4550 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
4552 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
4553 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4554 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4556 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4558 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4560 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
4562 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4563 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
4565 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4567 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4569 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
4570 imm:$src3)))]>, OpSize;
4573 let Predicates = [HasAVX] in
4574 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
4575 let Constraints = "$src1 = $dst" in
4576 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
4578 // insertps has a few different modes, there's the first two here below which
4579 // are optimized inserts that won't zero arbitrary elements in the destination
4580 // vector. The next one matches the intrinsic and could zero arbitrary elements
4581 // in the target vector.
4582 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
4583 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4584 (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),
4586 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4588 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4590 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
4592 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4593 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
4595 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4597 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4599 (X86insrtps VR128:$src1,
4600 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
4601 imm:$src3))]>, OpSize;
4604 let Constraints = "$src1 = $dst" in
4605 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
4606 let Predicates = [HasAVX] in
4607 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
4609 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
4610 (VINSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
4612 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
4613 (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
4614 Requires<[HasSSE41]>;
4616 //===----------------------------------------------------------------------===//
4617 // SSE4.1 - Round Instructions
4618 //===----------------------------------------------------------------------===//
4620 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
4621 X86MemOperand x86memop, RegisterClass RC,
4622 PatFrag mem_frag32, PatFrag mem_frag64,
4623 Intrinsic V4F32Int, Intrinsic V2F64Int> {
4624 // Intrinsic operation, reg.
4625 // Vector intrinsic operation, reg
4626 def PSr : SS4AIi8<opcps, MRMSrcReg,
4627 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4628 !strconcat(OpcodeStr,
4629 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4630 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
4633 // Vector intrinsic operation, mem
4634 def PSm : Ii8<opcps, MRMSrcMem,
4635 (outs RC:$dst), (ins f256mem:$src1, i32i8imm:$src2),
4636 !strconcat(OpcodeStr,
4637 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4639 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
4641 Requires<[HasSSE41]>;
4643 // Vector intrinsic operation, reg
4644 def PDr : SS4AIi8<opcpd, MRMSrcReg,
4645 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4646 !strconcat(OpcodeStr,
4647 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4648 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
4651 // Vector intrinsic operation, mem
4652 def PDm : SS4AIi8<opcpd, MRMSrcMem,
4653 (outs RC:$dst), (ins f256mem:$src1, i32i8imm:$src2),
4654 !strconcat(OpcodeStr,
4655 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4657 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
4661 multiclass sse41_fp_unop_rm_avx_p<bits<8> opcps, bits<8> opcpd,
4662 RegisterClass RC, X86MemOperand x86memop, string OpcodeStr> {
4663 // Intrinsic operation, reg.
4664 // Vector intrinsic operation, reg
4665 def PSr_AVX : SS4AIi8<opcps, MRMSrcReg,
4666 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4667 !strconcat(OpcodeStr,
4668 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4671 // Vector intrinsic operation, mem
4672 def PSm_AVX : Ii8<opcps, MRMSrcMem,
4673 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4674 !strconcat(OpcodeStr,
4675 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4676 []>, TA, OpSize, Requires<[HasSSE41]>;
4678 // Vector intrinsic operation, reg
4679 def PDr_AVX : SS4AIi8<opcpd, MRMSrcReg,
4680 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4681 !strconcat(OpcodeStr,
4682 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4685 // Vector intrinsic operation, mem
4686 def PDm_AVX : SS4AIi8<opcpd, MRMSrcMem,
4687 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4688 !strconcat(OpcodeStr,
4689 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4693 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
4696 Intrinsic F64Int, bit Is2Addr = 1> {
4697 // Intrinsic operation, reg.
4698 def SSr : SS4AIi8<opcss, MRMSrcReg,
4699 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4701 !strconcat(OpcodeStr,
4702 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4703 !strconcat(OpcodeStr,
4704 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4705 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
4708 // Intrinsic operation, mem.
4709 def SSm : SS4AIi8<opcss, MRMSrcMem,
4710 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
4712 !strconcat(OpcodeStr,
4713 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4714 !strconcat(OpcodeStr,
4715 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4717 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
4720 // Intrinsic operation, reg.
4721 def SDr : SS4AIi8<opcsd, MRMSrcReg,
4722 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4724 !strconcat(OpcodeStr,
4725 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4726 !strconcat(OpcodeStr,
4727 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4728 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
4731 // Intrinsic operation, mem.
4732 def SDm : SS4AIi8<opcsd, MRMSrcMem,
4733 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
4735 !strconcat(OpcodeStr,
4736 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4737 !strconcat(OpcodeStr,
4738 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4740 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
4744 multiclass sse41_fp_binop_rm_avx_s<bits<8> opcss, bits<8> opcsd,
4746 // Intrinsic operation, reg.
4747 def SSr_AVX : SS4AIi8<opcss, MRMSrcReg,
4748 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4749 !strconcat(OpcodeStr,
4750 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4753 // Intrinsic operation, mem.
4754 def SSm_AVX : SS4AIi8<opcss, MRMSrcMem,
4755 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
4756 !strconcat(OpcodeStr,
4757 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4760 // Intrinsic operation, reg.
4761 def SDr_AVX : SS4AIi8<opcsd, MRMSrcReg,
4762 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4763 !strconcat(OpcodeStr,
4764 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4767 // Intrinsic operation, mem.
4768 def SDm_AVX : SS4AIi8<opcsd, MRMSrcMem,
4769 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
4770 !strconcat(OpcodeStr,
4771 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4775 // FP round - roundss, roundps, roundsd, roundpd
4776 let Predicates = [HasAVX] in {
4778 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
4779 memopv4f32, memopv2f64,
4780 int_x86_sse41_round_ps,
4781 int_x86_sse41_round_pd>, VEX;
4782 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
4783 memopv8f32, memopv4f64,
4784 int_x86_avx_round_ps_256,
4785 int_x86_avx_round_pd_256>, VEX;
4786 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
4787 int_x86_sse41_round_ss,
4788 int_x86_sse41_round_sd, 0>, VEX_4V;
4790 // Instructions for the assembler
4791 defm VROUND : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR128, f128mem, "vround">,
4793 defm VROUNDY : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR256, f256mem, "vround">,
4795 defm VROUND : sse41_fp_binop_rm_avx_s<0x0A, 0x0B, "vround">, VEX_4V;
4798 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
4799 memopv4f32, memopv2f64,
4800 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
4801 let Constraints = "$src1 = $dst" in
4802 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
4803 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
4805 //===----------------------------------------------------------------------===//
4806 // SSE4.1 - Packed Bit Test
4807 //===----------------------------------------------------------------------===//
4809 // ptest instruction we'll lower to this in X86ISelLowering primarily from
4810 // the intel intrinsic that corresponds to this.
4811 let Defs = [EFLAGS], Predicates = [HasAVX] in {
4812 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
4813 "vptest\t{$src2, $src1|$src1, $src2}",
4814 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
4816 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
4817 "vptest\t{$src2, $src1|$src1, $src2}",
4818 [(set EFLAGS,(X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
4821 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
4822 "vptest\t{$src2, $src1|$src1, $src2}",
4823 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
4825 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
4826 "vptest\t{$src2, $src1|$src1, $src2}",
4827 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
4831 let Defs = [EFLAGS] in {
4832 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
4833 "ptest \t{$src2, $src1|$src1, $src2}",
4834 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
4836 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
4837 "ptest \t{$src2, $src1|$src1, $src2}",
4838 [(set EFLAGS, (X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
4842 // The bit test instructions below are AVX only
4843 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
4844 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
4845 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
4846 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
4847 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
4848 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
4849 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
4850 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
4854 let Defs = [EFLAGS], Predicates = [HasAVX] in {
4855 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
4856 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>;
4857 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
4858 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>;
4861 //===----------------------------------------------------------------------===//
4862 // SSE4.1 - Misc Instructions
4863 //===----------------------------------------------------------------------===//
4865 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4866 "popcnt{w}\t{$src, $dst|$dst, $src}",
4867 [(set GR16:$dst, (ctpop GR16:$src))]>, OpSize, XS;
4868 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4869 "popcnt{w}\t{$src, $dst|$dst, $src}",
4870 [(set GR16:$dst, (ctpop (loadi16 addr:$src)))]>, OpSize, XS;
4872 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4873 "popcnt{l}\t{$src, $dst|$dst, $src}",
4874 [(set GR32:$dst, (ctpop GR32:$src))]>, XS;
4875 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4876 "popcnt{l}\t{$src, $dst|$dst, $src}",
4877 [(set GR32:$dst, (ctpop (loadi32 addr:$src)))]>, XS;
4879 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
4880 "popcnt{q}\t{$src, $dst|$dst, $src}",
4881 [(set GR64:$dst, (ctpop GR64:$src))]>, XS;
4882 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
4883 "popcnt{q}\t{$src, $dst|$dst, $src}",
4884 [(set GR64:$dst, (ctpop (loadi64 addr:$src)))]>, XS;
4888 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
4889 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
4890 Intrinsic IntId128> {
4891 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4893 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4894 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
4895 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4897 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4900 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
4903 let Predicates = [HasAVX] in
4904 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
4905 int_x86_sse41_phminposuw>, VEX;
4906 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
4907 int_x86_sse41_phminposuw>;
4909 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
4910 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
4911 Intrinsic IntId128, bit Is2Addr = 1> {
4912 let isCommutable = 1 in
4913 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4914 (ins VR128:$src1, VR128:$src2),
4916 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4917 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4918 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
4919 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4920 (ins VR128:$src1, i128mem:$src2),
4922 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4923 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4925 (IntId128 VR128:$src1,
4926 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
4929 let Predicates = [HasAVX] in {
4930 let isCommutable = 0 in
4931 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
4933 defm VPCMPEQQ : SS41I_binop_rm_int<0x29, "vpcmpeqq", int_x86_sse41_pcmpeqq,
4935 defm VPMINSB : SS41I_binop_rm_int<0x38, "vpminsb", int_x86_sse41_pminsb,
4937 defm VPMINSD : SS41I_binop_rm_int<0x39, "vpminsd", int_x86_sse41_pminsd,
4939 defm VPMINUD : SS41I_binop_rm_int<0x3B, "vpminud", int_x86_sse41_pminud,
4941 defm VPMINUW : SS41I_binop_rm_int<0x3A, "vpminuw", int_x86_sse41_pminuw,
4943 defm VPMAXSB : SS41I_binop_rm_int<0x3C, "vpmaxsb", int_x86_sse41_pmaxsb,
4945 defm VPMAXSD : SS41I_binop_rm_int<0x3D, "vpmaxsd", int_x86_sse41_pmaxsd,
4947 defm VPMAXUD : SS41I_binop_rm_int<0x3F, "vpmaxud", int_x86_sse41_pmaxud,
4949 defm VPMAXUW : SS41I_binop_rm_int<0x3E, "vpmaxuw", int_x86_sse41_pmaxuw,
4951 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
4954 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
4955 (VPCMPEQQrr VR128:$src1, VR128:$src2)>;
4956 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
4957 (VPCMPEQQrm VR128:$src1, addr:$src2)>;
4960 let Constraints = "$src1 = $dst" in {
4961 let isCommutable = 0 in
4962 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
4963 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq", int_x86_sse41_pcmpeqq>;
4964 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb", int_x86_sse41_pminsb>;
4965 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd", int_x86_sse41_pminsd>;
4966 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud", int_x86_sse41_pminud>;
4967 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw", int_x86_sse41_pminuw>;
4968 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb", int_x86_sse41_pmaxsb>;
4969 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd", int_x86_sse41_pmaxsd>;
4970 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud", int_x86_sse41_pmaxud>;
4971 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw", int_x86_sse41_pmaxuw>;
4972 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
4975 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
4976 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
4977 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
4978 (PCMPEQQrm VR128:$src1, addr:$src2)>;
4980 /// SS48I_binop_rm - Simple SSE41 binary operator.
4981 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4982 ValueType OpVT, bit Is2Addr = 1> {
4983 let isCommutable = 1 in
4984 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4985 (ins VR128:$src1, VR128:$src2),
4987 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4988 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4989 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
4991 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4992 (ins VR128:$src1, i128mem:$src2),
4994 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4995 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4996 [(set VR128:$dst, (OpNode VR128:$src1,
4997 (bc_v4i32 (memopv2i64 addr:$src2))))]>,
5001 let Predicates = [HasAVX] in
5002 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, 0>, VEX_4V;
5003 let Constraints = "$src1 = $dst" in
5004 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32>;
5006 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
5007 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
5008 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
5009 X86MemOperand x86memop, bit Is2Addr = 1> {
5010 let isCommutable = 1 in
5011 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
5012 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
5014 !strconcat(OpcodeStr,
5015 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5016 !strconcat(OpcodeStr,
5017 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5018 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
5020 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
5021 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
5023 !strconcat(OpcodeStr,
5024 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5025 !strconcat(OpcodeStr,
5026 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5029 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
5033 let Predicates = [HasAVX] in {
5034 let isCommutable = 0 in {
5035 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
5036 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5037 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
5038 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5039 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
5040 int_x86_avx_blend_ps_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
5041 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
5042 int_x86_avx_blend_pd_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
5043 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
5044 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5045 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
5046 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5048 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
5049 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5050 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
5051 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5052 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
5053 VR256, memopv32i8, i256mem, 0>, VEX_4V;
5056 let Constraints = "$src1 = $dst" in {
5057 let isCommutable = 0 in {
5058 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
5059 VR128, memopv16i8, i128mem>;
5060 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
5061 VR128, memopv16i8, i128mem>;
5062 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
5063 VR128, memopv16i8, i128mem>;
5064 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
5065 VR128, memopv16i8, i128mem>;
5067 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
5068 VR128, memopv16i8, i128mem>;
5069 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
5070 VR128, memopv16i8, i128mem>;
5073 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
5074 let Predicates = [HasAVX] in {
5075 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
5076 RegisterClass RC, X86MemOperand x86memop,
5077 PatFrag mem_frag, Intrinsic IntId> {
5078 def rr : I<opc, MRMSrcReg, (outs RC:$dst),
5079 (ins RC:$src1, RC:$src2, RC:$src3),
5080 !strconcat(OpcodeStr,
5081 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5082 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
5083 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
5085 def rm : I<opc, MRMSrcMem, (outs RC:$dst),
5086 (ins RC:$src1, x86memop:$src2, RC:$src3),
5087 !strconcat(OpcodeStr,
5088 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5090 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
5092 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
5096 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, i128mem,
5097 memopv16i8, int_x86_sse41_blendvpd>;
5098 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, i128mem,
5099 memopv16i8, int_x86_sse41_blendvps>;
5100 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
5101 memopv16i8, int_x86_sse41_pblendvb>;
5102 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, i256mem,
5103 memopv32i8, int_x86_avx_blendv_pd_256>;
5104 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem,
5105 memopv32i8, int_x86_avx_blendv_ps_256>;
5107 /// SS41I_ternary_int - SSE 4.1 ternary operator
5108 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
5109 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5110 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
5111 (ins VR128:$src1, VR128:$src2),
5112 !strconcat(OpcodeStr,
5113 "\t{$src2, $dst|$dst, $src2}"),
5114 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
5117 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
5118 (ins VR128:$src1, i128mem:$src2),
5119 !strconcat(OpcodeStr,
5120 "\t{$src2, $dst|$dst, $src2}"),
5123 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
5127 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
5128 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
5129 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
5131 def : Pat<(X86pblendv VR128:$src1, VR128:$src2, XMM0),
5132 (PBLENDVBrr0 VR128:$src1, VR128:$src2)>;
5134 let Predicates = [HasAVX] in
5135 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5136 "vmovntdqa\t{$src, $dst|$dst, $src}",
5137 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
5139 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5140 "movntdqa\t{$src, $dst|$dst, $src}",
5141 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
5144 //===----------------------------------------------------------------------===//
5145 // SSE4.2 - Compare Instructions
5146 //===----------------------------------------------------------------------===//
5148 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
5149 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
5150 Intrinsic IntId128, bit Is2Addr = 1> {
5151 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
5152 (ins VR128:$src1, VR128:$src2),
5154 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5155 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5156 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5158 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
5159 (ins VR128:$src1, i128mem:$src2),
5161 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5162 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5164 (IntId128 VR128:$src1,
5165 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
5168 let Predicates = [HasAVX] in {
5169 defm VPCMPGTQ : SS42I_binop_rm_int<0x37, "vpcmpgtq", int_x86_sse42_pcmpgtq,
5172 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
5173 (VPCMPGTQrr VR128:$src1, VR128:$src2)>;
5174 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
5175 (VPCMPGTQrm VR128:$src1, addr:$src2)>;
5178 let Constraints = "$src1 = $dst" in
5179 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
5181 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
5182 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
5183 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
5184 (PCMPGTQrm VR128:$src1, addr:$src2)>;
5186 //===----------------------------------------------------------------------===//
5187 // SSE4.2 - String/text Processing Instructions
5188 //===----------------------------------------------------------------------===//
5190 // Packed Compare Implicit Length Strings, Return Mask
5191 multiclass pseudo_pcmpistrm<string asm> {
5192 def REG : PseudoI<(outs VR128:$dst),
5193 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5194 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
5196 def MEM : PseudoI<(outs VR128:$dst),
5197 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5198 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128
5199 VR128:$src1, (load addr:$src2), imm:$src3))]>;
5202 let Defs = [EFLAGS], usesCustomInserter = 1 in {
5203 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[HasSSE42]>;
5204 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
5207 let Defs = [XMM0, EFLAGS], Predicates = [HasAVX] in {
5208 def VPCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
5209 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5210 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
5211 def VPCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
5212 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5213 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
5216 let Defs = [XMM0, EFLAGS] in {
5217 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
5218 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5219 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
5220 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
5221 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5222 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
5225 // Packed Compare Explicit Length Strings, Return Mask
5226 multiclass pseudo_pcmpestrm<string asm> {
5227 def REG : PseudoI<(outs VR128:$dst),
5228 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
5229 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
5230 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
5231 def MEM : PseudoI<(outs VR128:$dst),
5232 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
5233 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
5234 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>;
5237 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
5238 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[HasSSE42]>;
5239 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
5242 let Predicates = [HasAVX],
5243 Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
5244 def VPCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
5245 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
5246 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
5247 def VPCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
5248 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
5249 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
5252 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
5253 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
5254 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
5255 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
5256 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
5257 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
5258 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
5261 // Packed Compare Implicit Length Strings, Return Index
5262 let Defs = [ECX, EFLAGS] in {
5263 multiclass SS42AI_pcmpistri<Intrinsic IntId128, string asm = "pcmpistri"> {
5264 def rr : SS42AI<0x63, MRMSrcReg, (outs),
5265 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5266 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
5267 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
5268 (implicit EFLAGS)]>, OpSize;
5269 def rm : SS42AI<0x63, MRMSrcMem, (outs),
5270 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5271 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
5272 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
5273 (implicit EFLAGS)]>, OpSize;
5277 let Predicates = [HasAVX] in {
5278 defm VPCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128, "vpcmpistri">,
5280 defm VPCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128, "vpcmpistri">,
5282 defm VPCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128, "vpcmpistri">,
5284 defm VPCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128, "vpcmpistri">,
5286 defm VPCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128, "vpcmpistri">,
5288 defm VPCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128, "vpcmpistri">,
5292 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
5293 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
5294 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
5295 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
5296 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
5297 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
5299 // Packed Compare Explicit Length Strings, Return Index
5300 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX] in {
5301 multiclass SS42AI_pcmpestri<Intrinsic IntId128, string asm = "pcmpestri"> {
5302 def rr : SS42AI<0x61, MRMSrcReg, (outs),
5303 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
5304 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
5305 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
5306 (implicit EFLAGS)]>, OpSize;
5307 def rm : SS42AI<0x61, MRMSrcMem, (outs),
5308 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
5309 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
5311 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
5312 (implicit EFLAGS)]>, OpSize;
5316 let Predicates = [HasAVX] in {
5317 defm VPCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128, "vpcmpestri">,
5319 defm VPCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128, "vpcmpestri">,
5321 defm VPCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128, "vpcmpestri">,
5323 defm VPCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128, "vpcmpestri">,
5325 defm VPCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128, "vpcmpestri">,
5327 defm VPCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128, "vpcmpestri">,
5331 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
5332 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
5333 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
5334 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
5335 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
5336 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
5338 //===----------------------------------------------------------------------===//
5339 // SSE4.2 - CRC Instructions
5340 //===----------------------------------------------------------------------===//
5342 // No CRC instructions have AVX equivalents
5344 // crc intrinsic instruction
5345 // This set of instructions are only rm, the only difference is the size
5347 let Constraints = "$src1 = $dst" in {
5348 def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
5349 (ins GR32:$src1, i8mem:$src2),
5350 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5352 (int_x86_sse42_crc32_32_8 GR32:$src1,
5353 (load addr:$src2)))]>;
5354 def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
5355 (ins GR32:$src1, GR8:$src2),
5356 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5358 (int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))]>;
5359 def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
5360 (ins GR32:$src1, i16mem:$src2),
5361 "crc32{w} \t{$src2, $src1|$src1, $src2}",
5363 (int_x86_sse42_crc32_32_16 GR32:$src1,
5364 (load addr:$src2)))]>,
5366 def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
5367 (ins GR32:$src1, GR16:$src2),
5368 "crc32{w} \t{$src2, $src1|$src1, $src2}",
5370 (int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))]>,
5372 def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
5373 (ins GR32:$src1, i32mem:$src2),
5374 "crc32{l} \t{$src2, $src1|$src1, $src2}",
5376 (int_x86_sse42_crc32_32_32 GR32:$src1,
5377 (load addr:$src2)))]>;
5378 def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
5379 (ins GR32:$src1, GR32:$src2),
5380 "crc32{l} \t{$src2, $src1|$src1, $src2}",
5382 (int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))]>;
5383 def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
5384 (ins GR64:$src1, i8mem:$src2),
5385 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5387 (int_x86_sse42_crc32_64_8 GR64:$src1,
5388 (load addr:$src2)))]>,
5390 def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
5391 (ins GR64:$src1, GR8:$src2),
5392 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5394 (int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))]>,
5396 def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
5397 (ins GR64:$src1, i64mem:$src2),
5398 "crc32{q} \t{$src2, $src1|$src1, $src2}",
5400 (int_x86_sse42_crc32_64_64 GR64:$src1,
5401 (load addr:$src2)))]>,
5403 def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
5404 (ins GR64:$src1, GR64:$src2),
5405 "crc32{q} \t{$src2, $src1|$src1, $src2}",
5407 (int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))]>,
5411 //===----------------------------------------------------------------------===//
5412 // AES-NI Instructions
5413 //===----------------------------------------------------------------------===//
5415 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
5416 Intrinsic IntId128, bit Is2Addr = 1> {
5417 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
5418 (ins VR128:$src1, VR128:$src2),
5420 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5421 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5422 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5424 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
5425 (ins VR128:$src1, i128mem:$src2),
5427 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5428 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5430 (IntId128 VR128:$src1,
5431 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
5434 // Perform One Round of an AES Encryption/Decryption Flow
5435 let Predicates = [HasAVX, HasAES] in {
5436 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
5437 int_x86_aesni_aesenc, 0>, VEX_4V;
5438 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
5439 int_x86_aesni_aesenclast, 0>, VEX_4V;
5440 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
5441 int_x86_aesni_aesdec, 0>, VEX_4V;
5442 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
5443 int_x86_aesni_aesdeclast, 0>, VEX_4V;
5446 let Constraints = "$src1 = $dst" in {
5447 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
5448 int_x86_aesni_aesenc>;
5449 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
5450 int_x86_aesni_aesenclast>;
5451 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
5452 int_x86_aesni_aesdec>;
5453 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
5454 int_x86_aesni_aesdeclast>;
5457 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, VR128:$src2)),
5458 (AESENCrr VR128:$src1, VR128:$src2)>;
5459 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, (memop addr:$src2))),
5460 (AESENCrm VR128:$src1, addr:$src2)>;
5461 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, VR128:$src2)),
5462 (AESENCLASTrr VR128:$src1, VR128:$src2)>;
5463 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, (memop addr:$src2))),
5464 (AESENCLASTrm VR128:$src1, addr:$src2)>;
5465 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, VR128:$src2)),
5466 (AESDECrr VR128:$src1, VR128:$src2)>;
5467 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, (memop addr:$src2))),
5468 (AESDECrm VR128:$src1, addr:$src2)>;
5469 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, VR128:$src2)),
5470 (AESDECLASTrr VR128:$src1, VR128:$src2)>;
5471 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, (memop addr:$src2))),
5472 (AESDECLASTrm VR128:$src1, addr:$src2)>;
5474 // Perform the AES InvMixColumn Transformation
5475 let Predicates = [HasAVX, HasAES] in {
5476 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
5478 "vaesimc\t{$src1, $dst|$dst, $src1}",
5480 (int_x86_aesni_aesimc VR128:$src1))]>,
5482 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
5483 (ins i128mem:$src1),
5484 "vaesimc\t{$src1, $dst|$dst, $src1}",
5486 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
5489 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
5491 "aesimc\t{$src1, $dst|$dst, $src1}",
5493 (int_x86_aesni_aesimc VR128:$src1))]>,
5495 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
5496 (ins i128mem:$src1),
5497 "aesimc\t{$src1, $dst|$dst, $src1}",
5499 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
5502 // AES Round Key Generation Assist
5503 let Predicates = [HasAVX, HasAES] in {
5504 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
5505 (ins VR128:$src1, i8imm:$src2),
5506 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5508 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
5510 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
5511 (ins i128mem:$src1, i8imm:$src2),
5512 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5514 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
5518 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
5519 (ins VR128:$src1, i8imm:$src2),
5520 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5522 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
5524 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
5525 (ins i128mem:$src1, i8imm:$src2),
5526 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5528 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
5532 //===----------------------------------------------------------------------===//
5533 // CLMUL Instructions
5534 //===----------------------------------------------------------------------===//
5536 // Carry-less Multiplication instructions
5537 let Constraints = "$src1 = $dst" in {
5538 def PCLMULQDQrr : CLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
5539 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5540 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
5543 def PCLMULQDQrm : CLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
5544 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5545 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
5549 // AVX carry-less Multiplication instructions
5550 def VPCLMULQDQrr : AVXCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
5551 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5552 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5555 def VPCLMULQDQrm : AVXCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
5556 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5557 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5561 multiclass pclmul_alias<string asm, int immop> {
5562 def : InstAlias<!strconcat("pclmul", asm,
5563 "dq {$src, $dst|$dst, $src}"),
5564 (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
5566 def : InstAlias<!strconcat("pclmul", asm,
5567 "dq {$src, $dst|$dst, $src}"),
5568 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
5570 def : InstAlias<!strconcat("vpclmul", asm,
5571 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
5572 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
5574 def : InstAlias<!strconcat("vpclmul", asm,
5575 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
5576 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
5578 defm : pclmul_alias<"hqhq", 0x11>;
5579 defm : pclmul_alias<"hqlq", 0x01>;
5580 defm : pclmul_alias<"lqhq", 0x10>;
5581 defm : pclmul_alias<"lqlq", 0x00>;
5583 //===----------------------------------------------------------------------===//
5585 //===----------------------------------------------------------------------===//
5587 //===----------------------------------------------------------------------===//
5588 // VBROADCAST - Load from memory and broadcast to all elements of the
5589 // destination operand
5591 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
5592 X86MemOperand x86memop, Intrinsic Int> :
5593 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
5594 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5595 [(set RC:$dst, (Int addr:$src))]>, VEX;
5597 def VBROADCASTSS : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
5598 int_x86_avx_vbroadcastss>;
5599 def VBROADCASTSSY : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
5600 int_x86_avx_vbroadcastss_256>;
5601 def VBROADCASTSD : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
5602 int_x86_avx_vbroadcast_sd_256>;
5603 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
5604 int_x86_avx_vbroadcastf128_pd_256>;
5606 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
5607 (VBROADCASTF128 addr:$src)>;
5609 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
5610 (VBROADCASTSSY addr:$src)>;
5611 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
5612 (VBROADCASTSD addr:$src)>;
5613 def : Pat<(v8f32 (X86VBroadcast (loadf32 addr:$src))),
5614 (VBROADCASTSSY addr:$src)>;
5615 def : Pat<(v4f64 (X86VBroadcast (loadf64 addr:$src))),
5616 (VBROADCASTSD addr:$src)>;
5618 def : Pat<(v4f32 (X86VBroadcast (loadf32 addr:$src))),
5619 (VBROADCASTSS addr:$src)>;
5620 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
5621 (VBROADCASTSS addr:$src)>;
5623 //===----------------------------------------------------------------------===//
5624 // VINSERTF128 - Insert packed floating-point values
5626 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
5627 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
5628 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5630 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
5631 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
5632 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5635 def : Pat<(int_x86_avx_vinsertf128_pd_256 VR256:$src1, VR128:$src2, imm:$src3),
5636 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
5637 def : Pat<(int_x86_avx_vinsertf128_ps_256 VR256:$src1, VR128:$src2, imm:$src3),
5638 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
5639 def : Pat<(int_x86_avx_vinsertf128_si_256 VR256:$src1, VR128:$src2, imm:$src3),
5640 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
5642 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
5644 (VINSERTF128rr VR256:$src1, VR128:$src2,
5645 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5646 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
5648 (VINSERTF128rr VR256:$src1, VR128:$src2,
5649 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5650 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
5652 (VINSERTF128rr VR256:$src1, VR128:$src2,
5653 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5654 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
5656 (VINSERTF128rr VR256:$src1, VR128:$src2,
5657 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5658 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
5660 (VINSERTF128rr VR256:$src1, VR128:$src2,
5661 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5662 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
5664 (VINSERTF128rr VR256:$src1, VR128:$src2,
5665 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5667 // Special COPY patterns
5668 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (i32 0)),
5669 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
5670 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (i32 0)),
5671 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
5672 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (i32 0)),
5673 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
5674 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (i32 0)),
5675 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
5676 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (i32 0)),
5677 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
5678 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (i32 0)),
5679 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
5681 //===----------------------------------------------------------------------===//
5682 // VEXTRACTF128 - Extract packed floating-point values
5684 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
5685 (ins VR256:$src1, i8imm:$src2),
5686 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5688 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
5689 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
5690 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5693 def : Pat<(int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2),
5694 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
5695 def : Pat<(int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2),
5696 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
5697 def : Pat<(int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2),
5698 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
5700 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5701 (v4f32 (VEXTRACTF128rr
5702 (v8f32 VR256:$src1),
5703 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5704 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5705 (v2f64 (VEXTRACTF128rr
5706 (v4f64 VR256:$src1),
5707 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5708 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5709 (v4i32 (VEXTRACTF128rr
5710 (v8i32 VR256:$src1),
5711 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5712 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5713 (v2i64 (VEXTRACTF128rr
5714 (v4i64 VR256:$src1),
5715 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5716 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5717 (v8i16 (VEXTRACTF128rr
5718 (v16i16 VR256:$src1),
5719 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5720 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5721 (v16i8 (VEXTRACTF128rr
5722 (v32i8 VR256:$src1),
5723 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5725 // Special COPY patterns
5726 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (i32 0))),
5727 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
5728 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (i32 0))),
5729 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
5731 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (i32 0))),
5732 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
5733 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (i32 0))),
5734 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
5736 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (i32 0))),
5737 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
5738 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (i32 0))),
5739 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
5742 //===----------------------------------------------------------------------===//
5743 // VMASKMOV - Conditional SIMD Packed Loads and Stores
5745 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
5746 Intrinsic IntLd, Intrinsic IntLd256,
5747 Intrinsic IntSt, Intrinsic IntSt256,
5748 PatFrag pf128, PatFrag pf256> {
5749 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
5750 (ins VR128:$src1, f128mem:$src2),
5751 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5752 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
5754 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
5755 (ins VR256:$src1, f256mem:$src2),
5756 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5757 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
5759 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
5760 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
5761 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5762 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
5763 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
5764 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
5765 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5766 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
5769 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
5770 int_x86_avx_maskload_ps,
5771 int_x86_avx_maskload_ps_256,
5772 int_x86_avx_maskstore_ps,
5773 int_x86_avx_maskstore_ps_256,
5774 memopv4f32, memopv8f32>;
5775 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
5776 int_x86_avx_maskload_pd,
5777 int_x86_avx_maskload_pd_256,
5778 int_x86_avx_maskstore_pd,
5779 int_x86_avx_maskstore_pd_256,
5780 memopv2f64, memopv4f64>;
5782 //===----------------------------------------------------------------------===//
5783 // VPERMIL - Permute Single and Double Floating-Point Values
5785 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
5786 RegisterClass RC, X86MemOperand x86memop_f,
5787 X86MemOperand x86memop_i, PatFrag f_frag, PatFrag i_frag,
5788 Intrinsic IntVar, Intrinsic IntImm> {
5789 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
5790 (ins RC:$src1, RC:$src2),
5791 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5792 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
5793 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
5794 (ins RC:$src1, x86memop_i:$src2),
5795 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5796 [(set RC:$dst, (IntVar RC:$src1, (i_frag addr:$src2)))]>, VEX_4V;
5798 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
5799 (ins RC:$src1, i8imm:$src2),
5800 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5801 [(set RC:$dst, (IntImm RC:$src1, imm:$src2))]>, VEX;
5802 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
5803 (ins x86memop_f:$src1, i8imm:$src2),
5804 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5805 [(set RC:$dst, (IntImm (f_frag addr:$src1), imm:$src2))]>, VEX;
5808 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
5809 memopv4f32, memopv4i32,
5810 int_x86_avx_vpermilvar_ps,
5811 int_x86_avx_vpermil_ps>;
5812 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
5813 memopv8f32, memopv8i32,
5814 int_x86_avx_vpermilvar_ps_256,
5815 int_x86_avx_vpermil_ps_256>;
5816 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
5817 memopv2f64, memopv2i64,
5818 int_x86_avx_vpermilvar_pd,
5819 int_x86_avx_vpermil_pd>;
5820 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
5821 memopv4f64, memopv4i64,
5822 int_x86_avx_vpermilvar_pd_256,
5823 int_x86_avx_vpermil_pd_256>;
5825 def : Pat<(v8f32 (X86VPermilpsy VR256:$src1, (i8 imm:$imm))),
5826 (VPERMILPSYri VR256:$src1, imm:$imm)>;
5827 def : Pat<(v4f64 (X86VPermilpdy VR256:$src1, (i8 imm:$imm))),
5828 (VPERMILPDYri VR256:$src1, imm:$imm)>;
5829 def : Pat<(v8i32 (X86VPermilpsy VR256:$src1, (i8 imm:$imm))),
5830 (VPERMILPSYri VR256:$src1, imm:$imm)>;
5831 def : Pat<(v4i64 (X86VPermilpdy VR256:$src1, (i8 imm:$imm))),
5832 (VPERMILPDYri VR256:$src1, imm:$imm)>;
5834 //===----------------------------------------------------------------------===//
5835 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
5837 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
5838 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5839 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5841 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
5842 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
5843 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5846 def : Pat<(int_x86_avx_vperm2f128_ps_256 VR256:$src1, VR256:$src2, imm:$src3),
5847 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
5848 def : Pat<(int_x86_avx_vperm2f128_pd_256 VR256:$src1, VR256:$src2, imm:$src3),
5849 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
5850 def : Pat<(int_x86_avx_vperm2f128_si_256 VR256:$src1, VR256:$src2, imm:$src3),
5851 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
5853 def : Pat<(int_x86_avx_vperm2f128_ps_256
5854 VR256:$src1, (memopv8f32 addr:$src2), imm:$src3),
5855 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
5856 def : Pat<(int_x86_avx_vperm2f128_pd_256
5857 VR256:$src1, (memopv4f64 addr:$src2), imm:$src3),
5858 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
5859 def : Pat<(int_x86_avx_vperm2f128_si_256
5860 VR256:$src1, (memopv8i32 addr:$src2), imm:$src3),
5861 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
5863 def : Pat<(v8f32 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5864 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
5865 def : Pat<(v8i32 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5866 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
5867 def : Pat<(v4i64 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5868 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
5869 def : Pat<(v4f64 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5870 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
5871 def : Pat<(v32i8 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5872 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
5873 def : Pat<(v16i16 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5874 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
5876 //===----------------------------------------------------------------------===//
5877 // VZERO - Zero YMM registers
5879 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
5880 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
5881 // Zero All YMM registers
5882 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
5883 [(int_x86_avx_vzeroall)]>, VEX, VEX_L, Requires<[HasAVX]>;
5887 // Zero Upper bits of YMM registers
5888 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
5889 [(int_x86_avx_vzeroupper)]>, VEX, Requires<[HasAVX]>;
5891 //===----------------------------------------------------------------------===//
5892 // SSE Shuffle pattern fragments
5893 //===----------------------------------------------------------------------===//
5895 // This is part of a "work in progress" refactoring. The idea is that all
5896 // vector shuffles are going to be translated into target specific nodes and
5897 // directly matched by the patterns below (which can be changed along the way)
5898 // The AVX version of some but not all of them are described here, and more
5899 // should come in a near future.
5901 // Shuffle with PSHUFD instruction folding loads. The first two patterns match
5902 // SSE2 loads, which are always promoted to v2i64. The last one should match
5903 // the SSE1 case, where the only legal load is v4f32, but there is no PSHUFD
5904 // in SSE2, how does it ever worked? Anyway, the pattern will remain here until
5905 // we investigate further.
5906 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
5908 (VPSHUFDmi addr:$src1, imm:$imm)>, Requires<[HasAVX]>;
5909 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
5911 (PSHUFDmi addr:$src1, imm:$imm)>;
5912 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv4f32 addr:$src1)),
5914 (PSHUFDmi addr:$src1, imm:$imm)>; // FIXME: has this ever worked?
5916 // Shuffle with PSHUFD instruction.
5917 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
5918 (VPSHUFDri VR128:$src1, imm:$imm)>, Requires<[HasAVX]>;
5919 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
5920 (PSHUFDri VR128:$src1, imm:$imm)>;
5922 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
5923 (VPSHUFDri VR128:$src1, imm:$imm)>, Requires<[HasAVX]>;
5924 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
5925 (PSHUFDri VR128:$src1, imm:$imm)>;
5927 // Shuffle with SHUFPD instruction.
5928 def : Pat<(v2f64 (X86Shufps VR128:$src1,
5929 (memopv2f64 addr:$src2), (i8 imm:$imm))),
5930 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>, Requires<[HasAVX]>;
5931 def : Pat<(v2f64 (X86Shufps VR128:$src1,
5932 (memopv2f64 addr:$src2), (i8 imm:$imm))),
5933 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
5935 def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5936 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>;
5937 def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5938 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
5940 def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5941 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>;
5942 def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5943 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
5945 // Shuffle with SHUFPS instruction.
5946 def : Pat<(v4f32 (X86Shufps VR128:$src1,
5947 (memopv4f32 addr:$src2), (i8 imm:$imm))),
5948 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>, Requires<[HasAVX]>;
5949 def : Pat<(v4f32 (X86Shufps VR128:$src1,
5950 (memopv4f32 addr:$src2), (i8 imm:$imm))),
5951 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
5953 def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5954 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>;
5955 def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5956 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
5958 def : Pat<(v4i32 (X86Shufps VR128:$src1,
5959 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
5960 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>, Requires<[HasAVX]>;
5961 def : Pat<(v4i32 (X86Shufps VR128:$src1,
5962 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
5963 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
5965 def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5966 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>;
5967 def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5968 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
5970 // Shuffle with MOVHLPS instruction
5971 def : Pat<(v4f32 (X86Movhlps VR128:$src1, VR128:$src2)),
5972 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
5973 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
5974 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
5976 // Shuffle with MOVDDUP instruction
5977 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5978 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5979 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5980 (MOVDDUPrm addr:$src)>;
5982 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5983 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5984 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5985 (MOVDDUPrm addr:$src)>;
5987 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5988 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5989 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5990 (MOVDDUPrm addr:$src)>;
5992 def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))),
5993 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5994 def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))),
5995 (MOVDDUPrm addr:$src)>;
5997 def : Pat<(X86Movddup (bc_v2f64
5998 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5999 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
6000 def : Pat<(X86Movddup (bc_v2f64
6001 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
6002 (MOVDDUPrm addr:$src)>;
6005 // Shuffle with UNPCKLPS
6006 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
6007 (VUNPCKLPSrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
6008 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
6009 (UNPCKLPSrm VR128:$src1, addr:$src2)>;
6011 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
6012 (VUNPCKLPSrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
6013 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
6014 (UNPCKLPSrr VR128:$src1, VR128:$src2)>;
6016 // Shuffle with VUNPCKHPSY
6017 def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, (memopv8f32 addr:$src2))),
6018 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
6019 def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, VR256:$src2)),
6020 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
6021 def : Pat<(v8i32 (X86Unpcklpsy VR256:$src1, VR256:$src2)),
6022 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
6023 def : Pat<(v8i32 (X86Unpcklpsy VR256:$src1, (memopv8i32 addr:$src2))),
6024 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
6026 // Shuffle with UNPCKHPS
6027 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))),
6028 (VUNPCKHPSrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
6029 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))),
6030 (UNPCKHPSrm VR128:$src1, addr:$src2)>;
6032 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
6033 (VUNPCKHPSrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
6034 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
6035 (UNPCKHPSrr VR128:$src1, VR128:$src2)>;
6037 // Shuffle with VUNPCKHPSY
6038 def : Pat<(v8f32 (X86Unpckhpsy VR256:$src1, (memopv8f32 addr:$src2))),
6039 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
6040 def : Pat<(v8f32 (X86Unpckhpsy VR256:$src1, VR256:$src2)),
6041 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
6043 def : Pat<(v8i32 (X86Unpckhpsy VR256:$src1, (memopv8i32 addr:$src2))),
6044 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
6045 def : Pat<(v8i32 (X86Unpckhpsy VR256:$src1, VR256:$src2)),
6046 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
6048 // Shuffle with UNPCKLPD
6049 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
6050 (VUNPCKLPDrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
6051 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
6052 (UNPCKLPDrm VR128:$src1, addr:$src2)>;
6054 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
6055 (VUNPCKLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
6056 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
6057 (UNPCKLPDrr VR128:$src1, VR128:$src2)>;
6059 // Shuffle with VUNPCKLPDY
6060 def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, (memopv4f64 addr:$src2))),
6061 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
6062 def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, VR256:$src2)),
6063 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
6065 def : Pat<(v4i64 (X86Unpcklpdy VR256:$src1, (memopv4i64 addr:$src2))),
6066 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
6067 def : Pat<(v4i64 (X86Unpcklpdy VR256:$src1, VR256:$src2)),
6068 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
6070 // Shuffle with UNPCKHPD
6071 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))),
6072 (VUNPCKHPDrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
6073 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))),
6074 (UNPCKHPDrm VR128:$src1, addr:$src2)>;
6076 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
6077 (VUNPCKHPDrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
6078 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
6079 (UNPCKHPDrr VR128:$src1, VR128:$src2)>;
6081 // Shuffle with VUNPCKHPDY
6082 def : Pat<(v4f64 (X86Unpckhpdy VR256:$src1, (memopv4f64 addr:$src2))),
6083 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
6084 def : Pat<(v4f64 (X86Unpckhpdy VR256:$src1, VR256:$src2)),
6085 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
6086 def : Pat<(v4i64 (X86Unpckhpdy VR256:$src1, (memopv4i64 addr:$src2))),
6087 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
6088 def : Pat<(v4i64 (X86Unpckhpdy VR256:$src1, VR256:$src2)),
6089 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
6091 // FIXME: Instead of X86Movddup, there should be a X86Unpcklpd here, the problem
6092 // is during lowering, where it's not possible to recognize the load fold cause
6093 // it has two uses through a bitcast. One use disappears at isel time and the
6094 // fold opportunity reappears.
6095 def : Pat<(v2f64 (X86Movddup VR128:$src)),
6096 (UNPCKLPDrr VR128:$src, VR128:$src)>;
6098 // Shuffle with MOVLHPD
6099 def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
6100 (scalar_to_vector (loadf64 addr:$src2)))),
6101 (MOVHPDrm VR128:$src1, addr:$src2)>;
6103 // FIXME: Instead of X86Unpcklpd, there should be a X86Movlhpd here, the problem
6104 // is during lowering, where it's not possible to recognize the load fold cause
6105 // it has two uses through a bitcast. One use disappears at isel time and the
6106 // fold opportunity reappears.
6107 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1,
6108 (scalar_to_vector (loadf64 addr:$src2)))),
6109 (MOVHPDrm VR128:$src1, addr:$src2)>;
6111 // Shuffle with MOVSS
6112 def : Pat<(v4f32 (X86Movss VR128:$src1, (scalar_to_vector FR32:$src2))),
6113 (MOVSSrr VR128:$src1, FR32:$src2)>;
6114 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
6115 (MOVSSrr (v4i32 VR128:$src1),
6116 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
6117 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
6118 (MOVSSrr (v4f32 VR128:$src1),
6119 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
6121 // Shuffle with MOVSD
6122 def : Pat<(v2f64 (X86Movsd VR128:$src1, (scalar_to_vector FR64:$src2))),
6123 (MOVSDrr VR128:$src1, FR64:$src2)>;
6124 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
6125 (MOVSDrr (v2i64 VR128:$src1),
6126 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
6127 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
6128 (MOVSDrr (v2f64 VR128:$src1),
6129 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
6130 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
6131 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_sd))>;
6132 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
6133 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_sd))>;
6135 // Shuffle with PSHUFHW
6136 def : Pat<(v8i16 (X86PShufhw VR128:$src, (i8 imm:$imm))),
6137 (PSHUFHWri VR128:$src, imm:$imm)>;
6138 def : Pat<(v8i16 (X86PShufhw (bc_v8i16 (memopv2i64 addr:$src)), (i8 imm:$imm))),
6139 (PSHUFHWmi addr:$src, imm:$imm)>;
6141 // Shuffle with PSHUFLW
6142 def : Pat<(v8i16 (X86PShuflw VR128:$src, (i8 imm:$imm))),
6143 (PSHUFLWri VR128:$src, imm:$imm)>;
6144 def : Pat<(v8i16 (X86PShuflw (bc_v8i16 (memopv2i64 addr:$src)), (i8 imm:$imm))),
6145 (PSHUFLWmi addr:$src, imm:$imm)>;
6147 // Shuffle with MOVLPS
6148 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
6149 (MOVLPSrm VR128:$src1, addr:$src2)>;
6150 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
6151 (MOVLPSrm VR128:$src1, addr:$src2)>;
6152 def : Pat<(X86Movlps VR128:$src1,
6153 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
6154 (MOVLPSrm VR128:$src1, addr:$src2)>;
6155 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
6156 // is during lowering, where it's not possible to recognize the load fold cause
6157 // it has two uses through a bitcast. One use disappears at isel time and the
6158 // fold opportunity reappears.
6159 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
6160 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_sd))>;
6162 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
6163 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_sd))>;
6165 // Shuffle with MOVLPD
6166 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
6167 (MOVLPDrm VR128:$src1, addr:$src2)>;
6168 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
6169 (MOVLPDrm VR128:$src1, addr:$src2)>;
6170 def : Pat<(v2f64 (X86Movlpd VR128:$src1,
6171 (scalar_to_vector (loadf64 addr:$src2)))),
6172 (MOVLPDrm VR128:$src1, addr:$src2)>;
6174 // Extra patterns to match stores with MOVHPS/PD and MOVLPS/PD
6175 def : Pat<(store (f64 (vector_extract
6176 (v2f64 (X86Unpckhps VR128:$src, (undef))), (iPTR 0))),addr:$dst),
6177 (MOVHPSmr addr:$dst, VR128:$src)>;
6178 def : Pat<(store (f64 (vector_extract
6179 (v2f64 (X86Unpckhpd VR128:$src, (undef))), (iPTR 0))),addr:$dst),
6180 (MOVHPDmr addr:$dst, VR128:$src)>;
6182 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),addr:$src1),
6183 (MOVLPSmr addr:$src1, VR128:$src2)>;
6184 def : Pat<(store (v4i32 (X86Movlps
6185 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
6186 (MOVLPSmr addr:$src1, VR128:$src2)>;
6188 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),addr:$src1),
6189 (MOVLPDmr addr:$src1, VR128:$src2)>;
6190 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),addr:$src1),
6191 (MOVLPDmr addr:$src1, VR128:$src2)>;